1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "amdgpu_pm.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 30 #include "vcn/vcn_2_0_0_offset.h" 31 #include "vcn/vcn_2_0_0_sh_mask.h" 32 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 33 34 #define mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET 0x1bfff 35 #define mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET 0x4029 36 #define mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET 0x402a 37 #define mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET 0x402b 38 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ea 39 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40eb 40 #define mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET 0x40cf 41 #define mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET 0x40d1 42 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40e8 43 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40e9 44 #define mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET 0x4082 45 #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ec 46 #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40ed 47 #define mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET 0x4085 48 #define mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET 0x4084 49 #define mmUVD_JRBC_STATUS_INTERNAL_OFFSET 0x4089 50 #define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f 51 52 #define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR 0x18000 53 54 static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev); 55 static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev); 56 static int jpeg_v2_0_set_powergating_state(void *handle, 57 enum amd_powergating_state state); 58 59 /** 60 * jpeg_v2_0_early_init - set function pointers 61 * 62 * @handle: amdgpu_device pointer 63 * 64 * Set ring and irq function pointers 65 */ 66 static int jpeg_v2_0_early_init(void *handle) 67 { 68 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 69 70 adev->jpeg.num_jpeg_inst = 1; 71 72 jpeg_v2_0_set_dec_ring_funcs(adev); 73 jpeg_v2_0_set_irq_funcs(adev); 74 75 return 0; 76 } 77 78 /** 79 * jpeg_v2_0_sw_init - sw init for JPEG block 80 * 81 * @handle: amdgpu_device pointer 82 * 83 * Load firmware and sw initialization 84 */ 85 static int jpeg_v2_0_sw_init(void *handle) 86 { 87 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 88 struct amdgpu_ring *ring; 89 int r; 90 91 /* JPEG TRAP */ 92 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 93 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); 94 if (r) 95 return r; 96 97 r = amdgpu_jpeg_sw_init(adev); 98 if (r) 99 return r; 100 101 r = amdgpu_jpeg_resume(adev); 102 if (r) 103 return r; 104 105 ring = &adev->jpeg.inst->ring_dec; 106 ring->use_doorbell = true; 107 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1; 108 sprintf(ring->name, "jpeg_dec"); 109 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0); 110 if (r) 111 return r; 112 113 adev->jpeg.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET; 114 adev->jpeg.inst->external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH); 115 116 return 0; 117 } 118 119 /** 120 * jpeg_v2_0_sw_fini - sw fini for JPEG block 121 * 122 * @handle: amdgpu_device pointer 123 * 124 * JPEG suspend and free up sw allocation 125 */ 126 static int jpeg_v2_0_sw_fini(void *handle) 127 { 128 int r; 129 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 130 131 r = amdgpu_jpeg_suspend(adev); 132 if (r) 133 return r; 134 135 r = amdgpu_jpeg_sw_fini(adev); 136 137 return r; 138 } 139 140 /** 141 * jpeg_v2_0_hw_init - start and test JPEG block 142 * 143 * @handle: amdgpu_device pointer 144 * 145 */ 146 static int jpeg_v2_0_hw_init(void *handle) 147 { 148 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 149 struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec; 150 int r; 151 152 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 153 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0); 154 155 r = amdgpu_ring_test_helper(ring); 156 if (!r) 157 DRM_INFO("JPEG decode initialized successfully.\n"); 158 159 return r; 160 } 161 162 /** 163 * jpeg_v2_0_hw_fini - stop the hardware block 164 * 165 * @handle: amdgpu_device pointer 166 * 167 * Stop the JPEG block, mark ring as not ready any more 168 */ 169 static int jpeg_v2_0_hw_fini(void *handle) 170 { 171 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 172 struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec; 173 174 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && 175 RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS)) 176 jpeg_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 177 178 ring->sched.ready = false; 179 180 return 0; 181 } 182 183 /** 184 * jpeg_v2_0_suspend - suspend JPEG block 185 * 186 * @handle: amdgpu_device pointer 187 * 188 * HW fini and suspend JPEG block 189 */ 190 static int jpeg_v2_0_suspend(void *handle) 191 { 192 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 193 int r; 194 195 r = jpeg_v2_0_hw_fini(adev); 196 if (r) 197 return r; 198 199 r = amdgpu_jpeg_suspend(adev); 200 201 return r; 202 } 203 204 /** 205 * jpeg_v2_0_resume - resume JPEG block 206 * 207 * @handle: amdgpu_device pointer 208 * 209 * Resume firmware and hw init JPEG block 210 */ 211 static int jpeg_v2_0_resume(void *handle) 212 { 213 int r; 214 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 215 216 r = amdgpu_jpeg_resume(adev); 217 if (r) 218 return r; 219 220 r = jpeg_v2_0_hw_init(adev); 221 222 return r; 223 } 224 225 static int jpeg_v2_0_disable_power_gating(struct amdgpu_device *adev) 226 { 227 uint32_t data; 228 int r = 0; 229 230 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 231 data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 232 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data); 233 234 SOC15_WAIT_ON_RREG(JPEG, 0, 235 mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON, 236 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r); 237 238 if (r) { 239 DRM_ERROR("amdgpu: JPEG disable power gating failed\n"); 240 return r; 241 } 242 } 243 244 /* Removing the anti hang mechanism to indicate the UVDJ tile is ON */ 245 data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS)) & ~0x1; 246 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data); 247 248 return 0; 249 } 250 251 static int jpeg_v2_0_enable_power_gating(struct amdgpu_device* adev) 252 { 253 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 254 uint32_t data; 255 int r = 0; 256 257 data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS)); 258 data &= ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK; 259 data |= 0x1; //UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_TILES_OFF; 260 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data); 261 262 data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 263 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data); 264 265 SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS, 266 (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT), 267 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r); 268 269 if (r) { 270 DRM_ERROR("amdgpu: JPEG enable power gating failed\n"); 271 return r; 272 } 273 } 274 275 return 0; 276 } 277 278 static void jpeg_v2_0_disable_clock_gating(struct amdgpu_device* adev) 279 { 280 uint32_t data; 281 282 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL); 283 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) 284 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 285 else 286 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 287 288 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 289 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 290 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data); 291 292 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); 293 data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK 294 | JPEG_CGC_GATE__JPEG2_DEC_MASK 295 | JPEG_CGC_GATE__JPEG_ENC_MASK 296 | JPEG_CGC_GATE__JMCIF_MASK 297 | JPEG_CGC_GATE__JRBBM_MASK); 298 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data); 299 } 300 301 static void jpeg_v2_0_enable_clock_gating(struct amdgpu_device* adev) 302 { 303 uint32_t data; 304 305 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL); 306 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) 307 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 308 else 309 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 310 311 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 312 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 313 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data); 314 315 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); 316 data |= (JPEG_CGC_GATE__JPEG_DEC_MASK 317 |JPEG_CGC_GATE__JPEG2_DEC_MASK 318 |JPEG_CGC_GATE__JPEG_ENC_MASK 319 |JPEG_CGC_GATE__JMCIF_MASK 320 |JPEG_CGC_GATE__JRBBM_MASK); 321 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data); 322 } 323 324 /** 325 * jpeg_v2_0_start - start JPEG block 326 * 327 * @adev: amdgpu_device pointer 328 * 329 * Setup and start the JPEG block 330 */ 331 static int jpeg_v2_0_start(struct amdgpu_device *adev) 332 { 333 struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec; 334 int r; 335 336 if (adev->pm.dpm_enabled) 337 amdgpu_dpm_enable_jpeg(adev, true); 338 339 /* disable power gating */ 340 r = jpeg_v2_0_disable_power_gating(adev); 341 if (r) 342 return r; 343 344 /* JPEG disable CGC */ 345 jpeg_v2_0_disable_clock_gating(adev); 346 347 WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 348 349 /* enable JMI channel */ 350 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0, 351 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 352 353 /* enable System Interrupt for JRBC */ 354 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN), 355 JPEG_SYS_INT_EN__DJRBC_MASK, 356 ~JPEG_SYS_INT_EN__DJRBC_MASK); 357 358 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0); 359 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); 360 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 361 lower_32_bits(ring->gpu_addr)); 362 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 363 upper_32_bits(ring->gpu_addr)); 364 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0); 365 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0); 366 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L); 367 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4); 368 ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); 369 370 return 0; 371 } 372 373 /** 374 * jpeg_v2_0_stop - stop JPEG block 375 * 376 * @adev: amdgpu_device pointer 377 * 378 * stop the JPEG block 379 */ 380 static int jpeg_v2_0_stop(struct amdgpu_device *adev) 381 { 382 int r; 383 384 /* reset JMI */ 385 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 386 UVD_JMI_CNTL__SOFT_RESET_MASK, 387 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 388 389 /* enable JPEG CGC */ 390 jpeg_v2_0_enable_clock_gating(adev); 391 392 /* enable power gating */ 393 r = jpeg_v2_0_enable_power_gating(adev); 394 if (r) 395 return r; 396 397 if (adev->pm.dpm_enabled) 398 amdgpu_dpm_enable_jpeg(adev, false); 399 400 return 0; 401 } 402 403 /** 404 * jpeg_v2_0_dec_ring_get_rptr - get read pointer 405 * 406 * @ring: amdgpu_ring pointer 407 * 408 * Returns the current hardware read pointer 409 */ 410 static uint64_t jpeg_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 411 { 412 struct amdgpu_device *adev = ring->adev; 413 414 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR); 415 } 416 417 /** 418 * jpeg_v2_0_dec_ring_get_wptr - get write pointer 419 * 420 * @ring: amdgpu_ring pointer 421 * 422 * Returns the current hardware write pointer 423 */ 424 static uint64_t jpeg_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 425 { 426 struct amdgpu_device *adev = ring->adev; 427 428 if (ring->use_doorbell) 429 return adev->wb.wb[ring->wptr_offs]; 430 else 431 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); 432 } 433 434 /** 435 * jpeg_v2_0_dec_ring_set_wptr - set write pointer 436 * 437 * @ring: amdgpu_ring pointer 438 * 439 * Commits the write pointer to the hardware 440 */ 441 static void jpeg_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 442 { 443 struct amdgpu_device *adev = ring->adev; 444 445 if (ring->use_doorbell) { 446 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 447 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 448 } else { 449 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); 450 } 451 } 452 453 /** 454 * jpeg_v2_0_dec_ring_insert_start - insert a start command 455 * 456 * @ring: amdgpu_ring pointer 457 * 458 * Write a start command to the ring. 459 */ 460 void jpeg_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring) 461 { 462 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 463 0, 0, PACKETJ_TYPE0)); 464 amdgpu_ring_write(ring, 0x68e04); 465 466 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 467 0, 0, PACKETJ_TYPE0)); 468 amdgpu_ring_write(ring, 0x80010000); 469 } 470 471 /** 472 * jpeg_v2_0_dec_ring_insert_end - insert a end command 473 * 474 * @ring: amdgpu_ring pointer 475 * 476 * Write a end command to the ring. 477 */ 478 void jpeg_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring) 479 { 480 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 481 0, 0, PACKETJ_TYPE0)); 482 amdgpu_ring_write(ring, 0x68e04); 483 484 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 485 0, 0, PACKETJ_TYPE0)); 486 amdgpu_ring_write(ring, 0x00010000); 487 } 488 489 /** 490 * jpeg_v2_0_dec_ring_emit_fence - emit an fence & trap command 491 * 492 * @ring: amdgpu_ring pointer 493 * @fence: fence to emit 494 * 495 * Write a fence and a trap command to the ring. 496 */ 497 void jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 498 unsigned flags) 499 { 500 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 501 502 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET, 503 0, 0, PACKETJ_TYPE0)); 504 amdgpu_ring_write(ring, seq); 505 506 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET, 507 0, 0, PACKETJ_TYPE0)); 508 amdgpu_ring_write(ring, seq); 509 510 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET, 511 0, 0, PACKETJ_TYPE0)); 512 amdgpu_ring_write(ring, lower_32_bits(addr)); 513 514 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET, 515 0, 0, PACKETJ_TYPE0)); 516 amdgpu_ring_write(ring, upper_32_bits(addr)); 517 518 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, 519 0, 0, PACKETJ_TYPE0)); 520 amdgpu_ring_write(ring, 0x8); 521 522 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, 523 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4)); 524 amdgpu_ring_write(ring, 0); 525 526 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 527 0, 0, PACKETJ_TYPE0)); 528 amdgpu_ring_write(ring, 0x3fbc); 529 530 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 531 0, 0, PACKETJ_TYPE0)); 532 amdgpu_ring_write(ring, 0x1); 533 534 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7)); 535 amdgpu_ring_write(ring, 0); 536 } 537 538 /** 539 * jpeg_v2_0_dec_ring_emit_ib - execute indirect buffer 540 * 541 * @ring: amdgpu_ring pointer 542 * @ib: indirect buffer to execute 543 * 544 * Write ring commands to execute the indirect buffer. 545 */ 546 void jpeg_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, 547 struct amdgpu_job *job, 548 struct amdgpu_ib *ib, 549 uint32_t flags) 550 { 551 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 552 553 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET, 554 0, 0, PACKETJ_TYPE0)); 555 amdgpu_ring_write(ring, (vmid | (vmid << 4))); 556 557 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET, 558 0, 0, PACKETJ_TYPE0)); 559 amdgpu_ring_write(ring, (vmid | (vmid << 4))); 560 561 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET, 562 0, 0, PACKETJ_TYPE0)); 563 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 564 565 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET, 566 0, 0, PACKETJ_TYPE0)); 567 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 568 569 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET, 570 0, 0, PACKETJ_TYPE0)); 571 amdgpu_ring_write(ring, ib->length_dw); 572 573 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET, 574 0, 0, PACKETJ_TYPE0)); 575 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr)); 576 577 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET, 578 0, 0, PACKETJ_TYPE0)); 579 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr)); 580 581 amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2)); 582 amdgpu_ring_write(ring, 0); 583 584 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, 585 0, 0, PACKETJ_TYPE0)); 586 amdgpu_ring_write(ring, 0x01400200); 587 588 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, 589 0, 0, PACKETJ_TYPE0)); 590 amdgpu_ring_write(ring, 0x2); 591 592 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_STATUS_INTERNAL_OFFSET, 593 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3)); 594 amdgpu_ring_write(ring, 0x2); 595 } 596 597 void jpeg_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 598 uint32_t val, uint32_t mask) 599 { 600 uint32_t reg_offset = (reg << 2); 601 602 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, 603 0, 0, PACKETJ_TYPE0)); 604 amdgpu_ring_write(ring, 0x01400200); 605 606 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, 607 0, 0, PACKETJ_TYPE0)); 608 amdgpu_ring_write(ring, val); 609 610 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 611 0, 0, PACKETJ_TYPE0)); 612 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 613 amdgpu_ring_write(ring, 0); 614 amdgpu_ring_write(ring, 615 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); 616 } else { 617 amdgpu_ring_write(ring, reg_offset); 618 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 619 0, 0, PACKETJ_TYPE3)); 620 } 621 amdgpu_ring_write(ring, mask); 622 } 623 624 void jpeg_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 625 unsigned vmid, uint64_t pd_addr) 626 { 627 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 628 uint32_t data0, data1, mask; 629 630 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 631 632 /* wait for register write */ 633 data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2; 634 data1 = lower_32_bits(pd_addr); 635 mask = 0xffffffff; 636 jpeg_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); 637 } 638 639 void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 640 { 641 uint32_t reg_offset = (reg << 2); 642 643 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 644 0, 0, PACKETJ_TYPE0)); 645 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 646 amdgpu_ring_write(ring, 0); 647 amdgpu_ring_write(ring, 648 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); 649 } else { 650 amdgpu_ring_write(ring, reg_offset); 651 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 652 0, 0, PACKETJ_TYPE0)); 653 } 654 amdgpu_ring_write(ring, val); 655 } 656 657 void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count) 658 { 659 int i; 660 661 WARN_ON(ring->wptr % 2 || count % 2); 662 663 for (i = 0; i < count / 2; i++) { 664 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 665 amdgpu_ring_write(ring, 0); 666 } 667 } 668 669 static bool jpeg_v2_0_is_idle(void *handle) 670 { 671 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 672 673 return ((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) & 674 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 675 UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 676 } 677 678 static int jpeg_v2_0_wait_for_idle(void *handle) 679 { 680 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 681 int ret = 0; 682 683 SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 684 UVD_JRBC_STATUS__RB_JOB_DONE_MASK, ret); 685 686 return ret; 687 } 688 689 static int jpeg_v2_0_set_clockgating_state(void *handle, 690 enum amd_clockgating_state state) 691 { 692 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 693 bool enable = (state == AMD_CG_STATE_GATE); 694 695 if (enable) { 696 if (jpeg_v2_0_is_idle(handle)) 697 return -EBUSY; 698 jpeg_v2_0_enable_clock_gating(adev); 699 } else { 700 jpeg_v2_0_disable_clock_gating(adev); 701 } 702 703 return 0; 704 } 705 706 static int jpeg_v2_0_set_powergating_state(void *handle, 707 enum amd_powergating_state state) 708 { 709 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 710 int ret; 711 712 if (state == adev->jpeg.cur_state) 713 return 0; 714 715 if (state == AMD_PG_STATE_GATE) 716 ret = jpeg_v2_0_stop(adev); 717 else 718 ret = jpeg_v2_0_start(adev); 719 720 if (!ret) 721 adev->jpeg.cur_state = state; 722 723 return ret; 724 } 725 726 static int jpeg_v2_0_set_interrupt_state(struct amdgpu_device *adev, 727 struct amdgpu_irq_src *source, 728 unsigned type, 729 enum amdgpu_interrupt_state state) 730 { 731 return 0; 732 } 733 734 static int jpeg_v2_0_process_interrupt(struct amdgpu_device *adev, 735 struct amdgpu_irq_src *source, 736 struct amdgpu_iv_entry *entry) 737 { 738 DRM_DEBUG("IH: JPEG TRAP\n"); 739 740 switch (entry->src_id) { 741 case VCN_2_0__SRCID__JPEG_DECODE: 742 amdgpu_fence_process(&adev->jpeg.inst->ring_dec); 743 break; 744 default: 745 DRM_ERROR("Unhandled interrupt: %d %d\n", 746 entry->src_id, entry->src_data[0]); 747 break; 748 } 749 750 return 0; 751 } 752 753 static const struct amd_ip_funcs jpeg_v2_0_ip_funcs = { 754 .name = "jpeg_v2_0", 755 .early_init = jpeg_v2_0_early_init, 756 .late_init = NULL, 757 .sw_init = jpeg_v2_0_sw_init, 758 .sw_fini = jpeg_v2_0_sw_fini, 759 .hw_init = jpeg_v2_0_hw_init, 760 .hw_fini = jpeg_v2_0_hw_fini, 761 .suspend = jpeg_v2_0_suspend, 762 .resume = jpeg_v2_0_resume, 763 .is_idle = jpeg_v2_0_is_idle, 764 .wait_for_idle = jpeg_v2_0_wait_for_idle, 765 .check_soft_reset = NULL, 766 .pre_soft_reset = NULL, 767 .soft_reset = NULL, 768 .post_soft_reset = NULL, 769 .set_clockgating_state = jpeg_v2_0_set_clockgating_state, 770 .set_powergating_state = jpeg_v2_0_set_powergating_state, 771 }; 772 773 static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = { 774 .type = AMDGPU_RING_TYPE_VCN_JPEG, 775 .align_mask = 0xf, 776 .vmhub = AMDGPU_MMHUB_0, 777 .get_rptr = jpeg_v2_0_dec_ring_get_rptr, 778 .get_wptr = jpeg_v2_0_dec_ring_get_wptr, 779 .set_wptr = jpeg_v2_0_dec_ring_set_wptr, 780 .emit_frame_size = 781 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 782 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 783 8 + /* jpeg_v2_0_dec_ring_emit_vm_flush */ 784 18 + 18 + /* jpeg_v2_0_dec_ring_emit_fence x2 vm fence */ 785 8 + 16, 786 .emit_ib_size = 22, /* jpeg_v2_0_dec_ring_emit_ib */ 787 .emit_ib = jpeg_v2_0_dec_ring_emit_ib, 788 .emit_fence = jpeg_v2_0_dec_ring_emit_fence, 789 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush, 790 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 791 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 792 .insert_nop = jpeg_v2_0_dec_ring_nop, 793 .insert_start = jpeg_v2_0_dec_ring_insert_start, 794 .insert_end = jpeg_v2_0_dec_ring_insert_end, 795 .pad_ib = amdgpu_ring_generic_pad_ib, 796 .begin_use = amdgpu_jpeg_ring_begin_use, 797 .end_use = amdgpu_jpeg_ring_end_use, 798 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg, 799 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait, 800 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 801 }; 802 803 static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev) 804 { 805 adev->jpeg.inst->ring_dec.funcs = &jpeg_v2_0_dec_ring_vm_funcs; 806 DRM_INFO("JPEG decode is enabled in VM mode\n"); 807 } 808 809 static const struct amdgpu_irq_src_funcs jpeg_v2_0_irq_funcs = { 810 .set = jpeg_v2_0_set_interrupt_state, 811 .process = jpeg_v2_0_process_interrupt, 812 }; 813 814 static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev) 815 { 816 adev->jpeg.inst->irq.num_types = 1; 817 adev->jpeg.inst->irq.funcs = &jpeg_v2_0_irq_funcs; 818 } 819 820 const struct amdgpu_ip_block_version jpeg_v2_0_ip_block = 821 { 822 .type = AMD_IP_BLOCK_TYPE_JPEG, 823 .major = 2, 824 .minor = 0, 825 .rev = 0, 826 .funcs = &jpeg_v2_0_ip_funcs, 827 }; 828