1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_imu.h" 27 28 #include "gc/gc_11_0_0_offset.h" 29 #include "gc/gc_11_0_0_sh_mask.h" 30 31 MODULE_FIRMWARE("amdgpu/gc_11_0_0_imu.bin"); 32 MODULE_FIRMWARE("amdgpu/gc_11_0_2_imu.bin"); 33 34 static int imu_v11_0_init_microcode(struct amdgpu_device *adev) 35 { 36 char fw_name[40]; 37 char ucode_prefix[30]; 38 int err; 39 const struct imu_firmware_header_v1_0 *imu_hdr; 40 struct amdgpu_firmware_info *info = NULL; 41 42 DRM_DEBUG("\n"); 43 44 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 45 46 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_imu.bin", ucode_prefix); 47 err = request_firmware(&adev->gfx.imu_fw, fw_name, adev->dev); 48 if (err) 49 goto out; 50 err = amdgpu_ucode_validate(adev->gfx.imu_fw); 51 if (err) 52 goto out; 53 imu_hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; 54 adev->gfx.imu_fw_version = le32_to_cpu(imu_hdr->header.ucode_version); 55 //adev->gfx.imu_feature_version = le32_to_cpu(imu_hdr->ucode_feature_version); 56 57 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 58 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_IMU_I]; 59 info->ucode_id = AMDGPU_UCODE_ID_IMU_I; 60 info->fw = adev->gfx.imu_fw; 61 adev->firmware.fw_size += 62 ALIGN(le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes), PAGE_SIZE); 63 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_IMU_D]; 64 info->ucode_id = AMDGPU_UCODE_ID_IMU_D; 65 info->fw = adev->gfx.imu_fw; 66 adev->firmware.fw_size += 67 ALIGN(le32_to_cpu(imu_hdr->imu_dram_ucode_size_bytes), PAGE_SIZE); 68 } 69 70 out: 71 if (err) { 72 dev_err(adev->dev, 73 "gfx11: Failed to load firmware \"%s\"\n", 74 fw_name); 75 release_firmware(adev->gfx.imu_fw); 76 } 77 78 return err; 79 } 80 81 static int imu_v11_0_load_microcode(struct amdgpu_device *adev) 82 { 83 const struct imu_firmware_header_v1_0 *hdr; 84 const __le32 *fw_data; 85 unsigned i, fw_size; 86 87 if (!adev->gfx.imu_fw) 88 return -EINVAL; 89 90 hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; 91 //amdgpu_ucode_print_rlc_hdr(&hdr->header); 92 93 fw_data = (const __le32 *)(adev->gfx.imu_fw->data + 94 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 95 fw_size = le32_to_cpu(hdr->imu_iram_ucode_size_bytes) / 4; 96 97 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, 0); 98 99 for (i = 0; i < fw_size; i++) 100 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_DATA, le32_to_cpup(fw_data++)); 101 102 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, adev->gfx.imu_fw_version); 103 104 fw_data = (const __le32 *)(adev->gfx.imu_fw->data + 105 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 106 le32_to_cpu(hdr->imu_iram_ucode_size_bytes)); 107 fw_size = le32_to_cpu(hdr->imu_dram_ucode_size_bytes) / 4; 108 109 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, 0); 110 111 for (i = 0; i < fw_size; i++) 112 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_DATA, le32_to_cpup(fw_data++)); 113 114 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, adev->gfx.imu_fw_version); 115 116 return 0; 117 } 118 119 static void imu_v11_0_setup(struct amdgpu_device *adev) 120 { 121 int imu_reg_val; 122 123 //enable IMU debug mode 124 WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL0, 0xffffff); 125 WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL1, 0xffff); 126 127 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16); 128 imu_reg_val |= 0x1; 129 WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16, imu_reg_val); 130 131 //disble imu Rtavfs, SmsRepair, DfllBTC, and ClkB 132 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10); 133 imu_reg_val |= 0x10007; 134 WREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10, imu_reg_val); 135 } 136 137 static int imu_v11_0_start(struct amdgpu_device *adev) 138 { 139 int imu_reg_val, i; 140 141 //Start IMU by set GFX_IMU_CORE_CTRL.CRESET = 0 142 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL); 143 imu_reg_val &= 0xfffffffe; 144 WREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL, imu_reg_val); 145 146 for (i = 0; i < adev->usec_timeout; i++) { 147 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL); 148 if ((imu_reg_val & 0x1f) == 0x1f) 149 break; 150 udelay(1); 151 } 152 153 if (i >= adev->usec_timeout) { 154 dev_err(adev->dev, "init imu: IMU start timeout\n"); 155 return -ETIMEDOUT; 156 } 157 158 return 0; 159 } 160 161 static const struct imu_rlc_ram_golden imu_rlc_ram_golden_11[] = 162 { 163 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_IO_RD_COMBINE_FLUSH, 0x00055555, 0xe0000000), 164 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_IO_WR_COMBINE_FLUSH, 0x00055555, 0xe0000000), 165 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_DRAM_COMBINE_FLUSH, 0x00555555, 0xe0000000), 166 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_MISC2, 0x00001ffe, 0xe0000000), 167 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_CREDITS , 0x003f3fff, 0xe0000000), 168 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_TAG_RESERVE1, 0x00000000, 0xe0000000), 169 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCC_RESERVE0, 0x00041000, 0xe0000000), 170 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCC_RESERVE1, 0x00000000, 0xe0000000), 171 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCD_RESERVE0, 0x00040000, 0xe0000000), 172 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCD_RESERVE1, 0x00000000, 0xe0000000), 173 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_MISC, 0x00000017, 0xe0000000), 174 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_ENABLE, 0x00000001, 0xe0000000), 175 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_CREDITS , 0x003f3fbf, 0xe0000000), 176 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_TAG_RESERVE0, 0x10201000, 0xe0000000), 177 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_TAG_RESERVE1, 0x00000080, 0xe0000000), 178 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_VCC_RESERVE0, 0x1d041040, 0xe0000000), 179 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_VCC_RESERVE1, 0x80000000, 0xe0000000), 180 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_IO_PRIORITY, 0x88888888, 0xe0000000), 181 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_MAM_CTRL, 0x0000d800, 0xe0000000), 182 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_ARB_FINAL, 0x000003f7, 0xe0000000), 183 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_SDP_ENABLE, 0x00000001, 0xe0000000), 184 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2, 0x00020000, 0xe0000000), 185 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_APT_CNTL, 0x0000000c, 0xe0000000), 186 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0x000fffff, 0xe0000000), 187 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCEA_MISC, 0x0c48bff0, 0xe0000000), 188 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_SA_UNIT_DISABLE, 0x00fffc01, 0xe0000000), 189 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_PRIM_CONFIG, 0x000fffe1, 0xe0000000), 190 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_RB_BACKEND_DISABLE, 0x0fffff01, 0xe0000000), 191 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG, 0xfffe0001, 0xe0000000), 192 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, 0x00000500, 0xe0000000), 193 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x00000001, 0xe0000000), 194 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0x00000000, 0xe0000000), 195 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_START, 0x00000000, 0xe0000000), 196 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_END, 0x000fffff, 0xe0000000), 197 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT0_CNTL, 0x00000000, 0xe0000000), 198 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT1_CNTL, 0x00000000, 0xe0000000), 199 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_NB_TOP_OF_DRAM_SLOT1, 0xff800000, 0xe0000000), 200 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_NB_LOWER_TOP_OF_DRAM2, 0x00000001, 0xe0000000), 201 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_NB_UPPER_TOP_OF_DRAM2, 0x00000fff, 0xe0000000), 202 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, 0x00001ffc, 0xe0000000), 203 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, 0x00000501, 0xe0000000), 204 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL, 0x00080603, 0xe0000000), 205 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL2, 0x00000003, 0xe0000000), 206 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL3, 0x00100003, 0xe0000000), 207 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL5, 0x00003fe0, 0xe0000000), 208 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT0_CNTL, 0x00000001, 0xe0000000), 209 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES, 0x00000c00, 0xe0000000), 210 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT1_CNTL, 0x00000001, 0xe0000000), 211 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES, 0x00000c00, 0xe0000000), 212 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0x00000545, 0xe0000000), 213 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_0, 0x13455431, 0xe0000000), 214 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_1, 0x13455431, 0xe0000000), 215 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_2, 0x76027602, 0xe0000000), 216 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_3, 0x76207620, 0xe0000000), 217 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0x00000345, 0xe0000000), 218 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCUTCL2_HARVEST_BYPASS_GROUPS, 0x0000003e, 0xe0000000), 219 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_FB_LOCATION_BASE, 0x00006000, 0xe0000000), 220 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_FB_LOCATION_TOP, 0x000061ff, 0xe0000000), 221 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_APT_CNTL, 0x0000000c, 0xe0000000), 222 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_BASE, 0x00000000, 0xe0000000), 223 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_BOT, 0x00000002, 0xe0000000), 224 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_TOP, 0x00000000, 0xe0000000), 225 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2, 0x00020000, 0xe0000000), 226 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA0_UCODE_SELFLOAD_CONTROL, 0x00000210, 0), 227 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA1_UCODE_SELFLOAD_CONTROL, 0x00000210, 0), 228 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPC_PSP_DEBUG, CPC_PSP_DEBUG__GPA_OVERRIDE_MASK, 0), 229 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPG_PSP_DEBUG, CPG_PSP_DEBUG__GPA_OVERRIDE_MASK, 0) 230 }; 231 232 void program_imu_rlc_ram(struct amdgpu_device *adev, 233 const struct imu_rlc_ram_golden *regs, 234 const u32 array_size) 235 { 236 const struct imu_rlc_ram_golden *entry; 237 u32 reg, data; 238 int i; 239 240 for (i = 0; i < array_size; ++i) { 241 entry = ®s[i]; 242 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 243 reg |= entry->addr_mask; 244 245 data = entry->data; 246 if (entry->reg == regGCMC_VM_AGP_BASE) 247 data = 0x00ffffff; 248 else if (entry->reg == regGCMC_VM_AGP_TOP) 249 data = 0x0; 250 else if (entry->reg == regGCMC_VM_FB_LOCATION_BASE) 251 data = adev->gmc.vram_start >> 24; 252 else if (entry->reg == regGCMC_VM_FB_LOCATION_TOP) 253 data = adev->gmc.vram_end >> 24; 254 255 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, 0); 256 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, reg); 257 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, data); 258 } 259 //Indicate the latest entry 260 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, 0); 261 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, 0); 262 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, 0); 263 } 264 265 static void imu_v11_0_program_rlc_ram(struct amdgpu_device *adev) 266 { 267 u32 reg_data; 268 269 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX, 0x2); 270 271 program_imu_rlc_ram(adev, 272 imu_rlc_ram_golden_11, 273 (const u32)ARRAY_SIZE(imu_rlc_ram_golden_11)); 274 275 //Indicate the contents of the RAM are valid 276 reg_data = RREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX); 277 reg_data |= GFX_IMU_RLC_RAM_INDEX__RAM_VALID_MASK; 278 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX, reg_data); 279 } 280 281 const struct amdgpu_imu_funcs gfx_v11_0_imu_funcs = { 282 .init_microcode = imu_v11_0_init_microcode, 283 .load_microcode = imu_v11_0_load_microcode, 284 .setup_imu = imu_v11_0_setup, 285 .start_imu = imu_v11_0_start, 286 .program_rlc_ram = imu_v11_0_program_rlc_ram, 287 }; 288