1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_atombios.h" 25 #include "hdp_v6_0.h" 26 27 #include "hdp/hdp_6_0_0_offset.h" 28 #include "hdp/hdp_6_0_0_sh_mask.h" 29 #include <uapi/linux/kfd_ioctl.h> 30 31 static void hdp_v6_0_flush_hdp(struct amdgpu_device *adev, 32 struct amdgpu_ring *ring) 33 { 34 if (!ring || !ring->funcs->emit_wreg) 35 WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 36 else 37 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 38 } 39 40 static void hdp_v6_0_update_clock_gating(struct amdgpu_device *adev, 41 bool enable) 42 { 43 uint32_t hdp_clk_cntl; 44 45 if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 46 return; 47 48 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); 49 50 if (enable) { 51 hdp_clk_cntl &= 52 ~(uint32_t) 53 (HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK | 54 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 55 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 56 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 57 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 58 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK); 59 } else { 60 hdp_clk_cntl |= HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK | 61 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 62 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 63 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 64 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 65 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK; 66 } 67 68 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); 69 } 70 71 static void hdp_v6_0_get_clockgating_state(struct amdgpu_device *adev, 72 u64 *flags) 73 { 74 uint32_t tmp; 75 76 /* AMD_CG_SUPPORT_HDP_MGCG */ 77 tmp = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); 78 if (!(tmp & (HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK | 79 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 80 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 81 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 82 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 83 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK))) 84 *flags |= AMD_CG_SUPPORT_HDP_MGCG; 85 86 /* AMD_CG_SUPPORT_HDP_LS/DS/SD */ 87 tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); 88 if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK) 89 *flags |= AMD_CG_SUPPORT_HDP_LS; 90 else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK) 91 *flags |= AMD_CG_SUPPORT_HDP_DS; 92 else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK) 93 *flags |= AMD_CG_SUPPORT_HDP_SD; 94 } 95 96 const struct amdgpu_hdp_funcs hdp_v6_0_funcs = { 97 .flush_hdp = hdp_v6_0_flush_hdp, 98 .update_clock_gating = hdp_v6_0_update_clock_gating, 99 .get_clock_gating_state = hdp_v6_0_get_clockgating_state, 100 }; 101