1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_atombios.h" 25 #include "hdp_v4_0.h" 26 #include "amdgpu_ras.h" 27 28 #include "hdp/hdp_4_0_offset.h" 29 #include "hdp/hdp_4_0_sh_mask.h" 30 #include <uapi/linux/kfd_ioctl.h> 31 32 /* for Vega20 register name change */ 33 #define mmHDP_MEM_POWER_CTRL 0x00d4 34 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L 35 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L 36 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L 37 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L 38 #define mmHDP_MEM_POWER_CTRL_BASE_IDX 0 39 40 static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev, 41 struct amdgpu_ring *ring) 42 { 43 if (!ring || !ring->funcs->emit_wreg) 44 WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 45 else 46 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 47 } 48 49 static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev, 50 struct amdgpu_ring *ring) 51 { 52 if (adev->asic_type == CHIP_ALDEBARAN) 53 return; 54 55 if (!ring || !ring->funcs->emit_wreg) 56 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 57 else 58 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 59 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 60 } 61 62 static void hdp_v4_0_query_ras_error_count(struct amdgpu_device *adev, 63 void *ras_error_status) 64 { 65 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 66 67 err_data->ue_count = 0; 68 err_data->ce_count = 0; 69 70 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP)) 71 return; 72 73 /* HDP SRAM errors are uncorrectable ones (i.e. fatal errors) */ 74 err_data->ue_count += RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT); 75 }; 76 77 static void hdp_v4_0_reset_ras_error_count(struct amdgpu_device *adev) 78 { 79 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP)) 80 return; 81 82 if (adev->asic_type >= CHIP_ALDEBARAN) 83 WREG32_SOC15(HDP, 0, mmHDP_EDC_CNT, 0); 84 else 85 /*read back hdp ras counter to reset it to 0 */ 86 RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT); 87 } 88 89 static void hdp_v4_0_update_clock_gating(struct amdgpu_device *adev, 90 bool enable) 91 { 92 uint32_t def, data; 93 94 if (adev->asic_type == CHIP_VEGA10 || 95 adev->asic_type == CHIP_VEGA12 || 96 adev->asic_type == CHIP_RAVEN) { 97 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); 98 99 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 100 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK; 101 else 102 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK; 103 104 if (def != data) 105 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data); 106 } else { 107 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL)); 108 109 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 110 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK | 111 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK | 112 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK | 113 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK; 114 else 115 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK | 116 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK | 117 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK | 118 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK); 119 120 if (def != data) 121 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data); 122 } 123 } 124 125 static void hdp_v4_0_get_clockgating_state(struct amdgpu_device *adev, 126 u32 *flags) 127 { 128 int data; 129 130 /* AMD_CG_SUPPORT_HDP_LS */ 131 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); 132 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK) 133 *flags |= AMD_CG_SUPPORT_HDP_LS; 134 } 135 136 static void hdp_v4_0_init_registers(struct amdgpu_device *adev) 137 { 138 switch (adev->asic_type) { 139 case CHIP_ARCTURUS: 140 WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1); 141 break; 142 default: 143 break; 144 } 145 146 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1); 147 148 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); 149 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40)); 150 } 151 152 const struct amdgpu_hdp_ras_funcs hdp_v4_0_ras_funcs = { 153 .ras_late_init = amdgpu_hdp_ras_late_init, 154 .ras_fini = amdgpu_hdp_ras_fini, 155 .query_ras_error_count = hdp_v4_0_query_ras_error_count, 156 .reset_ras_error_count = hdp_v4_0_reset_ras_error_count, 157 }; 158 159 const struct amdgpu_hdp_funcs hdp_v4_0_funcs = { 160 .flush_hdp = hdp_v4_0_flush_hdp, 161 .invalidate_hdp = hdp_v4_0_invalidate_hdp, 162 .update_clock_gating = hdp_v4_0_update_clock_gating, 163 .get_clock_gating_state = hdp_v4_0_get_clockgating_state, 164 .init_registers = hdp_v4_0_init_registers, 165 }; 166