1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_atombios.h" 25 #include "hdp_v4_0.h" 26 #include "amdgpu_ras.h" 27 28 #include "hdp/hdp_4_0_offset.h" 29 #include "hdp/hdp_4_0_sh_mask.h" 30 #include <uapi/linux/kfd_ioctl.h> 31 32 /* for Vega20 register name change */ 33 #define mmHDP_MEM_POWER_CTRL 0x00d4 34 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L 35 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L 36 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L 37 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L 38 #define mmHDP_MEM_POWER_CTRL_BASE_IDX 0 39 40 static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev, 41 struct amdgpu_ring *ring) 42 { 43 if (!ring || !ring->funcs->emit_wreg) 44 WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 45 else 46 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 47 } 48 49 static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev, 50 struct amdgpu_ring *ring) 51 { 52 if (!ring || !ring->funcs->emit_wreg) 53 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 54 else 55 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 56 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 57 } 58 59 static void hdp_v4_0_reset_ras_error_count(struct amdgpu_device *adev) 60 { 61 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP)) 62 return; 63 /*read back hdp ras counter to reset it to 0 */ 64 RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT); 65 } 66 67 static void hdp_v4_0_update_clock_gating(struct amdgpu_device *adev, 68 bool enable) 69 { 70 uint32_t def, data; 71 72 if (adev->asic_type == CHIP_VEGA10 || 73 adev->asic_type == CHIP_VEGA12 || 74 adev->asic_type == CHIP_RAVEN) { 75 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); 76 77 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 78 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK; 79 else 80 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK; 81 82 if (def != data) 83 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data); 84 } else { 85 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL)); 86 87 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 88 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK | 89 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK | 90 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK | 91 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK; 92 else 93 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK | 94 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK | 95 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK | 96 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK); 97 98 if (def != data) 99 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data); 100 } 101 } 102 103 static void hdp_v4_0_get_clockgating_state(struct amdgpu_device *adev, 104 u32 *flags) 105 { 106 int data; 107 108 /* AMD_CG_SUPPORT_HDP_LS */ 109 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); 110 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK) 111 *flags |= AMD_CG_SUPPORT_HDP_LS; 112 } 113 114 static void hdp_v4_0_init_registers(struct amdgpu_device *adev) 115 { 116 switch (adev->asic_type) { 117 case CHIP_ARCTURUS: 118 WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1); 119 break; 120 default: 121 break; 122 } 123 124 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1); 125 126 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); 127 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40)); 128 } 129 130 const struct amdgpu_hdp_funcs hdp_v4_0_funcs = { 131 .flush_hdp = hdp_v4_0_flush_hdp, 132 .invalidate_hdp = hdp_v4_0_invalidate_hdp, 133 .reset_ras_error_count = hdp_v4_0_reset_ras_error_count, 134 .update_clock_gating = hdp_v4_0_update_clock_gating, 135 .get_clock_gating_state = hdp_v4_0_get_clockgating_state, 136 .init_registers = hdp_v4_0_init_registers, 137 }; 138