1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <drm/drm_cache.h> 25 #include "amdgpu.h" 26 #include "gmc_v9_0.h" 27 #include "amdgpu_atomfirmware.h" 28 #include "amdgpu_gem.h" 29 30 #include "hdp/hdp_4_0_offset.h" 31 #include "hdp/hdp_4_0_sh_mask.h" 32 #include "gc/gc_9_0_sh_mask.h" 33 #include "dce/dce_12_0_offset.h" 34 #include "dce/dce_12_0_sh_mask.h" 35 #include "vega10_enum.h" 36 #include "mmhub/mmhub_1_0_offset.h" 37 #include "athub/athub_1_0_offset.h" 38 #include "oss/osssys_4_0_offset.h" 39 40 #include "soc15.h" 41 #include "soc15_common.h" 42 #include "umc/umc_6_0_sh_mask.h" 43 44 #include "gfxhub_v1_0.h" 45 #include "mmhub_v1_0.h" 46 #include "gfxhub_v1_1.h" 47 48 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 49 50 #include "amdgpu_ras.h" 51 52 /* add these here since we already include dce12 headers and these are for DCN */ 53 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 54 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 55 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 56 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 57 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL 58 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L 59 60 /* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/ 61 #define AMDGPU_NUM_OF_VMIDS 8 62 63 static const u32 golden_settings_vega10_hdp[] = 64 { 65 0xf64, 0x0fffffff, 0x00000000, 66 0xf65, 0x0fffffff, 0x00000000, 67 0xf66, 0x0fffffff, 0x00000000, 68 0xf67, 0x0fffffff, 0x00000000, 69 0xf68, 0x0fffffff, 0x00000000, 70 0xf6a, 0x0fffffff, 0x00000000, 71 0xf6b, 0x0fffffff, 0x00000000, 72 0xf6c, 0x0fffffff, 0x00000000, 73 0xf6d, 0x0fffffff, 0x00000000, 74 0xf6e, 0x0fffffff, 0x00000000, 75 }; 76 77 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = 78 { 79 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), 80 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) 81 }; 82 83 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = 84 { 85 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), 86 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) 87 }; 88 89 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { 90 (0x000143c0 + 0x00000000), 91 (0x000143c0 + 0x00000800), 92 (0x000143c0 + 0x00001000), 93 (0x000143c0 + 0x00001800), 94 (0x000543c0 + 0x00000000), 95 (0x000543c0 + 0x00000800), 96 (0x000543c0 + 0x00001000), 97 (0x000543c0 + 0x00001800), 98 (0x000943c0 + 0x00000000), 99 (0x000943c0 + 0x00000800), 100 (0x000943c0 + 0x00001000), 101 (0x000943c0 + 0x00001800), 102 (0x000d43c0 + 0x00000000), 103 (0x000d43c0 + 0x00000800), 104 (0x000d43c0 + 0x00001000), 105 (0x000d43c0 + 0x00001800), 106 (0x001143c0 + 0x00000000), 107 (0x001143c0 + 0x00000800), 108 (0x001143c0 + 0x00001000), 109 (0x001143c0 + 0x00001800), 110 (0x001543c0 + 0x00000000), 111 (0x001543c0 + 0x00000800), 112 (0x001543c0 + 0x00001000), 113 (0x001543c0 + 0x00001800), 114 (0x001943c0 + 0x00000000), 115 (0x001943c0 + 0x00000800), 116 (0x001943c0 + 0x00001000), 117 (0x001943c0 + 0x00001800), 118 (0x001d43c0 + 0x00000000), 119 (0x001d43c0 + 0x00000800), 120 (0x001d43c0 + 0x00001000), 121 (0x001d43c0 + 0x00001800), 122 }; 123 124 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { 125 (0x000143e0 + 0x00000000), 126 (0x000143e0 + 0x00000800), 127 (0x000143e0 + 0x00001000), 128 (0x000143e0 + 0x00001800), 129 (0x000543e0 + 0x00000000), 130 (0x000543e0 + 0x00000800), 131 (0x000543e0 + 0x00001000), 132 (0x000543e0 + 0x00001800), 133 (0x000943e0 + 0x00000000), 134 (0x000943e0 + 0x00000800), 135 (0x000943e0 + 0x00001000), 136 (0x000943e0 + 0x00001800), 137 (0x000d43e0 + 0x00000000), 138 (0x000d43e0 + 0x00000800), 139 (0x000d43e0 + 0x00001000), 140 (0x000d43e0 + 0x00001800), 141 (0x001143e0 + 0x00000000), 142 (0x001143e0 + 0x00000800), 143 (0x001143e0 + 0x00001000), 144 (0x001143e0 + 0x00001800), 145 (0x001543e0 + 0x00000000), 146 (0x001543e0 + 0x00000800), 147 (0x001543e0 + 0x00001000), 148 (0x001543e0 + 0x00001800), 149 (0x001943e0 + 0x00000000), 150 (0x001943e0 + 0x00000800), 151 (0x001943e0 + 0x00001000), 152 (0x001943e0 + 0x00001800), 153 (0x001d43e0 + 0x00000000), 154 (0x001d43e0 + 0x00000800), 155 (0x001d43e0 + 0x00001000), 156 (0x001d43e0 + 0x00001800), 157 }; 158 159 static const uint32_t ecc_umc_mcumc_status_addrs[] = { 160 (0x000143c2 + 0x00000000), 161 (0x000143c2 + 0x00000800), 162 (0x000143c2 + 0x00001000), 163 (0x000143c2 + 0x00001800), 164 (0x000543c2 + 0x00000000), 165 (0x000543c2 + 0x00000800), 166 (0x000543c2 + 0x00001000), 167 (0x000543c2 + 0x00001800), 168 (0x000943c2 + 0x00000000), 169 (0x000943c2 + 0x00000800), 170 (0x000943c2 + 0x00001000), 171 (0x000943c2 + 0x00001800), 172 (0x000d43c2 + 0x00000000), 173 (0x000d43c2 + 0x00000800), 174 (0x000d43c2 + 0x00001000), 175 (0x000d43c2 + 0x00001800), 176 (0x001143c2 + 0x00000000), 177 (0x001143c2 + 0x00000800), 178 (0x001143c2 + 0x00001000), 179 (0x001143c2 + 0x00001800), 180 (0x001543c2 + 0x00000000), 181 (0x001543c2 + 0x00000800), 182 (0x001543c2 + 0x00001000), 183 (0x001543c2 + 0x00001800), 184 (0x001943c2 + 0x00000000), 185 (0x001943c2 + 0x00000800), 186 (0x001943c2 + 0x00001000), 187 (0x001943c2 + 0x00001800), 188 (0x001d43c2 + 0x00000000), 189 (0x001d43c2 + 0x00000800), 190 (0x001d43c2 + 0x00001000), 191 (0x001d43c2 + 0x00001800), 192 }; 193 194 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, 195 struct amdgpu_irq_src *src, 196 unsigned type, 197 enum amdgpu_interrupt_state state) 198 { 199 u32 bits, i, tmp, reg; 200 201 bits = 0x7f; 202 203 switch (state) { 204 case AMDGPU_IRQ_STATE_DISABLE: 205 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 206 reg = ecc_umc_mcumc_ctrl_addrs[i]; 207 tmp = RREG32(reg); 208 tmp &= ~bits; 209 WREG32(reg, tmp); 210 } 211 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 212 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 213 tmp = RREG32(reg); 214 tmp &= ~bits; 215 WREG32(reg, tmp); 216 } 217 break; 218 case AMDGPU_IRQ_STATE_ENABLE: 219 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 220 reg = ecc_umc_mcumc_ctrl_addrs[i]; 221 tmp = RREG32(reg); 222 tmp |= bits; 223 WREG32(reg, tmp); 224 } 225 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 226 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 227 tmp = RREG32(reg); 228 tmp |= bits; 229 WREG32(reg, tmp); 230 } 231 break; 232 default: 233 break; 234 } 235 236 return 0; 237 } 238 239 static int gmc_v9_0_process_ras_data_cb(struct amdgpu_device *adev, 240 struct amdgpu_iv_entry *entry) 241 { 242 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); 243 amdgpu_ras_reset_gpu(adev, 0); 244 return AMDGPU_RAS_UE; 245 } 246 247 static int gmc_v9_0_process_ecc_irq(struct amdgpu_device *adev, 248 struct amdgpu_irq_src *source, 249 struct amdgpu_iv_entry *entry) 250 { 251 struct ras_common_if *ras_if = adev->gmc.ras_if; 252 struct ras_dispatch_if ih_data = { 253 .entry = entry, 254 }; 255 256 if (!ras_if) 257 return 0; 258 259 ih_data.head = *ras_if; 260 261 amdgpu_ras_interrupt_dispatch(adev, &ih_data); 262 return 0; 263 } 264 265 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 266 struct amdgpu_irq_src *src, 267 unsigned type, 268 enum amdgpu_interrupt_state state) 269 { 270 struct amdgpu_vmhub *hub; 271 u32 tmp, reg, bits, i, j; 272 273 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 274 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 275 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 276 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 277 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 278 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 279 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 280 281 switch (state) { 282 case AMDGPU_IRQ_STATE_DISABLE: 283 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) { 284 hub = &adev->vmhub[j]; 285 for (i = 0; i < 16; i++) { 286 reg = hub->vm_context0_cntl + i; 287 tmp = RREG32(reg); 288 tmp &= ~bits; 289 WREG32(reg, tmp); 290 } 291 } 292 break; 293 case AMDGPU_IRQ_STATE_ENABLE: 294 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) { 295 hub = &adev->vmhub[j]; 296 for (i = 0; i < 16; i++) { 297 reg = hub->vm_context0_cntl + i; 298 tmp = RREG32(reg); 299 tmp |= bits; 300 WREG32(reg, tmp); 301 } 302 } 303 default: 304 break; 305 } 306 307 return 0; 308 } 309 310 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 311 struct amdgpu_irq_src *source, 312 struct amdgpu_iv_entry *entry) 313 { 314 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; 315 bool retry_fault = !!(entry->src_data[1] & 0x80); 316 uint32_t status = 0; 317 u64 addr; 318 319 addr = (u64)entry->src_data[0] << 12; 320 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 321 322 if (retry_fault && amdgpu_gmc_filter_faults(adev, addr, entry->pasid, 323 entry->timestamp)) 324 return 1; /* This also prevents sending it to KFD */ 325 326 /* If it's the first fault for this address, process it normally */ 327 if (!amdgpu_sriov_vf(adev)) { 328 status = RREG32(hub->vm_l2_pro_fault_status); 329 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 330 } 331 332 if (printk_ratelimit()) { 333 struct amdgpu_task_info task_info; 334 335 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 336 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 337 338 dev_err(adev->dev, 339 "[%s] %s page fault (src_id:%u ring:%u vmid:%u " 340 "pasid:%u, for process %s pid %d thread %s pid %d)\n", 341 entry->vmid_src ? "mmhub" : "gfxhub", 342 retry_fault ? "retry" : "no-retry", 343 entry->src_id, entry->ring_id, entry->vmid, 344 entry->pasid, task_info.process_name, task_info.tgid, 345 task_info.task_name, task_info.pid); 346 dev_err(adev->dev, " in page starting at address 0x%016llx from %d\n", 347 addr, entry->client_id); 348 if (!amdgpu_sriov_vf(adev)) 349 dev_err(adev->dev, 350 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 351 status); 352 } 353 354 return 0; 355 } 356 357 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 358 .set = gmc_v9_0_vm_fault_interrupt_state, 359 .process = gmc_v9_0_process_interrupt, 360 }; 361 362 363 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { 364 .set = gmc_v9_0_ecc_interrupt_state, 365 .process = gmc_v9_0_process_ecc_irq, 366 }; 367 368 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 369 { 370 adev->gmc.vm_fault.num_types = 1; 371 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 372 373 adev->gmc.ecc_irq.num_types = 1; 374 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; 375 } 376 377 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, 378 uint32_t flush_type) 379 { 380 u32 req = 0; 381 382 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 383 PER_VMID_INVALIDATE_REQ, 1 << vmid); 384 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 385 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 386 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 387 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 388 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 389 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 390 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 391 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 392 393 return req; 394 } 395 396 /* 397 * GART 398 * VMID 0 is the physical GPU addresses as used by the kernel. 399 * VMIDs 1-15 are used for userspace clients and are handled 400 * by the amdgpu vm/hsa code. 401 */ 402 403 /** 404 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type 405 * 406 * @adev: amdgpu_device pointer 407 * @vmid: vm instance to flush 408 * @flush_type: the flush type 409 * 410 * Flush the TLB for the requested page table using certain type. 411 */ 412 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, 413 uint32_t vmid, uint32_t flush_type) 414 { 415 const unsigned eng = 17; 416 unsigned i, j; 417 418 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { 419 struct amdgpu_vmhub *hub = &adev->vmhub[i]; 420 u32 tmp = gmc_v9_0_get_invalidate_req(vmid, flush_type); 421 422 /* This is necessary for a HW workaround under SRIOV as well 423 * as GFXOFF under bare metal 424 */ 425 if (adev->gfx.kiq.ring.sched.ready && 426 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && 427 !adev->in_gpu_reset) { 428 uint32_t req = hub->vm_inv_eng0_req + eng; 429 uint32_t ack = hub->vm_inv_eng0_ack + eng; 430 431 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, tmp, 432 1 << vmid); 433 continue; 434 } 435 436 spin_lock(&adev->gmc.invalidate_lock); 437 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp); 438 for (j = 0; j < adev->usec_timeout; j++) { 439 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); 440 if (tmp & (1 << vmid)) 441 break; 442 udelay(1); 443 } 444 spin_unlock(&adev->gmc.invalidate_lock); 445 if (j < adev->usec_timeout) 446 continue; 447 448 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 449 } 450 } 451 452 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 453 unsigned vmid, uint64_t pd_addr) 454 { 455 struct amdgpu_device *adev = ring->adev; 456 struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub]; 457 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); 458 unsigned eng = ring->vm_inv_eng; 459 460 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid), 461 lower_32_bits(pd_addr)); 462 463 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid), 464 upper_32_bits(pd_addr)); 465 466 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng, 467 hub->vm_inv_eng0_ack + eng, 468 req, 1 << vmid); 469 470 return pd_addr; 471 } 472 473 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 474 unsigned pasid) 475 { 476 struct amdgpu_device *adev = ring->adev; 477 uint32_t reg; 478 479 if (ring->funcs->vmhub == AMDGPU_GFXHUB) 480 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 481 else 482 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 483 484 amdgpu_ring_emit_wreg(ring, reg, pasid); 485 } 486 487 /* 488 * PTE format on VEGA 10: 489 * 63:59 reserved 490 * 58:57 mtype 491 * 56 F 492 * 55 L 493 * 54 P 494 * 53 SW 495 * 52 T 496 * 50:48 reserved 497 * 47:12 4k physical page base address 498 * 11:7 fragment 499 * 6 write 500 * 5 read 501 * 4 exe 502 * 3 Z 503 * 2 snooped 504 * 1 system 505 * 0 valid 506 * 507 * PDE format on VEGA 10: 508 * 63:59 block fragment size 509 * 58:55 reserved 510 * 54 P 511 * 53:48 reserved 512 * 47:6 physical base address of PD or PTE 513 * 5:3 reserved 514 * 2 C 515 * 1 system 516 * 0 valid 517 */ 518 519 static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev, 520 uint32_t flags) 521 522 { 523 uint64_t pte_flag = 0; 524 525 if (flags & AMDGPU_VM_PAGE_EXECUTABLE) 526 pte_flag |= AMDGPU_PTE_EXECUTABLE; 527 if (flags & AMDGPU_VM_PAGE_READABLE) 528 pte_flag |= AMDGPU_PTE_READABLE; 529 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 530 pte_flag |= AMDGPU_PTE_WRITEABLE; 531 532 switch (flags & AMDGPU_VM_MTYPE_MASK) { 533 case AMDGPU_VM_MTYPE_DEFAULT: 534 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC); 535 break; 536 case AMDGPU_VM_MTYPE_NC: 537 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC); 538 break; 539 case AMDGPU_VM_MTYPE_WC: 540 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_WC); 541 break; 542 case AMDGPU_VM_MTYPE_CC: 543 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_CC); 544 break; 545 case AMDGPU_VM_MTYPE_UC: 546 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_UC); 547 break; 548 default: 549 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC); 550 break; 551 } 552 553 if (flags & AMDGPU_VM_PAGE_PRT) 554 pte_flag |= AMDGPU_PTE_PRT; 555 556 return pte_flag; 557 } 558 559 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, 560 uint64_t *addr, uint64_t *flags) 561 { 562 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 563 *addr = adev->vm_manager.vram_base_offset + *addr - 564 adev->gmc.vram_start; 565 BUG_ON(*addr & 0xFFFF00000000003FULL); 566 567 if (!adev->gmc.translate_further) 568 return; 569 570 if (level == AMDGPU_VM_PDB1) { 571 /* Set the block fragment size */ 572 if (!(*flags & AMDGPU_PDE_PTE)) 573 *flags |= AMDGPU_PDE_BFS(0x9); 574 575 } else if (level == AMDGPU_VM_PDB0) { 576 if (*flags & AMDGPU_PDE_PTE) 577 *flags &= ~AMDGPU_PDE_PTE; 578 else 579 *flags |= AMDGPU_PTE_TF; 580 } 581 } 582 583 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { 584 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, 585 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, 586 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, 587 .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags, 588 .get_vm_pde = gmc_v9_0_get_vm_pde 589 }; 590 591 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) 592 { 593 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; 594 } 595 596 static int gmc_v9_0_early_init(void *handle) 597 { 598 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 599 600 gmc_v9_0_set_gmc_funcs(adev); 601 gmc_v9_0_set_irq_funcs(adev); 602 603 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 604 adev->gmc.shared_aperture_end = 605 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 606 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 607 adev->gmc.private_aperture_end = 608 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 609 610 return 0; 611 } 612 613 static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev) 614 { 615 616 /* 617 * TODO: 618 * Currently there is a bug where some memory client outside 619 * of the driver writes to first 8M of VRAM on S3 resume, 620 * this overrides GART which by default gets placed in first 8M and 621 * causes VM_FAULTS once GTT is accessed. 622 * Keep the stolen memory reservation until the while this is not solved. 623 * Also check code in gmc_v9_0_get_vbios_fb_size and gmc_v9_0_late_init 624 */ 625 switch (adev->asic_type) { 626 case CHIP_VEGA10: 627 return true; 628 case CHIP_RAVEN: 629 return (adev->pdev->device == 0x15d8); 630 case CHIP_VEGA12: 631 case CHIP_VEGA20: 632 default: 633 return false; 634 } 635 } 636 637 static int gmc_v9_0_allocate_vm_inv_eng(struct amdgpu_device *adev) 638 { 639 struct amdgpu_ring *ring; 640 unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] = 641 {GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP}; 642 unsigned i; 643 unsigned vmhub, inv_eng; 644 645 for (i = 0; i < adev->num_rings; ++i) { 646 ring = adev->rings[i]; 647 vmhub = ring->funcs->vmhub; 648 649 inv_eng = ffs(vm_inv_engs[vmhub]); 650 if (!inv_eng) { 651 dev_err(adev->dev, "no VM inv eng for ring %s\n", 652 ring->name); 653 return -EINVAL; 654 } 655 656 ring->vm_inv_eng = inv_eng - 1; 657 vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng); 658 659 dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n", 660 ring->name, ring->vm_inv_eng, ring->funcs->vmhub); 661 } 662 663 return 0; 664 } 665 666 static int gmc_v9_0_ecc_late_init(void *handle) 667 { 668 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 669 struct ras_common_if **ras_if = &adev->gmc.ras_if; 670 struct ras_ih_if ih_info = { 671 .cb = gmc_v9_0_process_ras_data_cb, 672 }; 673 struct ras_fs_if fs_info = { 674 .sysfs_name = "umc_err_count", 675 .debugfs_name = "umc_err_inject", 676 }; 677 struct ras_common_if ras_block = { 678 .block = AMDGPU_RAS_BLOCK__UMC, 679 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 680 .sub_block_index = 0, 681 .name = "umc", 682 }; 683 int r; 684 685 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) { 686 amdgpu_ras_feature_enable_on_boot(adev, &ras_block, 0); 687 return 0; 688 } 689 /* handle resume path. */ 690 if (*ras_if) { 691 /* resend ras TA enable cmd during resume. 692 * prepare to handle failure. 693 */ 694 ih_info.head = **ras_if; 695 r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1); 696 if (r) { 697 if (r == -EAGAIN) { 698 /* request a gpu reset. will run again. */ 699 amdgpu_ras_request_reset_on_boot(adev, 700 AMDGPU_RAS_BLOCK__UMC); 701 return 0; 702 } 703 /* fail to enable ras, cleanup all. */ 704 goto irq; 705 } 706 /* enable successfully. continue. */ 707 goto resume; 708 } 709 710 *ras_if = kmalloc(sizeof(**ras_if), GFP_KERNEL); 711 if (!*ras_if) 712 return -ENOMEM; 713 714 **ras_if = ras_block; 715 716 r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1); 717 if (r) { 718 if (r == -EAGAIN) { 719 amdgpu_ras_request_reset_on_boot(adev, 720 AMDGPU_RAS_BLOCK__UMC); 721 r = 0; 722 } 723 goto feature; 724 } 725 726 ih_info.head = **ras_if; 727 fs_info.head = **ras_if; 728 729 r = amdgpu_ras_interrupt_add_handler(adev, &ih_info); 730 if (r) 731 goto interrupt; 732 733 amdgpu_ras_debugfs_create(adev, &fs_info); 734 735 r = amdgpu_ras_sysfs_create(adev, &fs_info); 736 if (r) 737 goto sysfs; 738 resume: 739 r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0); 740 if (r) 741 goto irq; 742 743 return 0; 744 irq: 745 amdgpu_ras_sysfs_remove(adev, *ras_if); 746 sysfs: 747 amdgpu_ras_debugfs_remove(adev, *ras_if); 748 amdgpu_ras_interrupt_remove_handler(adev, &ih_info); 749 interrupt: 750 amdgpu_ras_feature_enable(adev, *ras_if, 0); 751 feature: 752 kfree(*ras_if); 753 *ras_if = NULL; 754 return r; 755 } 756 757 758 static int gmc_v9_0_late_init(void *handle) 759 { 760 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 761 bool r; 762 763 if (!gmc_v9_0_keep_stolen_memory(adev)) 764 amdgpu_bo_late_init(adev); 765 766 r = gmc_v9_0_allocate_vm_inv_eng(adev); 767 if (r) 768 return r; 769 /* Check if ecc is available */ 770 if (!amdgpu_sriov_vf(adev)) { 771 switch (adev->asic_type) { 772 case CHIP_VEGA10: 773 case CHIP_VEGA20: 774 r = amdgpu_atomfirmware_mem_ecc_supported(adev); 775 if (!r) { 776 DRM_INFO("ECC is not present.\n"); 777 if (adev->df_funcs->enable_ecc_force_par_wr_rmw) 778 adev->df_funcs->enable_ecc_force_par_wr_rmw(adev, false); 779 } else { 780 DRM_INFO("ECC is active.\n"); 781 } 782 783 r = amdgpu_atomfirmware_sram_ecc_supported(adev); 784 if (!r) { 785 DRM_INFO("SRAM ECC is not present.\n"); 786 } else { 787 DRM_INFO("SRAM ECC is active.\n"); 788 } 789 break; 790 default: 791 break; 792 } 793 } 794 795 r = gmc_v9_0_ecc_late_init(handle); 796 if (r) 797 return r; 798 799 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 800 } 801 802 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 803 struct amdgpu_gmc *mc) 804 { 805 u64 base = 0; 806 if (!amdgpu_sriov_vf(adev)) 807 base = mmhub_v1_0_get_fb_location(adev); 808 /* add the xgmi offset of the physical node */ 809 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 810 amdgpu_gmc_vram_location(adev, mc, base); 811 amdgpu_gmc_gart_location(adev, mc); 812 if (!amdgpu_sriov_vf(adev)) 813 amdgpu_gmc_agp_location(adev, mc); 814 /* base offset of vram pages */ 815 adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev); 816 817 /* XXX: add the xgmi offset of the physical node? */ 818 adev->vm_manager.vram_base_offset += 819 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 820 } 821 822 /** 823 * gmc_v9_0_mc_init - initialize the memory controller driver params 824 * 825 * @adev: amdgpu_device pointer 826 * 827 * Look up the amount of vram, vram width, and decide how to place 828 * vram and gart within the GPU's physical address space. 829 * Returns 0 for success. 830 */ 831 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 832 { 833 int chansize, numchan; 834 int r; 835 836 if (amdgpu_sriov_vf(adev)) { 837 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, 838 * and DF related registers is not readable, seems hardcord is the 839 * only way to set the correct vram_width 840 */ 841 adev->gmc.vram_width = 2048; 842 } else if (amdgpu_emu_mode != 1) { 843 adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev); 844 } 845 846 if (!adev->gmc.vram_width) { 847 /* hbm memory channel size */ 848 if (adev->flags & AMD_IS_APU) 849 chansize = 64; 850 else 851 chansize = 128; 852 853 numchan = adev->df_funcs->get_hbm_channel_number(adev); 854 adev->gmc.vram_width = numchan * chansize; 855 } 856 857 /* size in MB on si */ 858 adev->gmc.mc_vram_size = 859 adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL; 860 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 861 862 if (!(adev->flags & AMD_IS_APU)) { 863 r = amdgpu_device_resize_fb_bar(adev); 864 if (r) 865 return r; 866 } 867 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 868 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 869 870 #ifdef CONFIG_X86_64 871 if (adev->flags & AMD_IS_APU) { 872 adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev); 873 adev->gmc.aper_size = adev->gmc.real_vram_size; 874 } 875 #endif 876 /* In case the PCI BAR is larger than the actual amount of vram */ 877 adev->gmc.visible_vram_size = adev->gmc.aper_size; 878 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 879 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 880 881 /* set the gart size */ 882 if (amdgpu_gart_size == -1) { 883 switch (adev->asic_type) { 884 case CHIP_VEGA10: /* all engines support GPUVM */ 885 case CHIP_VEGA12: /* all engines support GPUVM */ 886 case CHIP_VEGA20: 887 default: 888 adev->gmc.gart_size = 512ULL << 20; 889 break; 890 case CHIP_RAVEN: /* DCE SG support */ 891 adev->gmc.gart_size = 1024ULL << 20; 892 break; 893 } 894 } else { 895 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 896 } 897 898 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); 899 900 return 0; 901 } 902 903 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 904 { 905 int r; 906 907 if (adev->gart.bo) { 908 WARN(1, "VEGA10 PCIE GART already initialized\n"); 909 return 0; 910 } 911 /* Initialize common gart structure */ 912 r = amdgpu_gart_init(adev); 913 if (r) 914 return r; 915 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 916 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE(MTYPE_UC) | 917 AMDGPU_PTE_EXECUTABLE; 918 return amdgpu_gart_table_vram_alloc(adev); 919 } 920 921 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 922 { 923 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 924 unsigned size; 925 926 /* 927 * TODO Remove once GART corruption is resolved 928 * Check related code in gmc_v9_0_sw_fini 929 * */ 930 if (gmc_v9_0_keep_stolen_memory(adev)) 931 return 9 * 1024 * 1024; 932 933 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 934 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */ 935 } else { 936 u32 viewport; 937 938 switch (adev->asic_type) { 939 case CHIP_RAVEN: 940 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 941 size = (REG_GET_FIELD(viewport, 942 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 943 REG_GET_FIELD(viewport, 944 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 945 4); 946 break; 947 case CHIP_VEGA10: 948 case CHIP_VEGA12: 949 case CHIP_VEGA20: 950 default: 951 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); 952 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 953 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * 954 4); 955 break; 956 } 957 } 958 /* return 0 if the pre-OS buffer uses up most of vram */ 959 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 960 return 0; 961 962 return size; 963 } 964 965 static int gmc_v9_0_sw_init(void *handle) 966 { 967 int r; 968 int dma_bits; 969 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 970 971 gfxhub_v1_0_init(adev); 972 mmhub_v1_0_init(adev); 973 974 spin_lock_init(&adev->gmc.invalidate_lock); 975 976 adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev); 977 switch (adev->asic_type) { 978 case CHIP_RAVEN: 979 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 980 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 981 } else { 982 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 983 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 984 adev->gmc.translate_further = 985 adev->vm_manager.num_level > 1; 986 } 987 break; 988 case CHIP_VEGA10: 989 case CHIP_VEGA12: 990 case CHIP_VEGA20: 991 /* 992 * To fulfill 4-level page support, 993 * vm size is 256TB (48bit), maximum size of Vega10, 994 * block size 512 (9bit) 995 */ 996 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */ 997 if (amdgpu_sriov_vf(adev)) 998 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47); 999 else 1000 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1001 break; 1002 default: 1003 break; 1004 } 1005 1006 /* This interrupt is VMC page fault.*/ 1007 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, 1008 &adev->gmc.vm_fault); 1009 if (r) 1010 return r; 1011 1012 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, 1013 &adev->gmc.vm_fault); 1014 1015 if (r) 1016 return r; 1017 1018 /* interrupt sent to DF. */ 1019 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 1020 &adev->gmc.ecc_irq); 1021 if (r) 1022 return r; 1023 1024 /* Set the internal MC address mask 1025 * This is the max address of the GPU's 1026 * internal address space. 1027 */ 1028 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 1029 1030 /* set DMA mask + need_dma32 flags. 1031 * PCIE - can handle 44-bits. 1032 * IGP - can handle 44-bits 1033 * PCI - dma32 for legacy pci gart, 44 bits on vega10 1034 */ 1035 adev->need_dma32 = false; 1036 dma_bits = adev->need_dma32 ? 32 : 44; 1037 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 1038 if (r) { 1039 adev->need_dma32 = true; 1040 dma_bits = 32; 1041 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 1042 } 1043 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 1044 if (r) { 1045 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); 1046 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n"); 1047 } 1048 adev->need_swiotlb = drm_need_swiotlb(dma_bits); 1049 1050 if (adev->gmc.xgmi.supported) { 1051 r = gfxhub_v1_1_get_xgmi_info(adev); 1052 if (r) 1053 return r; 1054 } 1055 1056 r = gmc_v9_0_mc_init(adev); 1057 if (r) 1058 return r; 1059 1060 adev->gmc.stolen_size = gmc_v9_0_get_vbios_fb_size(adev); 1061 1062 /* Memory manager */ 1063 r = amdgpu_bo_init(adev); 1064 if (r) 1065 return r; 1066 1067 r = gmc_v9_0_gart_init(adev); 1068 if (r) 1069 return r; 1070 1071 /* 1072 * number of VMs 1073 * VMID 0 is reserved for System 1074 * amdgpu graphics/compute will use VMIDs 1-7 1075 * amdkfd will use VMIDs 8-15 1076 */ 1077 adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS; 1078 adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS; 1079 1080 amdgpu_vm_manager_init(adev); 1081 1082 return 0; 1083 } 1084 1085 static int gmc_v9_0_sw_fini(void *handle) 1086 { 1087 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1088 1089 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) && 1090 adev->gmc.ras_if) { 1091 struct ras_common_if *ras_if = adev->gmc.ras_if; 1092 struct ras_ih_if ih_info = { 1093 .head = *ras_if, 1094 }; 1095 1096 /*remove fs first*/ 1097 amdgpu_ras_debugfs_remove(adev, ras_if); 1098 amdgpu_ras_sysfs_remove(adev, ras_if); 1099 /*remove the IH*/ 1100 amdgpu_ras_interrupt_remove_handler(adev, &ih_info); 1101 amdgpu_ras_feature_enable(adev, ras_if, 0); 1102 kfree(ras_if); 1103 } 1104 1105 amdgpu_gem_force_release(adev); 1106 amdgpu_vm_manager_fini(adev); 1107 1108 if (gmc_v9_0_keep_stolen_memory(adev)) 1109 amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL); 1110 1111 amdgpu_gart_table_vram_free(adev); 1112 amdgpu_bo_fini(adev); 1113 amdgpu_gart_fini(adev); 1114 1115 return 0; 1116 } 1117 1118 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 1119 { 1120 1121 switch (adev->asic_type) { 1122 case CHIP_VEGA10: 1123 if (amdgpu_virt_support_skip_setting(adev)) 1124 break; 1125 /* fall through */ 1126 case CHIP_VEGA20: 1127 soc15_program_register_sequence(adev, 1128 golden_settings_mmhub_1_0_0, 1129 ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 1130 soc15_program_register_sequence(adev, 1131 golden_settings_athub_1_0_0, 1132 ARRAY_SIZE(golden_settings_athub_1_0_0)); 1133 break; 1134 case CHIP_VEGA12: 1135 break; 1136 case CHIP_RAVEN: 1137 soc15_program_register_sequence(adev, 1138 golden_settings_athub_1_0_0, 1139 ARRAY_SIZE(golden_settings_athub_1_0_0)); 1140 break; 1141 default: 1142 break; 1143 } 1144 } 1145 1146 /** 1147 * gmc_v9_0_gart_enable - gart enable 1148 * 1149 * @adev: amdgpu_device pointer 1150 */ 1151 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 1152 { 1153 int r; 1154 bool value; 1155 u32 tmp; 1156 1157 amdgpu_device_program_register_sequence(adev, 1158 golden_settings_vega10_hdp, 1159 ARRAY_SIZE(golden_settings_vega10_hdp)); 1160 1161 if (adev->gart.bo == NULL) { 1162 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 1163 return -EINVAL; 1164 } 1165 r = amdgpu_gart_table_vram_pin(adev); 1166 if (r) 1167 return r; 1168 1169 switch (adev->asic_type) { 1170 case CHIP_RAVEN: 1171 mmhub_v1_0_update_power_gating(adev, true); 1172 break; 1173 default: 1174 break; 1175 } 1176 1177 r = gfxhub_v1_0_gart_enable(adev); 1178 if (r) 1179 return r; 1180 1181 r = mmhub_v1_0_gart_enable(adev); 1182 if (r) 1183 return r; 1184 1185 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1); 1186 1187 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL); 1188 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp); 1189 1190 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); 1191 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40)); 1192 1193 /* After HDP is initialized, flush HDP.*/ 1194 adev->nbio_funcs->hdp_flush(adev, NULL); 1195 1196 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 1197 value = false; 1198 else 1199 value = true; 1200 1201 gfxhub_v1_0_set_fault_enable_default(adev, value); 1202 mmhub_v1_0_set_fault_enable_default(adev, value); 1203 gmc_v9_0_flush_gpu_tlb(adev, 0, 0); 1204 1205 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1206 (unsigned)(adev->gmc.gart_size >> 20), 1207 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 1208 adev->gart.ready = true; 1209 return 0; 1210 } 1211 1212 static int gmc_v9_0_hw_init(void *handle) 1213 { 1214 int r; 1215 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1216 1217 /* The sequence of these two function calls matters.*/ 1218 gmc_v9_0_init_golden_registers(adev); 1219 1220 if (adev->mode_info.num_crtc) { 1221 /* Lockout access through VGA aperture*/ 1222 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 1223 1224 /* disable VGA render */ 1225 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 1226 } 1227 1228 r = gmc_v9_0_gart_enable(adev); 1229 1230 return r; 1231 } 1232 1233 /** 1234 * gmc_v9_0_gart_disable - gart disable 1235 * 1236 * @adev: amdgpu_device pointer 1237 * 1238 * This disables all VM page table. 1239 */ 1240 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 1241 { 1242 gfxhub_v1_0_gart_disable(adev); 1243 mmhub_v1_0_gart_disable(adev); 1244 amdgpu_gart_table_vram_unpin(adev); 1245 } 1246 1247 static int gmc_v9_0_hw_fini(void *handle) 1248 { 1249 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1250 1251 if (amdgpu_sriov_vf(adev)) { 1252 /* full access mode, so don't touch any GMC register */ 1253 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 1254 return 0; 1255 } 1256 1257 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 1258 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1259 gmc_v9_0_gart_disable(adev); 1260 1261 return 0; 1262 } 1263 1264 static int gmc_v9_0_suspend(void *handle) 1265 { 1266 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1267 1268 return gmc_v9_0_hw_fini(adev); 1269 } 1270 1271 static int gmc_v9_0_resume(void *handle) 1272 { 1273 int r; 1274 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1275 1276 r = gmc_v9_0_hw_init(adev); 1277 if (r) 1278 return r; 1279 1280 amdgpu_vmid_reset_all(adev); 1281 1282 return 0; 1283 } 1284 1285 static bool gmc_v9_0_is_idle(void *handle) 1286 { 1287 /* MC is always ready in GMC v9.*/ 1288 return true; 1289 } 1290 1291 static int gmc_v9_0_wait_for_idle(void *handle) 1292 { 1293 /* There is no need to wait for MC idle in GMC v9.*/ 1294 return 0; 1295 } 1296 1297 static int gmc_v9_0_soft_reset(void *handle) 1298 { 1299 /* XXX for emulation.*/ 1300 return 0; 1301 } 1302 1303 static int gmc_v9_0_set_clockgating_state(void *handle, 1304 enum amd_clockgating_state state) 1305 { 1306 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1307 1308 return mmhub_v1_0_set_clockgating(adev, state); 1309 } 1310 1311 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags) 1312 { 1313 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1314 1315 mmhub_v1_0_get_clockgating(adev, flags); 1316 } 1317 1318 static int gmc_v9_0_set_powergating_state(void *handle, 1319 enum amd_powergating_state state) 1320 { 1321 return 0; 1322 } 1323 1324 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 1325 .name = "gmc_v9_0", 1326 .early_init = gmc_v9_0_early_init, 1327 .late_init = gmc_v9_0_late_init, 1328 .sw_init = gmc_v9_0_sw_init, 1329 .sw_fini = gmc_v9_0_sw_fini, 1330 .hw_init = gmc_v9_0_hw_init, 1331 .hw_fini = gmc_v9_0_hw_fini, 1332 .suspend = gmc_v9_0_suspend, 1333 .resume = gmc_v9_0_resume, 1334 .is_idle = gmc_v9_0_is_idle, 1335 .wait_for_idle = gmc_v9_0_wait_for_idle, 1336 .soft_reset = gmc_v9_0_soft_reset, 1337 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 1338 .set_powergating_state = gmc_v9_0_set_powergating_state, 1339 .get_clockgating_state = gmc_v9_0_get_clockgating_state, 1340 }; 1341 1342 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = 1343 { 1344 .type = AMD_IP_BLOCK_TYPE_GMC, 1345 .major = 9, 1346 .minor = 0, 1347 .rev = 0, 1348 .funcs = &gmc_v9_0_ip_funcs, 1349 }; 1350