1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include "amdgpu.h" 25 #include "gmc_v9_0.h" 26 27 #include "vega10/soc15ip.h" 28 #include "vega10/HDP/hdp_4_0_offset.h" 29 #include "vega10/HDP/hdp_4_0_sh_mask.h" 30 #include "vega10/GC/gc_9_0_sh_mask.h" 31 #include "vega10/vega10_enum.h" 32 33 #include "soc15_common.h" 34 35 #include "nbio_v6_1.h" 36 #include "gfxhub_v1_0.h" 37 #include "mmhub_v1_0.h" 38 39 #define mmDF_CS_AON0_DramBaseAddress0 0x0044 40 #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX 0 41 //DF_CS_AON0_DramBaseAddress0 42 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0 43 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1 44 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4 45 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8 46 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc 47 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L 48 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L 49 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x000000F0L 50 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L 51 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L 52 53 /* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/ 54 #define AMDGPU_NUM_OF_VMIDS 8 55 56 static const u32 golden_settings_vega10_hdp[] = 57 { 58 0xf64, 0x0fffffff, 0x00000000, 59 0xf65, 0x0fffffff, 0x00000000, 60 0xf66, 0x0fffffff, 0x00000000, 61 0xf67, 0x0fffffff, 0x00000000, 62 0xf68, 0x0fffffff, 0x00000000, 63 0xf6a, 0x0fffffff, 0x00000000, 64 0xf6b, 0x0fffffff, 0x00000000, 65 0xf6c, 0x0fffffff, 0x00000000, 66 0xf6d, 0x0fffffff, 0x00000000, 67 0xf6e, 0x0fffffff, 0x00000000, 68 }; 69 70 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 71 struct amdgpu_irq_src *src, 72 unsigned type, 73 enum amdgpu_interrupt_state state) 74 { 75 struct amdgpu_vmhub *hub; 76 u32 tmp, reg, bits, i; 77 78 switch (state) { 79 case AMDGPU_IRQ_STATE_DISABLE: 80 /* MM HUB */ 81 hub = &adev->vmhub[AMDGPU_MMHUB]; 82 bits = hub->get_vm_protection_bits(); 83 for (i = 0; i< 16; i++) { 84 reg = hub->vm_context0_cntl + i; 85 tmp = RREG32(reg); 86 tmp &= ~bits; 87 WREG32(reg, tmp); 88 } 89 90 /* GFX HUB */ 91 hub = &adev->vmhub[AMDGPU_GFXHUB]; 92 bits = hub->get_vm_protection_bits(); 93 for (i = 0; i < 16; i++) { 94 reg = hub->vm_context0_cntl + i; 95 tmp = RREG32(reg); 96 tmp &= ~bits; 97 WREG32(reg, tmp); 98 } 99 break; 100 case AMDGPU_IRQ_STATE_ENABLE: 101 /* MM HUB */ 102 hub = &adev->vmhub[AMDGPU_MMHUB]; 103 bits = hub->get_vm_protection_bits(); 104 for (i = 0; i< 16; i++) { 105 reg = hub->vm_context0_cntl + i; 106 tmp = RREG32(reg); 107 tmp |= bits; 108 WREG32(reg, tmp); 109 } 110 111 /* GFX HUB */ 112 hub = &adev->vmhub[AMDGPU_GFXHUB]; 113 bits = hub->get_vm_protection_bits(); 114 for (i = 0; i < 16; i++) { 115 reg = hub->vm_context0_cntl + i; 116 tmp = RREG32(reg); 117 tmp |= bits; 118 WREG32(reg, tmp); 119 } 120 break; 121 default: 122 break; 123 } 124 125 return 0; 126 } 127 128 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 129 struct amdgpu_irq_src *source, 130 struct amdgpu_iv_entry *entry) 131 { 132 struct amdgpu_vmhub *gfxhub = &adev->vmhub[AMDGPU_GFXHUB]; 133 struct amdgpu_vmhub *mmhub = &adev->vmhub[AMDGPU_MMHUB]; 134 uint32_t status; 135 u64 addr; 136 137 addr = (u64)entry->src_data[0] << 12; 138 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 139 140 if (!amdgpu_sriov_vf(adev)) { 141 if (entry->vm_id_src) { 142 status = RREG32(mmhub->vm_l2_pro_fault_status); 143 WREG32_P(mmhub->vm_l2_pro_fault_cntl, 1, ~1); 144 } else { 145 status = RREG32(gfxhub->vm_l2_pro_fault_status); 146 WREG32_P(gfxhub->vm_l2_pro_fault_cntl, 1, ~1); 147 } 148 149 DRM_ERROR("[%s]VMC page fault (src_id:%u ring:%u vm_id:%u pas_id:%u) " 150 "at page 0x%016llx from %d\n" 151 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 152 entry->vm_id_src ? "mmhub" : "gfxhub", 153 entry->src_id, entry->ring_id, entry->vm_id, entry->pas_id, 154 addr, entry->client_id, status); 155 } else { 156 DRM_ERROR("[%s]VMC page fault (src_id:%u ring:%u vm_id:%u pas_id:%u) " 157 "at page 0x%016llx from %d\n", 158 entry->vm_id_src ? "mmhub" : "gfxhub", 159 entry->src_id, entry->ring_id, entry->vm_id, entry->pas_id, 160 addr, entry->client_id); 161 } 162 163 return 0; 164 } 165 166 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 167 .set = gmc_v9_0_vm_fault_interrupt_state, 168 .process = gmc_v9_0_process_interrupt, 169 }; 170 171 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 172 { 173 adev->mc.vm_fault.num_types = 1; 174 adev->mc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 175 } 176 177 /* 178 * GART 179 * VMID 0 is the physical GPU addresses as used by the kernel. 180 * VMIDs 1-15 are used for userspace clients and are handled 181 * by the amdgpu vm/hsa code. 182 */ 183 184 /** 185 * gmc_v9_0_gart_flush_gpu_tlb - gart tlb flush callback 186 * 187 * @adev: amdgpu_device pointer 188 * @vmid: vm instance to flush 189 * 190 * Flush the TLB for the requested page table. 191 */ 192 static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, 193 uint32_t vmid) 194 { 195 /* Use register 17 for GART */ 196 const unsigned eng = 17; 197 unsigned i, j; 198 199 /* flush hdp cache */ 200 nbio_v6_1_hdp_flush(adev); 201 202 spin_lock(&adev->mc.invalidate_lock); 203 204 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { 205 struct amdgpu_vmhub *hub = &adev->vmhub[i]; 206 u32 tmp = hub->get_invalidate_req(vmid); 207 208 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp); 209 210 /* Busy wait for ACK.*/ 211 for (j = 0; j < 100; j++) { 212 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); 213 tmp &= 1 << vmid; 214 if (tmp) 215 break; 216 cpu_relax(); 217 } 218 if (j < 100) 219 continue; 220 221 /* Wait for ACK with a delay.*/ 222 for (j = 0; j < adev->usec_timeout; j++) { 223 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); 224 tmp &= 1 << vmid; 225 if (tmp) 226 break; 227 udelay(1); 228 } 229 if (j < adev->usec_timeout) 230 continue; 231 232 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 233 } 234 235 spin_unlock(&adev->mc.invalidate_lock); 236 } 237 238 /** 239 * gmc_v9_0_gart_set_pte_pde - update the page tables using MMIO 240 * 241 * @adev: amdgpu_device pointer 242 * @cpu_pt_addr: cpu address of the page table 243 * @gpu_page_idx: entry in the page table to update 244 * @addr: dst addr to write into pte/pde 245 * @flags: access flags 246 * 247 * Update the page tables using the CPU. 248 */ 249 static int gmc_v9_0_gart_set_pte_pde(struct amdgpu_device *adev, 250 void *cpu_pt_addr, 251 uint32_t gpu_page_idx, 252 uint64_t addr, 253 uint64_t flags) 254 { 255 void __iomem *ptr = (void *)cpu_pt_addr; 256 uint64_t value; 257 258 /* 259 * PTE format on VEGA 10: 260 * 63:59 reserved 261 * 58:57 mtype 262 * 56 F 263 * 55 L 264 * 54 P 265 * 53 SW 266 * 52 T 267 * 50:48 reserved 268 * 47:12 4k physical page base address 269 * 11:7 fragment 270 * 6 write 271 * 5 read 272 * 4 exe 273 * 3 Z 274 * 2 snooped 275 * 1 system 276 * 0 valid 277 * 278 * PDE format on VEGA 10: 279 * 63:59 block fragment size 280 * 58:55 reserved 281 * 54 P 282 * 53:48 reserved 283 * 47:6 physical base address of PD or PTE 284 * 5:3 reserved 285 * 2 C 286 * 1 system 287 * 0 valid 288 */ 289 290 /* 291 * The following is for PTE only. GART does not have PDEs. 292 */ 293 value = addr & 0x0000FFFFFFFFF000ULL; 294 value |= flags; 295 writeq(value, ptr + (gpu_page_idx * 8)); 296 return 0; 297 } 298 299 static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev, 300 uint32_t flags) 301 302 { 303 uint64_t pte_flag = 0; 304 305 if (flags & AMDGPU_VM_PAGE_EXECUTABLE) 306 pte_flag |= AMDGPU_PTE_EXECUTABLE; 307 if (flags & AMDGPU_VM_PAGE_READABLE) 308 pte_flag |= AMDGPU_PTE_READABLE; 309 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 310 pte_flag |= AMDGPU_PTE_WRITEABLE; 311 312 switch (flags & AMDGPU_VM_MTYPE_MASK) { 313 case AMDGPU_VM_MTYPE_DEFAULT: 314 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC); 315 break; 316 case AMDGPU_VM_MTYPE_NC: 317 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC); 318 break; 319 case AMDGPU_VM_MTYPE_WC: 320 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_WC); 321 break; 322 case AMDGPU_VM_MTYPE_CC: 323 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_CC); 324 break; 325 case AMDGPU_VM_MTYPE_UC: 326 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_UC); 327 break; 328 default: 329 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC); 330 break; 331 } 332 333 if (flags & AMDGPU_VM_PAGE_PRT) 334 pte_flag |= AMDGPU_PTE_PRT; 335 336 return pte_flag; 337 } 338 339 static const struct amdgpu_gart_funcs gmc_v9_0_gart_funcs = { 340 .flush_gpu_tlb = gmc_v9_0_gart_flush_gpu_tlb, 341 .set_pte_pde = gmc_v9_0_gart_set_pte_pde, 342 .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags 343 }; 344 345 static void gmc_v9_0_set_gart_funcs(struct amdgpu_device *adev) 346 { 347 if (adev->gart.gart_funcs == NULL) 348 adev->gart.gart_funcs = &gmc_v9_0_gart_funcs; 349 } 350 351 static u64 gmc_v9_0_adjust_mc_addr(struct amdgpu_device *adev, u64 mc_addr) 352 { 353 return adev->vm_manager.vram_base_offset + mc_addr - adev->mc.vram_start; 354 } 355 356 static const struct amdgpu_mc_funcs gmc_v9_0_mc_funcs = { 357 .adjust_mc_addr = gmc_v9_0_adjust_mc_addr, 358 }; 359 360 static void gmc_v9_0_set_mc_funcs(struct amdgpu_device *adev) 361 { 362 adev->mc.mc_funcs = &gmc_v9_0_mc_funcs; 363 } 364 365 static int gmc_v9_0_early_init(void *handle) 366 { 367 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 368 369 gmc_v9_0_set_gart_funcs(adev); 370 gmc_v9_0_set_mc_funcs(adev); 371 gmc_v9_0_set_irq_funcs(adev); 372 373 return 0; 374 } 375 376 static int gmc_v9_0_late_init(void *handle) 377 { 378 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 379 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0); 380 } 381 382 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 383 struct amdgpu_mc *mc) 384 { 385 u64 base = 0; 386 if (!amdgpu_sriov_vf(adev)) 387 base = mmhub_v1_0_get_fb_location(adev); 388 amdgpu_vram_location(adev, &adev->mc, base); 389 adev->mc.gtt_base_align = 0; 390 amdgpu_gtt_location(adev, mc); 391 } 392 393 /** 394 * gmc_v9_0_mc_init - initialize the memory controller driver params 395 * 396 * @adev: amdgpu_device pointer 397 * 398 * Look up the amount of vram, vram width, and decide how to place 399 * vram and gart within the GPU's physical address space. 400 * Returns 0 for success. 401 */ 402 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 403 { 404 u32 tmp; 405 int chansize, numchan; 406 407 /* hbm memory channel size */ 408 chansize = 128; 409 410 tmp = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_CS_AON0_DramBaseAddress0)); 411 tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK; 412 tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT; 413 switch (tmp) { 414 case 0: 415 default: 416 numchan = 1; 417 break; 418 case 1: 419 numchan = 2; 420 break; 421 case 2: 422 numchan = 0; 423 break; 424 case 3: 425 numchan = 4; 426 break; 427 case 4: 428 numchan = 0; 429 break; 430 case 5: 431 numchan = 8; 432 break; 433 case 6: 434 numchan = 0; 435 break; 436 case 7: 437 numchan = 16; 438 break; 439 case 8: 440 numchan = 2; 441 break; 442 } 443 adev->mc.vram_width = numchan * chansize; 444 445 /* Could aper size report 0 ? */ 446 adev->mc.aper_base = pci_resource_start(adev->pdev, 0); 447 adev->mc.aper_size = pci_resource_len(adev->pdev, 0); 448 /* size in MB on si */ 449 adev->mc.mc_vram_size = 450 nbio_v6_1_get_memsize(adev) * 1024ULL * 1024ULL; 451 adev->mc.real_vram_size = adev->mc.mc_vram_size; 452 adev->mc.visible_vram_size = adev->mc.aper_size; 453 454 /* In case the PCI BAR is larger than the actual amount of vram */ 455 if (adev->mc.visible_vram_size > adev->mc.real_vram_size) 456 adev->mc.visible_vram_size = adev->mc.real_vram_size; 457 458 /* unless the user had overridden it, set the gart 459 * size equal to the 1024 or vram, whichever is larger. 460 */ 461 if (amdgpu_gart_size == -1) 462 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size); 463 else 464 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20; 465 466 gmc_v9_0_vram_gtt_location(adev, &adev->mc); 467 468 return 0; 469 } 470 471 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 472 { 473 int r; 474 475 if (adev->gart.robj) { 476 WARN(1, "VEGA10 PCIE GART already initialized\n"); 477 return 0; 478 } 479 /* Initialize common gart structure */ 480 r = amdgpu_gart_init(adev); 481 if (r) 482 return r; 483 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 484 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE(MTYPE_UC) | 485 AMDGPU_PTE_EXECUTABLE; 486 return amdgpu_gart_table_vram_alloc(adev); 487 } 488 489 /* 490 * vm 491 * VMID 0 is the physical GPU addresses as used by the kernel. 492 * VMIDs 1-15 are used for userspace clients and are handled 493 * by the amdgpu vm/hsa code. 494 */ 495 /** 496 * gmc_v9_0_vm_init - vm init callback 497 * 498 * @adev: amdgpu_device pointer 499 * 500 * Inits vega10 specific vm parameters (number of VMs, base of vram for 501 * VMIDs 1-15) (vega10). 502 * Returns 0 for success. 503 */ 504 static int gmc_v9_0_vm_init(struct amdgpu_device *adev) 505 { 506 /* 507 * number of VMs 508 * VMID 0 is reserved for System 509 * amdgpu graphics/compute will use VMIDs 1-7 510 * amdkfd will use VMIDs 8-15 511 */ 512 adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS; 513 /* Because of four level VMPTs, vm size at least is 256GB. 514 256TB is OK as well */ 515 if (amdgpu_vm_size < 256) { 516 DRM_WARN("vm size at least is 256GB!\n"); 517 amdgpu_vm_size = 256; 518 } 519 adev->vm_manager.num_level = 3; 520 amdgpu_vm_manager_init(adev); 521 522 /* base offset of vram pages */ 523 /*XXX This value is not zero for APU*/ 524 adev->vm_manager.vram_base_offset = 0; 525 526 return 0; 527 } 528 529 /** 530 * gmc_v9_0_vm_fini - vm fini callback 531 * 532 * @adev: amdgpu_device pointer 533 * 534 * Tear down any asic specific VM setup. 535 */ 536 static void gmc_v9_0_vm_fini(struct amdgpu_device *adev) 537 { 538 return; 539 } 540 541 static int gmc_v9_0_sw_init(void *handle) 542 { 543 int r; 544 int dma_bits; 545 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 546 547 spin_lock_init(&adev->mc.invalidate_lock); 548 549 if (adev->flags & AMD_IS_APU) { 550 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 551 } else { 552 /* XXX Don't know how to get VRAM type yet. */ 553 adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM; 554 } 555 556 /* This interrupt is VMC page fault.*/ 557 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0, 558 &adev->mc.vm_fault); 559 560 if (r) 561 return r; 562 563 /* Adjust VM size here. 564 * Currently default to 64GB ((16 << 20) 4k pages). 565 * Max GPUVM size is 48 bits. 566 */ 567 adev->vm_manager.max_pfn = amdgpu_vm_size << 18; 568 569 /* Set the internal MC address mask 570 * This is the max address of the GPU's 571 * internal address space. 572 */ 573 adev->mc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 574 575 /* set DMA mask + need_dma32 flags. 576 * PCIE - can handle 44-bits. 577 * IGP - can handle 44-bits 578 * PCI - dma32 for legacy pci gart, 44 bits on vega10 579 */ 580 adev->need_dma32 = false; 581 dma_bits = adev->need_dma32 ? 32 : 44; 582 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 583 if (r) { 584 adev->need_dma32 = true; 585 dma_bits = 32; 586 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 587 } 588 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 589 if (r) { 590 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); 591 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n"); 592 } 593 594 r = gmc_v9_0_mc_init(adev); 595 if (r) 596 return r; 597 598 /* Memory manager */ 599 r = amdgpu_bo_init(adev); 600 if (r) 601 return r; 602 603 r = gmc_v9_0_gart_init(adev); 604 if (r) 605 return r; 606 607 if (!adev->vm_manager.enabled) { 608 r = gmc_v9_0_vm_init(adev); 609 if (r) { 610 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r); 611 return r; 612 } 613 adev->vm_manager.enabled = true; 614 } 615 return r; 616 } 617 618 /** 619 * gmc_v8_0_gart_fini - vm fini callback 620 * 621 * @adev: amdgpu_device pointer 622 * 623 * Tears down the driver GART/VM setup (CIK). 624 */ 625 static void gmc_v9_0_gart_fini(struct amdgpu_device *adev) 626 { 627 amdgpu_gart_table_vram_free(adev); 628 amdgpu_gart_fini(adev); 629 } 630 631 static int gmc_v9_0_sw_fini(void *handle) 632 { 633 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 634 635 if (adev->vm_manager.enabled) { 636 amdgpu_vm_manager_fini(adev); 637 gmc_v9_0_vm_fini(adev); 638 adev->vm_manager.enabled = false; 639 } 640 gmc_v9_0_gart_fini(adev); 641 amdgpu_gem_force_release(adev); 642 amdgpu_bo_fini(adev); 643 644 return 0; 645 } 646 647 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 648 { 649 switch (adev->asic_type) { 650 case CHIP_VEGA10: 651 break; 652 default: 653 break; 654 } 655 } 656 657 /** 658 * gmc_v9_0_gart_enable - gart enable 659 * 660 * @adev: amdgpu_device pointer 661 */ 662 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 663 { 664 int r; 665 bool value; 666 u32 tmp; 667 668 amdgpu_program_register_sequence(adev, 669 golden_settings_vega10_hdp, 670 (const u32)ARRAY_SIZE(golden_settings_vega10_hdp)); 671 672 if (adev->gart.robj == NULL) { 673 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 674 return -EINVAL; 675 } 676 r = amdgpu_gart_table_vram_pin(adev); 677 if (r) 678 return r; 679 680 /* After HDP is initialized, flush HDP.*/ 681 nbio_v6_1_hdp_flush(adev); 682 683 r = gfxhub_v1_0_gart_enable(adev); 684 if (r) 685 return r; 686 687 r = mmhub_v1_0_gart_enable(adev); 688 if (r) 689 return r; 690 691 tmp = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MISC_CNTL)); 692 tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK; 693 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MISC_CNTL), tmp); 694 695 tmp = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_HOST_PATH_CNTL)); 696 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_HOST_PATH_CNTL), tmp); 697 698 699 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 700 value = false; 701 else 702 value = true; 703 704 gfxhub_v1_0_set_fault_enable_default(adev, value); 705 mmhub_v1_0_set_fault_enable_default(adev, value); 706 707 gmc_v9_0_gart_flush_gpu_tlb(adev, 0); 708 709 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 710 (unsigned)(adev->mc.gtt_size >> 20), 711 (unsigned long long)adev->gart.table_addr); 712 adev->gart.ready = true; 713 return 0; 714 } 715 716 static int gmc_v9_0_hw_init(void *handle) 717 { 718 int r; 719 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 720 721 /* The sequence of these two function calls matters.*/ 722 gmc_v9_0_init_golden_registers(adev); 723 724 r = gmc_v9_0_gart_enable(adev); 725 726 return r; 727 } 728 729 /** 730 * gmc_v9_0_gart_disable - gart disable 731 * 732 * @adev: amdgpu_device pointer 733 * 734 * This disables all VM page table. 735 */ 736 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 737 { 738 gfxhub_v1_0_gart_disable(adev); 739 mmhub_v1_0_gart_disable(adev); 740 amdgpu_gart_table_vram_unpin(adev); 741 } 742 743 static int gmc_v9_0_hw_fini(void *handle) 744 { 745 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 746 747 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0); 748 gmc_v9_0_gart_disable(adev); 749 750 return 0; 751 } 752 753 static int gmc_v9_0_suspend(void *handle) 754 { 755 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 756 757 if (adev->vm_manager.enabled) { 758 gmc_v9_0_vm_fini(adev); 759 adev->vm_manager.enabled = false; 760 } 761 gmc_v9_0_hw_fini(adev); 762 763 return 0; 764 } 765 766 static int gmc_v9_0_resume(void *handle) 767 { 768 int r; 769 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 770 771 r = gmc_v9_0_hw_init(adev); 772 if (r) 773 return r; 774 775 if (!adev->vm_manager.enabled) { 776 r = gmc_v9_0_vm_init(adev); 777 if (r) { 778 dev_err(adev->dev, 779 "vm manager initialization failed (%d).\n", r); 780 return r; 781 } 782 adev->vm_manager.enabled = true; 783 } 784 785 return r; 786 } 787 788 static bool gmc_v9_0_is_idle(void *handle) 789 { 790 /* MC is always ready in GMC v9.*/ 791 return true; 792 } 793 794 static int gmc_v9_0_wait_for_idle(void *handle) 795 { 796 /* There is no need to wait for MC idle in GMC v9.*/ 797 return 0; 798 } 799 800 static int gmc_v9_0_soft_reset(void *handle) 801 { 802 /* XXX for emulation.*/ 803 return 0; 804 } 805 806 static int gmc_v9_0_set_clockgating_state(void *handle, 807 enum amd_clockgating_state state) 808 { 809 return 0; 810 } 811 812 static int gmc_v9_0_set_powergating_state(void *handle, 813 enum amd_powergating_state state) 814 { 815 return 0; 816 } 817 818 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 819 .name = "gmc_v9_0", 820 .early_init = gmc_v9_0_early_init, 821 .late_init = gmc_v9_0_late_init, 822 .sw_init = gmc_v9_0_sw_init, 823 .sw_fini = gmc_v9_0_sw_fini, 824 .hw_init = gmc_v9_0_hw_init, 825 .hw_fini = gmc_v9_0_hw_fini, 826 .suspend = gmc_v9_0_suspend, 827 .resume = gmc_v9_0_resume, 828 .is_idle = gmc_v9_0_is_idle, 829 .wait_for_idle = gmc_v9_0_wait_for_idle, 830 .soft_reset = gmc_v9_0_soft_reset, 831 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 832 .set_powergating_state = gmc_v9_0_set_powergating_state, 833 }; 834 835 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = 836 { 837 .type = AMD_IP_BLOCK_TYPE_GMC, 838 .major = 9, 839 .minor = 0, 840 .rev = 0, 841 .funcs = &gmc_v9_0_ip_funcs, 842 }; 843