1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/pci.h> 26 27 #include <drm/drm_cache.h> 28 29 #include "amdgpu.h" 30 #include "gmc_v9_0.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_gem.h" 33 34 #include "gc/gc_9_0_sh_mask.h" 35 #include "dce/dce_12_0_offset.h" 36 #include "dce/dce_12_0_sh_mask.h" 37 #include "vega10_enum.h" 38 #include "mmhub/mmhub_1_0_offset.h" 39 #include "athub/athub_1_0_sh_mask.h" 40 #include "athub/athub_1_0_offset.h" 41 #include "oss/osssys_4_0_offset.h" 42 43 #include "soc15.h" 44 #include "soc15d.h" 45 #include "soc15_common.h" 46 #include "umc/umc_6_0_sh_mask.h" 47 48 #include "gfxhub_v1_0.h" 49 #include "mmhub_v1_0.h" 50 #include "athub_v1_0.h" 51 #include "gfxhub_v1_1.h" 52 #include "gfxhub_v1_2.h" 53 #include "mmhub_v9_4.h" 54 #include "mmhub_v1_7.h" 55 #include "mmhub_v1_8.h" 56 #include "umc_v6_1.h" 57 #include "umc_v6_0.h" 58 #include "umc_v6_7.h" 59 #include "hdp_v4_0.h" 60 #include "mca_v3_0.h" 61 62 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 63 64 #include "amdgpu_ras.h" 65 #include "amdgpu_xgmi.h" 66 67 #include "amdgpu_reset.h" 68 69 /* add these here since we already include dce12 headers and these are for DCN */ 70 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 71 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 72 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 73 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 74 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL 75 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L 76 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d 77 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2 78 79 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2 0x05ea 80 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX 2 81 82 #define MAX_MEM_RANGES 8 83 84 static const char *gfxhub_client_ids[] = { 85 "CB", 86 "DB", 87 "IA", 88 "WD", 89 "CPF", 90 "CPC", 91 "CPG", 92 "RLC", 93 "TCP", 94 "SQC (inst)", 95 "SQC (data)", 96 "SQG", 97 "PA", 98 }; 99 100 static const char *mmhub_client_ids_raven[][2] = { 101 [0][0] = "MP1", 102 [1][0] = "MP0", 103 [2][0] = "VCN", 104 [3][0] = "VCNU", 105 [4][0] = "HDP", 106 [5][0] = "DCE", 107 [13][0] = "UTCL2", 108 [19][0] = "TLS", 109 [26][0] = "OSS", 110 [27][0] = "SDMA0", 111 [0][1] = "MP1", 112 [1][1] = "MP0", 113 [2][1] = "VCN", 114 [3][1] = "VCNU", 115 [4][1] = "HDP", 116 [5][1] = "XDP", 117 [6][1] = "DBGU0", 118 [7][1] = "DCE", 119 [8][1] = "DCEDWB0", 120 [9][1] = "DCEDWB1", 121 [26][1] = "OSS", 122 [27][1] = "SDMA0", 123 }; 124 125 static const char *mmhub_client_ids_renoir[][2] = { 126 [0][0] = "MP1", 127 [1][0] = "MP0", 128 [2][0] = "HDP", 129 [4][0] = "DCEDMC", 130 [5][0] = "DCEVGA", 131 [13][0] = "UTCL2", 132 [19][0] = "TLS", 133 [26][0] = "OSS", 134 [27][0] = "SDMA0", 135 [28][0] = "VCN", 136 [29][0] = "VCNU", 137 [30][0] = "JPEG", 138 [0][1] = "MP1", 139 [1][1] = "MP0", 140 [2][1] = "HDP", 141 [3][1] = "XDP", 142 [6][1] = "DBGU0", 143 [7][1] = "DCEDMC", 144 [8][1] = "DCEVGA", 145 [9][1] = "DCEDWB", 146 [26][1] = "OSS", 147 [27][1] = "SDMA0", 148 [28][1] = "VCN", 149 [29][1] = "VCNU", 150 [30][1] = "JPEG", 151 }; 152 153 static const char *mmhub_client_ids_vega10[][2] = { 154 [0][0] = "MP0", 155 [1][0] = "UVD", 156 [2][0] = "UVDU", 157 [3][0] = "HDP", 158 [13][0] = "UTCL2", 159 [14][0] = "OSS", 160 [15][0] = "SDMA1", 161 [32+0][0] = "VCE0", 162 [32+1][0] = "VCE0U", 163 [32+2][0] = "XDMA", 164 [32+3][0] = "DCE", 165 [32+4][0] = "MP1", 166 [32+14][0] = "SDMA0", 167 [0][1] = "MP0", 168 [1][1] = "UVD", 169 [2][1] = "UVDU", 170 [3][1] = "DBGU0", 171 [4][1] = "HDP", 172 [5][1] = "XDP", 173 [14][1] = "OSS", 174 [15][1] = "SDMA0", 175 [32+0][1] = "VCE0", 176 [32+1][1] = "VCE0U", 177 [32+2][1] = "XDMA", 178 [32+3][1] = "DCE", 179 [32+4][1] = "DCEDWB", 180 [32+5][1] = "MP1", 181 [32+6][1] = "DBGU1", 182 [32+14][1] = "SDMA1", 183 }; 184 185 static const char *mmhub_client_ids_vega12[][2] = { 186 [0][0] = "MP0", 187 [1][0] = "VCE0", 188 [2][0] = "VCE0U", 189 [3][0] = "HDP", 190 [13][0] = "UTCL2", 191 [14][0] = "OSS", 192 [15][0] = "SDMA1", 193 [32+0][0] = "DCE", 194 [32+1][0] = "XDMA", 195 [32+2][0] = "UVD", 196 [32+3][0] = "UVDU", 197 [32+4][0] = "MP1", 198 [32+15][0] = "SDMA0", 199 [0][1] = "MP0", 200 [1][1] = "VCE0", 201 [2][1] = "VCE0U", 202 [3][1] = "DBGU0", 203 [4][1] = "HDP", 204 [5][1] = "XDP", 205 [14][1] = "OSS", 206 [15][1] = "SDMA0", 207 [32+0][1] = "DCE", 208 [32+1][1] = "DCEDWB", 209 [32+2][1] = "XDMA", 210 [32+3][1] = "UVD", 211 [32+4][1] = "UVDU", 212 [32+5][1] = "MP1", 213 [32+6][1] = "DBGU1", 214 [32+15][1] = "SDMA1", 215 }; 216 217 static const char *mmhub_client_ids_vega20[][2] = { 218 [0][0] = "XDMA", 219 [1][0] = "DCE", 220 [2][0] = "VCE0", 221 [3][0] = "VCE0U", 222 [4][0] = "UVD", 223 [5][0] = "UVD1U", 224 [13][0] = "OSS", 225 [14][0] = "HDP", 226 [15][0] = "SDMA0", 227 [32+0][0] = "UVD", 228 [32+1][0] = "UVDU", 229 [32+2][0] = "MP1", 230 [32+3][0] = "MP0", 231 [32+12][0] = "UTCL2", 232 [32+14][0] = "SDMA1", 233 [0][1] = "XDMA", 234 [1][1] = "DCE", 235 [2][1] = "DCEDWB", 236 [3][1] = "VCE0", 237 [4][1] = "VCE0U", 238 [5][1] = "UVD1", 239 [6][1] = "UVD1U", 240 [7][1] = "DBGU0", 241 [8][1] = "XDP", 242 [13][1] = "OSS", 243 [14][1] = "HDP", 244 [15][1] = "SDMA0", 245 [32+0][1] = "UVD", 246 [32+1][1] = "UVDU", 247 [32+2][1] = "DBGU1", 248 [32+3][1] = "MP1", 249 [32+4][1] = "MP0", 250 [32+14][1] = "SDMA1", 251 }; 252 253 static const char *mmhub_client_ids_arcturus[][2] = { 254 [0][0] = "DBGU1", 255 [1][0] = "XDP", 256 [2][0] = "MP1", 257 [14][0] = "HDP", 258 [171][0] = "JPEG", 259 [172][0] = "VCN", 260 [173][0] = "VCNU", 261 [203][0] = "JPEG1", 262 [204][0] = "VCN1", 263 [205][0] = "VCN1U", 264 [256][0] = "SDMA0", 265 [257][0] = "SDMA1", 266 [258][0] = "SDMA2", 267 [259][0] = "SDMA3", 268 [260][0] = "SDMA4", 269 [261][0] = "SDMA5", 270 [262][0] = "SDMA6", 271 [263][0] = "SDMA7", 272 [384][0] = "OSS", 273 [0][1] = "DBGU1", 274 [1][1] = "XDP", 275 [2][1] = "MP1", 276 [14][1] = "HDP", 277 [171][1] = "JPEG", 278 [172][1] = "VCN", 279 [173][1] = "VCNU", 280 [203][1] = "JPEG1", 281 [204][1] = "VCN1", 282 [205][1] = "VCN1U", 283 [256][1] = "SDMA0", 284 [257][1] = "SDMA1", 285 [258][1] = "SDMA2", 286 [259][1] = "SDMA3", 287 [260][1] = "SDMA4", 288 [261][1] = "SDMA5", 289 [262][1] = "SDMA6", 290 [263][1] = "SDMA7", 291 [384][1] = "OSS", 292 }; 293 294 static const char *mmhub_client_ids_aldebaran[][2] = { 295 [2][0] = "MP1", 296 [3][0] = "MP0", 297 [32+1][0] = "DBGU_IO0", 298 [32+2][0] = "DBGU_IO2", 299 [32+4][0] = "MPIO", 300 [96+11][0] = "JPEG0", 301 [96+12][0] = "VCN0", 302 [96+13][0] = "VCNU0", 303 [128+11][0] = "JPEG1", 304 [128+12][0] = "VCN1", 305 [128+13][0] = "VCNU1", 306 [160+1][0] = "XDP", 307 [160+14][0] = "HDP", 308 [256+0][0] = "SDMA0", 309 [256+1][0] = "SDMA1", 310 [256+2][0] = "SDMA2", 311 [256+3][0] = "SDMA3", 312 [256+4][0] = "SDMA4", 313 [384+0][0] = "OSS", 314 [2][1] = "MP1", 315 [3][1] = "MP0", 316 [32+1][1] = "DBGU_IO0", 317 [32+2][1] = "DBGU_IO2", 318 [32+4][1] = "MPIO", 319 [96+11][1] = "JPEG0", 320 [96+12][1] = "VCN0", 321 [96+13][1] = "VCNU0", 322 [128+11][1] = "JPEG1", 323 [128+12][1] = "VCN1", 324 [128+13][1] = "VCNU1", 325 [160+1][1] = "XDP", 326 [160+14][1] = "HDP", 327 [256+0][1] = "SDMA0", 328 [256+1][1] = "SDMA1", 329 [256+2][1] = "SDMA2", 330 [256+3][1] = "SDMA3", 331 [256+4][1] = "SDMA4", 332 [384+0][1] = "OSS", 333 }; 334 335 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = 336 { 337 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), 338 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) 339 }; 340 341 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = 342 { 343 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), 344 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) 345 }; 346 347 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { 348 (0x000143c0 + 0x00000000), 349 (0x000143c0 + 0x00000800), 350 (0x000143c0 + 0x00001000), 351 (0x000143c0 + 0x00001800), 352 (0x000543c0 + 0x00000000), 353 (0x000543c0 + 0x00000800), 354 (0x000543c0 + 0x00001000), 355 (0x000543c0 + 0x00001800), 356 (0x000943c0 + 0x00000000), 357 (0x000943c0 + 0x00000800), 358 (0x000943c0 + 0x00001000), 359 (0x000943c0 + 0x00001800), 360 (0x000d43c0 + 0x00000000), 361 (0x000d43c0 + 0x00000800), 362 (0x000d43c0 + 0x00001000), 363 (0x000d43c0 + 0x00001800), 364 (0x001143c0 + 0x00000000), 365 (0x001143c0 + 0x00000800), 366 (0x001143c0 + 0x00001000), 367 (0x001143c0 + 0x00001800), 368 (0x001543c0 + 0x00000000), 369 (0x001543c0 + 0x00000800), 370 (0x001543c0 + 0x00001000), 371 (0x001543c0 + 0x00001800), 372 (0x001943c0 + 0x00000000), 373 (0x001943c0 + 0x00000800), 374 (0x001943c0 + 0x00001000), 375 (0x001943c0 + 0x00001800), 376 (0x001d43c0 + 0x00000000), 377 (0x001d43c0 + 0x00000800), 378 (0x001d43c0 + 0x00001000), 379 (0x001d43c0 + 0x00001800), 380 }; 381 382 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { 383 (0x000143e0 + 0x00000000), 384 (0x000143e0 + 0x00000800), 385 (0x000143e0 + 0x00001000), 386 (0x000143e0 + 0x00001800), 387 (0x000543e0 + 0x00000000), 388 (0x000543e0 + 0x00000800), 389 (0x000543e0 + 0x00001000), 390 (0x000543e0 + 0x00001800), 391 (0x000943e0 + 0x00000000), 392 (0x000943e0 + 0x00000800), 393 (0x000943e0 + 0x00001000), 394 (0x000943e0 + 0x00001800), 395 (0x000d43e0 + 0x00000000), 396 (0x000d43e0 + 0x00000800), 397 (0x000d43e0 + 0x00001000), 398 (0x000d43e0 + 0x00001800), 399 (0x001143e0 + 0x00000000), 400 (0x001143e0 + 0x00000800), 401 (0x001143e0 + 0x00001000), 402 (0x001143e0 + 0x00001800), 403 (0x001543e0 + 0x00000000), 404 (0x001543e0 + 0x00000800), 405 (0x001543e0 + 0x00001000), 406 (0x001543e0 + 0x00001800), 407 (0x001943e0 + 0x00000000), 408 (0x001943e0 + 0x00000800), 409 (0x001943e0 + 0x00001000), 410 (0x001943e0 + 0x00001800), 411 (0x001d43e0 + 0x00000000), 412 (0x001d43e0 + 0x00000800), 413 (0x001d43e0 + 0x00001000), 414 (0x001d43e0 + 0x00001800), 415 }; 416 417 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, 418 struct amdgpu_irq_src *src, 419 unsigned type, 420 enum amdgpu_interrupt_state state) 421 { 422 u32 bits, i, tmp, reg; 423 424 /* Devices newer then VEGA10/12 shall have these programming 425 sequences performed by PSP BL */ 426 if (adev->asic_type >= CHIP_VEGA20) 427 return 0; 428 429 bits = 0x7f; 430 431 switch (state) { 432 case AMDGPU_IRQ_STATE_DISABLE: 433 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 434 reg = ecc_umc_mcumc_ctrl_addrs[i]; 435 tmp = RREG32(reg); 436 tmp &= ~bits; 437 WREG32(reg, tmp); 438 } 439 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 440 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 441 tmp = RREG32(reg); 442 tmp &= ~bits; 443 WREG32(reg, tmp); 444 } 445 break; 446 case AMDGPU_IRQ_STATE_ENABLE: 447 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 448 reg = ecc_umc_mcumc_ctrl_addrs[i]; 449 tmp = RREG32(reg); 450 tmp |= bits; 451 WREG32(reg, tmp); 452 } 453 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 454 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 455 tmp = RREG32(reg); 456 tmp |= bits; 457 WREG32(reg, tmp); 458 } 459 break; 460 default: 461 break; 462 } 463 464 return 0; 465 } 466 467 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 468 struct amdgpu_irq_src *src, 469 unsigned type, 470 enum amdgpu_interrupt_state state) 471 { 472 struct amdgpu_vmhub *hub; 473 u32 tmp, reg, bits, i, j; 474 475 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 476 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 477 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 478 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 479 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 480 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 481 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 482 483 switch (state) { 484 case AMDGPU_IRQ_STATE_DISABLE: 485 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 486 hub = &adev->vmhub[j]; 487 for (i = 0; i < 16; i++) { 488 reg = hub->vm_context0_cntl + i; 489 490 /* This works because this interrupt is only 491 * enabled at init/resume and disabled in 492 * fini/suspend, so the overall state doesn't 493 * change over the course of suspend/resume. 494 */ 495 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 496 continue; 497 498 if (j >= AMDGPU_MMHUB0(0)) 499 tmp = RREG32_SOC15_IP(MMHUB, reg); 500 else 501 tmp = RREG32_SOC15_IP(GC, reg); 502 503 tmp &= ~bits; 504 505 if (j >= AMDGPU_MMHUB0(0)) 506 WREG32_SOC15_IP(MMHUB, reg, tmp); 507 else 508 WREG32_SOC15_IP(GC, reg, tmp); 509 } 510 } 511 break; 512 case AMDGPU_IRQ_STATE_ENABLE: 513 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 514 hub = &adev->vmhub[j]; 515 for (i = 0; i < 16; i++) { 516 reg = hub->vm_context0_cntl + i; 517 518 /* This works because this interrupt is only 519 * enabled at init/resume and disabled in 520 * fini/suspend, so the overall state doesn't 521 * change over the course of suspend/resume. 522 */ 523 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 524 continue; 525 526 if (j >= AMDGPU_MMHUB0(0)) 527 tmp = RREG32_SOC15_IP(MMHUB, reg); 528 else 529 tmp = RREG32_SOC15_IP(GC, reg); 530 531 tmp |= bits; 532 533 if (j >= AMDGPU_MMHUB0(0)) 534 WREG32_SOC15_IP(MMHUB, reg, tmp); 535 else 536 WREG32_SOC15_IP(GC, reg, tmp); 537 } 538 } 539 break; 540 default: 541 break; 542 } 543 544 return 0; 545 } 546 547 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 548 struct amdgpu_irq_src *source, 549 struct amdgpu_iv_entry *entry) 550 { 551 bool retry_fault = !!(entry->src_data[1] & 0x80); 552 bool write_fault = !!(entry->src_data[1] & 0x20); 553 uint32_t status = 0, cid = 0, rw = 0; 554 struct amdgpu_task_info task_info; 555 struct amdgpu_vmhub *hub; 556 const char *mmhub_cid; 557 const char *hub_name; 558 u64 addr; 559 uint32_t cam_index = 0; 560 int ret; 561 uint32_t node_id, xcc_id = 0; 562 563 node_id = entry->node_id; 564 565 addr = (u64)entry->src_data[0] << 12; 566 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 567 568 if (entry->client_id == SOC15_IH_CLIENTID_VMC) { 569 hub_name = "mmhub0"; 570 hub = &adev->vmhub[AMDGPU_MMHUB0(node_id / 4)]; 571 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) { 572 hub_name = "mmhub1"; 573 hub = &adev->vmhub[AMDGPU_MMHUB1(0)]; 574 } else { 575 hub_name = "gfxhub0"; 576 if (adev->gfx.funcs->ih_node_to_logical_xcc) { 577 xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev, 578 node_id); 579 if (xcc_id < 0) 580 xcc_id = 0; 581 } 582 hub = &adev->vmhub[xcc_id]; 583 } 584 585 if (retry_fault) { 586 if (adev->irq.retry_cam_enabled) { 587 /* Delegate it to a different ring if the hardware hasn't 588 * already done it. 589 */ 590 if (entry->ih == &adev->irq.ih) { 591 amdgpu_irq_delegate(adev, entry, 8); 592 return 1; 593 } 594 595 cam_index = entry->src_data[2] & 0x3ff; 596 597 ret = amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 598 addr, write_fault); 599 WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index); 600 if (ret) 601 return 1; 602 } else { 603 /* Process it onyl if it's the first fault for this address */ 604 if (entry->ih != &adev->irq.ih_soft && 605 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, 606 entry->timestamp)) 607 return 1; 608 609 /* Delegate it to a different ring if the hardware hasn't 610 * already done it. 611 */ 612 if (entry->ih == &adev->irq.ih) { 613 amdgpu_irq_delegate(adev, entry, 8); 614 return 1; 615 } 616 617 /* Try to handle the recoverable page faults by filling page 618 * tables 619 */ 620 if (amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 621 addr, write_fault)) 622 return 1; 623 } 624 } 625 626 if (!printk_ratelimit()) 627 return 0; 628 629 630 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 631 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 632 633 dev_err(adev->dev, 634 "[%s] %s page fault (src_id:%u ring:%u vmid:%u " 635 "pasid:%u, for process %s pid %d thread %s pid %d)\n", 636 hub_name, retry_fault ? "retry" : "no-retry", 637 entry->src_id, entry->ring_id, entry->vmid, 638 entry->pasid, task_info.process_name, task_info.tgid, 639 task_info.task_name, task_info.pid); 640 dev_err(adev->dev, " in page starting at address 0x%016llx from IH client 0x%x (%s)\n", 641 addr, entry->client_id, 642 soc15_ih_clientid_name[entry->client_id]); 643 644 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) 645 dev_err(adev->dev, " cookie node_id %d fault from die %s%d%s\n", 646 node_id, node_id % 4 == 3 ? "RSV" : "AID", node_id / 4, 647 node_id % 4 == 1 ? ".XCD0" : node_id % 4 == 2 ? ".XCD1" : ""); 648 649 if (amdgpu_sriov_vf(adev)) 650 return 0; 651 652 /* 653 * Issue a dummy read to wait for the status register to 654 * be updated to avoid reading an incorrect value due to 655 * the new fast GRBM interface. 656 */ 657 if ((entry->vmid_src == AMDGPU_GFXHUB(0)) && 658 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2))) 659 RREG32(hub->vm_l2_pro_fault_status); 660 661 status = RREG32(hub->vm_l2_pro_fault_status); 662 cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID); 663 rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW); 664 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 665 666 dev_err(adev->dev, 667 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 668 status); 669 if (entry->vmid_src == AMDGPU_GFXHUB(0)) { 670 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 671 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : 672 gfxhub_client_ids[cid], 673 cid); 674 } else { 675 switch (adev->ip_versions[MMHUB_HWIP][0]) { 676 case IP_VERSION(9, 0, 0): 677 mmhub_cid = mmhub_client_ids_vega10[cid][rw]; 678 break; 679 case IP_VERSION(9, 3, 0): 680 mmhub_cid = mmhub_client_ids_vega12[cid][rw]; 681 break; 682 case IP_VERSION(9, 4, 0): 683 mmhub_cid = mmhub_client_ids_vega20[cid][rw]; 684 break; 685 case IP_VERSION(9, 4, 1): 686 mmhub_cid = mmhub_client_ids_arcturus[cid][rw]; 687 break; 688 case IP_VERSION(9, 1, 0): 689 case IP_VERSION(9, 2, 0): 690 mmhub_cid = mmhub_client_ids_raven[cid][rw]; 691 break; 692 case IP_VERSION(1, 5, 0): 693 case IP_VERSION(2, 4, 0): 694 mmhub_cid = mmhub_client_ids_renoir[cid][rw]; 695 break; 696 case IP_VERSION(1, 8, 0): 697 case IP_VERSION(9, 4, 2): 698 mmhub_cid = mmhub_client_ids_aldebaran[cid][rw]; 699 break; 700 default: 701 mmhub_cid = NULL; 702 break; 703 } 704 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 705 mmhub_cid ? mmhub_cid : "unknown", cid); 706 } 707 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 708 REG_GET_FIELD(status, 709 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 710 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 711 REG_GET_FIELD(status, 712 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 713 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 714 REG_GET_FIELD(status, 715 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 716 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 717 REG_GET_FIELD(status, 718 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 719 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 720 return 0; 721 } 722 723 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 724 .set = gmc_v9_0_vm_fault_interrupt_state, 725 .process = gmc_v9_0_process_interrupt, 726 }; 727 728 729 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { 730 .set = gmc_v9_0_ecc_interrupt_state, 731 .process = amdgpu_umc_process_ecc_irq, 732 }; 733 734 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 735 { 736 adev->gmc.vm_fault.num_types = 1; 737 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 738 739 if (!amdgpu_sriov_vf(adev) && 740 !adev->gmc.xgmi.connected_to_cpu) { 741 adev->gmc.ecc_irq.num_types = 1; 742 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; 743 } 744 } 745 746 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, 747 uint32_t flush_type) 748 { 749 u32 req = 0; 750 751 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 752 PER_VMID_INVALIDATE_REQ, 1 << vmid); 753 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 754 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 755 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 756 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 757 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 758 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 759 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 760 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 761 762 return req; 763 } 764 765 /** 766 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore 767 * 768 * @adev: amdgpu_device pointer 769 * @vmhub: vmhub type 770 * 771 */ 772 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev, 773 uint32_t vmhub) 774 { 775 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) || 776 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) 777 return false; 778 779 return ((vmhub == AMDGPU_MMHUB0(0) || 780 vmhub == AMDGPU_MMHUB1(0)) && 781 (!amdgpu_sriov_vf(adev)) && 782 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) && 783 (adev->apu_flags & AMD_APU_IS_PICASSO)))); 784 } 785 786 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, 787 uint8_t vmid, uint16_t *p_pasid) 788 { 789 uint32_t value; 790 791 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 792 + vmid); 793 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 794 795 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 796 } 797 798 /* 799 * GART 800 * VMID 0 is the physical GPU addresses as used by the kernel. 801 * VMIDs 1-15 are used for userspace clients and are handled 802 * by the amdgpu vm/hsa code. 803 */ 804 805 /** 806 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type 807 * 808 * @adev: amdgpu_device pointer 809 * @vmid: vm instance to flush 810 * @vmhub: which hub to flush 811 * @flush_type: the flush type 812 * 813 * Flush the TLB for the requested page table using certain type. 814 */ 815 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 816 uint32_t vmhub, uint32_t flush_type) 817 { 818 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub); 819 const unsigned eng = 17; 820 u32 j, inv_req, inv_req2, tmp; 821 struct amdgpu_vmhub *hub; 822 823 BUG_ON(vmhub >= AMDGPU_MAX_VMHUBS); 824 825 hub = &adev->vmhub[vmhub]; 826 if (adev->gmc.xgmi.num_physical_nodes && 827 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0)) { 828 /* Vega20+XGMI caches PTEs in TC and TLB. Add a 829 * heavy-weight TLB flush (type 2), which flushes 830 * both. Due to a race condition with concurrent 831 * memory accesses using the same TLB cache line, we 832 * still need a second TLB flush after this. 833 */ 834 inv_req = gmc_v9_0_get_invalidate_req(vmid, 2); 835 inv_req2 = gmc_v9_0_get_invalidate_req(vmid, flush_type); 836 } else if (flush_type == 2 && 837 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3) && 838 adev->rev_id == 0) { 839 inv_req = gmc_v9_0_get_invalidate_req(vmid, 0); 840 inv_req2 = gmc_v9_0_get_invalidate_req(vmid, flush_type); 841 } else { 842 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type); 843 inv_req2 = 0; 844 } 845 846 /* This is necessary for a HW workaround under SRIOV as well 847 * as GFXOFF under bare metal 848 */ 849 if (adev->gfx.kiq[0].ring.sched.ready && 850 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && 851 down_read_trylock(&adev->reset_domain->sem)) { 852 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 853 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 854 855 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 856 1 << vmid); 857 up_read(&adev->reset_domain->sem); 858 return; 859 } 860 861 spin_lock(&adev->gmc.invalidate_lock); 862 863 /* 864 * It may lose gpuvm invalidate acknowldege state across power-gating 865 * off cycle, add semaphore acquire before invalidation and semaphore 866 * release after invalidation to avoid entering power gated state 867 * to WA the Issue 868 */ 869 870 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 871 if (use_semaphore) { 872 for (j = 0; j < adev->usec_timeout; j++) { 873 /* a read return value of 1 means semaphore acquire */ 874 if (vmhub >= AMDGPU_MMHUB0(0)) 875 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_sem + hub->eng_distance * eng); 876 else 877 tmp = RREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_sem + hub->eng_distance * eng); 878 if (tmp & 0x1) 879 break; 880 udelay(1); 881 } 882 883 if (j >= adev->usec_timeout) 884 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 885 } 886 887 do { 888 if (vmhub >= AMDGPU_MMHUB0(0)) 889 WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req); 890 else 891 WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req); 892 893 /* 894 * Issue a dummy read to wait for the ACK register to 895 * be cleared to avoid a false ACK due to the new fast 896 * GRBM interface. 897 */ 898 if ((vmhub == AMDGPU_GFXHUB(0)) && 899 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2))) 900 RREG32_NO_KIQ(hub->vm_inv_eng0_req + 901 hub->eng_distance * eng); 902 903 for (j = 0; j < adev->usec_timeout; j++) { 904 if (vmhub >= AMDGPU_MMHUB0(0)) 905 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_ack + hub->eng_distance * eng); 906 else 907 tmp = RREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_ack + hub->eng_distance * eng); 908 if (tmp & (1 << vmid)) 909 break; 910 udelay(1); 911 } 912 913 inv_req = inv_req2; 914 inv_req2 = 0; 915 } while (inv_req); 916 917 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 918 if (use_semaphore) { 919 /* 920 * add semaphore release after invalidation, 921 * write with 0 means semaphore release 922 */ 923 if (vmhub >= AMDGPU_MMHUB0(0)) 924 WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_sem + hub->eng_distance * eng, 0); 925 else 926 WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_sem + hub->eng_distance * eng, 0); 927 } 928 929 spin_unlock(&adev->gmc.invalidate_lock); 930 931 if (j < adev->usec_timeout) 932 return; 933 934 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 935 } 936 937 /** 938 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid 939 * 940 * @adev: amdgpu_device pointer 941 * @pasid: pasid to be flush 942 * @flush_type: the flush type 943 * @all_hub: flush all hubs 944 * 945 * Flush the TLB for the requested pasid. 946 */ 947 static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 948 uint16_t pasid, uint32_t flush_type, 949 bool all_hub, uint32_t inst) 950 { 951 int vmid, i; 952 signed long r; 953 uint32_t seq; 954 uint16_t queried_pasid; 955 bool ret; 956 u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT : adev->usec_timeout; 957 struct amdgpu_ring *ring = &adev->gfx.kiq[inst].ring; 958 struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst]; 959 960 if (amdgpu_in_reset(adev)) 961 return -EIO; 962 963 if (ring->sched.ready && down_read_trylock(&adev->reset_domain->sem)) { 964 /* Vega20+XGMI caches PTEs in TC and TLB. Add a 965 * heavy-weight TLB flush (type 2), which flushes 966 * both. Due to a race condition with concurrent 967 * memory accesses using the same TLB cache line, we 968 * still need a second TLB flush after this. 969 */ 970 bool vega20_xgmi_wa = (adev->gmc.xgmi.num_physical_nodes && 971 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0)); 972 /* 2 dwords flush + 8 dwords fence */ 973 unsigned int ndw = kiq->pmf->invalidate_tlbs_size + 8; 974 975 if (vega20_xgmi_wa) 976 ndw += kiq->pmf->invalidate_tlbs_size; 977 978 spin_lock(&adev->gfx.kiq[inst].ring_lock); 979 /* 2 dwords flush + 8 dwords fence */ 980 amdgpu_ring_alloc(ring, ndw); 981 if (vega20_xgmi_wa) 982 kiq->pmf->kiq_invalidate_tlbs(ring, 983 pasid, 2, all_hub); 984 985 if (flush_type == 2 && 986 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3) && 987 adev->rev_id == 0) 988 kiq->pmf->kiq_invalidate_tlbs(ring, 989 pasid, 0, all_hub); 990 991 kiq->pmf->kiq_invalidate_tlbs(ring, 992 pasid, flush_type, all_hub); 993 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 994 if (r) { 995 amdgpu_ring_undo(ring); 996 spin_unlock(&adev->gfx.kiq[inst].ring_lock); 997 up_read(&adev->reset_domain->sem); 998 return -ETIME; 999 } 1000 1001 amdgpu_ring_commit(ring); 1002 spin_unlock(&adev->gfx.kiq[inst].ring_lock); 1003 r = amdgpu_fence_wait_polling(ring, seq, usec_timeout); 1004 if (r < 1) { 1005 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r); 1006 up_read(&adev->reset_domain->sem); 1007 return -ETIME; 1008 } 1009 up_read(&adev->reset_domain->sem); 1010 return 0; 1011 } 1012 1013 for (vmid = 1; vmid < 16; vmid++) { 1014 1015 ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 1016 &queried_pasid); 1017 if (ret && queried_pasid == pasid) { 1018 if (all_hub) { 1019 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) 1020 gmc_v9_0_flush_gpu_tlb(adev, vmid, 1021 i, flush_type); 1022 } else { 1023 gmc_v9_0_flush_gpu_tlb(adev, vmid, 1024 AMDGPU_GFXHUB(0), flush_type); 1025 } 1026 break; 1027 } 1028 } 1029 1030 return 0; 1031 1032 } 1033 1034 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 1035 unsigned vmid, uint64_t pd_addr) 1036 { 1037 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 1038 struct amdgpu_device *adev = ring->adev; 1039 struct amdgpu_vmhub *hub = &adev->vmhub[ring->vm_hub]; 1040 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); 1041 unsigned eng = ring->vm_inv_eng; 1042 1043 /* 1044 * It may lose gpuvm invalidate acknowldege state across power-gating 1045 * off cycle, add semaphore acquire before invalidation and semaphore 1046 * release after invalidation to avoid entering power gated state 1047 * to WA the Issue 1048 */ 1049 1050 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 1051 if (use_semaphore) 1052 /* a read return value of 1 means semaphore acuqire */ 1053 amdgpu_ring_emit_reg_wait(ring, 1054 hub->vm_inv_eng0_sem + 1055 hub->eng_distance * eng, 0x1, 0x1); 1056 1057 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 1058 (hub->ctx_addr_distance * vmid), 1059 lower_32_bits(pd_addr)); 1060 1061 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 1062 (hub->ctx_addr_distance * vmid), 1063 upper_32_bits(pd_addr)); 1064 1065 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 1066 hub->eng_distance * eng, 1067 hub->vm_inv_eng0_ack + 1068 hub->eng_distance * eng, 1069 req, 1 << vmid); 1070 1071 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 1072 if (use_semaphore) 1073 /* 1074 * add semaphore release after invalidation, 1075 * write with 0 means semaphore release 1076 */ 1077 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 1078 hub->eng_distance * eng, 0); 1079 1080 return pd_addr; 1081 } 1082 1083 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 1084 unsigned pasid) 1085 { 1086 struct amdgpu_device *adev = ring->adev; 1087 uint32_t reg; 1088 1089 /* Do nothing because there's no lut register for mmhub1. */ 1090 if (ring->vm_hub == AMDGPU_MMHUB1(0)) 1091 return; 1092 1093 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 1094 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 1095 else 1096 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 1097 1098 amdgpu_ring_emit_wreg(ring, reg, pasid); 1099 } 1100 1101 /* 1102 * PTE format on VEGA 10: 1103 * 63:59 reserved 1104 * 58:57 mtype 1105 * 56 F 1106 * 55 L 1107 * 54 P 1108 * 53 SW 1109 * 52 T 1110 * 50:48 reserved 1111 * 47:12 4k physical page base address 1112 * 11:7 fragment 1113 * 6 write 1114 * 5 read 1115 * 4 exe 1116 * 3 Z 1117 * 2 snooped 1118 * 1 system 1119 * 0 valid 1120 * 1121 * PDE format on VEGA 10: 1122 * 63:59 block fragment size 1123 * 58:55 reserved 1124 * 54 P 1125 * 53:48 reserved 1126 * 47:6 physical base address of PD or PTE 1127 * 5:3 reserved 1128 * 2 C 1129 * 1 system 1130 * 0 valid 1131 */ 1132 1133 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 1134 1135 { 1136 switch (flags) { 1137 case AMDGPU_VM_MTYPE_DEFAULT: 1138 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1139 case AMDGPU_VM_MTYPE_NC: 1140 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1141 case AMDGPU_VM_MTYPE_WC: 1142 return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC); 1143 case AMDGPU_VM_MTYPE_RW: 1144 return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW); 1145 case AMDGPU_VM_MTYPE_CC: 1146 return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC); 1147 case AMDGPU_VM_MTYPE_UC: 1148 return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC); 1149 default: 1150 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1151 } 1152 } 1153 1154 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, 1155 uint64_t *addr, uint64_t *flags) 1156 { 1157 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 1158 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 1159 BUG_ON(*addr & 0xFFFF00000000003FULL); 1160 1161 if (!adev->gmc.translate_further) 1162 return; 1163 1164 if (level == AMDGPU_VM_PDB1) { 1165 /* Set the block fragment size */ 1166 if (!(*flags & AMDGPU_PDE_PTE)) 1167 *flags |= AMDGPU_PDE_BFS(0x9); 1168 1169 } else if (level == AMDGPU_VM_PDB0) { 1170 if (*flags & AMDGPU_PDE_PTE) { 1171 *flags &= ~AMDGPU_PDE_PTE; 1172 if (!(*flags & AMDGPU_PTE_VALID)) 1173 *addr |= 1 << PAGE_SHIFT; 1174 } else { 1175 *flags |= AMDGPU_PTE_TF; 1176 } 1177 } 1178 } 1179 1180 static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev, 1181 struct amdgpu_bo *bo, 1182 struct amdgpu_bo_va_mapping *mapping, 1183 uint64_t *flags) 1184 { 1185 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev); 1186 bool is_vram = bo->tbo.resource->mem_type == TTM_PL_VRAM; 1187 bool coherent = bo->flags & AMDGPU_GEM_CREATE_COHERENT; 1188 bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED; 1189 struct amdgpu_vm *vm = mapping->bo_va->base.vm; 1190 unsigned int mtype_local, mtype; 1191 bool snoop = false; 1192 bool is_local; 1193 1194 switch (adev->ip_versions[GC_HWIP][0]) { 1195 case IP_VERSION(9, 4, 1): 1196 case IP_VERSION(9, 4, 2): 1197 if (is_vram) { 1198 if (bo_adev == adev) { 1199 if (uncached) 1200 mtype = MTYPE_UC; 1201 else if (coherent) 1202 mtype = MTYPE_CC; 1203 else 1204 mtype = MTYPE_RW; 1205 /* FIXME: is this still needed? Or does 1206 * amdgpu_ttm_tt_pde_flags already handle this? 1207 */ 1208 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) || 1209 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) && 1210 adev->gmc.xgmi.connected_to_cpu) 1211 snoop = true; 1212 } else { 1213 if (uncached || coherent) 1214 mtype = MTYPE_UC; 1215 else 1216 mtype = MTYPE_NC; 1217 if (mapping->bo_va->is_xgmi) 1218 snoop = true; 1219 } 1220 } else { 1221 if (uncached || coherent) 1222 mtype = MTYPE_UC; 1223 else 1224 mtype = MTYPE_NC; 1225 /* FIXME: is this still needed? Or does 1226 * amdgpu_ttm_tt_pde_flags already handle this? 1227 */ 1228 snoop = true; 1229 } 1230 break; 1231 case IP_VERSION(9, 4, 3): 1232 /* Only local VRAM BOs or system memory on non-NUMA APUs 1233 * can be assumed to be local in their entirety. Choose 1234 * MTYPE_NC as safe fallback for all system memory BOs on 1235 * NUMA systems. Their MTYPE can be overridden per-page in 1236 * gmc_v9_0_override_vm_pte_flags. 1237 */ 1238 mtype_local = MTYPE_RW; 1239 if (amdgpu_mtype_local == 1) { 1240 DRM_INFO_ONCE("Using MTYPE_NC for local memory\n"); 1241 mtype_local = MTYPE_NC; 1242 } else if (amdgpu_mtype_local == 2) { 1243 DRM_INFO_ONCE("Using MTYPE_CC for local memory\n"); 1244 mtype_local = MTYPE_CC; 1245 } else { 1246 DRM_INFO_ONCE("Using MTYPE_RW for local memory\n"); 1247 } 1248 is_local = (!is_vram && (adev->flags & AMD_IS_APU) && 1249 num_possible_nodes() <= 1) || 1250 (is_vram && adev == bo_adev && 1251 bo->mem_id == vm->mem_id); 1252 snoop = true; 1253 if (uncached) { 1254 mtype = MTYPE_UC; 1255 } else if (adev->flags & AMD_IS_APU) { 1256 mtype = is_local ? mtype_local : MTYPE_NC; 1257 } else { 1258 /* dGPU */ 1259 if (is_local) 1260 mtype = mtype_local; 1261 else if (is_vram) 1262 mtype = MTYPE_NC; 1263 else 1264 mtype = MTYPE_UC; 1265 } 1266 1267 break; 1268 default: 1269 if (uncached || coherent) 1270 mtype = MTYPE_UC; 1271 else 1272 mtype = MTYPE_NC; 1273 1274 /* FIXME: is this still needed? Or does 1275 * amdgpu_ttm_tt_pde_flags already handle this? 1276 */ 1277 if (!is_vram) 1278 snoop = true; 1279 } 1280 1281 if (mtype != MTYPE_NC) 1282 *flags = (*flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) | 1283 AMDGPU_PTE_MTYPE_VG10(mtype); 1284 *flags |= snoop ? AMDGPU_PTE_SNOOPED : 0; 1285 } 1286 1287 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev, 1288 struct amdgpu_bo_va_mapping *mapping, 1289 uint64_t *flags) 1290 { 1291 struct amdgpu_bo *bo = mapping->bo_va->base.bo; 1292 1293 *flags &= ~AMDGPU_PTE_EXECUTABLE; 1294 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 1295 1296 *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 1297 *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK; 1298 1299 if (mapping->flags & AMDGPU_PTE_PRT) { 1300 *flags |= AMDGPU_PTE_PRT; 1301 *flags &= ~AMDGPU_PTE_VALID; 1302 } 1303 1304 if (bo && bo->tbo.resource) 1305 gmc_v9_0_get_coherence_flags(adev, mapping->bo_va->base.bo, 1306 mapping, flags); 1307 } 1308 1309 static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev, 1310 struct amdgpu_vm *vm, 1311 uint64_t addr, uint64_t *flags) 1312 { 1313 int local_node, nid; 1314 1315 /* Only GFX 9.4.3 APUs associate GPUs with NUMA nodes. Local system 1316 * memory can use more efficient MTYPEs. 1317 */ 1318 if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 3)) 1319 return; 1320 1321 /* Only direct-mapped memory allows us to determine the NUMA node from 1322 * the DMA address. 1323 */ 1324 if (!adev->ram_is_direct_mapped) { 1325 dev_dbg(adev->dev, "RAM is not direct mapped\n"); 1326 return; 1327 } 1328 1329 /* Only override mappings with MTYPE_NC, which is the safe default for 1330 * cacheable memory. 1331 */ 1332 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) != 1333 AMDGPU_PTE_MTYPE_VG10(MTYPE_NC)) { 1334 dev_dbg(adev->dev, "MTYPE is not NC\n"); 1335 return; 1336 } 1337 1338 /* FIXME: Only supported on native mode for now. For carve-out, the 1339 * NUMA affinity of the GPU/VM needs to come from the PCI info because 1340 * memory partitions are not associated with different NUMA nodes. 1341 */ 1342 if (adev->gmc.is_app_apu && vm->mem_id >= 0) { 1343 local_node = adev->gmc.mem_partitions[vm->mem_id].numa.node; 1344 } else { 1345 dev_dbg(adev->dev, "Only native mode APU is supported.\n"); 1346 return; 1347 } 1348 1349 /* Only handle real RAM. Mappings of PCIe resources don't have struct 1350 * page or NUMA nodes. 1351 */ 1352 if (!page_is_ram(addr >> PAGE_SHIFT)) { 1353 dev_dbg(adev->dev, "Page is not RAM.\n"); 1354 return; 1355 } 1356 nid = pfn_to_nid(addr >> PAGE_SHIFT); 1357 dev_dbg(adev->dev, "vm->mem_id=%d, local_node=%d, nid=%d\n", 1358 vm->mem_id, local_node, nid); 1359 if (nid == local_node) { 1360 uint64_t old_flags = *flags; 1361 unsigned int mtype_local = MTYPE_RW; 1362 1363 if (amdgpu_mtype_local == 1) 1364 mtype_local = MTYPE_NC; 1365 else if (amdgpu_mtype_local == 2) 1366 mtype_local = MTYPE_CC; 1367 1368 *flags = (*flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) | 1369 AMDGPU_PTE_MTYPE_VG10(mtype_local); 1370 dev_dbg(adev->dev, "flags updated from %llx to %llx\n", 1371 old_flags, *flags); 1372 } 1373 } 1374 1375 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 1376 { 1377 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 1378 unsigned size; 1379 1380 /* TODO move to DC so GMC doesn't need to hard-code DCN registers */ 1381 1382 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1383 size = AMDGPU_VBIOS_VGA_ALLOCATION; 1384 } else { 1385 u32 viewport; 1386 1387 switch (adev->ip_versions[DCE_HWIP][0]) { 1388 case IP_VERSION(1, 0, 0): 1389 case IP_VERSION(1, 0, 1): 1390 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 1391 size = (REG_GET_FIELD(viewport, 1392 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1393 REG_GET_FIELD(viewport, 1394 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1395 4); 1396 break; 1397 case IP_VERSION(2, 1, 0): 1398 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2); 1399 size = (REG_GET_FIELD(viewport, 1400 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1401 REG_GET_FIELD(viewport, 1402 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1403 4); 1404 break; 1405 default: 1406 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); 1407 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1408 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1409 4); 1410 break; 1411 } 1412 } 1413 1414 return size; 1415 } 1416 1417 static enum amdgpu_memory_partition 1418 gmc_v9_0_get_memory_partition(struct amdgpu_device *adev, u32 *supp_modes) 1419 { 1420 enum amdgpu_memory_partition mode = UNKNOWN_MEMORY_PARTITION_MODE; 1421 1422 if (adev->nbio.funcs->get_memory_partition_mode) 1423 mode = adev->nbio.funcs->get_memory_partition_mode(adev, 1424 supp_modes); 1425 1426 return mode; 1427 } 1428 1429 static enum amdgpu_memory_partition 1430 gmc_v9_0_query_memory_partition(struct amdgpu_device *adev) 1431 { 1432 if (amdgpu_sriov_vf(adev)) 1433 return AMDGPU_NPS1_PARTITION_MODE; 1434 1435 return gmc_v9_0_get_memory_partition(adev, NULL); 1436 } 1437 1438 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { 1439 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, 1440 .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid, 1441 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, 1442 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, 1443 .map_mtype = gmc_v9_0_map_mtype, 1444 .get_vm_pde = gmc_v9_0_get_vm_pde, 1445 .get_vm_pte = gmc_v9_0_get_vm_pte, 1446 .override_vm_pte_flags = gmc_v9_0_override_vm_pte_flags, 1447 .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size, 1448 .query_mem_partition_mode = &gmc_v9_0_query_memory_partition, 1449 }; 1450 1451 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) 1452 { 1453 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; 1454 } 1455 1456 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) 1457 { 1458 switch (adev->ip_versions[UMC_HWIP][0]) { 1459 case IP_VERSION(6, 0, 0): 1460 adev->umc.funcs = &umc_v6_0_funcs; 1461 break; 1462 case IP_VERSION(6, 1, 1): 1463 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1464 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1465 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1466 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20; 1467 adev->umc.retire_unit = 1; 1468 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1469 adev->umc.ras = &umc_v6_1_ras; 1470 break; 1471 case IP_VERSION(6, 1, 2): 1472 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1473 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1474 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1475 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT; 1476 adev->umc.retire_unit = 1; 1477 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1478 adev->umc.ras = &umc_v6_1_ras; 1479 break; 1480 case IP_VERSION(6, 7, 0): 1481 adev->umc.max_ras_err_cnt_per_query = 1482 UMC_V6_7_TOTAL_CHANNEL_NUM * UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL; 1483 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM; 1484 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM; 1485 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET; 1486 adev->umc.retire_unit = (UMC_V6_7_NA_MAP_PA_NUM * 2); 1487 if (!adev->gmc.xgmi.connected_to_cpu) 1488 adev->umc.ras = &umc_v6_7_ras; 1489 if (1 & adev->smuio.funcs->get_die_id(adev)) 1490 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0]; 1491 else 1492 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0]; 1493 break; 1494 default: 1495 break; 1496 } 1497 } 1498 1499 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) 1500 { 1501 switch (adev->ip_versions[MMHUB_HWIP][0]) { 1502 case IP_VERSION(9, 4, 1): 1503 adev->mmhub.funcs = &mmhub_v9_4_funcs; 1504 break; 1505 case IP_VERSION(9, 4, 2): 1506 adev->mmhub.funcs = &mmhub_v1_7_funcs; 1507 break; 1508 case IP_VERSION(1, 8, 0): 1509 adev->mmhub.funcs = &mmhub_v1_8_funcs; 1510 break; 1511 default: 1512 adev->mmhub.funcs = &mmhub_v1_0_funcs; 1513 break; 1514 } 1515 } 1516 1517 static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev) 1518 { 1519 switch (adev->ip_versions[MMHUB_HWIP][0]) { 1520 case IP_VERSION(9, 4, 0): 1521 adev->mmhub.ras = &mmhub_v1_0_ras; 1522 break; 1523 case IP_VERSION(9, 4, 1): 1524 adev->mmhub.ras = &mmhub_v9_4_ras; 1525 break; 1526 case IP_VERSION(9, 4, 2): 1527 adev->mmhub.ras = &mmhub_v1_7_ras; 1528 break; 1529 case IP_VERSION(1, 8, 0): 1530 adev->mmhub.ras = &mmhub_v1_8_ras; 1531 break; 1532 default: 1533 /* mmhub ras is not available */ 1534 break; 1535 } 1536 } 1537 1538 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev) 1539 { 1540 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) 1541 adev->gfxhub.funcs = &gfxhub_v1_2_funcs; 1542 else 1543 adev->gfxhub.funcs = &gfxhub_v1_0_funcs; 1544 } 1545 1546 static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev) 1547 { 1548 adev->hdp.ras = &hdp_v4_0_ras; 1549 } 1550 1551 static void gmc_v9_0_set_mca_ras_funcs(struct amdgpu_device *adev) 1552 { 1553 struct amdgpu_mca *mca = &adev->mca; 1554 1555 /* is UMC the right IP to check for MCA? Maybe DF? */ 1556 switch (adev->ip_versions[UMC_HWIP][0]) { 1557 case IP_VERSION(6, 7, 0): 1558 if (!adev->gmc.xgmi.connected_to_cpu) { 1559 mca->mp0.ras = &mca_v3_0_mp0_ras; 1560 mca->mp1.ras = &mca_v3_0_mp1_ras; 1561 mca->mpio.ras = &mca_v3_0_mpio_ras; 1562 } 1563 break; 1564 default: 1565 break; 1566 } 1567 } 1568 1569 static void gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device *adev) 1570 { 1571 if (!adev->gmc.xgmi.connected_to_cpu) 1572 adev->gmc.xgmi.ras = &xgmi_ras; 1573 } 1574 1575 static int gmc_v9_0_early_init(void *handle) 1576 { 1577 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1578 1579 /* 1580 * 9.4.0, 9.4.1 and 9.4.3 don't have XGMI defined 1581 * in their IP discovery tables 1582 */ 1583 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0) || 1584 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) || 1585 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) 1586 adev->gmc.xgmi.supported = true; 1587 1588 if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(6, 1, 0)) { 1589 adev->gmc.xgmi.supported = true; 1590 adev->gmc.xgmi.connected_to_cpu = 1591 adev->smuio.funcs->is_host_gpu_xgmi_supported(adev); 1592 } 1593 1594 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) { 1595 enum amdgpu_pkg_type pkg_type = 1596 adev->smuio.funcs->get_pkg_type(adev); 1597 /* On GFXIP 9.4.3. APU, there is no physical VRAM domain present 1598 * and the APU, can be in used two possible modes: 1599 * - carveout mode 1600 * - native APU mode 1601 * "is_app_apu" can be used to identify the APU in the native 1602 * mode. 1603 */ 1604 adev->gmc.is_app_apu = (pkg_type == AMDGPU_PKG_TYPE_APU && 1605 !pci_resource_len(adev->pdev, 0)); 1606 } 1607 1608 gmc_v9_0_set_gmc_funcs(adev); 1609 gmc_v9_0_set_irq_funcs(adev); 1610 gmc_v9_0_set_umc_funcs(adev); 1611 gmc_v9_0_set_mmhub_funcs(adev); 1612 gmc_v9_0_set_mmhub_ras_funcs(adev); 1613 gmc_v9_0_set_gfxhub_funcs(adev); 1614 gmc_v9_0_set_hdp_ras_funcs(adev); 1615 gmc_v9_0_set_mca_ras_funcs(adev); 1616 gmc_v9_0_set_xgmi_ras_funcs(adev); 1617 1618 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1619 adev->gmc.shared_aperture_end = 1620 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1621 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 1622 adev->gmc.private_aperture_end = 1623 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1624 1625 return 0; 1626 } 1627 1628 static int gmc_v9_0_late_init(void *handle) 1629 { 1630 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1631 int r; 1632 1633 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 1634 if (r) 1635 return r; 1636 1637 /* 1638 * Workaround performance drop issue with VBIOS enables partial 1639 * writes, while disables HBM ECC for vega10. 1640 */ 1641 if (!amdgpu_sriov_vf(adev) && 1642 (adev->ip_versions[UMC_HWIP][0] == IP_VERSION(6, 0, 0))) { 1643 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) { 1644 if (adev->df.funcs && 1645 adev->df.funcs->enable_ecc_force_par_wr_rmw) 1646 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false); 1647 } 1648 } 1649 1650 if (!amdgpu_persistent_edc_harvesting_supported(adev)) { 1651 if (adev->mmhub.ras && adev->mmhub.ras->ras_block.hw_ops && 1652 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count) 1653 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(adev); 1654 1655 if (adev->hdp.ras && adev->hdp.ras->ras_block.hw_ops && 1656 adev->hdp.ras->ras_block.hw_ops->reset_ras_error_count) 1657 adev->hdp.ras->ras_block.hw_ops->reset_ras_error_count(adev); 1658 } 1659 1660 r = amdgpu_gmc_ras_late_init(adev); 1661 if (r) 1662 return r; 1663 1664 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1665 } 1666 1667 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 1668 struct amdgpu_gmc *mc) 1669 { 1670 u64 base = adev->mmhub.funcs->get_fb_location(adev); 1671 1672 /* add the xgmi offset of the physical node */ 1673 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1674 if (adev->gmc.xgmi.connected_to_cpu) { 1675 amdgpu_gmc_sysvm_location(adev, mc); 1676 } else { 1677 amdgpu_gmc_vram_location(adev, mc, base); 1678 amdgpu_gmc_gart_location(adev, mc); 1679 amdgpu_gmc_agp_location(adev, mc); 1680 } 1681 /* base offset of vram pages */ 1682 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 1683 1684 /* XXX: add the xgmi offset of the physical node? */ 1685 adev->vm_manager.vram_base_offset += 1686 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1687 } 1688 1689 /** 1690 * gmc_v9_0_mc_init - initialize the memory controller driver params 1691 * 1692 * @adev: amdgpu_device pointer 1693 * 1694 * Look up the amount of vram, vram width, and decide how to place 1695 * vram and gart within the GPU's physical address space. 1696 * Returns 0 for success. 1697 */ 1698 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 1699 { 1700 int r; 1701 1702 /* size in MB on si */ 1703 if (!adev->gmc.is_app_apu) { 1704 adev->gmc.mc_vram_size = 1705 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 1706 } else { 1707 DRM_DEBUG("Set mc_vram_size = 0 for APP APU\n"); 1708 adev->gmc.mc_vram_size = 0; 1709 } 1710 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 1711 1712 if (!(adev->flags & AMD_IS_APU) && 1713 !adev->gmc.xgmi.connected_to_cpu) { 1714 r = amdgpu_device_resize_fb_bar(adev); 1715 if (r) 1716 return r; 1717 } 1718 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 1719 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 1720 1721 #ifdef CONFIG_X86_64 1722 /* 1723 * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi 1724 * interface can use VRAM through here as it appears system reserved 1725 * memory in host address space. 1726 * 1727 * For APUs, VRAM is just the stolen system memory and can be accessed 1728 * directly. 1729 * 1730 * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR. 1731 */ 1732 1733 /* check whether both host-gpu and gpu-gpu xgmi links exist */ 1734 if ((!amdgpu_sriov_vf(adev) && 1735 (adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) || 1736 (adev->gmc.xgmi.supported && 1737 adev->gmc.xgmi.connected_to_cpu)) { 1738 adev->gmc.aper_base = 1739 adev->gfxhub.funcs->get_mc_fb_offset(adev) + 1740 adev->gmc.xgmi.physical_node_id * 1741 adev->gmc.xgmi.node_segment_size; 1742 adev->gmc.aper_size = adev->gmc.real_vram_size; 1743 } 1744 1745 #endif 1746 adev->gmc.visible_vram_size = adev->gmc.aper_size; 1747 1748 /* set the gart size */ 1749 if (amdgpu_gart_size == -1) { 1750 switch (adev->ip_versions[GC_HWIP][0]) { 1751 case IP_VERSION(9, 0, 1): /* all engines support GPUVM */ 1752 case IP_VERSION(9, 2, 1): /* all engines support GPUVM */ 1753 case IP_VERSION(9, 4, 0): 1754 case IP_VERSION(9, 4, 1): 1755 case IP_VERSION(9, 4, 2): 1756 case IP_VERSION(9, 4, 3): 1757 default: 1758 adev->gmc.gart_size = 512ULL << 20; 1759 break; 1760 case IP_VERSION(9, 1, 0): /* DCE SG support */ 1761 case IP_VERSION(9, 2, 2): /* DCE SG support */ 1762 case IP_VERSION(9, 3, 0): 1763 adev->gmc.gart_size = 1024ULL << 20; 1764 break; 1765 } 1766 } else { 1767 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 1768 } 1769 1770 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; 1771 1772 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); 1773 1774 return 0; 1775 } 1776 1777 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 1778 { 1779 int r; 1780 1781 if (adev->gart.bo) { 1782 WARN(1, "VEGA10 PCIE GART already initialized\n"); 1783 return 0; 1784 } 1785 1786 if (adev->gmc.xgmi.connected_to_cpu) { 1787 adev->gmc.vmid0_page_table_depth = 1; 1788 adev->gmc.vmid0_page_table_block_size = 12; 1789 } else { 1790 adev->gmc.vmid0_page_table_depth = 0; 1791 adev->gmc.vmid0_page_table_block_size = 0; 1792 } 1793 1794 /* Initialize common gart structure */ 1795 r = amdgpu_gart_init(adev); 1796 if (r) 1797 return r; 1798 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 1799 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) | 1800 AMDGPU_PTE_EXECUTABLE; 1801 1802 if (!adev->gmc.real_vram_size) { 1803 dev_info(adev->dev, "Put GART in system memory for APU\n"); 1804 r = amdgpu_gart_table_ram_alloc(adev); 1805 if (r) 1806 dev_err(adev->dev, "Failed to allocate GART in system memory\n"); 1807 } else { 1808 r = amdgpu_gart_table_vram_alloc(adev); 1809 if (r) 1810 return r; 1811 1812 if (adev->gmc.xgmi.connected_to_cpu) 1813 r = amdgpu_gmc_pdb0_alloc(adev); 1814 } 1815 1816 return r; 1817 } 1818 1819 /** 1820 * gmc_v9_0_save_registers - saves regs 1821 * 1822 * @adev: amdgpu_device pointer 1823 * 1824 * This saves potential register values that should be 1825 * restored upon resume 1826 */ 1827 static void gmc_v9_0_save_registers(struct amdgpu_device *adev) 1828 { 1829 if ((adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 0)) || 1830 (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 1))) 1831 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); 1832 } 1833 1834 static bool gmc_v9_0_validate_partition_info(struct amdgpu_device *adev) 1835 { 1836 enum amdgpu_memory_partition mode; 1837 u32 supp_modes; 1838 bool valid; 1839 1840 mode = gmc_v9_0_get_memory_partition(adev, &supp_modes); 1841 1842 /* Mode detected by hardware not present in supported modes */ 1843 if ((mode != UNKNOWN_MEMORY_PARTITION_MODE) && 1844 !(BIT(mode - 1) & supp_modes)) 1845 return false; 1846 1847 switch (mode) { 1848 case UNKNOWN_MEMORY_PARTITION_MODE: 1849 case AMDGPU_NPS1_PARTITION_MODE: 1850 valid = (adev->gmc.num_mem_partitions == 1); 1851 break; 1852 case AMDGPU_NPS2_PARTITION_MODE: 1853 valid = (adev->gmc.num_mem_partitions == 2); 1854 break; 1855 case AMDGPU_NPS4_PARTITION_MODE: 1856 valid = (adev->gmc.num_mem_partitions == 3 || 1857 adev->gmc.num_mem_partitions == 4); 1858 break; 1859 default: 1860 valid = false; 1861 } 1862 1863 return valid; 1864 } 1865 1866 static bool gmc_v9_0_is_node_present(int *node_ids, int num_ids, int nid) 1867 { 1868 int i; 1869 1870 /* Check if node with id 'nid' is present in 'node_ids' array */ 1871 for (i = 0; i < num_ids; ++i) 1872 if (node_ids[i] == nid) 1873 return true; 1874 1875 return false; 1876 } 1877 1878 static void 1879 gmc_v9_0_init_acpi_mem_ranges(struct amdgpu_device *adev, 1880 struct amdgpu_mem_partition_info *mem_ranges) 1881 { 1882 int num_ranges = 0, ret, mem_groups; 1883 struct amdgpu_numa_info numa_info; 1884 int node_ids[MAX_MEM_RANGES]; 1885 int num_xcc, xcc_id; 1886 uint32_t xcc_mask; 1887 1888 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1889 xcc_mask = (1U << num_xcc) - 1; 1890 mem_groups = hweight32(adev->aid_mask); 1891 1892 for_each_inst(xcc_id, xcc_mask) { 1893 ret = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); 1894 if (ret) 1895 continue; 1896 1897 if (numa_info.nid == NUMA_NO_NODE) { 1898 mem_ranges[0].size = numa_info.size; 1899 mem_ranges[0].numa.node = numa_info.nid; 1900 num_ranges = 1; 1901 break; 1902 } 1903 1904 if (gmc_v9_0_is_node_present(node_ids, num_ranges, 1905 numa_info.nid)) 1906 continue; 1907 1908 node_ids[num_ranges] = numa_info.nid; 1909 mem_ranges[num_ranges].numa.node = numa_info.nid; 1910 mem_ranges[num_ranges].size = numa_info.size; 1911 ++num_ranges; 1912 } 1913 1914 adev->gmc.num_mem_partitions = num_ranges; 1915 1916 /* If there is only partition, don't use entire size */ 1917 if (adev->gmc.num_mem_partitions == 1) 1918 mem_ranges[0].size = 1919 (mem_ranges[0].size * (mem_groups - 1) / mem_groups); 1920 } 1921 1922 static void 1923 gmc_v9_0_init_sw_mem_ranges(struct amdgpu_device *adev, 1924 struct amdgpu_mem_partition_info *mem_ranges) 1925 { 1926 enum amdgpu_memory_partition mode; 1927 u32 start_addr = 0, size; 1928 int i; 1929 1930 mode = gmc_v9_0_query_memory_partition(adev); 1931 1932 switch (mode) { 1933 case UNKNOWN_MEMORY_PARTITION_MODE: 1934 case AMDGPU_NPS1_PARTITION_MODE: 1935 adev->gmc.num_mem_partitions = 1; 1936 break; 1937 case AMDGPU_NPS2_PARTITION_MODE: 1938 adev->gmc.num_mem_partitions = 2; 1939 break; 1940 case AMDGPU_NPS4_PARTITION_MODE: 1941 if (adev->flags & AMD_IS_APU) 1942 adev->gmc.num_mem_partitions = 3; 1943 else 1944 adev->gmc.num_mem_partitions = 4; 1945 break; 1946 default: 1947 adev->gmc.num_mem_partitions = 1; 1948 break; 1949 } 1950 1951 size = (adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT) / 1952 adev->gmc.num_mem_partitions; 1953 1954 for (i = 0; i < adev->gmc.num_mem_partitions; ++i) { 1955 mem_ranges[i].range.fpfn = start_addr; 1956 mem_ranges[i].size = ((u64)size << AMDGPU_GPU_PAGE_SHIFT); 1957 mem_ranges[i].range.lpfn = start_addr + size - 1; 1958 start_addr += size; 1959 } 1960 1961 /* Adjust the last one */ 1962 mem_ranges[adev->gmc.num_mem_partitions - 1].range.lpfn = 1963 (adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT) - 1; 1964 mem_ranges[adev->gmc.num_mem_partitions - 1].size = 1965 adev->gmc.real_vram_size - 1966 ((u64)mem_ranges[adev->gmc.num_mem_partitions - 1].range.fpfn 1967 << AMDGPU_GPU_PAGE_SHIFT); 1968 } 1969 1970 static int gmc_v9_0_init_mem_ranges(struct amdgpu_device *adev) 1971 { 1972 bool valid; 1973 1974 adev->gmc.mem_partitions = kzalloc( 1975 MAX_MEM_RANGES * sizeof(struct amdgpu_mem_partition_info), 1976 GFP_KERNEL); 1977 1978 if (!adev->gmc.mem_partitions) 1979 return -ENOMEM; 1980 1981 /* TODO : Get the range from PSP/Discovery for dGPU */ 1982 if (adev->gmc.is_app_apu) 1983 gmc_v9_0_init_acpi_mem_ranges(adev, adev->gmc.mem_partitions); 1984 else 1985 gmc_v9_0_init_sw_mem_ranges(adev, adev->gmc.mem_partitions); 1986 1987 if (amdgpu_sriov_vf(adev)) 1988 valid = true; 1989 else 1990 valid = gmc_v9_0_validate_partition_info(adev); 1991 if (!valid) { 1992 /* TODO: handle invalid case */ 1993 dev_WARN(adev->dev, 1994 "Mem ranges not matching with hardware config"); 1995 } 1996 1997 return 0; 1998 } 1999 2000 static int gmc_v9_0_sw_init(void *handle) 2001 { 2002 int r, vram_width = 0, vram_type = 0, vram_vendor = 0, dma_addr_bits; 2003 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2004 unsigned long inst_mask = adev->aid_mask; 2005 2006 adev->gfxhub.funcs->init(adev); 2007 2008 adev->mmhub.funcs->init(adev); 2009 2010 spin_lock_init(&adev->gmc.invalidate_lock); 2011 2012 r = amdgpu_atomfirmware_get_vram_info(adev, 2013 &vram_width, &vram_type, &vram_vendor); 2014 if (amdgpu_sriov_vf(adev)) 2015 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, 2016 * and DF related registers is not readable, seems hardcord is the 2017 * only way to set the correct vram_width 2018 */ 2019 adev->gmc.vram_width = 2048; 2020 else if (amdgpu_emu_mode != 1) 2021 adev->gmc.vram_width = vram_width; 2022 2023 if (!adev->gmc.vram_width) { 2024 int chansize, numchan; 2025 2026 /* hbm memory channel size */ 2027 if (adev->flags & AMD_IS_APU) 2028 chansize = 64; 2029 else 2030 chansize = 128; 2031 if (adev->df.funcs && 2032 adev->df.funcs->get_hbm_channel_number) { 2033 numchan = adev->df.funcs->get_hbm_channel_number(adev); 2034 adev->gmc.vram_width = numchan * chansize; 2035 } 2036 } 2037 2038 adev->gmc.vram_type = vram_type; 2039 adev->gmc.vram_vendor = vram_vendor; 2040 switch (adev->ip_versions[GC_HWIP][0]) { 2041 case IP_VERSION(9, 1, 0): 2042 case IP_VERSION(9, 2, 2): 2043 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2044 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2045 2046 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 2047 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2048 } else { 2049 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 2050 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 2051 adev->gmc.translate_further = 2052 adev->vm_manager.num_level > 1; 2053 } 2054 break; 2055 case IP_VERSION(9, 0, 1): 2056 case IP_VERSION(9, 2, 1): 2057 case IP_VERSION(9, 4, 0): 2058 case IP_VERSION(9, 3, 0): 2059 case IP_VERSION(9, 4, 2): 2060 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2061 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2062 2063 /* 2064 * To fulfill 4-level page support, 2065 * vm size is 256TB (48bit), maximum size of Vega10, 2066 * block size 512 (9bit) 2067 */ 2068 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */ 2069 if (amdgpu_sriov_vf(adev)) 2070 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47); 2071 else 2072 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2073 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) 2074 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2075 break; 2076 case IP_VERSION(9, 4, 1): 2077 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2078 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2079 set_bit(AMDGPU_MMHUB1(0), adev->vmhubs_mask); 2080 2081 /* Keep the vm size same with Vega20 */ 2082 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2083 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2084 break; 2085 case IP_VERSION(9, 4, 3): 2086 bitmap_set(adev->vmhubs_mask, AMDGPU_GFXHUB(0), 2087 NUM_XCC(adev->gfx.xcc_mask)); 2088 2089 inst_mask <<= AMDGPU_MMHUB0(0); 2090 bitmap_or(adev->vmhubs_mask, adev->vmhubs_mask, &inst_mask, 32); 2091 2092 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2093 break; 2094 default: 2095 break; 2096 } 2097 2098 /* This interrupt is VMC page fault.*/ 2099 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, 2100 &adev->gmc.vm_fault); 2101 if (r) 2102 return r; 2103 2104 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)) { 2105 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT, 2106 &adev->gmc.vm_fault); 2107 if (r) 2108 return r; 2109 } 2110 2111 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, 2112 &adev->gmc.vm_fault); 2113 2114 if (r) 2115 return r; 2116 2117 if (!amdgpu_sriov_vf(adev) && 2118 !adev->gmc.xgmi.connected_to_cpu) { 2119 /* interrupt sent to DF. */ 2120 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 2121 &adev->gmc.ecc_irq); 2122 if (r) 2123 return r; 2124 } 2125 2126 /* Set the internal MC address mask 2127 * This is the max address of the GPU's 2128 * internal address space. 2129 */ 2130 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 2131 2132 dma_addr_bits = adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2) ? 48:44; 2133 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(dma_addr_bits)); 2134 if (r) { 2135 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 2136 return r; 2137 } 2138 adev->need_swiotlb = drm_need_swiotlb(dma_addr_bits); 2139 2140 r = gmc_v9_0_mc_init(adev); 2141 if (r) 2142 return r; 2143 2144 amdgpu_gmc_get_vbios_allocations(adev); 2145 2146 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) { 2147 r = gmc_v9_0_init_mem_ranges(adev); 2148 if (r) 2149 return r; 2150 } 2151 2152 /* Memory manager */ 2153 r = amdgpu_bo_init(adev); 2154 if (r) 2155 return r; 2156 2157 r = gmc_v9_0_gart_init(adev); 2158 if (r) 2159 return r; 2160 2161 /* 2162 * number of VMs 2163 * VMID 0 is reserved for System 2164 * amdgpu graphics/compute will use VMIDs 1..n-1 2165 * amdkfd will use VMIDs n..15 2166 * 2167 * The first KFD VMID is 8 for GPUs with graphics, 3 for 2168 * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs 2169 * for video processing. 2170 */ 2171 adev->vm_manager.first_kfd_vmid = 2172 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) || 2173 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) || 2174 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) ? 3 : 8; 2175 2176 amdgpu_vm_manager_init(adev); 2177 2178 gmc_v9_0_save_registers(adev); 2179 2180 r = amdgpu_gmc_ras_sw_init(adev); 2181 if (r) 2182 return r; 2183 2184 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) 2185 amdgpu_gmc_sysfs_init(adev); 2186 2187 return 0; 2188 } 2189 2190 static int gmc_v9_0_sw_fini(void *handle) 2191 { 2192 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2193 2194 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) 2195 amdgpu_gmc_sysfs_fini(adev); 2196 adev->gmc.num_mem_partitions = 0; 2197 kfree(adev->gmc.mem_partitions); 2198 2199 amdgpu_gmc_ras_fini(adev); 2200 amdgpu_gem_force_release(adev); 2201 amdgpu_vm_manager_fini(adev); 2202 if (!adev->gmc.real_vram_size) { 2203 dev_info(adev->dev, "Put GART in system memory for APU free\n"); 2204 amdgpu_gart_table_ram_free(adev); 2205 } else { 2206 amdgpu_gart_table_vram_free(adev); 2207 } 2208 amdgpu_bo_free_kernel(&adev->gmc.pdb0_bo, NULL, &adev->gmc.ptr_pdb0); 2209 amdgpu_bo_fini(adev); 2210 2211 return 0; 2212 } 2213 2214 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 2215 { 2216 2217 switch (adev->ip_versions[MMHUB_HWIP][0]) { 2218 case IP_VERSION(9, 0, 0): 2219 if (amdgpu_sriov_vf(adev)) 2220 break; 2221 fallthrough; 2222 case IP_VERSION(9, 4, 0): 2223 soc15_program_register_sequence(adev, 2224 golden_settings_mmhub_1_0_0, 2225 ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 2226 soc15_program_register_sequence(adev, 2227 golden_settings_athub_1_0_0, 2228 ARRAY_SIZE(golden_settings_athub_1_0_0)); 2229 break; 2230 case IP_VERSION(9, 1, 0): 2231 case IP_VERSION(9, 2, 0): 2232 /* TODO for renoir */ 2233 soc15_program_register_sequence(adev, 2234 golden_settings_athub_1_0_0, 2235 ARRAY_SIZE(golden_settings_athub_1_0_0)); 2236 break; 2237 default: 2238 break; 2239 } 2240 } 2241 2242 /** 2243 * gmc_v9_0_restore_registers - restores regs 2244 * 2245 * @adev: amdgpu_device pointer 2246 * 2247 * This restores register values, saved at suspend. 2248 */ 2249 void gmc_v9_0_restore_registers(struct amdgpu_device *adev) 2250 { 2251 if ((adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 0)) || 2252 (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 1))) { 2253 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register); 2254 WARN_ON(adev->gmc.sdpif_register != 2255 RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0)); 2256 } 2257 } 2258 2259 /** 2260 * gmc_v9_0_gart_enable - gart enable 2261 * 2262 * @adev: amdgpu_device pointer 2263 */ 2264 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 2265 { 2266 int r; 2267 2268 if (adev->gmc.xgmi.connected_to_cpu) 2269 amdgpu_gmc_init_pdb0(adev); 2270 2271 if (adev->gart.bo == NULL) { 2272 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 2273 return -EINVAL; 2274 } 2275 2276 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 2277 2278 if (!adev->in_s0ix) { 2279 r = adev->gfxhub.funcs->gart_enable(adev); 2280 if (r) 2281 return r; 2282 } 2283 2284 r = adev->mmhub.funcs->gart_enable(adev); 2285 if (r) 2286 return r; 2287 2288 DRM_INFO("PCIE GART of %uM enabled.\n", 2289 (unsigned)(adev->gmc.gart_size >> 20)); 2290 if (adev->gmc.pdb0_bo) 2291 DRM_INFO("PDB0 located at 0x%016llX\n", 2292 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo)); 2293 DRM_INFO("PTB located at 0x%016llX\n", 2294 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 2295 2296 return 0; 2297 } 2298 2299 static int gmc_v9_0_hw_init(void *handle) 2300 { 2301 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2302 bool value; 2303 int i, r; 2304 2305 /* The sequence of these two function calls matters.*/ 2306 gmc_v9_0_init_golden_registers(adev); 2307 2308 if (adev->mode_info.num_crtc) { 2309 /* Lockout access through VGA aperture*/ 2310 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 2311 /* disable VGA render */ 2312 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 2313 } 2314 2315 if (adev->mmhub.funcs->update_power_gating) 2316 adev->mmhub.funcs->update_power_gating(adev, true); 2317 2318 adev->hdp.funcs->init_registers(adev); 2319 2320 /* After HDP is initialized, flush HDP.*/ 2321 adev->hdp.funcs->flush_hdp(adev, NULL); 2322 2323 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 2324 value = false; 2325 else 2326 value = true; 2327 2328 if (!amdgpu_sriov_vf(adev)) { 2329 if (!adev->in_s0ix) 2330 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 2331 adev->mmhub.funcs->set_fault_enable_default(adev, value); 2332 } 2333 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 2334 if (adev->in_s0ix && (i == AMDGPU_GFXHUB(0))) 2335 continue; 2336 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0); 2337 } 2338 2339 if (adev->umc.funcs && adev->umc.funcs->init_registers) 2340 adev->umc.funcs->init_registers(adev); 2341 2342 r = gmc_v9_0_gart_enable(adev); 2343 if (r) 2344 return r; 2345 2346 if (amdgpu_emu_mode == 1) 2347 return amdgpu_gmc_vram_checking(adev); 2348 else 2349 return r; 2350 } 2351 2352 /** 2353 * gmc_v9_0_gart_disable - gart disable 2354 * 2355 * @adev: amdgpu_device pointer 2356 * 2357 * This disables all VM page table. 2358 */ 2359 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 2360 { 2361 if (!adev->in_s0ix) 2362 adev->gfxhub.funcs->gart_disable(adev); 2363 adev->mmhub.funcs->gart_disable(adev); 2364 } 2365 2366 static int gmc_v9_0_hw_fini(void *handle) 2367 { 2368 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2369 2370 gmc_v9_0_gart_disable(adev); 2371 2372 if (amdgpu_sriov_vf(adev)) { 2373 /* full access mode, so don't touch any GMC register */ 2374 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 2375 return 0; 2376 } 2377 2378 /* 2379 * Pair the operations did in gmc_v9_0_hw_init and thus maintain 2380 * a correct cached state for GMC. Otherwise, the "gate" again 2381 * operation on S3 resuming will fail due to wrong cached state. 2382 */ 2383 if (adev->mmhub.funcs->update_power_gating) 2384 adev->mmhub.funcs->update_power_gating(adev, false); 2385 2386 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 2387 2388 return 0; 2389 } 2390 2391 static int gmc_v9_0_suspend(void *handle) 2392 { 2393 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2394 2395 return gmc_v9_0_hw_fini(adev); 2396 } 2397 2398 static int gmc_v9_0_resume(void *handle) 2399 { 2400 int r; 2401 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2402 2403 r = gmc_v9_0_hw_init(adev); 2404 if (r) 2405 return r; 2406 2407 amdgpu_vmid_reset_all(adev); 2408 2409 return 0; 2410 } 2411 2412 static bool gmc_v9_0_is_idle(void *handle) 2413 { 2414 /* MC is always ready in GMC v9.*/ 2415 return true; 2416 } 2417 2418 static int gmc_v9_0_wait_for_idle(void *handle) 2419 { 2420 /* There is no need to wait for MC idle in GMC v9.*/ 2421 return 0; 2422 } 2423 2424 static int gmc_v9_0_soft_reset(void *handle) 2425 { 2426 /* XXX for emulation.*/ 2427 return 0; 2428 } 2429 2430 static int gmc_v9_0_set_clockgating_state(void *handle, 2431 enum amd_clockgating_state state) 2432 { 2433 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2434 2435 adev->mmhub.funcs->set_clockgating(adev, state); 2436 2437 athub_v1_0_set_clockgating(adev, state); 2438 2439 return 0; 2440 } 2441 2442 static void gmc_v9_0_get_clockgating_state(void *handle, u64 *flags) 2443 { 2444 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2445 2446 adev->mmhub.funcs->get_clockgating(adev, flags); 2447 2448 athub_v1_0_get_clockgating(adev, flags); 2449 } 2450 2451 static int gmc_v9_0_set_powergating_state(void *handle, 2452 enum amd_powergating_state state) 2453 { 2454 return 0; 2455 } 2456 2457 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 2458 .name = "gmc_v9_0", 2459 .early_init = gmc_v9_0_early_init, 2460 .late_init = gmc_v9_0_late_init, 2461 .sw_init = gmc_v9_0_sw_init, 2462 .sw_fini = gmc_v9_0_sw_fini, 2463 .hw_init = gmc_v9_0_hw_init, 2464 .hw_fini = gmc_v9_0_hw_fini, 2465 .suspend = gmc_v9_0_suspend, 2466 .resume = gmc_v9_0_resume, 2467 .is_idle = gmc_v9_0_is_idle, 2468 .wait_for_idle = gmc_v9_0_wait_for_idle, 2469 .soft_reset = gmc_v9_0_soft_reset, 2470 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 2471 .set_powergating_state = gmc_v9_0_set_powergating_state, 2472 .get_clockgating_state = gmc_v9_0_get_clockgating_state, 2473 }; 2474 2475 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = 2476 { 2477 .type = AMD_IP_BLOCK_TYPE_GMC, 2478 .major = 9, 2479 .minor = 0, 2480 .rev = 0, 2481 .funcs = &gmc_v9_0_ip_funcs, 2482 }; 2483