1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <drm/drm_cache.h> 25 #include "amdgpu.h" 26 #include "gmc_v9_0.h" 27 #include "amdgpu_atomfirmware.h" 28 #include "amdgpu_gem.h" 29 30 #include "hdp/hdp_4_0_offset.h" 31 #include "hdp/hdp_4_0_sh_mask.h" 32 #include "gc/gc_9_0_sh_mask.h" 33 #include "dce/dce_12_0_offset.h" 34 #include "dce/dce_12_0_sh_mask.h" 35 #include "vega10_enum.h" 36 #include "mmhub/mmhub_1_0_offset.h" 37 #include "athub/athub_1_0_offset.h" 38 #include "oss/osssys_4_0_offset.h" 39 40 #include "soc15.h" 41 #include "soc15_common.h" 42 #include "umc/umc_6_0_sh_mask.h" 43 44 #include "gfxhub_v1_0.h" 45 #include "mmhub_v1_0.h" 46 47 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 48 49 /* add these here since we already include dce12 headers and these are for DCN */ 50 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 51 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 52 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 53 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 54 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL 55 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L 56 57 /* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/ 58 #define AMDGPU_NUM_OF_VMIDS 8 59 60 static const u32 golden_settings_vega10_hdp[] = 61 { 62 0xf64, 0x0fffffff, 0x00000000, 63 0xf65, 0x0fffffff, 0x00000000, 64 0xf66, 0x0fffffff, 0x00000000, 65 0xf67, 0x0fffffff, 0x00000000, 66 0xf68, 0x0fffffff, 0x00000000, 67 0xf6a, 0x0fffffff, 0x00000000, 68 0xf6b, 0x0fffffff, 0x00000000, 69 0xf6c, 0x0fffffff, 0x00000000, 70 0xf6d, 0x0fffffff, 0x00000000, 71 0xf6e, 0x0fffffff, 0x00000000, 72 }; 73 74 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = 75 { 76 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), 77 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) 78 }; 79 80 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = 81 { 82 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), 83 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) 84 }; 85 86 /* Ecc related register addresses, (BASE + reg offset) */ 87 /* Universal Memory Controller caps (may be fused). */ 88 /* UMCCH:UmcLocalCap */ 89 #define UMCLOCALCAPS_ADDR0 (0x00014306 + 0x00000000) 90 #define UMCLOCALCAPS_ADDR1 (0x00014306 + 0x00000800) 91 #define UMCLOCALCAPS_ADDR2 (0x00014306 + 0x00001000) 92 #define UMCLOCALCAPS_ADDR3 (0x00014306 + 0x00001800) 93 #define UMCLOCALCAPS_ADDR4 (0x00054306 + 0x00000000) 94 #define UMCLOCALCAPS_ADDR5 (0x00054306 + 0x00000800) 95 #define UMCLOCALCAPS_ADDR6 (0x00054306 + 0x00001000) 96 #define UMCLOCALCAPS_ADDR7 (0x00054306 + 0x00001800) 97 #define UMCLOCALCAPS_ADDR8 (0x00094306 + 0x00000000) 98 #define UMCLOCALCAPS_ADDR9 (0x00094306 + 0x00000800) 99 #define UMCLOCALCAPS_ADDR10 (0x00094306 + 0x00001000) 100 #define UMCLOCALCAPS_ADDR11 (0x00094306 + 0x00001800) 101 #define UMCLOCALCAPS_ADDR12 (0x000d4306 + 0x00000000) 102 #define UMCLOCALCAPS_ADDR13 (0x000d4306 + 0x00000800) 103 #define UMCLOCALCAPS_ADDR14 (0x000d4306 + 0x00001000) 104 #define UMCLOCALCAPS_ADDR15 (0x000d4306 + 0x00001800) 105 106 /* Universal Memory Controller Channel config. */ 107 /* UMCCH:UMC_CONFIG */ 108 #define UMCCH_UMC_CONFIG_ADDR0 (0x00014040 + 0x00000000) 109 #define UMCCH_UMC_CONFIG_ADDR1 (0x00014040 + 0x00000800) 110 #define UMCCH_UMC_CONFIG_ADDR2 (0x00014040 + 0x00001000) 111 #define UMCCH_UMC_CONFIG_ADDR3 (0x00014040 + 0x00001800) 112 #define UMCCH_UMC_CONFIG_ADDR4 (0x00054040 + 0x00000000) 113 #define UMCCH_UMC_CONFIG_ADDR5 (0x00054040 + 0x00000800) 114 #define UMCCH_UMC_CONFIG_ADDR6 (0x00054040 + 0x00001000) 115 #define UMCCH_UMC_CONFIG_ADDR7 (0x00054040 + 0x00001800) 116 #define UMCCH_UMC_CONFIG_ADDR8 (0x00094040 + 0x00000000) 117 #define UMCCH_UMC_CONFIG_ADDR9 (0x00094040 + 0x00000800) 118 #define UMCCH_UMC_CONFIG_ADDR10 (0x00094040 + 0x00001000) 119 #define UMCCH_UMC_CONFIG_ADDR11 (0x00094040 + 0x00001800) 120 #define UMCCH_UMC_CONFIG_ADDR12 (0x000d4040 + 0x00000000) 121 #define UMCCH_UMC_CONFIG_ADDR13 (0x000d4040 + 0x00000800) 122 #define UMCCH_UMC_CONFIG_ADDR14 (0x000d4040 + 0x00001000) 123 #define UMCCH_UMC_CONFIG_ADDR15 (0x000d4040 + 0x00001800) 124 125 /* Universal Memory Controller Channel Ecc config. */ 126 /* UMCCH:EccCtrl */ 127 #define UMCCH_ECCCTRL_ADDR0 (0x00014053 + 0x00000000) 128 #define UMCCH_ECCCTRL_ADDR1 (0x00014053 + 0x00000800) 129 #define UMCCH_ECCCTRL_ADDR2 (0x00014053 + 0x00001000) 130 #define UMCCH_ECCCTRL_ADDR3 (0x00014053 + 0x00001800) 131 #define UMCCH_ECCCTRL_ADDR4 (0x00054053 + 0x00000000) 132 #define UMCCH_ECCCTRL_ADDR5 (0x00054053 + 0x00000800) 133 #define UMCCH_ECCCTRL_ADDR6 (0x00054053 + 0x00001000) 134 #define UMCCH_ECCCTRL_ADDR7 (0x00054053 + 0x00001800) 135 #define UMCCH_ECCCTRL_ADDR8 (0x00094053 + 0x00000000) 136 #define UMCCH_ECCCTRL_ADDR9 (0x00094053 + 0x00000800) 137 #define UMCCH_ECCCTRL_ADDR10 (0x00094053 + 0x00001000) 138 #define UMCCH_ECCCTRL_ADDR11 (0x00094053 + 0x00001800) 139 #define UMCCH_ECCCTRL_ADDR12 (0x000d4053 + 0x00000000) 140 #define UMCCH_ECCCTRL_ADDR13 (0x000d4053 + 0x00000800) 141 #define UMCCH_ECCCTRL_ADDR14 (0x000d4053 + 0x00001000) 142 #define UMCCH_ECCCTRL_ADDR15 (0x000d4053 + 0x00001800) 143 144 static const uint32_t ecc_umclocalcap_addrs[] = { 145 UMCLOCALCAPS_ADDR0, 146 UMCLOCALCAPS_ADDR1, 147 UMCLOCALCAPS_ADDR2, 148 UMCLOCALCAPS_ADDR3, 149 UMCLOCALCAPS_ADDR4, 150 UMCLOCALCAPS_ADDR5, 151 UMCLOCALCAPS_ADDR6, 152 UMCLOCALCAPS_ADDR7, 153 UMCLOCALCAPS_ADDR8, 154 UMCLOCALCAPS_ADDR9, 155 UMCLOCALCAPS_ADDR10, 156 UMCLOCALCAPS_ADDR11, 157 UMCLOCALCAPS_ADDR12, 158 UMCLOCALCAPS_ADDR13, 159 UMCLOCALCAPS_ADDR14, 160 UMCLOCALCAPS_ADDR15, 161 }; 162 163 static const uint32_t ecc_umcch_umc_config_addrs[] = { 164 UMCCH_UMC_CONFIG_ADDR0, 165 UMCCH_UMC_CONFIG_ADDR1, 166 UMCCH_UMC_CONFIG_ADDR2, 167 UMCCH_UMC_CONFIG_ADDR3, 168 UMCCH_UMC_CONFIG_ADDR4, 169 UMCCH_UMC_CONFIG_ADDR5, 170 UMCCH_UMC_CONFIG_ADDR6, 171 UMCCH_UMC_CONFIG_ADDR7, 172 UMCCH_UMC_CONFIG_ADDR8, 173 UMCCH_UMC_CONFIG_ADDR9, 174 UMCCH_UMC_CONFIG_ADDR10, 175 UMCCH_UMC_CONFIG_ADDR11, 176 UMCCH_UMC_CONFIG_ADDR12, 177 UMCCH_UMC_CONFIG_ADDR13, 178 UMCCH_UMC_CONFIG_ADDR14, 179 UMCCH_UMC_CONFIG_ADDR15, 180 }; 181 182 static const uint32_t ecc_umcch_eccctrl_addrs[] = { 183 UMCCH_ECCCTRL_ADDR0, 184 UMCCH_ECCCTRL_ADDR1, 185 UMCCH_ECCCTRL_ADDR2, 186 UMCCH_ECCCTRL_ADDR3, 187 UMCCH_ECCCTRL_ADDR4, 188 UMCCH_ECCCTRL_ADDR5, 189 UMCCH_ECCCTRL_ADDR6, 190 UMCCH_ECCCTRL_ADDR7, 191 UMCCH_ECCCTRL_ADDR8, 192 UMCCH_ECCCTRL_ADDR9, 193 UMCCH_ECCCTRL_ADDR10, 194 UMCCH_ECCCTRL_ADDR11, 195 UMCCH_ECCCTRL_ADDR12, 196 UMCCH_ECCCTRL_ADDR13, 197 UMCCH_ECCCTRL_ADDR14, 198 UMCCH_ECCCTRL_ADDR15, 199 }; 200 201 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 202 struct amdgpu_irq_src *src, 203 unsigned type, 204 enum amdgpu_interrupt_state state) 205 { 206 struct amdgpu_vmhub *hub; 207 u32 tmp, reg, bits, i, j; 208 209 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 210 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 211 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 212 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 213 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 214 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 215 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 216 217 switch (state) { 218 case AMDGPU_IRQ_STATE_DISABLE: 219 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) { 220 hub = &adev->vmhub[j]; 221 for (i = 0; i < 16; i++) { 222 reg = hub->vm_context0_cntl + i; 223 tmp = RREG32(reg); 224 tmp &= ~bits; 225 WREG32(reg, tmp); 226 } 227 } 228 break; 229 case AMDGPU_IRQ_STATE_ENABLE: 230 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) { 231 hub = &adev->vmhub[j]; 232 for (i = 0; i < 16; i++) { 233 reg = hub->vm_context0_cntl + i; 234 tmp = RREG32(reg); 235 tmp |= bits; 236 WREG32(reg, tmp); 237 } 238 } 239 default: 240 break; 241 } 242 243 return 0; 244 } 245 246 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 247 struct amdgpu_irq_src *source, 248 struct amdgpu_iv_entry *entry) 249 { 250 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; 251 uint32_t status = 0; 252 u64 addr; 253 254 addr = (u64)entry->src_data[0] << 12; 255 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 256 257 if (!amdgpu_sriov_vf(adev)) { 258 status = RREG32(hub->vm_l2_pro_fault_status); 259 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 260 } 261 262 if (printk_ratelimit()) { 263 struct amdgpu_task_info task_info = { 0 }; 264 265 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 266 267 dev_err(adev->dev, 268 "[%s] VMC page fault (src_id:%u ring:%u vmid:%u pasid:%u, for process %s pid %d thread %s pid %d\n)\n", 269 entry->vmid_src ? "mmhub" : "gfxhub", 270 entry->src_id, entry->ring_id, entry->vmid, 271 entry->pasid, task_info.process_name, task_info.tgid, 272 task_info.task_name, task_info.pid); 273 dev_err(adev->dev, " at address 0x%016llx from %d\n", 274 addr, entry->client_id); 275 if (!amdgpu_sriov_vf(adev)) 276 dev_err(adev->dev, 277 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 278 status); 279 } 280 281 return 0; 282 } 283 284 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 285 .set = gmc_v9_0_vm_fault_interrupt_state, 286 .process = gmc_v9_0_process_interrupt, 287 }; 288 289 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 290 { 291 adev->gmc.vm_fault.num_types = 1; 292 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 293 } 294 295 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid) 296 { 297 u32 req = 0; 298 299 /* invalidate using legacy mode on vmid*/ 300 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 301 PER_VMID_INVALIDATE_REQ, 1 << vmid); 302 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0); 303 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 304 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 305 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 306 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 307 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 308 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 309 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 310 311 return req; 312 } 313 314 /* 315 * GART 316 * VMID 0 is the physical GPU addresses as used by the kernel. 317 * VMIDs 1-15 are used for userspace clients and are handled 318 * by the amdgpu vm/hsa code. 319 */ 320 321 /** 322 * gmc_v9_0_flush_gpu_tlb - gart tlb flush callback 323 * 324 * @adev: amdgpu_device pointer 325 * @vmid: vm instance to flush 326 * 327 * Flush the TLB for the requested page table. 328 */ 329 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, 330 uint32_t vmid) 331 { 332 /* Use register 17 for GART */ 333 const unsigned eng = 17; 334 unsigned i, j; 335 336 spin_lock(&adev->gmc.invalidate_lock); 337 338 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { 339 struct amdgpu_vmhub *hub = &adev->vmhub[i]; 340 u32 tmp = gmc_v9_0_get_invalidate_req(vmid); 341 342 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp); 343 344 /* Busy wait for ACK.*/ 345 for (j = 0; j < 100; j++) { 346 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); 347 tmp &= 1 << vmid; 348 if (tmp) 349 break; 350 cpu_relax(); 351 } 352 if (j < 100) 353 continue; 354 355 /* Wait for ACK with a delay.*/ 356 for (j = 0; j < adev->usec_timeout; j++) { 357 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); 358 tmp &= 1 << vmid; 359 if (tmp) 360 break; 361 udelay(1); 362 } 363 if (j < adev->usec_timeout) 364 continue; 365 366 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 367 } 368 369 spin_unlock(&adev->gmc.invalidate_lock); 370 } 371 372 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 373 unsigned vmid, uint64_t pd_addr) 374 { 375 struct amdgpu_device *adev = ring->adev; 376 struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub]; 377 uint32_t req = gmc_v9_0_get_invalidate_req(vmid); 378 uint64_t flags = AMDGPU_PTE_VALID; 379 unsigned eng = ring->vm_inv_eng; 380 381 amdgpu_gmc_get_vm_pde(adev, -1, &pd_addr, &flags); 382 pd_addr |= flags; 383 384 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid), 385 lower_32_bits(pd_addr)); 386 387 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid), 388 upper_32_bits(pd_addr)); 389 390 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng, 391 hub->vm_inv_eng0_ack + eng, 392 req, 1 << vmid); 393 394 return pd_addr; 395 } 396 397 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 398 unsigned pasid) 399 { 400 struct amdgpu_device *adev = ring->adev; 401 uint32_t reg; 402 403 if (ring->funcs->vmhub == AMDGPU_GFXHUB) 404 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 405 else 406 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 407 408 amdgpu_ring_emit_wreg(ring, reg, pasid); 409 } 410 411 /** 412 * gmc_v9_0_set_pte_pde - update the page tables using MMIO 413 * 414 * @adev: amdgpu_device pointer 415 * @cpu_pt_addr: cpu address of the page table 416 * @gpu_page_idx: entry in the page table to update 417 * @addr: dst addr to write into pte/pde 418 * @flags: access flags 419 * 420 * Update the page tables using the CPU. 421 */ 422 static int gmc_v9_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 423 uint32_t gpu_page_idx, uint64_t addr, 424 uint64_t flags) 425 { 426 void __iomem *ptr = (void *)cpu_pt_addr; 427 uint64_t value; 428 429 /* 430 * PTE format on VEGA 10: 431 * 63:59 reserved 432 * 58:57 mtype 433 * 56 F 434 * 55 L 435 * 54 P 436 * 53 SW 437 * 52 T 438 * 50:48 reserved 439 * 47:12 4k physical page base address 440 * 11:7 fragment 441 * 6 write 442 * 5 read 443 * 4 exe 444 * 3 Z 445 * 2 snooped 446 * 1 system 447 * 0 valid 448 * 449 * PDE format on VEGA 10: 450 * 63:59 block fragment size 451 * 58:55 reserved 452 * 54 P 453 * 53:48 reserved 454 * 47:6 physical base address of PD or PTE 455 * 5:3 reserved 456 * 2 C 457 * 1 system 458 * 0 valid 459 */ 460 461 /* 462 * The following is for PTE only. GART does not have PDEs. 463 */ 464 value = addr & 0x0000FFFFFFFFF000ULL; 465 value |= flags; 466 writeq(value, ptr + (gpu_page_idx * 8)); 467 return 0; 468 } 469 470 static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev, 471 uint32_t flags) 472 473 { 474 uint64_t pte_flag = 0; 475 476 if (flags & AMDGPU_VM_PAGE_EXECUTABLE) 477 pte_flag |= AMDGPU_PTE_EXECUTABLE; 478 if (flags & AMDGPU_VM_PAGE_READABLE) 479 pte_flag |= AMDGPU_PTE_READABLE; 480 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 481 pte_flag |= AMDGPU_PTE_WRITEABLE; 482 483 switch (flags & AMDGPU_VM_MTYPE_MASK) { 484 case AMDGPU_VM_MTYPE_DEFAULT: 485 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC); 486 break; 487 case AMDGPU_VM_MTYPE_NC: 488 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC); 489 break; 490 case AMDGPU_VM_MTYPE_WC: 491 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_WC); 492 break; 493 case AMDGPU_VM_MTYPE_CC: 494 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_CC); 495 break; 496 case AMDGPU_VM_MTYPE_UC: 497 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_UC); 498 break; 499 default: 500 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC); 501 break; 502 } 503 504 if (flags & AMDGPU_VM_PAGE_PRT) 505 pte_flag |= AMDGPU_PTE_PRT; 506 507 return pte_flag; 508 } 509 510 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, 511 uint64_t *addr, uint64_t *flags) 512 { 513 if (!(*flags & AMDGPU_PDE_PTE)) 514 *addr = adev->vm_manager.vram_base_offset + *addr - 515 adev->gmc.vram_start; 516 BUG_ON(*addr & 0xFFFF00000000003FULL); 517 518 if (!adev->gmc.translate_further) 519 return; 520 521 if (level == AMDGPU_VM_PDB1) { 522 /* Set the block fragment size */ 523 if (!(*flags & AMDGPU_PDE_PTE)) 524 *flags |= AMDGPU_PDE_BFS(0x9); 525 526 } else if (level == AMDGPU_VM_PDB0) { 527 if (*flags & AMDGPU_PDE_PTE) 528 *flags &= ~AMDGPU_PDE_PTE; 529 else 530 *flags |= AMDGPU_PTE_TF; 531 } 532 } 533 534 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { 535 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, 536 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, 537 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, 538 .set_pte_pde = gmc_v9_0_set_pte_pde, 539 .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags, 540 .get_vm_pde = gmc_v9_0_get_vm_pde 541 }; 542 543 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) 544 { 545 if (adev->gmc.gmc_funcs == NULL) 546 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; 547 } 548 549 static int gmc_v9_0_early_init(void *handle) 550 { 551 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 552 553 gmc_v9_0_set_gmc_funcs(adev); 554 gmc_v9_0_set_irq_funcs(adev); 555 556 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 557 adev->gmc.shared_aperture_end = 558 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 559 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 560 adev->gmc.private_aperture_end = 561 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 562 563 return 0; 564 } 565 566 static int gmc_v9_0_ecc_available(struct amdgpu_device *adev) 567 { 568 uint32_t reg_val; 569 uint32_t reg_addr; 570 uint32_t field_val; 571 size_t i; 572 uint32_t fv2; 573 size_t lost_sheep; 574 575 DRM_DEBUG("ecc: gmc_v9_0_ecc_available()\n"); 576 577 lost_sheep = 0; 578 for (i = 0; i < ARRAY_SIZE(ecc_umclocalcap_addrs); ++i) { 579 reg_addr = ecc_umclocalcap_addrs[i]; 580 DRM_DEBUG("ecc: " 581 "UMCCH_UmcLocalCap[%zu]: reg_addr: 0x%08x\n", 582 i, reg_addr); 583 reg_val = RREG32(reg_addr); 584 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UmcLocalCap, 585 EccDis); 586 DRM_DEBUG("ecc: " 587 "reg_val: 0x%08x, " 588 "EccDis: 0x%08x, ", 589 reg_val, field_val); 590 if (field_val) { 591 DRM_ERROR("ecc: UmcLocalCap:EccDis is set.\n"); 592 ++lost_sheep; 593 } 594 } 595 596 for (i = 0; i < ARRAY_SIZE(ecc_umcch_umc_config_addrs); ++i) { 597 reg_addr = ecc_umcch_umc_config_addrs[i]; 598 DRM_DEBUG("ecc: " 599 "UMCCH0_0_UMC_CONFIG[%zu]: reg_addr: 0x%08x", 600 i, reg_addr); 601 reg_val = RREG32(reg_addr); 602 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UMC_CONFIG, 603 DramReady); 604 DRM_DEBUG("ecc: " 605 "reg_val: 0x%08x, " 606 "DramReady: 0x%08x\n", 607 reg_val, field_val); 608 609 if (!field_val) { 610 DRM_ERROR("ecc: UMC_CONFIG:DramReady is not set.\n"); 611 ++lost_sheep; 612 } 613 } 614 615 for (i = 0; i < ARRAY_SIZE(ecc_umcch_eccctrl_addrs); ++i) { 616 reg_addr = ecc_umcch_eccctrl_addrs[i]; 617 DRM_DEBUG("ecc: " 618 "UMCCH_EccCtrl[%zu]: reg_addr: 0x%08x, ", 619 i, reg_addr); 620 reg_val = RREG32(reg_addr); 621 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl, 622 WrEccEn); 623 fv2 = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl, 624 RdEccEn); 625 DRM_DEBUG("ecc: " 626 "reg_val: 0x%08x, " 627 "WrEccEn: 0x%08x, " 628 "RdEccEn: 0x%08x\n", 629 reg_val, field_val, fv2); 630 631 if (!field_val) { 632 DRM_DEBUG("ecc: WrEccEn is not set\n"); 633 ++lost_sheep; 634 } 635 if (!fv2) { 636 DRM_DEBUG("ecc: RdEccEn is not set\n"); 637 ++lost_sheep; 638 } 639 } 640 641 DRM_DEBUG("ecc: lost_sheep: %zu\n", lost_sheep); 642 return lost_sheep == 0; 643 } 644 645 static int gmc_v9_0_late_init(void *handle) 646 { 647 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 648 /* 649 * The latest engine allocation on gfx9 is: 650 * Engine 0, 1: idle 651 * Engine 2, 3: firmware 652 * Engine 4~13: amdgpu ring, subject to change when ring number changes 653 * Engine 14~15: idle 654 * Engine 16: kfd tlb invalidation 655 * Engine 17: Gart flushes 656 */ 657 unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 }; 658 unsigned i; 659 int r; 660 661 /* 662 * TODO - Uncomment once GART corruption issue is fixed. 663 */ 664 /* amdgpu_bo_late_init(adev); */ 665 666 for(i = 0; i < adev->num_rings; ++i) { 667 struct amdgpu_ring *ring = adev->rings[i]; 668 unsigned vmhub = ring->funcs->vmhub; 669 670 ring->vm_inv_eng = vm_inv_eng[vmhub]++; 671 dev_info(adev->dev, "ring %u(%s) uses VM inv eng %u on hub %u\n", 672 ring->idx, ring->name, ring->vm_inv_eng, 673 ring->funcs->vmhub); 674 } 675 676 /* Engine 16 is used for KFD and 17 for GART flushes */ 677 for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i) 678 BUG_ON(vm_inv_eng[i] > 16); 679 680 if (adev->asic_type == CHIP_VEGA10 && !amdgpu_sriov_vf(adev)) { 681 r = gmc_v9_0_ecc_available(adev); 682 if (r == 1) { 683 DRM_INFO("ECC is active.\n"); 684 } else if (r == 0) { 685 DRM_INFO("ECC is not present.\n"); 686 adev->df_funcs->enable_ecc_force_par_wr_rmw(adev, false); 687 } else { 688 DRM_ERROR("gmc_v9_0_ecc_available() failed. r: %d\n", r); 689 return r; 690 } 691 } 692 693 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 694 } 695 696 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 697 struct amdgpu_gmc *mc) 698 { 699 u64 base = 0; 700 if (!amdgpu_sriov_vf(adev)) 701 base = mmhub_v1_0_get_fb_location(adev); 702 amdgpu_device_vram_location(adev, &adev->gmc, base); 703 amdgpu_device_gart_location(adev, mc); 704 /* base offset of vram pages */ 705 adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev); 706 } 707 708 /** 709 * gmc_v9_0_mc_init - initialize the memory controller driver params 710 * 711 * @adev: amdgpu_device pointer 712 * 713 * Look up the amount of vram, vram width, and decide how to place 714 * vram and gart within the GPU's physical address space. 715 * Returns 0 for success. 716 */ 717 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 718 { 719 int chansize, numchan; 720 int r; 721 722 if (amdgpu_emu_mode != 1) 723 adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev); 724 if (!adev->gmc.vram_width) { 725 /* hbm memory channel size */ 726 if (adev->flags & AMD_IS_APU) 727 chansize = 64; 728 else 729 chansize = 128; 730 731 numchan = adev->df_funcs->get_hbm_channel_number(adev); 732 adev->gmc.vram_width = numchan * chansize; 733 } 734 735 /* size in MB on si */ 736 adev->gmc.mc_vram_size = 737 adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL; 738 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 739 740 if (!(adev->flags & AMD_IS_APU)) { 741 r = amdgpu_device_resize_fb_bar(adev); 742 if (r) 743 return r; 744 } 745 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 746 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 747 748 #ifdef CONFIG_X86_64 749 if (adev->flags & AMD_IS_APU) { 750 adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev); 751 adev->gmc.aper_size = adev->gmc.real_vram_size; 752 } 753 #endif 754 /* In case the PCI BAR is larger than the actual amount of vram */ 755 adev->gmc.visible_vram_size = adev->gmc.aper_size; 756 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 757 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 758 759 /* set the gart size */ 760 if (amdgpu_gart_size == -1) { 761 switch (adev->asic_type) { 762 case CHIP_VEGA10: /* all engines support GPUVM */ 763 case CHIP_VEGA12: /* all engines support GPUVM */ 764 case CHIP_VEGA20: 765 default: 766 adev->gmc.gart_size = 512ULL << 20; 767 break; 768 case CHIP_RAVEN: /* DCE SG support */ 769 adev->gmc.gart_size = 1024ULL << 20; 770 break; 771 } 772 } else { 773 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 774 } 775 776 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); 777 778 return 0; 779 } 780 781 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 782 { 783 int r; 784 785 if (adev->gart.robj) { 786 WARN(1, "VEGA10 PCIE GART already initialized\n"); 787 return 0; 788 } 789 /* Initialize common gart structure */ 790 r = amdgpu_gart_init(adev); 791 if (r) 792 return r; 793 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 794 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE(MTYPE_UC) | 795 AMDGPU_PTE_EXECUTABLE; 796 return amdgpu_gart_table_vram_alloc(adev); 797 } 798 799 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 800 { 801 #if 0 802 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 803 #endif 804 unsigned size; 805 806 /* 807 * TODO Remove once GART corruption is resolved 808 * Check related code in gmc_v9_0_sw_fini 809 * */ 810 size = 9 * 1024 * 1024; 811 812 #if 0 813 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 814 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */ 815 } else { 816 u32 viewport; 817 818 switch (adev->asic_type) { 819 case CHIP_RAVEN: 820 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 821 size = (REG_GET_FIELD(viewport, 822 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 823 REG_GET_FIELD(viewport, 824 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 825 4); 826 break; 827 case CHIP_VEGA10: 828 case CHIP_VEGA12: 829 default: 830 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); 831 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 832 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * 833 4); 834 break; 835 } 836 } 837 /* return 0 if the pre-OS buffer uses up most of vram */ 838 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 839 return 0; 840 841 #endif 842 return size; 843 } 844 845 static int gmc_v9_0_sw_init(void *handle) 846 { 847 int r; 848 int dma_bits; 849 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 850 851 gfxhub_v1_0_init(adev); 852 mmhub_v1_0_init(adev); 853 854 spin_lock_init(&adev->gmc.invalidate_lock); 855 856 adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev); 857 switch (adev->asic_type) { 858 case CHIP_RAVEN: 859 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 860 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 861 } else { 862 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 863 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 864 adev->gmc.translate_further = 865 adev->vm_manager.num_level > 1; 866 } 867 break; 868 case CHIP_VEGA10: 869 case CHIP_VEGA12: 870 case CHIP_VEGA20: 871 /* 872 * To fulfill 4-level page support, 873 * vm size is 256TB (48bit), maximum size of Vega10, 874 * block size 512 (9bit) 875 */ 876 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 877 break; 878 default: 879 break; 880 } 881 882 /* This interrupt is VMC page fault.*/ 883 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, 884 &adev->gmc.vm_fault); 885 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, 886 &adev->gmc.vm_fault); 887 888 if (r) 889 return r; 890 891 /* Set the internal MC address mask 892 * This is the max address of the GPU's 893 * internal address space. 894 */ 895 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 896 897 /* set DMA mask + need_dma32 flags. 898 * PCIE - can handle 44-bits. 899 * IGP - can handle 44-bits 900 * PCI - dma32 for legacy pci gart, 44 bits on vega10 901 */ 902 adev->need_dma32 = false; 903 dma_bits = adev->need_dma32 ? 32 : 44; 904 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 905 if (r) { 906 adev->need_dma32 = true; 907 dma_bits = 32; 908 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 909 } 910 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 911 if (r) { 912 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); 913 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n"); 914 } 915 adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits); 916 917 r = gmc_v9_0_mc_init(adev); 918 if (r) 919 return r; 920 921 adev->gmc.stolen_size = gmc_v9_0_get_vbios_fb_size(adev); 922 923 /* Memory manager */ 924 r = amdgpu_bo_init(adev); 925 if (r) 926 return r; 927 928 r = gmc_v9_0_gart_init(adev); 929 if (r) 930 return r; 931 932 /* 933 * number of VMs 934 * VMID 0 is reserved for System 935 * amdgpu graphics/compute will use VMIDs 1-7 936 * amdkfd will use VMIDs 8-15 937 */ 938 adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS; 939 adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS; 940 941 amdgpu_vm_manager_init(adev); 942 943 return 0; 944 } 945 946 static int gmc_v9_0_sw_fini(void *handle) 947 { 948 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 949 950 amdgpu_gem_force_release(adev); 951 amdgpu_vm_manager_fini(adev); 952 953 /* 954 * TODO: 955 * Currently there is a bug where some memory client outside 956 * of the driver writes to first 8M of VRAM on S3 resume, 957 * this overrides GART which by default gets placed in first 8M and 958 * causes VM_FAULTS once GTT is accessed. 959 * Keep the stolen memory reservation until the while this is not solved. 960 * Also check code in gmc_v9_0_get_vbios_fb_size and gmc_v9_0_late_init 961 */ 962 amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL); 963 964 amdgpu_gart_table_vram_free(adev); 965 amdgpu_bo_fini(adev); 966 amdgpu_gart_fini(adev); 967 968 return 0; 969 } 970 971 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 972 { 973 974 switch (adev->asic_type) { 975 case CHIP_VEGA10: 976 case CHIP_VEGA20: 977 soc15_program_register_sequence(adev, 978 golden_settings_mmhub_1_0_0, 979 ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 980 soc15_program_register_sequence(adev, 981 golden_settings_athub_1_0_0, 982 ARRAY_SIZE(golden_settings_athub_1_0_0)); 983 break; 984 case CHIP_VEGA12: 985 break; 986 case CHIP_RAVEN: 987 soc15_program_register_sequence(adev, 988 golden_settings_athub_1_0_0, 989 ARRAY_SIZE(golden_settings_athub_1_0_0)); 990 break; 991 default: 992 break; 993 } 994 } 995 996 /** 997 * gmc_v9_0_gart_enable - gart enable 998 * 999 * @adev: amdgpu_device pointer 1000 */ 1001 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 1002 { 1003 int r; 1004 bool value; 1005 u32 tmp; 1006 1007 amdgpu_device_program_register_sequence(adev, 1008 golden_settings_vega10_hdp, 1009 ARRAY_SIZE(golden_settings_vega10_hdp)); 1010 1011 if (adev->gart.robj == NULL) { 1012 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 1013 return -EINVAL; 1014 } 1015 r = amdgpu_gart_table_vram_pin(adev); 1016 if (r) 1017 return r; 1018 1019 switch (adev->asic_type) { 1020 case CHIP_RAVEN: 1021 mmhub_v1_0_initialize_power_gating(adev); 1022 mmhub_v1_0_update_power_gating(adev, true); 1023 break; 1024 default: 1025 break; 1026 } 1027 1028 r = gfxhub_v1_0_gart_enable(adev); 1029 if (r) 1030 return r; 1031 1032 r = mmhub_v1_0_gart_enable(adev); 1033 if (r) 1034 return r; 1035 1036 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1); 1037 1038 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL); 1039 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp); 1040 1041 /* After HDP is initialized, flush HDP.*/ 1042 adev->nbio_funcs->hdp_flush(adev, NULL); 1043 1044 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 1045 value = false; 1046 else 1047 value = true; 1048 1049 gfxhub_v1_0_set_fault_enable_default(adev, value); 1050 mmhub_v1_0_set_fault_enable_default(adev, value); 1051 gmc_v9_0_flush_gpu_tlb(adev, 0); 1052 1053 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1054 (unsigned)(adev->gmc.gart_size >> 20), 1055 (unsigned long long)adev->gart.table_addr); 1056 adev->gart.ready = true; 1057 return 0; 1058 } 1059 1060 static int gmc_v9_0_hw_init(void *handle) 1061 { 1062 int r; 1063 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1064 1065 /* The sequence of these two function calls matters.*/ 1066 gmc_v9_0_init_golden_registers(adev); 1067 1068 if (adev->mode_info.num_crtc) { 1069 /* Lockout access through VGA aperture*/ 1070 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 1071 1072 /* disable VGA render */ 1073 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 1074 } 1075 1076 r = gmc_v9_0_gart_enable(adev); 1077 1078 return r; 1079 } 1080 1081 /** 1082 * gmc_v9_0_gart_disable - gart disable 1083 * 1084 * @adev: amdgpu_device pointer 1085 * 1086 * This disables all VM page table. 1087 */ 1088 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 1089 { 1090 gfxhub_v1_0_gart_disable(adev); 1091 mmhub_v1_0_gart_disable(adev); 1092 amdgpu_gart_table_vram_unpin(adev); 1093 } 1094 1095 static int gmc_v9_0_hw_fini(void *handle) 1096 { 1097 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1098 1099 if (amdgpu_sriov_vf(adev)) { 1100 /* full access mode, so don't touch any GMC register */ 1101 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 1102 return 0; 1103 } 1104 1105 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1106 gmc_v9_0_gart_disable(adev); 1107 1108 return 0; 1109 } 1110 1111 static int gmc_v9_0_suspend(void *handle) 1112 { 1113 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1114 1115 return gmc_v9_0_hw_fini(adev); 1116 } 1117 1118 static int gmc_v9_0_resume(void *handle) 1119 { 1120 int r; 1121 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1122 1123 r = gmc_v9_0_hw_init(adev); 1124 if (r) 1125 return r; 1126 1127 amdgpu_vmid_reset_all(adev); 1128 1129 return 0; 1130 } 1131 1132 static bool gmc_v9_0_is_idle(void *handle) 1133 { 1134 /* MC is always ready in GMC v9.*/ 1135 return true; 1136 } 1137 1138 static int gmc_v9_0_wait_for_idle(void *handle) 1139 { 1140 /* There is no need to wait for MC idle in GMC v9.*/ 1141 return 0; 1142 } 1143 1144 static int gmc_v9_0_soft_reset(void *handle) 1145 { 1146 /* XXX for emulation.*/ 1147 return 0; 1148 } 1149 1150 static int gmc_v9_0_set_clockgating_state(void *handle, 1151 enum amd_clockgating_state state) 1152 { 1153 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1154 1155 return mmhub_v1_0_set_clockgating(adev, state); 1156 } 1157 1158 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags) 1159 { 1160 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1161 1162 mmhub_v1_0_get_clockgating(adev, flags); 1163 } 1164 1165 static int gmc_v9_0_set_powergating_state(void *handle, 1166 enum amd_powergating_state state) 1167 { 1168 return 0; 1169 } 1170 1171 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 1172 .name = "gmc_v9_0", 1173 .early_init = gmc_v9_0_early_init, 1174 .late_init = gmc_v9_0_late_init, 1175 .sw_init = gmc_v9_0_sw_init, 1176 .sw_fini = gmc_v9_0_sw_fini, 1177 .hw_init = gmc_v9_0_hw_init, 1178 .hw_fini = gmc_v9_0_hw_fini, 1179 .suspend = gmc_v9_0_suspend, 1180 .resume = gmc_v9_0_resume, 1181 .is_idle = gmc_v9_0_is_idle, 1182 .wait_for_idle = gmc_v9_0_wait_for_idle, 1183 .soft_reset = gmc_v9_0_soft_reset, 1184 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 1185 .set_powergating_state = gmc_v9_0_set_powergating_state, 1186 .get_clockgating_state = gmc_v9_0_get_clockgating_state, 1187 }; 1188 1189 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = 1190 { 1191 .type = AMD_IP_BLOCK_TYPE_GMC, 1192 .major = 9, 1193 .minor = 0, 1194 .rev = 0, 1195 .funcs = &gmc_v9_0_ip_funcs, 1196 }; 1197