1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include "amdgpu.h" 25 #include "gmc_v9_0.h" 26 27 #include "vega10/soc15ip.h" 28 #include "vega10/HDP/hdp_4_0_offset.h" 29 #include "vega10/HDP/hdp_4_0_sh_mask.h" 30 #include "vega10/GC/gc_9_0_sh_mask.h" 31 #include "vega10/vega10_enum.h" 32 33 #include "soc15_common.h" 34 35 #include "nbio_v6_1.h" 36 #include "nbio_v7_0.h" 37 #include "gfxhub_v1_0.h" 38 #include "mmhub_v1_0.h" 39 40 #define mmDF_CS_AON0_DramBaseAddress0 0x0044 41 #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX 0 42 //DF_CS_AON0_DramBaseAddress0 43 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0 44 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1 45 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4 46 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8 47 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc 48 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L 49 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L 50 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x000000F0L 51 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L 52 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L 53 54 /* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/ 55 #define AMDGPU_NUM_OF_VMIDS 8 56 57 static const u32 golden_settings_vega10_hdp[] = 58 { 59 0xf64, 0x0fffffff, 0x00000000, 60 0xf65, 0x0fffffff, 0x00000000, 61 0xf66, 0x0fffffff, 0x00000000, 62 0xf67, 0x0fffffff, 0x00000000, 63 0xf68, 0x0fffffff, 0x00000000, 64 0xf6a, 0x0fffffff, 0x00000000, 65 0xf6b, 0x0fffffff, 0x00000000, 66 0xf6c, 0x0fffffff, 0x00000000, 67 0xf6d, 0x0fffffff, 0x00000000, 68 0xf6e, 0x0fffffff, 0x00000000, 69 }; 70 71 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 72 struct amdgpu_irq_src *src, 73 unsigned type, 74 enum amdgpu_interrupt_state state) 75 { 76 struct amdgpu_vmhub *hub; 77 u32 tmp, reg, bits, i; 78 79 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 80 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 81 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 82 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 83 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 84 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 85 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 86 87 switch (state) { 88 case AMDGPU_IRQ_STATE_DISABLE: 89 /* MM HUB */ 90 hub = &adev->vmhub[AMDGPU_MMHUB]; 91 for (i = 0; i< 16; i++) { 92 reg = hub->vm_context0_cntl + i; 93 tmp = RREG32(reg); 94 tmp &= ~bits; 95 WREG32(reg, tmp); 96 } 97 98 /* GFX HUB */ 99 hub = &adev->vmhub[AMDGPU_GFXHUB]; 100 for (i = 0; i < 16; i++) { 101 reg = hub->vm_context0_cntl + i; 102 tmp = RREG32(reg); 103 tmp &= ~bits; 104 WREG32(reg, tmp); 105 } 106 break; 107 case AMDGPU_IRQ_STATE_ENABLE: 108 /* MM HUB */ 109 hub = &adev->vmhub[AMDGPU_MMHUB]; 110 for (i = 0; i< 16; i++) { 111 reg = hub->vm_context0_cntl + i; 112 tmp = RREG32(reg); 113 tmp |= bits; 114 WREG32(reg, tmp); 115 } 116 117 /* GFX HUB */ 118 hub = &adev->vmhub[AMDGPU_GFXHUB]; 119 for (i = 0; i < 16; i++) { 120 reg = hub->vm_context0_cntl + i; 121 tmp = RREG32(reg); 122 tmp |= bits; 123 WREG32(reg, tmp); 124 } 125 break; 126 default: 127 break; 128 } 129 130 return 0; 131 } 132 133 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 134 struct amdgpu_irq_src *source, 135 struct amdgpu_iv_entry *entry) 136 { 137 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vm_id_src]; 138 uint32_t status = 0; 139 u64 addr; 140 141 addr = (u64)entry->src_data[0] << 12; 142 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 143 144 if (!amdgpu_sriov_vf(adev)) { 145 status = RREG32(hub->vm_l2_pro_fault_status); 146 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 147 } 148 149 if (printk_ratelimit()) { 150 dev_err(adev->dev, 151 "[%s] VMC page fault (src_id:%u ring:%u vm_id:%u pas_id:%u)\n", 152 entry->vm_id_src ? "mmhub" : "gfxhub", 153 entry->src_id, entry->ring_id, entry->vm_id, 154 entry->pas_id); 155 dev_err(adev->dev, " at page 0x%016llx from %d\n", 156 addr, entry->client_id); 157 if (!amdgpu_sriov_vf(adev)) 158 dev_err(adev->dev, 159 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 160 status); 161 } 162 163 return 0; 164 } 165 166 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 167 .set = gmc_v9_0_vm_fault_interrupt_state, 168 .process = gmc_v9_0_process_interrupt, 169 }; 170 171 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 172 { 173 adev->mc.vm_fault.num_types = 1; 174 adev->mc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 175 } 176 177 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vm_id) 178 { 179 u32 req = 0; 180 181 /* invalidate using legacy mode on vm_id*/ 182 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 183 PER_VMID_INVALIDATE_REQ, 1 << vm_id); 184 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0); 185 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 186 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 187 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 188 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 189 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 190 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 191 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 192 193 return req; 194 } 195 196 /* 197 * GART 198 * VMID 0 is the physical GPU addresses as used by the kernel. 199 * VMIDs 1-15 are used for userspace clients and are handled 200 * by the amdgpu vm/hsa code. 201 */ 202 203 /** 204 * gmc_v9_0_gart_flush_gpu_tlb - gart tlb flush callback 205 * 206 * @adev: amdgpu_device pointer 207 * @vmid: vm instance to flush 208 * 209 * Flush the TLB for the requested page table. 210 */ 211 static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, 212 uint32_t vmid) 213 { 214 /* Use register 17 for GART */ 215 const unsigned eng = 17; 216 unsigned i, j; 217 218 /* flush hdp cache */ 219 if (adev->flags & AMD_IS_APU) 220 nbio_v7_0_hdp_flush(adev); 221 else 222 nbio_v6_1_hdp_flush(adev); 223 224 spin_lock(&adev->mc.invalidate_lock); 225 226 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { 227 struct amdgpu_vmhub *hub = &adev->vmhub[i]; 228 u32 tmp = gmc_v9_0_get_invalidate_req(vmid); 229 230 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp); 231 232 /* Busy wait for ACK.*/ 233 for (j = 0; j < 100; j++) { 234 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); 235 tmp &= 1 << vmid; 236 if (tmp) 237 break; 238 cpu_relax(); 239 } 240 if (j < 100) 241 continue; 242 243 /* Wait for ACK with a delay.*/ 244 for (j = 0; j < adev->usec_timeout; j++) { 245 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); 246 tmp &= 1 << vmid; 247 if (tmp) 248 break; 249 udelay(1); 250 } 251 if (j < adev->usec_timeout) 252 continue; 253 254 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 255 } 256 257 spin_unlock(&adev->mc.invalidate_lock); 258 } 259 260 /** 261 * gmc_v9_0_gart_set_pte_pde - update the page tables using MMIO 262 * 263 * @adev: amdgpu_device pointer 264 * @cpu_pt_addr: cpu address of the page table 265 * @gpu_page_idx: entry in the page table to update 266 * @addr: dst addr to write into pte/pde 267 * @flags: access flags 268 * 269 * Update the page tables using the CPU. 270 */ 271 static int gmc_v9_0_gart_set_pte_pde(struct amdgpu_device *adev, 272 void *cpu_pt_addr, 273 uint32_t gpu_page_idx, 274 uint64_t addr, 275 uint64_t flags) 276 { 277 void __iomem *ptr = (void *)cpu_pt_addr; 278 uint64_t value; 279 280 /* 281 * PTE format on VEGA 10: 282 * 63:59 reserved 283 * 58:57 mtype 284 * 56 F 285 * 55 L 286 * 54 P 287 * 53 SW 288 * 52 T 289 * 50:48 reserved 290 * 47:12 4k physical page base address 291 * 11:7 fragment 292 * 6 write 293 * 5 read 294 * 4 exe 295 * 3 Z 296 * 2 snooped 297 * 1 system 298 * 0 valid 299 * 300 * PDE format on VEGA 10: 301 * 63:59 block fragment size 302 * 58:55 reserved 303 * 54 P 304 * 53:48 reserved 305 * 47:6 physical base address of PD or PTE 306 * 5:3 reserved 307 * 2 C 308 * 1 system 309 * 0 valid 310 */ 311 312 /* 313 * The following is for PTE only. GART does not have PDEs. 314 */ 315 value = addr & 0x0000FFFFFFFFF000ULL; 316 value |= flags; 317 writeq(value, ptr + (gpu_page_idx * 8)); 318 return 0; 319 } 320 321 static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev, 322 uint32_t flags) 323 324 { 325 uint64_t pte_flag = 0; 326 327 if (flags & AMDGPU_VM_PAGE_EXECUTABLE) 328 pte_flag |= AMDGPU_PTE_EXECUTABLE; 329 if (flags & AMDGPU_VM_PAGE_READABLE) 330 pte_flag |= AMDGPU_PTE_READABLE; 331 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 332 pte_flag |= AMDGPU_PTE_WRITEABLE; 333 334 switch (flags & AMDGPU_VM_MTYPE_MASK) { 335 case AMDGPU_VM_MTYPE_DEFAULT: 336 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC); 337 break; 338 case AMDGPU_VM_MTYPE_NC: 339 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC); 340 break; 341 case AMDGPU_VM_MTYPE_WC: 342 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_WC); 343 break; 344 case AMDGPU_VM_MTYPE_CC: 345 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_CC); 346 break; 347 case AMDGPU_VM_MTYPE_UC: 348 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_UC); 349 break; 350 default: 351 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC); 352 break; 353 } 354 355 if (flags & AMDGPU_VM_PAGE_PRT) 356 pte_flag |= AMDGPU_PTE_PRT; 357 358 return pte_flag; 359 } 360 361 static u64 gmc_v9_0_adjust_mc_addr(struct amdgpu_device *adev, u64 mc_addr) 362 { 363 return adev->vm_manager.vram_base_offset + mc_addr - adev->mc.vram_start; 364 } 365 366 static const struct amdgpu_gart_funcs gmc_v9_0_gart_funcs = { 367 .flush_gpu_tlb = gmc_v9_0_gart_flush_gpu_tlb, 368 .set_pte_pde = gmc_v9_0_gart_set_pte_pde, 369 .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags, 370 .adjust_mc_addr = gmc_v9_0_adjust_mc_addr, 371 .get_invalidate_req = gmc_v9_0_get_invalidate_req, 372 }; 373 374 static void gmc_v9_0_set_gart_funcs(struct amdgpu_device *adev) 375 { 376 if (adev->gart.gart_funcs == NULL) 377 adev->gart.gart_funcs = &gmc_v9_0_gart_funcs; 378 } 379 380 static int gmc_v9_0_early_init(void *handle) 381 { 382 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 383 384 gmc_v9_0_set_gart_funcs(adev); 385 gmc_v9_0_set_irq_funcs(adev); 386 387 return 0; 388 } 389 390 static int gmc_v9_0_late_init(void *handle) 391 { 392 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 393 unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 3, 3 }; 394 unsigned i; 395 396 for(i = 0; i < adev->num_rings; ++i) { 397 struct amdgpu_ring *ring = adev->rings[i]; 398 unsigned vmhub = ring->funcs->vmhub; 399 400 ring->vm_inv_eng = vm_inv_eng[vmhub]++; 401 dev_info(adev->dev, "ring %u(%s) uses VM inv eng %u on hub %u\n", 402 ring->idx, ring->name, ring->vm_inv_eng, 403 ring->funcs->vmhub); 404 } 405 406 /* Engine 17 is used for GART flushes */ 407 for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i) 408 BUG_ON(vm_inv_eng[i] > 17); 409 410 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0); 411 } 412 413 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 414 struct amdgpu_mc *mc) 415 { 416 u64 base = 0; 417 if (!amdgpu_sriov_vf(adev)) 418 base = mmhub_v1_0_get_fb_location(adev); 419 amdgpu_vram_location(adev, &adev->mc, base); 420 adev->mc.gtt_base_align = 0; 421 amdgpu_gtt_location(adev, mc); 422 /* base offset of vram pages */ 423 if (adev->flags & AMD_IS_APU) 424 adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev); 425 else 426 adev->vm_manager.vram_base_offset = 0; 427 } 428 429 /** 430 * gmc_v9_0_mc_init - initialize the memory controller driver params 431 * 432 * @adev: amdgpu_device pointer 433 * 434 * Look up the amount of vram, vram width, and decide how to place 435 * vram and gart within the GPU's physical address space. 436 * Returns 0 for success. 437 */ 438 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 439 { 440 u32 tmp; 441 int chansize, numchan; 442 443 /* hbm memory channel size */ 444 chansize = 128; 445 446 tmp = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_CS_AON0_DramBaseAddress0)); 447 tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK; 448 tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT; 449 switch (tmp) { 450 case 0: 451 default: 452 numchan = 1; 453 break; 454 case 1: 455 numchan = 2; 456 break; 457 case 2: 458 numchan = 0; 459 break; 460 case 3: 461 numchan = 4; 462 break; 463 case 4: 464 numchan = 0; 465 break; 466 case 5: 467 numchan = 8; 468 break; 469 case 6: 470 numchan = 0; 471 break; 472 case 7: 473 numchan = 16; 474 break; 475 case 8: 476 numchan = 2; 477 break; 478 } 479 adev->mc.vram_width = numchan * chansize; 480 481 /* Could aper size report 0 ? */ 482 adev->mc.aper_base = pci_resource_start(adev->pdev, 0); 483 adev->mc.aper_size = pci_resource_len(adev->pdev, 0); 484 /* size in MB on si */ 485 adev->mc.mc_vram_size = 486 ((adev->flags & AMD_IS_APU) ? nbio_v7_0_get_memsize(adev) : 487 nbio_v6_1_get_memsize(adev)) * 1024ULL * 1024ULL; 488 adev->mc.real_vram_size = adev->mc.mc_vram_size; 489 adev->mc.visible_vram_size = adev->mc.aper_size; 490 491 /* In case the PCI BAR is larger than the actual amount of vram */ 492 if (adev->mc.visible_vram_size > adev->mc.real_vram_size) 493 adev->mc.visible_vram_size = adev->mc.real_vram_size; 494 495 /* unless the user had overridden it, set the gart 496 * size equal to the 1024 or vram, whichever is larger. 497 */ 498 if (amdgpu_gart_size == -1) 499 adev->mc.gtt_size = max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20), 500 adev->mc.mc_vram_size); 501 else 502 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20; 503 504 gmc_v9_0_vram_gtt_location(adev, &adev->mc); 505 506 return 0; 507 } 508 509 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 510 { 511 int r; 512 513 if (adev->gart.robj) { 514 WARN(1, "VEGA10 PCIE GART already initialized\n"); 515 return 0; 516 } 517 /* Initialize common gart structure */ 518 r = amdgpu_gart_init(adev); 519 if (r) 520 return r; 521 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 522 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE(MTYPE_UC) | 523 AMDGPU_PTE_EXECUTABLE; 524 return amdgpu_gart_table_vram_alloc(adev); 525 } 526 527 /* 528 * vm 529 * VMID 0 is the physical GPU addresses as used by the kernel. 530 * VMIDs 1-15 are used for userspace clients and are handled 531 * by the amdgpu vm/hsa code. 532 */ 533 /** 534 * gmc_v9_0_vm_init - vm init callback 535 * 536 * @adev: amdgpu_device pointer 537 * 538 * Inits vega10 specific vm parameters (number of VMs, base of vram for 539 * VMIDs 1-15) (vega10). 540 * Returns 0 for success. 541 */ 542 static int gmc_v9_0_vm_init(struct amdgpu_device *adev) 543 { 544 /* 545 * number of VMs 546 * VMID 0 is reserved for System 547 * amdgpu graphics/compute will use VMIDs 1-7 548 * amdkfd will use VMIDs 8-15 549 */ 550 adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS; 551 adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS; 552 553 /* TODO: fix num_level for APU when updating vm size and block size */ 554 if (adev->flags & AMD_IS_APU) 555 adev->vm_manager.num_level = 1; 556 else 557 adev->vm_manager.num_level = 3; 558 amdgpu_vm_manager_init(adev); 559 560 return 0; 561 } 562 563 /** 564 * gmc_v9_0_vm_fini - vm fini callback 565 * 566 * @adev: amdgpu_device pointer 567 * 568 * Tear down any asic specific VM setup. 569 */ 570 static void gmc_v9_0_vm_fini(struct amdgpu_device *adev) 571 { 572 return; 573 } 574 575 static int gmc_v9_0_sw_init(void *handle) 576 { 577 int r; 578 int dma_bits; 579 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 580 581 spin_lock_init(&adev->mc.invalidate_lock); 582 583 if (adev->flags & AMD_IS_APU) { 584 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 585 amdgpu_vm_adjust_size(adev, 64); 586 } else { 587 /* XXX Don't know how to get VRAM type yet. */ 588 adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM; 589 /* 590 * To fulfill 4-level page support, 591 * vm size is 256TB (48bit), maximum size of Vega10, 592 * block size 512 (9bit) 593 */ 594 adev->vm_manager.vm_size = 1U << 18; 595 adev->vm_manager.block_size = 9; 596 DRM_INFO("vm size is %llu GB, block size is %u-bit\n", 597 adev->vm_manager.vm_size, 598 adev->vm_manager.block_size); 599 } 600 601 /* This interrupt is VMC page fault.*/ 602 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0, 603 &adev->mc.vm_fault); 604 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UTCL2, 0, 605 &adev->mc.vm_fault); 606 607 if (r) 608 return r; 609 610 adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; 611 612 /* Set the internal MC address mask 613 * This is the max address of the GPU's 614 * internal address space. 615 */ 616 adev->mc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 617 618 /* set DMA mask + need_dma32 flags. 619 * PCIE - can handle 44-bits. 620 * IGP - can handle 44-bits 621 * PCI - dma32 for legacy pci gart, 44 bits on vega10 622 */ 623 adev->need_dma32 = false; 624 dma_bits = adev->need_dma32 ? 32 : 44; 625 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 626 if (r) { 627 adev->need_dma32 = true; 628 dma_bits = 32; 629 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 630 } 631 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 632 if (r) { 633 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); 634 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n"); 635 } 636 637 r = gmc_v9_0_mc_init(adev); 638 if (r) 639 return r; 640 641 /* Memory manager */ 642 r = amdgpu_bo_init(adev); 643 if (r) 644 return r; 645 646 r = gmc_v9_0_gart_init(adev); 647 if (r) 648 return r; 649 650 if (!adev->vm_manager.enabled) { 651 r = gmc_v9_0_vm_init(adev); 652 if (r) { 653 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r); 654 return r; 655 } 656 adev->vm_manager.enabled = true; 657 } 658 return r; 659 } 660 661 /** 662 * gmc_v8_0_gart_fini - vm fini callback 663 * 664 * @adev: amdgpu_device pointer 665 * 666 * Tears down the driver GART/VM setup (CIK). 667 */ 668 static void gmc_v9_0_gart_fini(struct amdgpu_device *adev) 669 { 670 amdgpu_gart_table_vram_free(adev); 671 amdgpu_gart_fini(adev); 672 } 673 674 static int gmc_v9_0_sw_fini(void *handle) 675 { 676 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 677 678 if (adev->vm_manager.enabled) { 679 amdgpu_vm_manager_fini(adev); 680 gmc_v9_0_vm_fini(adev); 681 adev->vm_manager.enabled = false; 682 } 683 gmc_v9_0_gart_fini(adev); 684 amdgpu_gem_force_release(adev); 685 amdgpu_bo_fini(adev); 686 687 return 0; 688 } 689 690 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 691 { 692 switch (adev->asic_type) { 693 case CHIP_VEGA10: 694 break; 695 case CHIP_RAVEN: 696 break; 697 default: 698 break; 699 } 700 } 701 702 /** 703 * gmc_v9_0_gart_enable - gart enable 704 * 705 * @adev: amdgpu_device pointer 706 */ 707 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 708 { 709 int r; 710 bool value; 711 u32 tmp; 712 713 amdgpu_program_register_sequence(adev, 714 golden_settings_vega10_hdp, 715 (const u32)ARRAY_SIZE(golden_settings_vega10_hdp)); 716 717 if (adev->gart.robj == NULL) { 718 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 719 return -EINVAL; 720 } 721 r = amdgpu_gart_table_vram_pin(adev); 722 if (r) 723 return r; 724 725 /* After HDP is initialized, flush HDP.*/ 726 if (adev->flags & AMD_IS_APU) 727 nbio_v7_0_hdp_flush(adev); 728 else 729 nbio_v6_1_hdp_flush(adev); 730 731 r = gfxhub_v1_0_gart_enable(adev); 732 if (r) 733 return r; 734 735 r = mmhub_v1_0_gart_enable(adev); 736 if (r) 737 return r; 738 739 tmp = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MISC_CNTL)); 740 tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK; 741 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MISC_CNTL), tmp); 742 743 tmp = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_HOST_PATH_CNTL)); 744 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_HOST_PATH_CNTL), tmp); 745 746 747 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 748 value = false; 749 else 750 value = true; 751 752 gfxhub_v1_0_set_fault_enable_default(adev, value); 753 mmhub_v1_0_set_fault_enable_default(adev, value); 754 755 gmc_v9_0_gart_flush_gpu_tlb(adev, 0); 756 757 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 758 (unsigned)(adev->mc.gtt_size >> 20), 759 (unsigned long long)adev->gart.table_addr); 760 adev->gart.ready = true; 761 return 0; 762 } 763 764 static int gmc_v9_0_hw_init(void *handle) 765 { 766 int r; 767 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 768 769 /* The sequence of these two function calls matters.*/ 770 gmc_v9_0_init_golden_registers(adev); 771 772 r = gmc_v9_0_gart_enable(adev); 773 774 return r; 775 } 776 777 /** 778 * gmc_v9_0_gart_disable - gart disable 779 * 780 * @adev: amdgpu_device pointer 781 * 782 * This disables all VM page table. 783 */ 784 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 785 { 786 gfxhub_v1_0_gart_disable(adev); 787 mmhub_v1_0_gart_disable(adev); 788 amdgpu_gart_table_vram_unpin(adev); 789 } 790 791 static int gmc_v9_0_hw_fini(void *handle) 792 { 793 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 794 795 if (amdgpu_sriov_vf(adev)) { 796 /* full access mode, so don't touch any GMC register */ 797 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 798 return 0; 799 } 800 801 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0); 802 gmc_v9_0_gart_disable(adev); 803 804 return 0; 805 } 806 807 static int gmc_v9_0_suspend(void *handle) 808 { 809 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 810 811 gmc_v9_0_hw_fini(adev); 812 813 return 0; 814 } 815 816 static int gmc_v9_0_resume(void *handle) 817 { 818 int r; 819 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 820 821 r = gmc_v9_0_hw_init(adev); 822 if (r) 823 return r; 824 825 amdgpu_vm_reset_all_ids(adev); 826 827 return 0; 828 } 829 830 static bool gmc_v9_0_is_idle(void *handle) 831 { 832 /* MC is always ready in GMC v9.*/ 833 return true; 834 } 835 836 static int gmc_v9_0_wait_for_idle(void *handle) 837 { 838 /* There is no need to wait for MC idle in GMC v9.*/ 839 return 0; 840 } 841 842 static int gmc_v9_0_soft_reset(void *handle) 843 { 844 /* XXX for emulation.*/ 845 return 0; 846 } 847 848 static int gmc_v9_0_set_clockgating_state(void *handle, 849 enum amd_clockgating_state state) 850 { 851 return 0; 852 } 853 854 static int gmc_v9_0_set_powergating_state(void *handle, 855 enum amd_powergating_state state) 856 { 857 return 0; 858 } 859 860 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 861 .name = "gmc_v9_0", 862 .early_init = gmc_v9_0_early_init, 863 .late_init = gmc_v9_0_late_init, 864 .sw_init = gmc_v9_0_sw_init, 865 .sw_fini = gmc_v9_0_sw_fini, 866 .hw_init = gmc_v9_0_hw_init, 867 .hw_fini = gmc_v9_0_hw_fini, 868 .suspend = gmc_v9_0_suspend, 869 .resume = gmc_v9_0_resume, 870 .is_idle = gmc_v9_0_is_idle, 871 .wait_for_idle = gmc_v9_0_wait_for_idle, 872 .soft_reset = gmc_v9_0_soft_reset, 873 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 874 .set_powergating_state = gmc_v9_0_set_powergating_state, 875 }; 876 877 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = 878 { 879 .type = AMD_IP_BLOCK_TYPE_GMC, 880 .major = 9, 881 .minor = 0, 882 .rev = 0, 883 .funcs = &gmc_v9_0_ip_funcs, 884 }; 885