1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/pci.h> 26 27 #include <drm/drm_cache.h> 28 29 #include "amdgpu.h" 30 #include "gmc_v9_0.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_gem.h" 33 34 #include "gc/gc_9_0_sh_mask.h" 35 #include "dce/dce_12_0_offset.h" 36 #include "dce/dce_12_0_sh_mask.h" 37 #include "vega10_enum.h" 38 #include "mmhub/mmhub_1_0_offset.h" 39 #include "athub/athub_1_0_sh_mask.h" 40 #include "athub/athub_1_0_offset.h" 41 #include "oss/osssys_4_0_offset.h" 42 43 #include "soc15.h" 44 #include "soc15d.h" 45 #include "soc15_common.h" 46 #include "umc/umc_6_0_sh_mask.h" 47 48 #include "gfxhub_v1_0.h" 49 #include "mmhub_v1_0.h" 50 #include "athub_v1_0.h" 51 #include "gfxhub_v1_1.h" 52 #include "gfxhub_v1_2.h" 53 #include "mmhub_v9_4.h" 54 #include "mmhub_v1_7.h" 55 #include "mmhub_v1_8.h" 56 #include "umc_v6_1.h" 57 #include "umc_v6_0.h" 58 #include "umc_v6_7.h" 59 #include "hdp_v4_0.h" 60 #include "mca_v3_0.h" 61 62 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 63 64 #include "amdgpu_ras.h" 65 #include "amdgpu_xgmi.h" 66 67 #include "amdgpu_reset.h" 68 69 /* add these here since we already include dce12 headers and these are for DCN */ 70 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 71 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 72 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 73 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 74 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL 75 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L 76 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d 77 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2 78 79 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2 0x05ea 80 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX 2 81 82 83 static const char *gfxhub_client_ids[] = { 84 "CB", 85 "DB", 86 "IA", 87 "WD", 88 "CPF", 89 "CPC", 90 "CPG", 91 "RLC", 92 "TCP", 93 "SQC (inst)", 94 "SQC (data)", 95 "SQG", 96 "PA", 97 }; 98 99 static const char *mmhub_client_ids_raven[][2] = { 100 [0][0] = "MP1", 101 [1][0] = "MP0", 102 [2][0] = "VCN", 103 [3][0] = "VCNU", 104 [4][0] = "HDP", 105 [5][0] = "DCE", 106 [13][0] = "UTCL2", 107 [19][0] = "TLS", 108 [26][0] = "OSS", 109 [27][0] = "SDMA0", 110 [0][1] = "MP1", 111 [1][1] = "MP0", 112 [2][1] = "VCN", 113 [3][1] = "VCNU", 114 [4][1] = "HDP", 115 [5][1] = "XDP", 116 [6][1] = "DBGU0", 117 [7][1] = "DCE", 118 [8][1] = "DCEDWB0", 119 [9][1] = "DCEDWB1", 120 [26][1] = "OSS", 121 [27][1] = "SDMA0", 122 }; 123 124 static const char *mmhub_client_ids_renoir[][2] = { 125 [0][0] = "MP1", 126 [1][0] = "MP0", 127 [2][0] = "HDP", 128 [4][0] = "DCEDMC", 129 [5][0] = "DCEVGA", 130 [13][0] = "UTCL2", 131 [19][0] = "TLS", 132 [26][0] = "OSS", 133 [27][0] = "SDMA0", 134 [28][0] = "VCN", 135 [29][0] = "VCNU", 136 [30][0] = "JPEG", 137 [0][1] = "MP1", 138 [1][1] = "MP0", 139 [2][1] = "HDP", 140 [3][1] = "XDP", 141 [6][1] = "DBGU0", 142 [7][1] = "DCEDMC", 143 [8][1] = "DCEVGA", 144 [9][1] = "DCEDWB", 145 [26][1] = "OSS", 146 [27][1] = "SDMA0", 147 [28][1] = "VCN", 148 [29][1] = "VCNU", 149 [30][1] = "JPEG", 150 }; 151 152 static const char *mmhub_client_ids_vega10[][2] = { 153 [0][0] = "MP0", 154 [1][0] = "UVD", 155 [2][0] = "UVDU", 156 [3][0] = "HDP", 157 [13][0] = "UTCL2", 158 [14][0] = "OSS", 159 [15][0] = "SDMA1", 160 [32+0][0] = "VCE0", 161 [32+1][0] = "VCE0U", 162 [32+2][0] = "XDMA", 163 [32+3][0] = "DCE", 164 [32+4][0] = "MP1", 165 [32+14][0] = "SDMA0", 166 [0][1] = "MP0", 167 [1][1] = "UVD", 168 [2][1] = "UVDU", 169 [3][1] = "DBGU0", 170 [4][1] = "HDP", 171 [5][1] = "XDP", 172 [14][1] = "OSS", 173 [15][1] = "SDMA0", 174 [32+0][1] = "VCE0", 175 [32+1][1] = "VCE0U", 176 [32+2][1] = "XDMA", 177 [32+3][1] = "DCE", 178 [32+4][1] = "DCEDWB", 179 [32+5][1] = "MP1", 180 [32+6][1] = "DBGU1", 181 [32+14][1] = "SDMA1", 182 }; 183 184 static const char *mmhub_client_ids_vega12[][2] = { 185 [0][0] = "MP0", 186 [1][0] = "VCE0", 187 [2][0] = "VCE0U", 188 [3][0] = "HDP", 189 [13][0] = "UTCL2", 190 [14][0] = "OSS", 191 [15][0] = "SDMA1", 192 [32+0][0] = "DCE", 193 [32+1][0] = "XDMA", 194 [32+2][0] = "UVD", 195 [32+3][0] = "UVDU", 196 [32+4][0] = "MP1", 197 [32+15][0] = "SDMA0", 198 [0][1] = "MP0", 199 [1][1] = "VCE0", 200 [2][1] = "VCE0U", 201 [3][1] = "DBGU0", 202 [4][1] = "HDP", 203 [5][1] = "XDP", 204 [14][1] = "OSS", 205 [15][1] = "SDMA0", 206 [32+0][1] = "DCE", 207 [32+1][1] = "DCEDWB", 208 [32+2][1] = "XDMA", 209 [32+3][1] = "UVD", 210 [32+4][1] = "UVDU", 211 [32+5][1] = "MP1", 212 [32+6][1] = "DBGU1", 213 [32+15][1] = "SDMA1", 214 }; 215 216 static const char *mmhub_client_ids_vega20[][2] = { 217 [0][0] = "XDMA", 218 [1][0] = "DCE", 219 [2][0] = "VCE0", 220 [3][0] = "VCE0U", 221 [4][0] = "UVD", 222 [5][0] = "UVD1U", 223 [13][0] = "OSS", 224 [14][0] = "HDP", 225 [15][0] = "SDMA0", 226 [32+0][0] = "UVD", 227 [32+1][0] = "UVDU", 228 [32+2][0] = "MP1", 229 [32+3][0] = "MP0", 230 [32+12][0] = "UTCL2", 231 [32+14][0] = "SDMA1", 232 [0][1] = "XDMA", 233 [1][1] = "DCE", 234 [2][1] = "DCEDWB", 235 [3][1] = "VCE0", 236 [4][1] = "VCE0U", 237 [5][1] = "UVD1", 238 [6][1] = "UVD1U", 239 [7][1] = "DBGU0", 240 [8][1] = "XDP", 241 [13][1] = "OSS", 242 [14][1] = "HDP", 243 [15][1] = "SDMA0", 244 [32+0][1] = "UVD", 245 [32+1][1] = "UVDU", 246 [32+2][1] = "DBGU1", 247 [32+3][1] = "MP1", 248 [32+4][1] = "MP0", 249 [32+14][1] = "SDMA1", 250 }; 251 252 static const char *mmhub_client_ids_arcturus[][2] = { 253 [0][0] = "DBGU1", 254 [1][0] = "XDP", 255 [2][0] = "MP1", 256 [14][0] = "HDP", 257 [171][0] = "JPEG", 258 [172][0] = "VCN", 259 [173][0] = "VCNU", 260 [203][0] = "JPEG1", 261 [204][0] = "VCN1", 262 [205][0] = "VCN1U", 263 [256][0] = "SDMA0", 264 [257][0] = "SDMA1", 265 [258][0] = "SDMA2", 266 [259][0] = "SDMA3", 267 [260][0] = "SDMA4", 268 [261][0] = "SDMA5", 269 [262][0] = "SDMA6", 270 [263][0] = "SDMA7", 271 [384][0] = "OSS", 272 [0][1] = "DBGU1", 273 [1][1] = "XDP", 274 [2][1] = "MP1", 275 [14][1] = "HDP", 276 [171][1] = "JPEG", 277 [172][1] = "VCN", 278 [173][1] = "VCNU", 279 [203][1] = "JPEG1", 280 [204][1] = "VCN1", 281 [205][1] = "VCN1U", 282 [256][1] = "SDMA0", 283 [257][1] = "SDMA1", 284 [258][1] = "SDMA2", 285 [259][1] = "SDMA3", 286 [260][1] = "SDMA4", 287 [261][1] = "SDMA5", 288 [262][1] = "SDMA6", 289 [263][1] = "SDMA7", 290 [384][1] = "OSS", 291 }; 292 293 static const char *mmhub_client_ids_aldebaran[][2] = { 294 [2][0] = "MP1", 295 [3][0] = "MP0", 296 [32+1][0] = "DBGU_IO0", 297 [32+2][0] = "DBGU_IO2", 298 [32+4][0] = "MPIO", 299 [96+11][0] = "JPEG0", 300 [96+12][0] = "VCN0", 301 [96+13][0] = "VCNU0", 302 [128+11][0] = "JPEG1", 303 [128+12][0] = "VCN1", 304 [128+13][0] = "VCNU1", 305 [160+1][0] = "XDP", 306 [160+14][0] = "HDP", 307 [256+0][0] = "SDMA0", 308 [256+1][0] = "SDMA1", 309 [256+2][0] = "SDMA2", 310 [256+3][0] = "SDMA3", 311 [256+4][0] = "SDMA4", 312 [384+0][0] = "OSS", 313 [2][1] = "MP1", 314 [3][1] = "MP0", 315 [32+1][1] = "DBGU_IO0", 316 [32+2][1] = "DBGU_IO2", 317 [32+4][1] = "MPIO", 318 [96+11][1] = "JPEG0", 319 [96+12][1] = "VCN0", 320 [96+13][1] = "VCNU0", 321 [128+11][1] = "JPEG1", 322 [128+12][1] = "VCN1", 323 [128+13][1] = "VCNU1", 324 [160+1][1] = "XDP", 325 [160+14][1] = "HDP", 326 [256+0][1] = "SDMA0", 327 [256+1][1] = "SDMA1", 328 [256+2][1] = "SDMA2", 329 [256+3][1] = "SDMA3", 330 [256+4][1] = "SDMA4", 331 [384+0][1] = "OSS", 332 }; 333 334 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = 335 { 336 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), 337 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) 338 }; 339 340 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = 341 { 342 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), 343 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) 344 }; 345 346 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { 347 (0x000143c0 + 0x00000000), 348 (0x000143c0 + 0x00000800), 349 (0x000143c0 + 0x00001000), 350 (0x000143c0 + 0x00001800), 351 (0x000543c0 + 0x00000000), 352 (0x000543c0 + 0x00000800), 353 (0x000543c0 + 0x00001000), 354 (0x000543c0 + 0x00001800), 355 (0x000943c0 + 0x00000000), 356 (0x000943c0 + 0x00000800), 357 (0x000943c0 + 0x00001000), 358 (0x000943c0 + 0x00001800), 359 (0x000d43c0 + 0x00000000), 360 (0x000d43c0 + 0x00000800), 361 (0x000d43c0 + 0x00001000), 362 (0x000d43c0 + 0x00001800), 363 (0x001143c0 + 0x00000000), 364 (0x001143c0 + 0x00000800), 365 (0x001143c0 + 0x00001000), 366 (0x001143c0 + 0x00001800), 367 (0x001543c0 + 0x00000000), 368 (0x001543c0 + 0x00000800), 369 (0x001543c0 + 0x00001000), 370 (0x001543c0 + 0x00001800), 371 (0x001943c0 + 0x00000000), 372 (0x001943c0 + 0x00000800), 373 (0x001943c0 + 0x00001000), 374 (0x001943c0 + 0x00001800), 375 (0x001d43c0 + 0x00000000), 376 (0x001d43c0 + 0x00000800), 377 (0x001d43c0 + 0x00001000), 378 (0x001d43c0 + 0x00001800), 379 }; 380 381 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { 382 (0x000143e0 + 0x00000000), 383 (0x000143e0 + 0x00000800), 384 (0x000143e0 + 0x00001000), 385 (0x000143e0 + 0x00001800), 386 (0x000543e0 + 0x00000000), 387 (0x000543e0 + 0x00000800), 388 (0x000543e0 + 0x00001000), 389 (0x000543e0 + 0x00001800), 390 (0x000943e0 + 0x00000000), 391 (0x000943e0 + 0x00000800), 392 (0x000943e0 + 0x00001000), 393 (0x000943e0 + 0x00001800), 394 (0x000d43e0 + 0x00000000), 395 (0x000d43e0 + 0x00000800), 396 (0x000d43e0 + 0x00001000), 397 (0x000d43e0 + 0x00001800), 398 (0x001143e0 + 0x00000000), 399 (0x001143e0 + 0x00000800), 400 (0x001143e0 + 0x00001000), 401 (0x001143e0 + 0x00001800), 402 (0x001543e0 + 0x00000000), 403 (0x001543e0 + 0x00000800), 404 (0x001543e0 + 0x00001000), 405 (0x001543e0 + 0x00001800), 406 (0x001943e0 + 0x00000000), 407 (0x001943e0 + 0x00000800), 408 (0x001943e0 + 0x00001000), 409 (0x001943e0 + 0x00001800), 410 (0x001d43e0 + 0x00000000), 411 (0x001d43e0 + 0x00000800), 412 (0x001d43e0 + 0x00001000), 413 (0x001d43e0 + 0x00001800), 414 }; 415 416 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, 417 struct amdgpu_irq_src *src, 418 unsigned type, 419 enum amdgpu_interrupt_state state) 420 { 421 u32 bits, i, tmp, reg; 422 423 /* Devices newer then VEGA10/12 shall have these programming 424 sequences performed by PSP BL */ 425 if (adev->asic_type >= CHIP_VEGA20) 426 return 0; 427 428 bits = 0x7f; 429 430 switch (state) { 431 case AMDGPU_IRQ_STATE_DISABLE: 432 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 433 reg = ecc_umc_mcumc_ctrl_addrs[i]; 434 tmp = RREG32(reg); 435 tmp &= ~bits; 436 WREG32(reg, tmp); 437 } 438 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 439 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 440 tmp = RREG32(reg); 441 tmp &= ~bits; 442 WREG32(reg, tmp); 443 } 444 break; 445 case AMDGPU_IRQ_STATE_ENABLE: 446 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 447 reg = ecc_umc_mcumc_ctrl_addrs[i]; 448 tmp = RREG32(reg); 449 tmp |= bits; 450 WREG32(reg, tmp); 451 } 452 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 453 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 454 tmp = RREG32(reg); 455 tmp |= bits; 456 WREG32(reg, tmp); 457 } 458 break; 459 default: 460 break; 461 } 462 463 return 0; 464 } 465 466 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 467 struct amdgpu_irq_src *src, 468 unsigned type, 469 enum amdgpu_interrupt_state state) 470 { 471 struct amdgpu_vmhub *hub; 472 u32 tmp, reg, bits, i, j; 473 474 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 475 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 476 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 477 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 478 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 479 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 480 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 481 482 switch (state) { 483 case AMDGPU_IRQ_STATE_DISABLE: 484 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 485 hub = &adev->vmhub[j]; 486 for (i = 0; i < 16; i++) { 487 reg = hub->vm_context0_cntl + i; 488 489 /* This works because this interrupt is only 490 * enabled at init/resume and disabled in 491 * fini/suspend, so the overall state doesn't 492 * change over the course of suspend/resume. 493 */ 494 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 495 continue; 496 497 if (j >= AMDGPU_MMHUB0(0)) 498 tmp = RREG32_SOC15_IP(MMHUB, reg); 499 else 500 tmp = RREG32_SOC15_IP(GC, reg); 501 502 tmp &= ~bits; 503 504 if (j >= AMDGPU_MMHUB0(0)) 505 WREG32_SOC15_IP(MMHUB, reg, tmp); 506 else 507 WREG32_SOC15_IP(GC, reg, tmp); 508 } 509 } 510 break; 511 case AMDGPU_IRQ_STATE_ENABLE: 512 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 513 hub = &adev->vmhub[j]; 514 for (i = 0; i < 16; i++) { 515 reg = hub->vm_context0_cntl + i; 516 517 /* This works because this interrupt is only 518 * enabled at init/resume and disabled in 519 * fini/suspend, so the overall state doesn't 520 * change over the course of suspend/resume. 521 */ 522 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 523 continue; 524 525 if (j >= AMDGPU_MMHUB0(0)) 526 tmp = RREG32_SOC15_IP(MMHUB, reg); 527 else 528 tmp = RREG32_SOC15_IP(GC, reg); 529 530 tmp |= bits; 531 532 if (j >= AMDGPU_MMHUB0(0)) 533 WREG32_SOC15_IP(MMHUB, reg, tmp); 534 else 535 WREG32_SOC15_IP(GC, reg, tmp); 536 } 537 } 538 break; 539 default: 540 break; 541 } 542 543 return 0; 544 } 545 546 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 547 struct amdgpu_irq_src *source, 548 struct amdgpu_iv_entry *entry) 549 { 550 bool retry_fault = !!(entry->src_data[1] & 0x80); 551 bool write_fault = !!(entry->src_data[1] & 0x20); 552 uint32_t status = 0, cid = 0, rw = 0; 553 struct amdgpu_task_info task_info; 554 struct amdgpu_vmhub *hub; 555 const char *mmhub_cid; 556 const char *hub_name; 557 u64 addr; 558 uint32_t cam_index = 0; 559 int ret; 560 uint32_t node_id, xcc_id = 0; 561 562 node_id = entry->node_id; 563 564 addr = (u64)entry->src_data[0] << 12; 565 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 566 567 if (entry->client_id == SOC15_IH_CLIENTID_VMC) { 568 hub_name = "mmhub0"; 569 hub = &adev->vmhub[AMDGPU_MMHUB0(node_id / 4)]; 570 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) { 571 hub_name = "mmhub1"; 572 hub = &adev->vmhub[AMDGPU_MMHUB1(0)]; 573 } else { 574 hub_name = "gfxhub0"; 575 if (adev->gfx.funcs->ih_node_to_logical_xcc) { 576 xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev, 577 node_id); 578 if (xcc_id < 0) 579 xcc_id = 0; 580 } 581 hub = &adev->vmhub[xcc_id]; 582 } 583 584 if (retry_fault) { 585 if (adev->irq.retry_cam_enabled) { 586 /* Delegate it to a different ring if the hardware hasn't 587 * already done it. 588 */ 589 if (entry->ih == &adev->irq.ih) { 590 amdgpu_irq_delegate(adev, entry, 8); 591 return 1; 592 } 593 594 cam_index = entry->src_data[2] & 0x3ff; 595 596 ret = amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 597 addr, write_fault); 598 WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index); 599 if (ret) 600 return 1; 601 } else { 602 /* Process it onyl if it's the first fault for this address */ 603 if (entry->ih != &adev->irq.ih_soft && 604 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, 605 entry->timestamp)) 606 return 1; 607 608 /* Delegate it to a different ring if the hardware hasn't 609 * already done it. 610 */ 611 if (entry->ih == &adev->irq.ih) { 612 amdgpu_irq_delegate(adev, entry, 8); 613 return 1; 614 } 615 616 /* Try to handle the recoverable page faults by filling page 617 * tables 618 */ 619 if (amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 620 addr, write_fault)) 621 return 1; 622 } 623 } 624 625 if (!printk_ratelimit()) 626 return 0; 627 628 629 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 630 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 631 632 dev_err(adev->dev, 633 "[%s] %s page fault (src_id:%u ring:%u vmid:%u " 634 "pasid:%u, for process %s pid %d thread %s pid %d)\n", 635 hub_name, retry_fault ? "retry" : "no-retry", 636 entry->src_id, entry->ring_id, entry->vmid, 637 entry->pasid, task_info.process_name, task_info.tgid, 638 task_info.task_name, task_info.pid); 639 dev_err(adev->dev, " in page starting at address 0x%016llx from IH client 0x%x (%s)\n", 640 addr, entry->client_id, 641 soc15_ih_clientid_name[entry->client_id]); 642 643 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) 644 dev_err(adev->dev, " cookie node_id %d fault from die %s%d%s\n", 645 node_id, node_id % 4 == 3 ? "RSV" : "AID", node_id / 4, 646 node_id % 4 == 1 ? ".XCD0" : node_id % 4 == 2 ? ".XCD1" : ""); 647 648 if (amdgpu_sriov_vf(adev)) 649 return 0; 650 651 /* 652 * Issue a dummy read to wait for the status register to 653 * be updated to avoid reading an incorrect value due to 654 * the new fast GRBM interface. 655 */ 656 if ((entry->vmid_src == AMDGPU_GFXHUB(0)) && 657 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2))) 658 RREG32(hub->vm_l2_pro_fault_status); 659 660 status = RREG32(hub->vm_l2_pro_fault_status); 661 cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID); 662 rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW); 663 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 664 665 dev_err(adev->dev, 666 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 667 status); 668 if (entry->vmid_src == AMDGPU_GFXHUB(0)) { 669 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 670 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : 671 gfxhub_client_ids[cid], 672 cid); 673 } else { 674 switch (adev->ip_versions[MMHUB_HWIP][0]) { 675 case IP_VERSION(9, 0, 0): 676 mmhub_cid = mmhub_client_ids_vega10[cid][rw]; 677 break; 678 case IP_VERSION(9, 3, 0): 679 mmhub_cid = mmhub_client_ids_vega12[cid][rw]; 680 break; 681 case IP_VERSION(9, 4, 0): 682 mmhub_cid = mmhub_client_ids_vega20[cid][rw]; 683 break; 684 case IP_VERSION(9, 4, 1): 685 mmhub_cid = mmhub_client_ids_arcturus[cid][rw]; 686 break; 687 case IP_VERSION(9, 1, 0): 688 case IP_VERSION(9, 2, 0): 689 mmhub_cid = mmhub_client_ids_raven[cid][rw]; 690 break; 691 case IP_VERSION(1, 5, 0): 692 case IP_VERSION(2, 4, 0): 693 mmhub_cid = mmhub_client_ids_renoir[cid][rw]; 694 break; 695 case IP_VERSION(1, 8, 0): 696 case IP_VERSION(9, 4, 2): 697 mmhub_cid = mmhub_client_ids_aldebaran[cid][rw]; 698 break; 699 default: 700 mmhub_cid = NULL; 701 break; 702 } 703 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 704 mmhub_cid ? mmhub_cid : "unknown", cid); 705 } 706 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 707 REG_GET_FIELD(status, 708 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 709 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 710 REG_GET_FIELD(status, 711 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 712 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 713 REG_GET_FIELD(status, 714 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 715 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 716 REG_GET_FIELD(status, 717 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 718 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 719 return 0; 720 } 721 722 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 723 .set = gmc_v9_0_vm_fault_interrupt_state, 724 .process = gmc_v9_0_process_interrupt, 725 }; 726 727 728 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { 729 .set = gmc_v9_0_ecc_interrupt_state, 730 .process = amdgpu_umc_process_ecc_irq, 731 }; 732 733 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 734 { 735 adev->gmc.vm_fault.num_types = 1; 736 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 737 738 if (!amdgpu_sriov_vf(adev) && 739 !adev->gmc.xgmi.connected_to_cpu) { 740 adev->gmc.ecc_irq.num_types = 1; 741 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; 742 } 743 } 744 745 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, 746 uint32_t flush_type) 747 { 748 u32 req = 0; 749 750 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 751 PER_VMID_INVALIDATE_REQ, 1 << vmid); 752 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 753 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 754 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 755 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 756 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 757 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 758 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 759 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 760 761 return req; 762 } 763 764 /** 765 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore 766 * 767 * @adev: amdgpu_device pointer 768 * @vmhub: vmhub type 769 * 770 */ 771 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev, 772 uint32_t vmhub) 773 { 774 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) || 775 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) 776 return false; 777 778 return ((vmhub == AMDGPU_MMHUB0(0) || 779 vmhub == AMDGPU_MMHUB1(0)) && 780 (!amdgpu_sriov_vf(adev)) && 781 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) && 782 (adev->apu_flags & AMD_APU_IS_PICASSO)))); 783 } 784 785 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, 786 uint8_t vmid, uint16_t *p_pasid) 787 { 788 uint32_t value; 789 790 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 791 + vmid); 792 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 793 794 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 795 } 796 797 /* 798 * GART 799 * VMID 0 is the physical GPU addresses as used by the kernel. 800 * VMIDs 1-15 are used for userspace clients and are handled 801 * by the amdgpu vm/hsa code. 802 */ 803 804 /** 805 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type 806 * 807 * @adev: amdgpu_device pointer 808 * @vmid: vm instance to flush 809 * @vmhub: which hub to flush 810 * @flush_type: the flush type 811 * 812 * Flush the TLB for the requested page table using certain type. 813 */ 814 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 815 uint32_t vmhub, uint32_t flush_type) 816 { 817 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub); 818 const unsigned eng = 17; 819 u32 j, inv_req, inv_req2, tmp; 820 struct amdgpu_vmhub *hub; 821 822 BUG_ON(vmhub >= AMDGPU_MAX_VMHUBS); 823 824 hub = &adev->vmhub[vmhub]; 825 if (adev->gmc.xgmi.num_physical_nodes && 826 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0)) { 827 /* Vega20+XGMI caches PTEs in TC and TLB. Add a 828 * heavy-weight TLB flush (type 2), which flushes 829 * both. Due to a race condition with concurrent 830 * memory accesses using the same TLB cache line, we 831 * still need a second TLB flush after this. 832 */ 833 inv_req = gmc_v9_0_get_invalidate_req(vmid, 2); 834 inv_req2 = gmc_v9_0_get_invalidate_req(vmid, flush_type); 835 } else { 836 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type); 837 inv_req2 = 0; 838 } 839 840 /* This is necessary for a HW workaround under SRIOV as well 841 * as GFXOFF under bare metal 842 */ 843 if (adev->gfx.kiq[0].ring.sched.ready && 844 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && 845 down_read_trylock(&adev->reset_domain->sem)) { 846 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 847 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 848 849 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 850 1 << vmid); 851 up_read(&adev->reset_domain->sem); 852 return; 853 } 854 855 spin_lock(&adev->gmc.invalidate_lock); 856 857 /* 858 * It may lose gpuvm invalidate acknowldege state across power-gating 859 * off cycle, add semaphore acquire before invalidation and semaphore 860 * release after invalidation to avoid entering power gated state 861 * to WA the Issue 862 */ 863 864 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 865 if (use_semaphore) { 866 for (j = 0; j < adev->usec_timeout; j++) { 867 /* a read return value of 1 means semaphore acquire */ 868 if (vmhub >= AMDGPU_MMHUB0(0)) 869 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_sem + hub->eng_distance * eng); 870 else 871 tmp = RREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_sem + hub->eng_distance * eng); 872 if (tmp & 0x1) 873 break; 874 udelay(1); 875 } 876 877 if (j >= adev->usec_timeout) 878 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 879 } 880 881 do { 882 if (vmhub >= AMDGPU_MMHUB0(0)) 883 WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req); 884 else 885 WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req); 886 887 /* 888 * Issue a dummy read to wait for the ACK register to 889 * be cleared to avoid a false ACK due to the new fast 890 * GRBM interface. 891 */ 892 if ((vmhub == AMDGPU_GFXHUB(0)) && 893 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2))) 894 RREG32_NO_KIQ(hub->vm_inv_eng0_req + 895 hub->eng_distance * eng); 896 897 for (j = 0; j < adev->usec_timeout; j++) { 898 if (vmhub >= AMDGPU_MMHUB0(0)) 899 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_ack + hub->eng_distance * eng); 900 else 901 tmp = RREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_ack + hub->eng_distance * eng); 902 if (tmp & (1 << vmid)) 903 break; 904 udelay(1); 905 } 906 907 inv_req = inv_req2; 908 inv_req2 = 0; 909 } while (inv_req); 910 911 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 912 if (use_semaphore) { 913 /* 914 * add semaphore release after invalidation, 915 * write with 0 means semaphore release 916 */ 917 if (vmhub >= AMDGPU_MMHUB0(0)) 918 WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_sem + hub->eng_distance * eng, 0); 919 else 920 WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_sem + hub->eng_distance * eng, 0); 921 } 922 923 spin_unlock(&adev->gmc.invalidate_lock); 924 925 if (j < adev->usec_timeout) 926 return; 927 928 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 929 } 930 931 /** 932 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid 933 * 934 * @adev: amdgpu_device pointer 935 * @pasid: pasid to be flush 936 * @flush_type: the flush type 937 * @all_hub: flush all hubs 938 * 939 * Flush the TLB for the requested pasid. 940 */ 941 static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 942 uint16_t pasid, uint32_t flush_type, 943 bool all_hub, uint32_t inst) 944 { 945 int vmid, i; 946 signed long r; 947 uint32_t seq; 948 uint16_t queried_pasid; 949 bool ret; 950 u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT : adev->usec_timeout; 951 struct amdgpu_ring *ring = &adev->gfx.kiq[inst].ring; 952 struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst]; 953 954 if (amdgpu_in_reset(adev)) 955 return -EIO; 956 957 if (ring->sched.ready && down_read_trylock(&adev->reset_domain->sem)) { 958 /* Vega20+XGMI caches PTEs in TC and TLB. Add a 959 * heavy-weight TLB flush (type 2), which flushes 960 * both. Due to a race condition with concurrent 961 * memory accesses using the same TLB cache line, we 962 * still need a second TLB flush after this. 963 */ 964 bool vega20_xgmi_wa = (adev->gmc.xgmi.num_physical_nodes && 965 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0)); 966 /* 2 dwords flush + 8 dwords fence */ 967 unsigned int ndw = kiq->pmf->invalidate_tlbs_size + 8; 968 969 if (vega20_xgmi_wa) 970 ndw += kiq->pmf->invalidate_tlbs_size; 971 972 spin_lock(&adev->gfx.kiq[inst].ring_lock); 973 /* 2 dwords flush + 8 dwords fence */ 974 amdgpu_ring_alloc(ring, ndw); 975 if (vega20_xgmi_wa) 976 kiq->pmf->kiq_invalidate_tlbs(ring, 977 pasid, 2, all_hub); 978 kiq->pmf->kiq_invalidate_tlbs(ring, 979 pasid, flush_type, all_hub); 980 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 981 if (r) { 982 amdgpu_ring_undo(ring); 983 spin_unlock(&adev->gfx.kiq[inst].ring_lock); 984 up_read(&adev->reset_domain->sem); 985 return -ETIME; 986 } 987 988 amdgpu_ring_commit(ring); 989 spin_unlock(&adev->gfx.kiq[inst].ring_lock); 990 r = amdgpu_fence_wait_polling(ring, seq, usec_timeout); 991 if (r < 1) { 992 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r); 993 up_read(&adev->reset_domain->sem); 994 return -ETIME; 995 } 996 up_read(&adev->reset_domain->sem); 997 return 0; 998 } 999 1000 for (vmid = 1; vmid < 16; vmid++) { 1001 1002 ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 1003 &queried_pasid); 1004 if (ret && queried_pasid == pasid) { 1005 if (all_hub) { 1006 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) 1007 gmc_v9_0_flush_gpu_tlb(adev, vmid, 1008 i, flush_type); 1009 } else { 1010 gmc_v9_0_flush_gpu_tlb(adev, vmid, 1011 AMDGPU_GFXHUB(0), flush_type); 1012 } 1013 break; 1014 } 1015 } 1016 1017 return 0; 1018 1019 } 1020 1021 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 1022 unsigned vmid, uint64_t pd_addr) 1023 { 1024 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 1025 struct amdgpu_device *adev = ring->adev; 1026 struct amdgpu_vmhub *hub = &adev->vmhub[ring->vm_hub]; 1027 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); 1028 unsigned eng = ring->vm_inv_eng; 1029 1030 /* 1031 * It may lose gpuvm invalidate acknowldege state across power-gating 1032 * off cycle, add semaphore acquire before invalidation and semaphore 1033 * release after invalidation to avoid entering power gated state 1034 * to WA the Issue 1035 */ 1036 1037 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 1038 if (use_semaphore) 1039 /* a read return value of 1 means semaphore acuqire */ 1040 amdgpu_ring_emit_reg_wait(ring, 1041 hub->vm_inv_eng0_sem + 1042 hub->eng_distance * eng, 0x1, 0x1); 1043 1044 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 1045 (hub->ctx_addr_distance * vmid), 1046 lower_32_bits(pd_addr)); 1047 1048 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 1049 (hub->ctx_addr_distance * vmid), 1050 upper_32_bits(pd_addr)); 1051 1052 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 1053 hub->eng_distance * eng, 1054 hub->vm_inv_eng0_ack + 1055 hub->eng_distance * eng, 1056 req, 1 << vmid); 1057 1058 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 1059 if (use_semaphore) 1060 /* 1061 * add semaphore release after invalidation, 1062 * write with 0 means semaphore release 1063 */ 1064 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 1065 hub->eng_distance * eng, 0); 1066 1067 return pd_addr; 1068 } 1069 1070 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 1071 unsigned pasid) 1072 { 1073 struct amdgpu_device *adev = ring->adev; 1074 uint32_t reg; 1075 1076 /* Do nothing because there's no lut register for mmhub1. */ 1077 if (ring->vm_hub == AMDGPU_MMHUB1(0)) 1078 return; 1079 1080 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 1081 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 1082 else 1083 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 1084 1085 amdgpu_ring_emit_wreg(ring, reg, pasid); 1086 } 1087 1088 /* 1089 * PTE format on VEGA 10: 1090 * 63:59 reserved 1091 * 58:57 mtype 1092 * 56 F 1093 * 55 L 1094 * 54 P 1095 * 53 SW 1096 * 52 T 1097 * 50:48 reserved 1098 * 47:12 4k physical page base address 1099 * 11:7 fragment 1100 * 6 write 1101 * 5 read 1102 * 4 exe 1103 * 3 Z 1104 * 2 snooped 1105 * 1 system 1106 * 0 valid 1107 * 1108 * PDE format on VEGA 10: 1109 * 63:59 block fragment size 1110 * 58:55 reserved 1111 * 54 P 1112 * 53:48 reserved 1113 * 47:6 physical base address of PD or PTE 1114 * 5:3 reserved 1115 * 2 C 1116 * 1 system 1117 * 0 valid 1118 */ 1119 1120 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 1121 1122 { 1123 switch (flags) { 1124 case AMDGPU_VM_MTYPE_DEFAULT: 1125 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1126 case AMDGPU_VM_MTYPE_NC: 1127 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1128 case AMDGPU_VM_MTYPE_WC: 1129 return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC); 1130 case AMDGPU_VM_MTYPE_RW: 1131 return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW); 1132 case AMDGPU_VM_MTYPE_CC: 1133 return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC); 1134 case AMDGPU_VM_MTYPE_UC: 1135 return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC); 1136 default: 1137 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1138 } 1139 } 1140 1141 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, 1142 uint64_t *addr, uint64_t *flags) 1143 { 1144 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 1145 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 1146 BUG_ON(*addr & 0xFFFF00000000003FULL); 1147 1148 if (!adev->gmc.translate_further) 1149 return; 1150 1151 if (level == AMDGPU_VM_PDB1) { 1152 /* Set the block fragment size */ 1153 if (!(*flags & AMDGPU_PDE_PTE)) 1154 *flags |= AMDGPU_PDE_BFS(0x9); 1155 1156 } else if (level == AMDGPU_VM_PDB0) { 1157 if (*flags & AMDGPU_PDE_PTE) { 1158 *flags &= ~AMDGPU_PDE_PTE; 1159 if (!(*flags & AMDGPU_PTE_VALID)) 1160 *addr |= 1 << PAGE_SHIFT; 1161 } else { 1162 *flags |= AMDGPU_PTE_TF; 1163 } 1164 } 1165 } 1166 1167 static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev, 1168 struct amdgpu_bo *bo, 1169 struct amdgpu_bo_va_mapping *mapping, 1170 uint64_t *flags) 1171 { 1172 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev); 1173 bool is_vram = bo->tbo.resource->mem_type == TTM_PL_VRAM; 1174 bool coherent = bo->flags & AMDGPU_GEM_CREATE_COHERENT; 1175 bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED; 1176 unsigned int mtype; 1177 bool snoop = false; 1178 1179 switch (adev->ip_versions[GC_HWIP][0]) { 1180 case IP_VERSION(9, 4, 1): 1181 case IP_VERSION(9, 4, 2): 1182 if (is_vram) { 1183 if (bo_adev == adev) { 1184 if (uncached) 1185 mtype = MTYPE_UC; 1186 else if (coherent) 1187 mtype = MTYPE_CC; 1188 else 1189 mtype = MTYPE_RW; 1190 /* FIXME: is this still needed? Or does 1191 * amdgpu_ttm_tt_pde_flags already handle this? 1192 */ 1193 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) || 1194 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) && 1195 adev->gmc.xgmi.connected_to_cpu) 1196 snoop = true; 1197 } else { 1198 if (uncached || coherent) 1199 mtype = MTYPE_UC; 1200 else 1201 mtype = MTYPE_NC; 1202 if (mapping->bo_va->is_xgmi) 1203 snoop = true; 1204 } 1205 } else { 1206 if (uncached || coherent) 1207 mtype = MTYPE_UC; 1208 else 1209 mtype = MTYPE_NC; 1210 /* FIXME: is this still needed? Or does 1211 * amdgpu_ttm_tt_pde_flags already handle this? 1212 */ 1213 snoop = true; 1214 } 1215 break; 1216 case IP_VERSION(9, 4, 3): 1217 /* FIXME: Needs more work for handling multiple memory 1218 * partitions (> NPS1 mode) e.g. NPS4 for both APU and dGPU 1219 * modes. 1220 */ 1221 snoop = true; 1222 if (uncached) { 1223 mtype = MTYPE_UC; 1224 } else if (adev->gmc.is_app_apu) { 1225 /* FIXME: APU in native mode, NPS1 single socket only 1226 * 1227 * For suporting NUMA partitioned APU e.g. in NPS4 mode, 1228 * this need to look at the NUMA node on which the 1229 * system memory allocation was done. 1230 * 1231 * Memory access by a different partition within same 1232 * socket should be treated as remote access so MTYPE_RW 1233 * cannot be used always. 1234 */ 1235 mtype = MTYPE_RW; 1236 } else if (adev->flags & AMD_IS_APU) { 1237 /* APU on carve out mode */ 1238 mtype = MTYPE_RW; 1239 } else { 1240 /* dGPU */ 1241 if (is_vram && bo_adev == adev) 1242 mtype = MTYPE_RW; 1243 else if (is_vram) 1244 mtype = MTYPE_NC; 1245 else 1246 mtype = MTYPE_UC; 1247 } 1248 1249 break; 1250 default: 1251 if (uncached || coherent) 1252 mtype = MTYPE_UC; 1253 else 1254 mtype = MTYPE_NC; 1255 1256 /* FIXME: is this still needed? Or does 1257 * amdgpu_ttm_tt_pde_flags already handle this? 1258 */ 1259 if (!is_vram) 1260 snoop = true; 1261 } 1262 1263 if (mtype != MTYPE_NC) 1264 *flags = (*flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) | 1265 AMDGPU_PTE_MTYPE_VG10(mtype); 1266 *flags |= snoop ? AMDGPU_PTE_SNOOPED : 0; 1267 } 1268 1269 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev, 1270 struct amdgpu_bo_va_mapping *mapping, 1271 uint64_t *flags) 1272 { 1273 struct amdgpu_bo *bo = mapping->bo_va->base.bo; 1274 1275 *flags &= ~AMDGPU_PTE_EXECUTABLE; 1276 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 1277 1278 *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 1279 *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK; 1280 1281 if (mapping->flags & AMDGPU_PTE_PRT) { 1282 *flags |= AMDGPU_PTE_PRT; 1283 *flags &= ~AMDGPU_PTE_VALID; 1284 } 1285 1286 if (bo && bo->tbo.resource) 1287 gmc_v9_0_get_coherence_flags(adev, mapping->bo_va->base.bo, 1288 mapping, flags); 1289 } 1290 1291 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 1292 { 1293 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 1294 unsigned size; 1295 1296 /* TODO move to DC so GMC doesn't need to hard-code DCN registers */ 1297 1298 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1299 size = AMDGPU_VBIOS_VGA_ALLOCATION; 1300 } else { 1301 u32 viewport; 1302 1303 switch (adev->ip_versions[DCE_HWIP][0]) { 1304 case IP_VERSION(1, 0, 0): 1305 case IP_VERSION(1, 0, 1): 1306 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 1307 size = (REG_GET_FIELD(viewport, 1308 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1309 REG_GET_FIELD(viewport, 1310 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1311 4); 1312 break; 1313 case IP_VERSION(2, 1, 0): 1314 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2); 1315 size = (REG_GET_FIELD(viewport, 1316 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1317 REG_GET_FIELD(viewport, 1318 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1319 4); 1320 break; 1321 default: 1322 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); 1323 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1324 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1325 4); 1326 break; 1327 } 1328 } 1329 1330 return size; 1331 } 1332 1333 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { 1334 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, 1335 .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid, 1336 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, 1337 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, 1338 .map_mtype = gmc_v9_0_map_mtype, 1339 .get_vm_pde = gmc_v9_0_get_vm_pde, 1340 .get_vm_pte = gmc_v9_0_get_vm_pte, 1341 .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size, 1342 }; 1343 1344 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) 1345 { 1346 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; 1347 } 1348 1349 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) 1350 { 1351 switch (adev->ip_versions[UMC_HWIP][0]) { 1352 case IP_VERSION(6, 0, 0): 1353 adev->umc.funcs = &umc_v6_0_funcs; 1354 break; 1355 case IP_VERSION(6, 1, 1): 1356 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1357 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1358 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1359 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20; 1360 adev->umc.retire_unit = 1; 1361 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1362 adev->umc.ras = &umc_v6_1_ras; 1363 break; 1364 case IP_VERSION(6, 1, 2): 1365 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1366 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1367 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1368 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT; 1369 adev->umc.retire_unit = 1; 1370 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1371 adev->umc.ras = &umc_v6_1_ras; 1372 break; 1373 case IP_VERSION(6, 7, 0): 1374 adev->umc.max_ras_err_cnt_per_query = 1375 UMC_V6_7_TOTAL_CHANNEL_NUM * UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL; 1376 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM; 1377 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM; 1378 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET; 1379 adev->umc.retire_unit = (UMC_V6_7_NA_MAP_PA_NUM * 2); 1380 if (!adev->gmc.xgmi.connected_to_cpu) 1381 adev->umc.ras = &umc_v6_7_ras; 1382 if (1 & adev->smuio.funcs->get_die_id(adev)) 1383 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0]; 1384 else 1385 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0]; 1386 break; 1387 default: 1388 break; 1389 } 1390 } 1391 1392 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) 1393 { 1394 switch (adev->ip_versions[MMHUB_HWIP][0]) { 1395 case IP_VERSION(9, 4, 1): 1396 adev->mmhub.funcs = &mmhub_v9_4_funcs; 1397 break; 1398 case IP_VERSION(9, 4, 2): 1399 adev->mmhub.funcs = &mmhub_v1_7_funcs; 1400 break; 1401 case IP_VERSION(1, 8, 0): 1402 adev->mmhub.funcs = &mmhub_v1_8_funcs; 1403 break; 1404 default: 1405 adev->mmhub.funcs = &mmhub_v1_0_funcs; 1406 break; 1407 } 1408 } 1409 1410 static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev) 1411 { 1412 switch (adev->ip_versions[MMHUB_HWIP][0]) { 1413 case IP_VERSION(9, 4, 0): 1414 adev->mmhub.ras = &mmhub_v1_0_ras; 1415 break; 1416 case IP_VERSION(9, 4, 1): 1417 adev->mmhub.ras = &mmhub_v9_4_ras; 1418 break; 1419 case IP_VERSION(9, 4, 2): 1420 adev->mmhub.ras = &mmhub_v1_7_ras; 1421 break; 1422 default: 1423 /* mmhub ras is not available */ 1424 break; 1425 } 1426 } 1427 1428 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev) 1429 { 1430 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) 1431 adev->gfxhub.funcs = &gfxhub_v1_2_funcs; 1432 else 1433 adev->gfxhub.funcs = &gfxhub_v1_0_funcs; 1434 } 1435 1436 static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev) 1437 { 1438 adev->hdp.ras = &hdp_v4_0_ras; 1439 } 1440 1441 static void gmc_v9_0_set_mca_ras_funcs(struct amdgpu_device *adev) 1442 { 1443 struct amdgpu_mca *mca = &adev->mca; 1444 1445 /* is UMC the right IP to check for MCA? Maybe DF? */ 1446 switch (adev->ip_versions[UMC_HWIP][0]) { 1447 case IP_VERSION(6, 7, 0): 1448 if (!adev->gmc.xgmi.connected_to_cpu) { 1449 mca->mp0.ras = &mca_v3_0_mp0_ras; 1450 mca->mp1.ras = &mca_v3_0_mp1_ras; 1451 mca->mpio.ras = &mca_v3_0_mpio_ras; 1452 } 1453 break; 1454 default: 1455 break; 1456 } 1457 } 1458 1459 static void gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device *adev) 1460 { 1461 if (!adev->gmc.xgmi.connected_to_cpu) 1462 adev->gmc.xgmi.ras = &xgmi_ras; 1463 } 1464 1465 static int gmc_v9_0_early_init(void *handle) 1466 { 1467 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1468 1469 /* 1470 * 9.4.0, 9.4.1 and 9.4.3 don't have XGMI defined 1471 * in their IP discovery tables 1472 */ 1473 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0) || 1474 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) || 1475 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) 1476 adev->gmc.xgmi.supported = true; 1477 1478 if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(6, 1, 0)) { 1479 adev->gmc.xgmi.supported = true; 1480 adev->gmc.xgmi.connected_to_cpu = 1481 adev->smuio.funcs->is_host_gpu_xgmi_supported(adev); 1482 } 1483 1484 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) { 1485 enum amdgpu_pkg_type pkg_type = 1486 adev->smuio.funcs->get_pkg_type(adev); 1487 /* On GFXIP 9.4.3. APU, there is no physical VRAM domain present 1488 * and the APU, can be in used two possible modes: 1489 * - carveout mode 1490 * - native APU mode 1491 * "is_app_apu" can be used to identify the APU in the native 1492 * mode. 1493 */ 1494 adev->gmc.is_app_apu = (pkg_type == AMDGPU_PKG_TYPE_APU && 1495 !pci_resource_len(adev->pdev, 0)); 1496 } 1497 1498 gmc_v9_0_set_gmc_funcs(adev); 1499 gmc_v9_0_set_irq_funcs(adev); 1500 gmc_v9_0_set_umc_funcs(adev); 1501 gmc_v9_0_set_mmhub_funcs(adev); 1502 gmc_v9_0_set_mmhub_ras_funcs(adev); 1503 gmc_v9_0_set_gfxhub_funcs(adev); 1504 gmc_v9_0_set_hdp_ras_funcs(adev); 1505 gmc_v9_0_set_mca_ras_funcs(adev); 1506 gmc_v9_0_set_xgmi_ras_funcs(adev); 1507 1508 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1509 adev->gmc.shared_aperture_end = 1510 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1511 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 1512 adev->gmc.private_aperture_end = 1513 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1514 1515 return 0; 1516 } 1517 1518 static int gmc_v9_0_late_init(void *handle) 1519 { 1520 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1521 int r; 1522 1523 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 1524 if (r) 1525 return r; 1526 1527 /* 1528 * Workaround performance drop issue with VBIOS enables partial 1529 * writes, while disables HBM ECC for vega10. 1530 */ 1531 if (!amdgpu_sriov_vf(adev) && 1532 (adev->ip_versions[UMC_HWIP][0] == IP_VERSION(6, 0, 0))) { 1533 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) { 1534 if (adev->df.funcs && 1535 adev->df.funcs->enable_ecc_force_par_wr_rmw) 1536 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false); 1537 } 1538 } 1539 1540 if (!amdgpu_persistent_edc_harvesting_supported(adev)) { 1541 if (adev->mmhub.ras && adev->mmhub.ras->ras_block.hw_ops && 1542 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count) 1543 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(adev); 1544 1545 if (adev->hdp.ras && adev->hdp.ras->ras_block.hw_ops && 1546 adev->hdp.ras->ras_block.hw_ops->reset_ras_error_count) 1547 adev->hdp.ras->ras_block.hw_ops->reset_ras_error_count(adev); 1548 } 1549 1550 r = amdgpu_gmc_ras_late_init(adev); 1551 if (r) 1552 return r; 1553 1554 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1555 } 1556 1557 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 1558 struct amdgpu_gmc *mc) 1559 { 1560 u64 base = adev->mmhub.funcs->get_fb_location(adev); 1561 1562 /* add the xgmi offset of the physical node */ 1563 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1564 if (adev->gmc.xgmi.connected_to_cpu) { 1565 amdgpu_gmc_sysvm_location(adev, mc); 1566 } else { 1567 amdgpu_gmc_vram_location(adev, mc, base); 1568 amdgpu_gmc_gart_location(adev, mc); 1569 amdgpu_gmc_agp_location(adev, mc); 1570 } 1571 /* base offset of vram pages */ 1572 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 1573 1574 /* XXX: add the xgmi offset of the physical node? */ 1575 adev->vm_manager.vram_base_offset += 1576 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1577 } 1578 1579 /** 1580 * gmc_v9_0_mc_init - initialize the memory controller driver params 1581 * 1582 * @adev: amdgpu_device pointer 1583 * 1584 * Look up the amount of vram, vram width, and decide how to place 1585 * vram and gart within the GPU's physical address space. 1586 * Returns 0 for success. 1587 */ 1588 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 1589 { 1590 int r; 1591 1592 /* size in MB on si */ 1593 adev->gmc.mc_vram_size = 1594 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 1595 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 1596 1597 if (!(adev->flags & AMD_IS_APU) && 1598 !adev->gmc.xgmi.connected_to_cpu) { 1599 r = amdgpu_device_resize_fb_bar(adev); 1600 if (r) 1601 return r; 1602 } 1603 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 1604 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 1605 1606 #ifdef CONFIG_X86_64 1607 /* 1608 * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi 1609 * interface can use VRAM through here as it appears system reserved 1610 * memory in host address space. 1611 * 1612 * For APUs, VRAM is just the stolen system memory and can be accessed 1613 * directly. 1614 * 1615 * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR. 1616 */ 1617 1618 /* check whether both host-gpu and gpu-gpu xgmi links exist */ 1619 if (((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) || 1620 (adev->gmc.xgmi.supported && 1621 adev->gmc.xgmi.connected_to_cpu)) { 1622 adev->gmc.aper_base = 1623 adev->gfxhub.funcs->get_mc_fb_offset(adev) + 1624 adev->gmc.xgmi.physical_node_id * 1625 adev->gmc.xgmi.node_segment_size; 1626 adev->gmc.aper_size = adev->gmc.real_vram_size; 1627 } 1628 1629 #endif 1630 adev->gmc.visible_vram_size = adev->gmc.aper_size; 1631 1632 /* set the gart size */ 1633 if (amdgpu_gart_size == -1) { 1634 switch (adev->ip_versions[GC_HWIP][0]) { 1635 case IP_VERSION(9, 0, 1): /* all engines support GPUVM */ 1636 case IP_VERSION(9, 2, 1): /* all engines support GPUVM */ 1637 case IP_VERSION(9, 4, 0): 1638 case IP_VERSION(9, 4, 1): 1639 case IP_VERSION(9, 4, 2): 1640 case IP_VERSION(9, 4, 3): 1641 default: 1642 adev->gmc.gart_size = 512ULL << 20; 1643 break; 1644 case IP_VERSION(9, 1, 0): /* DCE SG support */ 1645 case IP_VERSION(9, 2, 2): /* DCE SG support */ 1646 case IP_VERSION(9, 3, 0): 1647 adev->gmc.gart_size = 1024ULL << 20; 1648 break; 1649 } 1650 } else { 1651 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 1652 } 1653 1654 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; 1655 1656 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); 1657 1658 return 0; 1659 } 1660 1661 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 1662 { 1663 int r; 1664 1665 if (adev->gart.bo) { 1666 WARN(1, "VEGA10 PCIE GART already initialized\n"); 1667 return 0; 1668 } 1669 1670 if (adev->gmc.xgmi.connected_to_cpu) { 1671 adev->gmc.vmid0_page_table_depth = 1; 1672 adev->gmc.vmid0_page_table_block_size = 12; 1673 } else { 1674 adev->gmc.vmid0_page_table_depth = 0; 1675 adev->gmc.vmid0_page_table_block_size = 0; 1676 } 1677 1678 /* Initialize common gart structure */ 1679 r = amdgpu_gart_init(adev); 1680 if (r) 1681 return r; 1682 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 1683 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) | 1684 AMDGPU_PTE_EXECUTABLE; 1685 1686 if (!adev->gmc.real_vram_size) { 1687 dev_info(adev->dev, "Put GART in system memory for APU\n"); 1688 r = amdgpu_gart_table_ram_alloc(adev); 1689 if (r) 1690 dev_err(adev->dev, "Failed to allocate GART in system memory\n"); 1691 } else { 1692 r = amdgpu_gart_table_vram_alloc(adev); 1693 if (r) 1694 return r; 1695 1696 if (adev->gmc.xgmi.connected_to_cpu) 1697 r = amdgpu_gmc_pdb0_alloc(adev); 1698 } 1699 1700 return r; 1701 } 1702 1703 /** 1704 * gmc_v9_0_save_registers - saves regs 1705 * 1706 * @adev: amdgpu_device pointer 1707 * 1708 * This saves potential register values that should be 1709 * restored upon resume 1710 */ 1711 static void gmc_v9_0_save_registers(struct amdgpu_device *adev) 1712 { 1713 if ((adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 0)) || 1714 (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 1))) 1715 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); 1716 } 1717 1718 static int gmc_v9_0_sw_init(void *handle) 1719 { 1720 int r, vram_width = 0, vram_type = 0, vram_vendor = 0, dma_addr_bits; 1721 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1722 unsigned long inst_mask = adev->aid_mask; 1723 1724 adev->gfxhub.funcs->init(adev); 1725 1726 adev->mmhub.funcs->init(adev); 1727 1728 spin_lock_init(&adev->gmc.invalidate_lock); 1729 1730 r = amdgpu_atomfirmware_get_vram_info(adev, 1731 &vram_width, &vram_type, &vram_vendor); 1732 if (amdgpu_sriov_vf(adev)) 1733 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, 1734 * and DF related registers is not readable, seems hardcord is the 1735 * only way to set the correct vram_width 1736 */ 1737 adev->gmc.vram_width = 2048; 1738 else if (amdgpu_emu_mode != 1) 1739 adev->gmc.vram_width = vram_width; 1740 1741 if (!adev->gmc.vram_width) { 1742 int chansize, numchan; 1743 1744 /* hbm memory channel size */ 1745 if (adev->flags & AMD_IS_APU) 1746 chansize = 64; 1747 else 1748 chansize = 128; 1749 if (adev->df.funcs && 1750 adev->df.funcs->get_hbm_channel_number) { 1751 numchan = adev->df.funcs->get_hbm_channel_number(adev); 1752 adev->gmc.vram_width = numchan * chansize; 1753 } 1754 } 1755 1756 adev->gmc.vram_type = vram_type; 1757 adev->gmc.vram_vendor = vram_vendor; 1758 switch (adev->ip_versions[GC_HWIP][0]) { 1759 case IP_VERSION(9, 1, 0): 1760 case IP_VERSION(9, 2, 2): 1761 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 1762 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 1763 1764 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 1765 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1766 } else { 1767 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 1768 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 1769 adev->gmc.translate_further = 1770 adev->vm_manager.num_level > 1; 1771 } 1772 break; 1773 case IP_VERSION(9, 0, 1): 1774 case IP_VERSION(9, 2, 1): 1775 case IP_VERSION(9, 4, 0): 1776 case IP_VERSION(9, 3, 0): 1777 case IP_VERSION(9, 4, 2): 1778 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 1779 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 1780 1781 /* 1782 * To fulfill 4-level page support, 1783 * vm size is 256TB (48bit), maximum size of Vega10, 1784 * block size 512 (9bit) 1785 */ 1786 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */ 1787 if (amdgpu_sriov_vf(adev)) 1788 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47); 1789 else 1790 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1791 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) 1792 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 1793 break; 1794 case IP_VERSION(9, 4, 1): 1795 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 1796 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 1797 set_bit(AMDGPU_MMHUB1(0), adev->vmhubs_mask); 1798 1799 /* Keep the vm size same with Vega20 */ 1800 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1801 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 1802 break; 1803 case IP_VERSION(9, 4, 3): 1804 bitmap_set(adev->vmhubs_mask, AMDGPU_GFXHUB(0), 1805 NUM_XCC(adev->gfx.xcc_mask)); 1806 1807 inst_mask <<= AMDGPU_MMHUB0(0); 1808 bitmap_or(adev->vmhubs_mask, adev->vmhubs_mask, &inst_mask, 32); 1809 1810 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1811 break; 1812 default: 1813 break; 1814 } 1815 1816 /* This interrupt is VMC page fault.*/ 1817 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, 1818 &adev->gmc.vm_fault); 1819 if (r) 1820 return r; 1821 1822 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)) { 1823 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT, 1824 &adev->gmc.vm_fault); 1825 if (r) 1826 return r; 1827 } 1828 1829 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, 1830 &adev->gmc.vm_fault); 1831 1832 if (r) 1833 return r; 1834 1835 if (!amdgpu_sriov_vf(adev) && 1836 !adev->gmc.xgmi.connected_to_cpu) { 1837 /* interrupt sent to DF. */ 1838 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 1839 &adev->gmc.ecc_irq); 1840 if (r) 1841 return r; 1842 } 1843 1844 /* Set the internal MC address mask 1845 * This is the max address of the GPU's 1846 * internal address space. 1847 */ 1848 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 1849 1850 dma_addr_bits = adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2) ? 48:44; 1851 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(dma_addr_bits)); 1852 if (r) { 1853 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 1854 return r; 1855 } 1856 adev->need_swiotlb = drm_need_swiotlb(dma_addr_bits); 1857 1858 r = gmc_v9_0_mc_init(adev); 1859 if (r) 1860 return r; 1861 1862 amdgpu_gmc_get_vbios_allocations(adev); 1863 1864 /* Memory manager */ 1865 r = amdgpu_bo_init(adev); 1866 if (r) 1867 return r; 1868 1869 r = gmc_v9_0_gart_init(adev); 1870 if (r) 1871 return r; 1872 1873 /* 1874 * number of VMs 1875 * VMID 0 is reserved for System 1876 * amdgpu graphics/compute will use VMIDs 1..n-1 1877 * amdkfd will use VMIDs n..15 1878 * 1879 * The first KFD VMID is 8 for GPUs with graphics, 3 for 1880 * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs 1881 * for video processing. 1882 */ 1883 adev->vm_manager.first_kfd_vmid = 1884 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) || 1885 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) || 1886 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) ? 3 : 8; 1887 1888 amdgpu_vm_manager_init(adev); 1889 1890 gmc_v9_0_save_registers(adev); 1891 1892 r = amdgpu_gmc_ras_sw_init(adev); 1893 if (r) 1894 return r; 1895 1896 return 0; 1897 } 1898 1899 static int gmc_v9_0_sw_fini(void *handle) 1900 { 1901 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1902 1903 amdgpu_gmc_ras_fini(adev); 1904 amdgpu_gem_force_release(adev); 1905 amdgpu_vm_manager_fini(adev); 1906 if (!adev->gmc.real_vram_size) { 1907 dev_info(adev->dev, "Put GART in system memory for APU free\n"); 1908 amdgpu_gart_table_ram_free(adev); 1909 } else { 1910 amdgpu_gart_table_vram_free(adev); 1911 } 1912 amdgpu_bo_free_kernel(&adev->gmc.pdb0_bo, NULL, &adev->gmc.ptr_pdb0); 1913 amdgpu_bo_fini(adev); 1914 1915 return 0; 1916 } 1917 1918 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 1919 { 1920 1921 switch (adev->ip_versions[MMHUB_HWIP][0]) { 1922 case IP_VERSION(9, 0, 0): 1923 if (amdgpu_sriov_vf(adev)) 1924 break; 1925 fallthrough; 1926 case IP_VERSION(9, 4, 0): 1927 soc15_program_register_sequence(adev, 1928 golden_settings_mmhub_1_0_0, 1929 ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 1930 soc15_program_register_sequence(adev, 1931 golden_settings_athub_1_0_0, 1932 ARRAY_SIZE(golden_settings_athub_1_0_0)); 1933 break; 1934 case IP_VERSION(9, 1, 0): 1935 case IP_VERSION(9, 2, 0): 1936 /* TODO for renoir */ 1937 soc15_program_register_sequence(adev, 1938 golden_settings_athub_1_0_0, 1939 ARRAY_SIZE(golden_settings_athub_1_0_0)); 1940 break; 1941 default: 1942 break; 1943 } 1944 } 1945 1946 /** 1947 * gmc_v9_0_restore_registers - restores regs 1948 * 1949 * @adev: amdgpu_device pointer 1950 * 1951 * This restores register values, saved at suspend. 1952 */ 1953 void gmc_v9_0_restore_registers(struct amdgpu_device *adev) 1954 { 1955 if ((adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 0)) || 1956 (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 1))) { 1957 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register); 1958 WARN_ON(adev->gmc.sdpif_register != 1959 RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0)); 1960 } 1961 } 1962 1963 /** 1964 * gmc_v9_0_gart_enable - gart enable 1965 * 1966 * @adev: amdgpu_device pointer 1967 */ 1968 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 1969 { 1970 int r; 1971 1972 if (adev->gmc.xgmi.connected_to_cpu) 1973 amdgpu_gmc_init_pdb0(adev); 1974 1975 if (adev->gart.bo == NULL) { 1976 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 1977 return -EINVAL; 1978 } 1979 1980 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 1981 1982 if (!adev->in_s0ix) { 1983 r = adev->gfxhub.funcs->gart_enable(adev); 1984 if (r) 1985 return r; 1986 } 1987 1988 r = adev->mmhub.funcs->gart_enable(adev); 1989 if (r) 1990 return r; 1991 1992 DRM_INFO("PCIE GART of %uM enabled.\n", 1993 (unsigned)(adev->gmc.gart_size >> 20)); 1994 if (adev->gmc.pdb0_bo) 1995 DRM_INFO("PDB0 located at 0x%016llX\n", 1996 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo)); 1997 DRM_INFO("PTB located at 0x%016llX\n", 1998 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 1999 2000 return 0; 2001 } 2002 2003 static int gmc_v9_0_hw_init(void *handle) 2004 { 2005 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2006 bool value; 2007 int i, r; 2008 2009 /* The sequence of these two function calls matters.*/ 2010 gmc_v9_0_init_golden_registers(adev); 2011 2012 if (adev->mode_info.num_crtc) { 2013 /* Lockout access through VGA aperture*/ 2014 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 2015 /* disable VGA render */ 2016 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 2017 } 2018 2019 if (adev->mmhub.funcs->update_power_gating) 2020 adev->mmhub.funcs->update_power_gating(adev, true); 2021 2022 adev->hdp.funcs->init_registers(adev); 2023 2024 /* After HDP is initialized, flush HDP.*/ 2025 adev->hdp.funcs->flush_hdp(adev, NULL); 2026 2027 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 2028 value = false; 2029 else 2030 value = true; 2031 2032 if (!amdgpu_sriov_vf(adev)) { 2033 if (!adev->in_s0ix) 2034 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 2035 adev->mmhub.funcs->set_fault_enable_default(adev, value); 2036 } 2037 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 2038 if (adev->in_s0ix && (i == AMDGPU_GFXHUB(0))) 2039 continue; 2040 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0); 2041 } 2042 2043 if (adev->umc.funcs && adev->umc.funcs->init_registers) 2044 adev->umc.funcs->init_registers(adev); 2045 2046 r = gmc_v9_0_gart_enable(adev); 2047 if (r) 2048 return r; 2049 2050 if (amdgpu_emu_mode == 1) 2051 return amdgpu_gmc_vram_checking(adev); 2052 else 2053 return r; 2054 } 2055 2056 /** 2057 * gmc_v9_0_gart_disable - gart disable 2058 * 2059 * @adev: amdgpu_device pointer 2060 * 2061 * This disables all VM page table. 2062 */ 2063 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 2064 { 2065 if (!adev->in_s0ix) 2066 adev->gfxhub.funcs->gart_disable(adev); 2067 adev->mmhub.funcs->gart_disable(adev); 2068 } 2069 2070 static int gmc_v9_0_hw_fini(void *handle) 2071 { 2072 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2073 2074 gmc_v9_0_gart_disable(adev); 2075 2076 if (amdgpu_sriov_vf(adev)) { 2077 /* full access mode, so don't touch any GMC register */ 2078 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 2079 return 0; 2080 } 2081 2082 /* 2083 * Pair the operations did in gmc_v9_0_hw_init and thus maintain 2084 * a correct cached state for GMC. Otherwise, the "gate" again 2085 * operation on S3 resuming will fail due to wrong cached state. 2086 */ 2087 if (adev->mmhub.funcs->update_power_gating) 2088 adev->mmhub.funcs->update_power_gating(adev, false); 2089 2090 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 2091 2092 return 0; 2093 } 2094 2095 static int gmc_v9_0_suspend(void *handle) 2096 { 2097 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2098 2099 return gmc_v9_0_hw_fini(adev); 2100 } 2101 2102 static int gmc_v9_0_resume(void *handle) 2103 { 2104 int r; 2105 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2106 2107 r = gmc_v9_0_hw_init(adev); 2108 if (r) 2109 return r; 2110 2111 amdgpu_vmid_reset_all(adev); 2112 2113 return 0; 2114 } 2115 2116 static bool gmc_v9_0_is_idle(void *handle) 2117 { 2118 /* MC is always ready in GMC v9.*/ 2119 return true; 2120 } 2121 2122 static int gmc_v9_0_wait_for_idle(void *handle) 2123 { 2124 /* There is no need to wait for MC idle in GMC v9.*/ 2125 return 0; 2126 } 2127 2128 static int gmc_v9_0_soft_reset(void *handle) 2129 { 2130 /* XXX for emulation.*/ 2131 return 0; 2132 } 2133 2134 static int gmc_v9_0_set_clockgating_state(void *handle, 2135 enum amd_clockgating_state state) 2136 { 2137 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2138 2139 adev->mmhub.funcs->set_clockgating(adev, state); 2140 2141 athub_v1_0_set_clockgating(adev, state); 2142 2143 return 0; 2144 } 2145 2146 static void gmc_v9_0_get_clockgating_state(void *handle, u64 *flags) 2147 { 2148 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2149 2150 adev->mmhub.funcs->get_clockgating(adev, flags); 2151 2152 athub_v1_0_get_clockgating(adev, flags); 2153 } 2154 2155 static int gmc_v9_0_set_powergating_state(void *handle, 2156 enum amd_powergating_state state) 2157 { 2158 return 0; 2159 } 2160 2161 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 2162 .name = "gmc_v9_0", 2163 .early_init = gmc_v9_0_early_init, 2164 .late_init = gmc_v9_0_late_init, 2165 .sw_init = gmc_v9_0_sw_init, 2166 .sw_fini = gmc_v9_0_sw_fini, 2167 .hw_init = gmc_v9_0_hw_init, 2168 .hw_fini = gmc_v9_0_hw_fini, 2169 .suspend = gmc_v9_0_suspend, 2170 .resume = gmc_v9_0_resume, 2171 .is_idle = gmc_v9_0_is_idle, 2172 .wait_for_idle = gmc_v9_0_wait_for_idle, 2173 .soft_reset = gmc_v9_0_soft_reset, 2174 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 2175 .set_powergating_state = gmc_v9_0_set_powergating_state, 2176 .get_clockgating_state = gmc_v9_0_get_clockgating_state, 2177 }; 2178 2179 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = 2180 { 2181 .type = AMD_IP_BLOCK_TYPE_GMC, 2182 .major = 9, 2183 .minor = 0, 2184 .rev = 0, 2185 .funcs = &gmc_v9_0_ip_funcs, 2186 }; 2187