1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/pci.h> 26 27 #include <drm/drm_cache.h> 28 29 #include "amdgpu.h" 30 #include "gmc_v9_0.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_gem.h" 33 34 #include "gc/gc_9_0_sh_mask.h" 35 #include "dce/dce_12_0_offset.h" 36 #include "dce/dce_12_0_sh_mask.h" 37 #include "vega10_enum.h" 38 #include "mmhub/mmhub_1_0_offset.h" 39 #include "athub/athub_1_0_sh_mask.h" 40 #include "athub/athub_1_0_offset.h" 41 #include "oss/osssys_4_0_offset.h" 42 43 #include "soc15.h" 44 #include "soc15d.h" 45 #include "soc15_common.h" 46 #include "umc/umc_6_0_sh_mask.h" 47 48 #include "gfxhub_v1_0.h" 49 #include "mmhub_v1_0.h" 50 #include "athub_v1_0.h" 51 #include "gfxhub_v1_1.h" 52 #include "mmhub_v9_4.h" 53 #include "mmhub_v1_7.h" 54 #include "umc_v6_1.h" 55 #include "umc_v6_0.h" 56 #include "umc_v6_7.h" 57 #include "hdp_v4_0.h" 58 #include "mca_v3_0.h" 59 60 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 61 62 #include "amdgpu_ras.h" 63 #include "amdgpu_xgmi.h" 64 65 /* add these here since we already include dce12 headers and these are for DCN */ 66 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 67 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 68 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 69 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 70 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL 71 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L 72 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d 73 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2 74 75 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2 0x05ea 76 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX 2 77 78 79 static const char *gfxhub_client_ids[] = { 80 "CB", 81 "DB", 82 "IA", 83 "WD", 84 "CPF", 85 "CPC", 86 "CPG", 87 "RLC", 88 "TCP", 89 "SQC (inst)", 90 "SQC (data)", 91 "SQG", 92 "PA", 93 }; 94 95 static const char *mmhub_client_ids_raven[][2] = { 96 [0][0] = "MP1", 97 [1][0] = "MP0", 98 [2][0] = "VCN", 99 [3][0] = "VCNU", 100 [4][0] = "HDP", 101 [5][0] = "DCE", 102 [13][0] = "UTCL2", 103 [19][0] = "TLS", 104 [26][0] = "OSS", 105 [27][0] = "SDMA0", 106 [0][1] = "MP1", 107 [1][1] = "MP0", 108 [2][1] = "VCN", 109 [3][1] = "VCNU", 110 [4][1] = "HDP", 111 [5][1] = "XDP", 112 [6][1] = "DBGU0", 113 [7][1] = "DCE", 114 [8][1] = "DCEDWB0", 115 [9][1] = "DCEDWB1", 116 [26][1] = "OSS", 117 [27][1] = "SDMA0", 118 }; 119 120 static const char *mmhub_client_ids_renoir[][2] = { 121 [0][0] = "MP1", 122 [1][0] = "MP0", 123 [2][0] = "HDP", 124 [4][0] = "DCEDMC", 125 [5][0] = "DCEVGA", 126 [13][0] = "UTCL2", 127 [19][0] = "TLS", 128 [26][0] = "OSS", 129 [27][0] = "SDMA0", 130 [28][0] = "VCN", 131 [29][0] = "VCNU", 132 [30][0] = "JPEG", 133 [0][1] = "MP1", 134 [1][1] = "MP0", 135 [2][1] = "HDP", 136 [3][1] = "XDP", 137 [6][1] = "DBGU0", 138 [7][1] = "DCEDMC", 139 [8][1] = "DCEVGA", 140 [9][1] = "DCEDWB", 141 [26][1] = "OSS", 142 [27][1] = "SDMA0", 143 [28][1] = "VCN", 144 [29][1] = "VCNU", 145 [30][1] = "JPEG", 146 }; 147 148 static const char *mmhub_client_ids_vega10[][2] = { 149 [0][0] = "MP0", 150 [1][0] = "UVD", 151 [2][0] = "UVDU", 152 [3][0] = "HDP", 153 [13][0] = "UTCL2", 154 [14][0] = "OSS", 155 [15][0] = "SDMA1", 156 [32+0][0] = "VCE0", 157 [32+1][0] = "VCE0U", 158 [32+2][0] = "XDMA", 159 [32+3][0] = "DCE", 160 [32+4][0] = "MP1", 161 [32+14][0] = "SDMA0", 162 [0][1] = "MP0", 163 [1][1] = "UVD", 164 [2][1] = "UVDU", 165 [3][1] = "DBGU0", 166 [4][1] = "HDP", 167 [5][1] = "XDP", 168 [14][1] = "OSS", 169 [15][1] = "SDMA0", 170 [32+0][1] = "VCE0", 171 [32+1][1] = "VCE0U", 172 [32+2][1] = "XDMA", 173 [32+3][1] = "DCE", 174 [32+4][1] = "DCEDWB", 175 [32+5][1] = "MP1", 176 [32+6][1] = "DBGU1", 177 [32+14][1] = "SDMA1", 178 }; 179 180 static const char *mmhub_client_ids_vega12[][2] = { 181 [0][0] = "MP0", 182 [1][0] = "VCE0", 183 [2][0] = "VCE0U", 184 [3][0] = "HDP", 185 [13][0] = "UTCL2", 186 [14][0] = "OSS", 187 [15][0] = "SDMA1", 188 [32+0][0] = "DCE", 189 [32+1][0] = "XDMA", 190 [32+2][0] = "UVD", 191 [32+3][0] = "UVDU", 192 [32+4][0] = "MP1", 193 [32+15][0] = "SDMA0", 194 [0][1] = "MP0", 195 [1][1] = "VCE0", 196 [2][1] = "VCE0U", 197 [3][1] = "DBGU0", 198 [4][1] = "HDP", 199 [5][1] = "XDP", 200 [14][1] = "OSS", 201 [15][1] = "SDMA0", 202 [32+0][1] = "DCE", 203 [32+1][1] = "DCEDWB", 204 [32+2][1] = "XDMA", 205 [32+3][1] = "UVD", 206 [32+4][1] = "UVDU", 207 [32+5][1] = "MP1", 208 [32+6][1] = "DBGU1", 209 [32+15][1] = "SDMA1", 210 }; 211 212 static const char *mmhub_client_ids_vega20[][2] = { 213 [0][0] = "XDMA", 214 [1][0] = "DCE", 215 [2][0] = "VCE0", 216 [3][0] = "VCE0U", 217 [4][0] = "UVD", 218 [5][0] = "UVD1U", 219 [13][0] = "OSS", 220 [14][0] = "HDP", 221 [15][0] = "SDMA0", 222 [32+0][0] = "UVD", 223 [32+1][0] = "UVDU", 224 [32+2][0] = "MP1", 225 [32+3][0] = "MP0", 226 [32+12][0] = "UTCL2", 227 [32+14][0] = "SDMA1", 228 [0][1] = "XDMA", 229 [1][1] = "DCE", 230 [2][1] = "DCEDWB", 231 [3][1] = "VCE0", 232 [4][1] = "VCE0U", 233 [5][1] = "UVD1", 234 [6][1] = "UVD1U", 235 [7][1] = "DBGU0", 236 [8][1] = "XDP", 237 [13][1] = "OSS", 238 [14][1] = "HDP", 239 [15][1] = "SDMA0", 240 [32+0][1] = "UVD", 241 [32+1][1] = "UVDU", 242 [32+2][1] = "DBGU1", 243 [32+3][1] = "MP1", 244 [32+4][1] = "MP0", 245 [32+14][1] = "SDMA1", 246 }; 247 248 static const char *mmhub_client_ids_arcturus[][2] = { 249 [0][0] = "DBGU1", 250 [1][0] = "XDP", 251 [2][0] = "MP1", 252 [14][0] = "HDP", 253 [171][0] = "JPEG", 254 [172][0] = "VCN", 255 [173][0] = "VCNU", 256 [203][0] = "JPEG1", 257 [204][0] = "VCN1", 258 [205][0] = "VCN1U", 259 [256][0] = "SDMA0", 260 [257][0] = "SDMA1", 261 [258][0] = "SDMA2", 262 [259][0] = "SDMA3", 263 [260][0] = "SDMA4", 264 [261][0] = "SDMA5", 265 [262][0] = "SDMA6", 266 [263][0] = "SDMA7", 267 [384][0] = "OSS", 268 [0][1] = "DBGU1", 269 [1][1] = "XDP", 270 [2][1] = "MP1", 271 [14][1] = "HDP", 272 [171][1] = "JPEG", 273 [172][1] = "VCN", 274 [173][1] = "VCNU", 275 [203][1] = "JPEG1", 276 [204][1] = "VCN1", 277 [205][1] = "VCN1U", 278 [256][1] = "SDMA0", 279 [257][1] = "SDMA1", 280 [258][1] = "SDMA2", 281 [259][1] = "SDMA3", 282 [260][1] = "SDMA4", 283 [261][1] = "SDMA5", 284 [262][1] = "SDMA6", 285 [263][1] = "SDMA7", 286 [384][1] = "OSS", 287 }; 288 289 static const char *mmhub_client_ids_aldebaran[][2] = { 290 [2][0] = "MP1", 291 [3][0] = "MP0", 292 [32+1][0] = "DBGU_IO0", 293 [32+2][0] = "DBGU_IO2", 294 [32+4][0] = "MPIO", 295 [96+11][0] = "JPEG0", 296 [96+12][0] = "VCN0", 297 [96+13][0] = "VCNU0", 298 [128+11][0] = "JPEG1", 299 [128+12][0] = "VCN1", 300 [128+13][0] = "VCNU1", 301 [160+1][0] = "XDP", 302 [160+14][0] = "HDP", 303 [256+0][0] = "SDMA0", 304 [256+1][0] = "SDMA1", 305 [256+2][0] = "SDMA2", 306 [256+3][0] = "SDMA3", 307 [256+4][0] = "SDMA4", 308 [384+0][0] = "OSS", 309 [2][1] = "MP1", 310 [3][1] = "MP0", 311 [32+1][1] = "DBGU_IO0", 312 [32+2][1] = "DBGU_IO2", 313 [32+4][1] = "MPIO", 314 [96+11][1] = "JPEG0", 315 [96+12][1] = "VCN0", 316 [96+13][1] = "VCNU0", 317 [128+11][1] = "JPEG1", 318 [128+12][1] = "VCN1", 319 [128+13][1] = "VCNU1", 320 [160+1][1] = "XDP", 321 [160+14][1] = "HDP", 322 [256+0][1] = "SDMA0", 323 [256+1][1] = "SDMA1", 324 [256+2][1] = "SDMA2", 325 [256+3][1] = "SDMA3", 326 [256+4][1] = "SDMA4", 327 [384+0][1] = "OSS", 328 }; 329 330 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = 331 { 332 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), 333 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) 334 }; 335 336 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = 337 { 338 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), 339 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) 340 }; 341 342 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { 343 (0x000143c0 + 0x00000000), 344 (0x000143c0 + 0x00000800), 345 (0x000143c0 + 0x00001000), 346 (0x000143c0 + 0x00001800), 347 (0x000543c0 + 0x00000000), 348 (0x000543c0 + 0x00000800), 349 (0x000543c0 + 0x00001000), 350 (0x000543c0 + 0x00001800), 351 (0x000943c0 + 0x00000000), 352 (0x000943c0 + 0x00000800), 353 (0x000943c0 + 0x00001000), 354 (0x000943c0 + 0x00001800), 355 (0x000d43c0 + 0x00000000), 356 (0x000d43c0 + 0x00000800), 357 (0x000d43c0 + 0x00001000), 358 (0x000d43c0 + 0x00001800), 359 (0x001143c0 + 0x00000000), 360 (0x001143c0 + 0x00000800), 361 (0x001143c0 + 0x00001000), 362 (0x001143c0 + 0x00001800), 363 (0x001543c0 + 0x00000000), 364 (0x001543c0 + 0x00000800), 365 (0x001543c0 + 0x00001000), 366 (0x001543c0 + 0x00001800), 367 (0x001943c0 + 0x00000000), 368 (0x001943c0 + 0x00000800), 369 (0x001943c0 + 0x00001000), 370 (0x001943c0 + 0x00001800), 371 (0x001d43c0 + 0x00000000), 372 (0x001d43c0 + 0x00000800), 373 (0x001d43c0 + 0x00001000), 374 (0x001d43c0 + 0x00001800), 375 }; 376 377 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { 378 (0x000143e0 + 0x00000000), 379 (0x000143e0 + 0x00000800), 380 (0x000143e0 + 0x00001000), 381 (0x000143e0 + 0x00001800), 382 (0x000543e0 + 0x00000000), 383 (0x000543e0 + 0x00000800), 384 (0x000543e0 + 0x00001000), 385 (0x000543e0 + 0x00001800), 386 (0x000943e0 + 0x00000000), 387 (0x000943e0 + 0x00000800), 388 (0x000943e0 + 0x00001000), 389 (0x000943e0 + 0x00001800), 390 (0x000d43e0 + 0x00000000), 391 (0x000d43e0 + 0x00000800), 392 (0x000d43e0 + 0x00001000), 393 (0x000d43e0 + 0x00001800), 394 (0x001143e0 + 0x00000000), 395 (0x001143e0 + 0x00000800), 396 (0x001143e0 + 0x00001000), 397 (0x001143e0 + 0x00001800), 398 (0x001543e0 + 0x00000000), 399 (0x001543e0 + 0x00000800), 400 (0x001543e0 + 0x00001000), 401 (0x001543e0 + 0x00001800), 402 (0x001943e0 + 0x00000000), 403 (0x001943e0 + 0x00000800), 404 (0x001943e0 + 0x00001000), 405 (0x001943e0 + 0x00001800), 406 (0x001d43e0 + 0x00000000), 407 (0x001d43e0 + 0x00000800), 408 (0x001d43e0 + 0x00001000), 409 (0x001d43e0 + 0x00001800), 410 }; 411 412 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, 413 struct amdgpu_irq_src *src, 414 unsigned type, 415 enum amdgpu_interrupt_state state) 416 { 417 u32 bits, i, tmp, reg; 418 419 /* Devices newer then VEGA10/12 shall have these programming 420 sequences performed by PSP BL */ 421 if (adev->asic_type >= CHIP_VEGA20) 422 return 0; 423 424 bits = 0x7f; 425 426 switch (state) { 427 case AMDGPU_IRQ_STATE_DISABLE: 428 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 429 reg = ecc_umc_mcumc_ctrl_addrs[i]; 430 tmp = RREG32(reg); 431 tmp &= ~bits; 432 WREG32(reg, tmp); 433 } 434 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 435 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 436 tmp = RREG32(reg); 437 tmp &= ~bits; 438 WREG32(reg, tmp); 439 } 440 break; 441 case AMDGPU_IRQ_STATE_ENABLE: 442 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 443 reg = ecc_umc_mcumc_ctrl_addrs[i]; 444 tmp = RREG32(reg); 445 tmp |= bits; 446 WREG32(reg, tmp); 447 } 448 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 449 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 450 tmp = RREG32(reg); 451 tmp |= bits; 452 WREG32(reg, tmp); 453 } 454 break; 455 default: 456 break; 457 } 458 459 return 0; 460 } 461 462 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 463 struct amdgpu_irq_src *src, 464 unsigned type, 465 enum amdgpu_interrupt_state state) 466 { 467 struct amdgpu_vmhub *hub; 468 u32 tmp, reg, bits, i, j; 469 470 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 471 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 472 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 473 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 474 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 475 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 476 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 477 478 switch (state) { 479 case AMDGPU_IRQ_STATE_DISABLE: 480 for (j = 0; j < adev->num_vmhubs; j++) { 481 hub = &adev->vmhub[j]; 482 for (i = 0; i < 16; i++) { 483 reg = hub->vm_context0_cntl + i; 484 485 if (j == AMDGPU_GFXHUB_0) 486 tmp = RREG32_SOC15_IP(GC, reg); 487 else 488 tmp = RREG32_SOC15_IP(MMHUB, reg); 489 490 tmp &= ~bits; 491 492 if (j == AMDGPU_GFXHUB_0) 493 WREG32_SOC15_IP(GC, reg, tmp); 494 else 495 WREG32_SOC15_IP(MMHUB, reg, tmp); 496 } 497 } 498 break; 499 case AMDGPU_IRQ_STATE_ENABLE: 500 for (j = 0; j < adev->num_vmhubs; j++) { 501 hub = &adev->vmhub[j]; 502 for (i = 0; i < 16; i++) { 503 reg = hub->vm_context0_cntl + i; 504 505 if (j == AMDGPU_GFXHUB_0) 506 tmp = RREG32_SOC15_IP(GC, reg); 507 else 508 tmp = RREG32_SOC15_IP(MMHUB, reg); 509 510 tmp |= bits; 511 512 if (j == AMDGPU_GFXHUB_0) 513 WREG32_SOC15_IP(GC, reg, tmp); 514 else 515 WREG32_SOC15_IP(MMHUB, reg, tmp); 516 } 517 } 518 break; 519 default: 520 break; 521 } 522 523 return 0; 524 } 525 526 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 527 struct amdgpu_irq_src *source, 528 struct amdgpu_iv_entry *entry) 529 { 530 bool retry_fault = !!(entry->src_data[1] & 0x80); 531 bool write_fault = !!(entry->src_data[1] & 0x20); 532 uint32_t status = 0, cid = 0, rw = 0; 533 struct amdgpu_task_info task_info; 534 struct amdgpu_vmhub *hub; 535 const char *mmhub_cid; 536 const char *hub_name; 537 u64 addr; 538 539 addr = (u64)entry->src_data[0] << 12; 540 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 541 542 if (retry_fault) { 543 /* Returning 1 here also prevents sending the IV to the KFD */ 544 545 /* Process it onyl if it's the first fault for this address */ 546 if (entry->ih != &adev->irq.ih_soft && 547 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, 548 entry->timestamp)) 549 return 1; 550 551 /* Delegate it to a different ring if the hardware hasn't 552 * already done it. 553 */ 554 if (entry->ih == &adev->irq.ih) { 555 amdgpu_irq_delegate(adev, entry, 8); 556 return 1; 557 } 558 559 /* Try to handle the recoverable page faults by filling page 560 * tables 561 */ 562 if (amdgpu_vm_handle_fault(adev, entry->pasid, addr, write_fault)) 563 return 1; 564 } 565 566 if (!printk_ratelimit()) 567 return 0; 568 569 if (entry->client_id == SOC15_IH_CLIENTID_VMC) { 570 hub_name = "mmhub0"; 571 hub = &adev->vmhub[AMDGPU_MMHUB_0]; 572 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) { 573 hub_name = "mmhub1"; 574 hub = &adev->vmhub[AMDGPU_MMHUB_1]; 575 } else { 576 hub_name = "gfxhub0"; 577 hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 578 } 579 580 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 581 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 582 583 dev_err(adev->dev, 584 "[%s] %s page fault (src_id:%u ring:%u vmid:%u " 585 "pasid:%u, for process %s pid %d thread %s pid %d)\n", 586 hub_name, retry_fault ? "retry" : "no-retry", 587 entry->src_id, entry->ring_id, entry->vmid, 588 entry->pasid, task_info.process_name, task_info.tgid, 589 task_info.task_name, task_info.pid); 590 dev_err(adev->dev, " in page starting at address 0x%016llx from IH client 0x%x (%s)\n", 591 addr, entry->client_id, 592 soc15_ih_clientid_name[entry->client_id]); 593 594 if (amdgpu_sriov_vf(adev)) 595 return 0; 596 597 /* 598 * Issue a dummy read to wait for the status register to 599 * be updated to avoid reading an incorrect value due to 600 * the new fast GRBM interface. 601 */ 602 if ((entry->vmid_src == AMDGPU_GFXHUB_0) && 603 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2))) 604 RREG32(hub->vm_l2_pro_fault_status); 605 606 status = RREG32(hub->vm_l2_pro_fault_status); 607 cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID); 608 rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW); 609 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 610 611 612 dev_err(adev->dev, 613 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 614 status); 615 if (hub == &adev->vmhub[AMDGPU_GFXHUB_0]) { 616 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 617 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : 618 gfxhub_client_ids[cid], 619 cid); 620 } else { 621 switch (adev->ip_versions[MMHUB_HWIP][0]) { 622 case IP_VERSION(9, 0, 0): 623 mmhub_cid = mmhub_client_ids_vega10[cid][rw]; 624 break; 625 case IP_VERSION(9, 3, 0): 626 mmhub_cid = mmhub_client_ids_vega12[cid][rw]; 627 break; 628 case IP_VERSION(9, 4, 0): 629 mmhub_cid = mmhub_client_ids_vega20[cid][rw]; 630 break; 631 case IP_VERSION(9, 4, 1): 632 mmhub_cid = mmhub_client_ids_arcturus[cid][rw]; 633 break; 634 case IP_VERSION(9, 1, 0): 635 case IP_VERSION(9, 2, 0): 636 mmhub_cid = mmhub_client_ids_raven[cid][rw]; 637 break; 638 case IP_VERSION(1, 5, 0): 639 case IP_VERSION(2, 4, 0): 640 mmhub_cid = mmhub_client_ids_renoir[cid][rw]; 641 break; 642 case IP_VERSION(9, 4, 2): 643 mmhub_cid = mmhub_client_ids_aldebaran[cid][rw]; 644 break; 645 default: 646 mmhub_cid = NULL; 647 break; 648 } 649 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 650 mmhub_cid ? mmhub_cid : "unknown", cid); 651 } 652 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 653 REG_GET_FIELD(status, 654 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 655 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 656 REG_GET_FIELD(status, 657 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 658 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 659 REG_GET_FIELD(status, 660 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 661 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 662 REG_GET_FIELD(status, 663 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 664 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 665 return 0; 666 } 667 668 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 669 .set = gmc_v9_0_vm_fault_interrupt_state, 670 .process = gmc_v9_0_process_interrupt, 671 }; 672 673 674 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { 675 .set = gmc_v9_0_ecc_interrupt_state, 676 .process = amdgpu_umc_process_ecc_irq, 677 }; 678 679 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 680 { 681 adev->gmc.vm_fault.num_types = 1; 682 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 683 684 if (!amdgpu_sriov_vf(adev) && 685 !adev->gmc.xgmi.connected_to_cpu) { 686 adev->gmc.ecc_irq.num_types = 1; 687 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; 688 } 689 } 690 691 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, 692 uint32_t flush_type) 693 { 694 u32 req = 0; 695 696 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 697 PER_VMID_INVALIDATE_REQ, 1 << vmid); 698 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 699 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 700 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 701 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 702 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 703 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 704 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 705 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 706 707 return req; 708 } 709 710 /** 711 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore 712 * 713 * @adev: amdgpu_device pointer 714 * @vmhub: vmhub type 715 * 716 */ 717 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev, 718 uint32_t vmhub) 719 { 720 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) 721 return false; 722 723 return ((vmhub == AMDGPU_MMHUB_0 || 724 vmhub == AMDGPU_MMHUB_1) && 725 (!amdgpu_sriov_vf(adev)) && 726 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) && 727 (adev->apu_flags & AMD_APU_IS_PICASSO)))); 728 } 729 730 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, 731 uint8_t vmid, uint16_t *p_pasid) 732 { 733 uint32_t value; 734 735 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 736 + vmid); 737 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 738 739 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 740 } 741 742 /* 743 * GART 744 * VMID 0 is the physical GPU addresses as used by the kernel. 745 * VMIDs 1-15 are used for userspace clients and are handled 746 * by the amdgpu vm/hsa code. 747 */ 748 749 /** 750 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type 751 * 752 * @adev: amdgpu_device pointer 753 * @vmid: vm instance to flush 754 * @vmhub: which hub to flush 755 * @flush_type: the flush type 756 * 757 * Flush the TLB for the requested page table using certain type. 758 */ 759 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 760 uint32_t vmhub, uint32_t flush_type) 761 { 762 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub); 763 const unsigned eng = 17; 764 u32 j, inv_req, inv_req2, tmp; 765 struct amdgpu_vmhub *hub; 766 767 BUG_ON(vmhub >= adev->num_vmhubs); 768 769 hub = &adev->vmhub[vmhub]; 770 if (adev->gmc.xgmi.num_physical_nodes && 771 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0)) { 772 /* Vega20+XGMI caches PTEs in TC and TLB. Add a 773 * heavy-weight TLB flush (type 2), which flushes 774 * both. Due to a race condition with concurrent 775 * memory accesses using the same TLB cache line, we 776 * still need a second TLB flush after this. 777 */ 778 inv_req = gmc_v9_0_get_invalidate_req(vmid, 2); 779 inv_req2 = gmc_v9_0_get_invalidate_req(vmid, flush_type); 780 } else { 781 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type); 782 inv_req2 = 0; 783 } 784 785 /* This is necessary for a HW workaround under SRIOV as well 786 * as GFXOFF under bare metal 787 */ 788 if (adev->gfx.kiq.ring.sched.ready && 789 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && 790 down_read_trylock(&adev->reset_sem)) { 791 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 792 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 793 794 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 795 1 << vmid); 796 up_read(&adev->reset_sem); 797 return; 798 } 799 800 spin_lock(&adev->gmc.invalidate_lock); 801 802 /* 803 * It may lose gpuvm invalidate acknowldege state across power-gating 804 * off cycle, add semaphore acquire before invalidation and semaphore 805 * release after invalidation to avoid entering power gated state 806 * to WA the Issue 807 */ 808 809 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 810 if (use_semaphore) { 811 for (j = 0; j < adev->usec_timeout; j++) { 812 /* a read return value of 1 means semaphore acquire */ 813 if (vmhub == AMDGPU_GFXHUB_0) 814 tmp = RREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_sem + hub->eng_distance * eng); 815 else 816 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_sem + hub->eng_distance * eng); 817 818 if (tmp & 0x1) 819 break; 820 udelay(1); 821 } 822 823 if (j >= adev->usec_timeout) 824 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 825 } 826 827 do { 828 if (vmhub == AMDGPU_GFXHUB_0) 829 WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req); 830 else 831 WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req); 832 833 /* 834 * Issue a dummy read to wait for the ACK register to 835 * be cleared to avoid a false ACK due to the new fast 836 * GRBM interface. 837 */ 838 if ((vmhub == AMDGPU_GFXHUB_0) && 839 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2))) 840 RREG32_NO_KIQ(hub->vm_inv_eng0_req + 841 hub->eng_distance * eng); 842 843 for (j = 0; j < adev->usec_timeout; j++) { 844 if (vmhub == AMDGPU_GFXHUB_0) 845 tmp = RREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_ack + hub->eng_distance * eng); 846 else 847 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_ack + hub->eng_distance * eng); 848 849 if (tmp & (1 << vmid)) 850 break; 851 udelay(1); 852 } 853 854 inv_req = inv_req2; 855 inv_req2 = 0; 856 } while (inv_req); 857 858 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 859 if (use_semaphore) { 860 /* 861 * add semaphore release after invalidation, 862 * write with 0 means semaphore release 863 */ 864 if (vmhub == AMDGPU_GFXHUB_0) 865 WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_sem + hub->eng_distance * eng, 0); 866 else 867 WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_sem + hub->eng_distance * eng, 0); 868 } 869 870 spin_unlock(&adev->gmc.invalidate_lock); 871 872 if (j < adev->usec_timeout) 873 return; 874 875 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 876 } 877 878 /** 879 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid 880 * 881 * @adev: amdgpu_device pointer 882 * @pasid: pasid to be flush 883 * @flush_type: the flush type 884 * @all_hub: flush all hubs 885 * 886 * Flush the TLB for the requested pasid. 887 */ 888 static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 889 uint16_t pasid, uint32_t flush_type, 890 bool all_hub) 891 { 892 int vmid, i; 893 signed long r; 894 uint32_t seq; 895 uint16_t queried_pasid; 896 bool ret; 897 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 898 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 899 900 if (amdgpu_in_reset(adev)) 901 return -EIO; 902 903 if (ring->sched.ready && down_read_trylock(&adev->reset_sem)) { 904 /* Vega20+XGMI caches PTEs in TC and TLB. Add a 905 * heavy-weight TLB flush (type 2), which flushes 906 * both. Due to a race condition with concurrent 907 * memory accesses using the same TLB cache line, we 908 * still need a second TLB flush after this. 909 */ 910 bool vega20_xgmi_wa = (adev->gmc.xgmi.num_physical_nodes && 911 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0)); 912 /* 2 dwords flush + 8 dwords fence */ 913 unsigned int ndw = kiq->pmf->invalidate_tlbs_size + 8; 914 915 if (vega20_xgmi_wa) 916 ndw += kiq->pmf->invalidate_tlbs_size; 917 918 spin_lock(&adev->gfx.kiq.ring_lock); 919 /* 2 dwords flush + 8 dwords fence */ 920 amdgpu_ring_alloc(ring, ndw); 921 if (vega20_xgmi_wa) 922 kiq->pmf->kiq_invalidate_tlbs(ring, 923 pasid, 2, all_hub); 924 kiq->pmf->kiq_invalidate_tlbs(ring, 925 pasid, flush_type, all_hub); 926 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 927 if (r) { 928 amdgpu_ring_undo(ring); 929 spin_unlock(&adev->gfx.kiq.ring_lock); 930 up_read(&adev->reset_sem); 931 return -ETIME; 932 } 933 934 amdgpu_ring_commit(ring); 935 spin_unlock(&adev->gfx.kiq.ring_lock); 936 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); 937 if (r < 1) { 938 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r); 939 up_read(&adev->reset_sem); 940 return -ETIME; 941 } 942 up_read(&adev->reset_sem); 943 return 0; 944 } 945 946 for (vmid = 1; vmid < 16; vmid++) { 947 948 ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 949 &queried_pasid); 950 if (ret && queried_pasid == pasid) { 951 if (all_hub) { 952 for (i = 0; i < adev->num_vmhubs; i++) 953 gmc_v9_0_flush_gpu_tlb(adev, vmid, 954 i, flush_type); 955 } else { 956 gmc_v9_0_flush_gpu_tlb(adev, vmid, 957 AMDGPU_GFXHUB_0, flush_type); 958 } 959 break; 960 } 961 } 962 963 return 0; 964 965 } 966 967 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 968 unsigned vmid, uint64_t pd_addr) 969 { 970 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub); 971 struct amdgpu_device *adev = ring->adev; 972 struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub]; 973 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); 974 unsigned eng = ring->vm_inv_eng; 975 976 /* 977 * It may lose gpuvm invalidate acknowldege state across power-gating 978 * off cycle, add semaphore acquire before invalidation and semaphore 979 * release after invalidation to avoid entering power gated state 980 * to WA the Issue 981 */ 982 983 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 984 if (use_semaphore) 985 /* a read return value of 1 means semaphore acuqire */ 986 amdgpu_ring_emit_reg_wait(ring, 987 hub->vm_inv_eng0_sem + 988 hub->eng_distance * eng, 0x1, 0x1); 989 990 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 991 (hub->ctx_addr_distance * vmid), 992 lower_32_bits(pd_addr)); 993 994 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 995 (hub->ctx_addr_distance * vmid), 996 upper_32_bits(pd_addr)); 997 998 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 999 hub->eng_distance * eng, 1000 hub->vm_inv_eng0_ack + 1001 hub->eng_distance * eng, 1002 req, 1 << vmid); 1003 1004 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 1005 if (use_semaphore) 1006 /* 1007 * add semaphore release after invalidation, 1008 * write with 0 means semaphore release 1009 */ 1010 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 1011 hub->eng_distance * eng, 0); 1012 1013 return pd_addr; 1014 } 1015 1016 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 1017 unsigned pasid) 1018 { 1019 struct amdgpu_device *adev = ring->adev; 1020 uint32_t reg; 1021 1022 /* Do nothing because there's no lut register for mmhub1. */ 1023 if (ring->funcs->vmhub == AMDGPU_MMHUB_1) 1024 return; 1025 1026 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) 1027 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 1028 else 1029 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 1030 1031 amdgpu_ring_emit_wreg(ring, reg, pasid); 1032 } 1033 1034 /* 1035 * PTE format on VEGA 10: 1036 * 63:59 reserved 1037 * 58:57 mtype 1038 * 56 F 1039 * 55 L 1040 * 54 P 1041 * 53 SW 1042 * 52 T 1043 * 50:48 reserved 1044 * 47:12 4k physical page base address 1045 * 11:7 fragment 1046 * 6 write 1047 * 5 read 1048 * 4 exe 1049 * 3 Z 1050 * 2 snooped 1051 * 1 system 1052 * 0 valid 1053 * 1054 * PDE format on VEGA 10: 1055 * 63:59 block fragment size 1056 * 58:55 reserved 1057 * 54 P 1058 * 53:48 reserved 1059 * 47:6 physical base address of PD or PTE 1060 * 5:3 reserved 1061 * 2 C 1062 * 1 system 1063 * 0 valid 1064 */ 1065 1066 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 1067 1068 { 1069 switch (flags) { 1070 case AMDGPU_VM_MTYPE_DEFAULT: 1071 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1072 case AMDGPU_VM_MTYPE_NC: 1073 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1074 case AMDGPU_VM_MTYPE_WC: 1075 return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC); 1076 case AMDGPU_VM_MTYPE_RW: 1077 return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW); 1078 case AMDGPU_VM_MTYPE_CC: 1079 return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC); 1080 case AMDGPU_VM_MTYPE_UC: 1081 return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC); 1082 default: 1083 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1084 } 1085 } 1086 1087 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, 1088 uint64_t *addr, uint64_t *flags) 1089 { 1090 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 1091 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 1092 BUG_ON(*addr & 0xFFFF00000000003FULL); 1093 1094 if (!adev->gmc.translate_further) 1095 return; 1096 1097 if (level == AMDGPU_VM_PDB1) { 1098 /* Set the block fragment size */ 1099 if (!(*flags & AMDGPU_PDE_PTE)) 1100 *flags |= AMDGPU_PDE_BFS(0x9); 1101 1102 } else if (level == AMDGPU_VM_PDB0) { 1103 if (*flags & AMDGPU_PDE_PTE) 1104 *flags &= ~AMDGPU_PDE_PTE; 1105 else 1106 *flags |= AMDGPU_PTE_TF; 1107 } 1108 } 1109 1110 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev, 1111 struct amdgpu_bo_va_mapping *mapping, 1112 uint64_t *flags) 1113 { 1114 *flags &= ~AMDGPU_PTE_EXECUTABLE; 1115 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 1116 1117 *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 1118 *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK; 1119 1120 if (mapping->flags & AMDGPU_PTE_PRT) { 1121 *flags |= AMDGPU_PTE_PRT; 1122 *flags &= ~AMDGPU_PTE_VALID; 1123 } 1124 1125 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) || 1126 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) && 1127 !(*flags & AMDGPU_PTE_SYSTEM) && 1128 mapping->bo_va->is_xgmi) 1129 *flags |= AMDGPU_PTE_SNOOPED; 1130 1131 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) 1132 *flags |= mapping->flags & AMDGPU_PTE_SNOOPED; 1133 } 1134 1135 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 1136 { 1137 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 1138 unsigned size; 1139 1140 /* TODO move to DC so GMC doesn't need to hard-code DCN registers */ 1141 1142 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1143 size = AMDGPU_VBIOS_VGA_ALLOCATION; 1144 } else { 1145 u32 viewport; 1146 1147 switch (adev->ip_versions[DCE_HWIP][0]) { 1148 case IP_VERSION(1, 0, 0): 1149 case IP_VERSION(1, 0, 1): 1150 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 1151 size = (REG_GET_FIELD(viewport, 1152 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1153 REG_GET_FIELD(viewport, 1154 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1155 4); 1156 break; 1157 case IP_VERSION(2, 1, 0): 1158 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2); 1159 size = (REG_GET_FIELD(viewport, 1160 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1161 REG_GET_FIELD(viewport, 1162 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1163 4); 1164 break; 1165 default: 1166 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); 1167 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1168 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1169 4); 1170 break; 1171 } 1172 } 1173 1174 return size; 1175 } 1176 1177 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { 1178 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, 1179 .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid, 1180 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, 1181 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, 1182 .map_mtype = gmc_v9_0_map_mtype, 1183 .get_vm_pde = gmc_v9_0_get_vm_pde, 1184 .get_vm_pte = gmc_v9_0_get_vm_pte, 1185 .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size, 1186 }; 1187 1188 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) 1189 { 1190 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; 1191 } 1192 1193 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) 1194 { 1195 switch (adev->ip_versions[UMC_HWIP][0]) { 1196 case IP_VERSION(6, 0, 0): 1197 adev->umc.funcs = &umc_v6_0_funcs; 1198 break; 1199 case IP_VERSION(6, 1, 1): 1200 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1201 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1202 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1203 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20; 1204 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1205 adev->umc.ras_funcs = &umc_v6_1_ras_funcs; 1206 break; 1207 case IP_VERSION(6, 1, 2): 1208 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1209 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1210 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1211 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT; 1212 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1213 adev->umc.ras_funcs = &umc_v6_1_ras_funcs; 1214 break; 1215 case IP_VERSION(6, 7, 0): 1216 adev->umc.max_ras_err_cnt_per_query = UMC_V6_7_TOTAL_CHANNEL_NUM; 1217 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM; 1218 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM; 1219 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET; 1220 if (!adev->gmc.xgmi.connected_to_cpu) 1221 adev->umc.ras_funcs = &umc_v6_7_ras_funcs; 1222 if (1 & adev->smuio.funcs->get_die_id(adev)) 1223 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0]; 1224 else 1225 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0]; 1226 break; 1227 default: 1228 break; 1229 } 1230 } 1231 1232 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) 1233 { 1234 switch (adev->ip_versions[MMHUB_HWIP][0]) { 1235 case IP_VERSION(9, 4, 1): 1236 adev->mmhub.funcs = &mmhub_v9_4_funcs; 1237 break; 1238 case IP_VERSION(9, 4, 2): 1239 adev->mmhub.funcs = &mmhub_v1_7_funcs; 1240 break; 1241 default: 1242 adev->mmhub.funcs = &mmhub_v1_0_funcs; 1243 break; 1244 } 1245 } 1246 1247 static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev) 1248 { 1249 switch (adev->ip_versions[MMHUB_HWIP][0]) { 1250 case IP_VERSION(9, 4, 0): 1251 adev->mmhub.ras_funcs = &mmhub_v1_0_ras_funcs; 1252 break; 1253 case IP_VERSION(9, 4, 1): 1254 adev->mmhub.ras_funcs = &mmhub_v9_4_ras_funcs; 1255 break; 1256 case IP_VERSION(9, 4, 2): 1257 adev->mmhub.ras_funcs = &mmhub_v1_7_ras_funcs; 1258 break; 1259 default: 1260 /* mmhub ras is not available */ 1261 break; 1262 } 1263 } 1264 1265 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev) 1266 { 1267 adev->gfxhub.funcs = &gfxhub_v1_0_funcs; 1268 } 1269 1270 static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev) 1271 { 1272 adev->hdp.ras_funcs = &hdp_v4_0_ras_funcs; 1273 } 1274 1275 static void gmc_v9_0_set_mca_funcs(struct amdgpu_device *adev) 1276 { 1277 /* is UMC the right IP to check for MCA? Maybe DF? */ 1278 switch (adev->ip_versions[UMC_HWIP][0]) { 1279 case IP_VERSION(6, 7, 0): 1280 if (!adev->gmc.xgmi.connected_to_cpu) 1281 adev->mca.funcs = &mca_v3_0_funcs; 1282 break; 1283 default: 1284 break; 1285 } 1286 } 1287 1288 static int gmc_v9_0_early_init(void *handle) 1289 { 1290 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1291 1292 /* ARCT and VEGA20 don't have XGMI defined in their IP discovery tables */ 1293 if (adev->asic_type == CHIP_VEGA20 || 1294 adev->asic_type == CHIP_ARCTURUS) 1295 adev->gmc.xgmi.supported = true; 1296 1297 if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(6, 1, 0)) { 1298 adev->gmc.xgmi.supported = true; 1299 adev->gmc.xgmi.connected_to_cpu = 1300 adev->smuio.funcs->is_host_gpu_xgmi_supported(adev); 1301 } 1302 1303 gmc_v9_0_set_gmc_funcs(adev); 1304 gmc_v9_0_set_irq_funcs(adev); 1305 gmc_v9_0_set_umc_funcs(adev); 1306 gmc_v9_0_set_mmhub_funcs(adev); 1307 gmc_v9_0_set_mmhub_ras_funcs(adev); 1308 gmc_v9_0_set_gfxhub_funcs(adev); 1309 gmc_v9_0_set_hdp_ras_funcs(adev); 1310 gmc_v9_0_set_mca_funcs(adev); 1311 1312 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1313 adev->gmc.shared_aperture_end = 1314 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1315 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 1316 adev->gmc.private_aperture_end = 1317 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1318 1319 return 0; 1320 } 1321 1322 static int gmc_v9_0_late_init(void *handle) 1323 { 1324 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1325 int r; 1326 1327 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 1328 if (r) 1329 return r; 1330 1331 /* 1332 * Workaround performance drop issue with VBIOS enables partial 1333 * writes, while disables HBM ECC for vega10. 1334 */ 1335 if (!amdgpu_sriov_vf(adev) && 1336 (adev->ip_versions[UMC_HWIP][0] == IP_VERSION(6, 0, 0))) { 1337 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) { 1338 if (adev->df.funcs && 1339 adev->df.funcs->enable_ecc_force_par_wr_rmw) 1340 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false); 1341 } 1342 } 1343 1344 if (!amdgpu_persistent_edc_harvesting_supported(adev)) { 1345 if (adev->mmhub.ras_funcs && 1346 adev->mmhub.ras_funcs->reset_ras_error_count) 1347 adev->mmhub.ras_funcs->reset_ras_error_count(adev); 1348 1349 if (adev->hdp.ras_funcs && 1350 adev->hdp.ras_funcs->reset_ras_error_count) 1351 adev->hdp.ras_funcs->reset_ras_error_count(adev); 1352 } 1353 1354 r = amdgpu_gmc_ras_late_init(adev); 1355 if (r) 1356 return r; 1357 1358 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1359 } 1360 1361 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 1362 struct amdgpu_gmc *mc) 1363 { 1364 u64 base = adev->mmhub.funcs->get_fb_location(adev); 1365 1366 /* add the xgmi offset of the physical node */ 1367 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1368 if (adev->gmc.xgmi.connected_to_cpu) { 1369 amdgpu_gmc_sysvm_location(adev, mc); 1370 } else { 1371 amdgpu_gmc_vram_location(adev, mc, base); 1372 amdgpu_gmc_gart_location(adev, mc); 1373 amdgpu_gmc_agp_location(adev, mc); 1374 } 1375 /* base offset of vram pages */ 1376 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 1377 1378 /* XXX: add the xgmi offset of the physical node? */ 1379 adev->vm_manager.vram_base_offset += 1380 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1381 } 1382 1383 /** 1384 * gmc_v9_0_mc_init - initialize the memory controller driver params 1385 * 1386 * @adev: amdgpu_device pointer 1387 * 1388 * Look up the amount of vram, vram width, and decide how to place 1389 * vram and gart within the GPU's physical address space. 1390 * Returns 0 for success. 1391 */ 1392 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 1393 { 1394 int r; 1395 1396 /* size in MB on si */ 1397 adev->gmc.mc_vram_size = 1398 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 1399 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 1400 1401 if (!(adev->flags & AMD_IS_APU) && 1402 !adev->gmc.xgmi.connected_to_cpu) { 1403 r = amdgpu_device_resize_fb_bar(adev); 1404 if (r) 1405 return r; 1406 } 1407 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 1408 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 1409 1410 #ifdef CONFIG_X86_64 1411 /* 1412 * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi 1413 * interface can use VRAM through here as it appears system reserved 1414 * memory in host address space. 1415 * 1416 * For APUs, VRAM is just the stolen system memory and can be accessed 1417 * directly. 1418 * 1419 * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR. 1420 */ 1421 1422 /* check whether both host-gpu and gpu-gpu xgmi links exist */ 1423 if ((adev->flags & AMD_IS_APU) || 1424 (adev->gmc.xgmi.supported && 1425 adev->gmc.xgmi.connected_to_cpu)) { 1426 adev->gmc.aper_base = 1427 adev->gfxhub.funcs->get_mc_fb_offset(adev) + 1428 adev->gmc.xgmi.physical_node_id * 1429 adev->gmc.xgmi.node_segment_size; 1430 adev->gmc.aper_size = adev->gmc.real_vram_size; 1431 } 1432 1433 #endif 1434 /* In case the PCI BAR is larger than the actual amount of vram */ 1435 adev->gmc.visible_vram_size = adev->gmc.aper_size; 1436 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 1437 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 1438 1439 /* set the gart size */ 1440 if (amdgpu_gart_size == -1) { 1441 switch (adev->ip_versions[GC_HWIP][0]) { 1442 case IP_VERSION(9, 0, 1): /* all engines support GPUVM */ 1443 case IP_VERSION(9, 2, 1): /* all engines support GPUVM */ 1444 case IP_VERSION(9, 4, 0): 1445 case IP_VERSION(9, 4, 1): 1446 case IP_VERSION(9, 4, 2): 1447 default: 1448 adev->gmc.gart_size = 512ULL << 20; 1449 break; 1450 case IP_VERSION(9, 1, 0): /* DCE SG support */ 1451 case IP_VERSION(9, 2, 2): /* DCE SG support */ 1452 case IP_VERSION(9, 3, 0): 1453 adev->gmc.gart_size = 1024ULL << 20; 1454 break; 1455 } 1456 } else { 1457 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 1458 } 1459 1460 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; 1461 1462 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); 1463 1464 return 0; 1465 } 1466 1467 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 1468 { 1469 int r; 1470 1471 if (adev->gart.bo) { 1472 WARN(1, "VEGA10 PCIE GART already initialized\n"); 1473 return 0; 1474 } 1475 1476 if (adev->gmc.xgmi.connected_to_cpu) { 1477 adev->gmc.vmid0_page_table_depth = 1; 1478 adev->gmc.vmid0_page_table_block_size = 12; 1479 } else { 1480 adev->gmc.vmid0_page_table_depth = 0; 1481 adev->gmc.vmid0_page_table_block_size = 0; 1482 } 1483 1484 /* Initialize common gart structure */ 1485 r = amdgpu_gart_init(adev); 1486 if (r) 1487 return r; 1488 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 1489 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) | 1490 AMDGPU_PTE_EXECUTABLE; 1491 1492 r = amdgpu_gart_table_vram_alloc(adev); 1493 if (r) 1494 return r; 1495 1496 if (adev->gmc.xgmi.connected_to_cpu) { 1497 r = amdgpu_gmc_pdb0_alloc(adev); 1498 } 1499 1500 return r; 1501 } 1502 1503 /** 1504 * gmc_v9_0_save_registers - saves regs 1505 * 1506 * @adev: amdgpu_device pointer 1507 * 1508 * This saves potential register values that should be 1509 * restored upon resume 1510 */ 1511 static void gmc_v9_0_save_registers(struct amdgpu_device *adev) 1512 { 1513 if ((adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 0)) || 1514 (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 1))) 1515 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); 1516 } 1517 1518 static int gmc_v9_0_sw_init(void *handle) 1519 { 1520 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 1521 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1522 1523 adev->gfxhub.funcs->init(adev); 1524 1525 adev->mmhub.funcs->init(adev); 1526 if (adev->mca.funcs) 1527 adev->mca.funcs->init(adev); 1528 1529 spin_lock_init(&adev->gmc.invalidate_lock); 1530 1531 r = amdgpu_atomfirmware_get_vram_info(adev, 1532 &vram_width, &vram_type, &vram_vendor); 1533 if (amdgpu_sriov_vf(adev)) 1534 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, 1535 * and DF related registers is not readable, seems hardcord is the 1536 * only way to set the correct vram_width 1537 */ 1538 adev->gmc.vram_width = 2048; 1539 else if (amdgpu_emu_mode != 1) 1540 adev->gmc.vram_width = vram_width; 1541 1542 if (!adev->gmc.vram_width) { 1543 int chansize, numchan; 1544 1545 /* hbm memory channel size */ 1546 if (adev->flags & AMD_IS_APU) 1547 chansize = 64; 1548 else 1549 chansize = 128; 1550 if (adev->df.funcs && 1551 adev->df.funcs->get_hbm_channel_number) { 1552 numchan = adev->df.funcs->get_hbm_channel_number(adev); 1553 adev->gmc.vram_width = numchan * chansize; 1554 } 1555 } 1556 1557 adev->gmc.vram_type = vram_type; 1558 adev->gmc.vram_vendor = vram_vendor; 1559 switch (adev->ip_versions[GC_HWIP][0]) { 1560 case IP_VERSION(9, 1, 0): 1561 case IP_VERSION(9, 2, 2): 1562 adev->num_vmhubs = 2; 1563 1564 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 1565 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1566 } else { 1567 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 1568 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 1569 adev->gmc.translate_further = 1570 adev->vm_manager.num_level > 1; 1571 } 1572 break; 1573 case IP_VERSION(9, 0, 1): 1574 case IP_VERSION(9, 2, 1): 1575 case IP_VERSION(9, 4, 0): 1576 case IP_VERSION(9, 3, 0): 1577 case IP_VERSION(9, 4, 2): 1578 adev->num_vmhubs = 2; 1579 1580 1581 /* 1582 * To fulfill 4-level page support, 1583 * vm size is 256TB (48bit), maximum size of Vega10, 1584 * block size 512 (9bit) 1585 */ 1586 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */ 1587 if (amdgpu_sriov_vf(adev)) 1588 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47); 1589 else 1590 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1591 break; 1592 case IP_VERSION(9, 4, 1): 1593 adev->num_vmhubs = 3; 1594 1595 /* Keep the vm size same with Vega20 */ 1596 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1597 break; 1598 default: 1599 break; 1600 } 1601 1602 /* This interrupt is VMC page fault.*/ 1603 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, 1604 &adev->gmc.vm_fault); 1605 if (r) 1606 return r; 1607 1608 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)) { 1609 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT, 1610 &adev->gmc.vm_fault); 1611 if (r) 1612 return r; 1613 } 1614 1615 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, 1616 &adev->gmc.vm_fault); 1617 1618 if (r) 1619 return r; 1620 1621 if (!amdgpu_sriov_vf(adev) && 1622 !adev->gmc.xgmi.connected_to_cpu) { 1623 /* interrupt sent to DF. */ 1624 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 1625 &adev->gmc.ecc_irq); 1626 if (r) 1627 return r; 1628 } 1629 1630 /* Set the internal MC address mask 1631 * This is the max address of the GPU's 1632 * internal address space. 1633 */ 1634 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 1635 1636 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 1637 if (r) { 1638 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 1639 return r; 1640 } 1641 adev->need_swiotlb = drm_need_swiotlb(44); 1642 1643 r = gmc_v9_0_mc_init(adev); 1644 if (r) 1645 return r; 1646 1647 amdgpu_gmc_get_vbios_allocations(adev); 1648 1649 /* Memory manager */ 1650 r = amdgpu_bo_init(adev); 1651 if (r) 1652 return r; 1653 1654 r = gmc_v9_0_gart_init(adev); 1655 if (r) 1656 return r; 1657 1658 /* 1659 * number of VMs 1660 * VMID 0 is reserved for System 1661 * amdgpu graphics/compute will use VMIDs 1..n-1 1662 * amdkfd will use VMIDs n..15 1663 * 1664 * The first KFD VMID is 8 for GPUs with graphics, 3 for 1665 * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs 1666 * for video processing. 1667 */ 1668 adev->vm_manager.first_kfd_vmid = 1669 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) || 1670 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) ? 3 : 8; 1671 1672 amdgpu_vm_manager_init(adev); 1673 1674 gmc_v9_0_save_registers(adev); 1675 1676 return 0; 1677 } 1678 1679 static int gmc_v9_0_sw_fini(void *handle) 1680 { 1681 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1682 1683 amdgpu_gmc_ras_fini(adev); 1684 amdgpu_gem_force_release(adev); 1685 amdgpu_vm_manager_fini(adev); 1686 amdgpu_gart_table_vram_free(adev); 1687 amdgpu_bo_unref(&adev->gmc.pdb0_bo); 1688 amdgpu_bo_fini(adev); 1689 1690 return 0; 1691 } 1692 1693 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 1694 { 1695 1696 switch (adev->ip_versions[MMHUB_HWIP][0]) { 1697 case IP_VERSION(9, 0, 0): 1698 if (amdgpu_sriov_vf(adev)) 1699 break; 1700 fallthrough; 1701 case IP_VERSION(9, 4, 0): 1702 soc15_program_register_sequence(adev, 1703 golden_settings_mmhub_1_0_0, 1704 ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 1705 soc15_program_register_sequence(adev, 1706 golden_settings_athub_1_0_0, 1707 ARRAY_SIZE(golden_settings_athub_1_0_0)); 1708 break; 1709 case IP_VERSION(9, 1, 0): 1710 case IP_VERSION(9, 2, 0): 1711 /* TODO for renoir */ 1712 soc15_program_register_sequence(adev, 1713 golden_settings_athub_1_0_0, 1714 ARRAY_SIZE(golden_settings_athub_1_0_0)); 1715 break; 1716 default: 1717 break; 1718 } 1719 } 1720 1721 /** 1722 * gmc_v9_0_restore_registers - restores regs 1723 * 1724 * @adev: amdgpu_device pointer 1725 * 1726 * This restores register values, saved at suspend. 1727 */ 1728 void gmc_v9_0_restore_registers(struct amdgpu_device *adev) 1729 { 1730 if ((adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 0)) || 1731 (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 1))) { 1732 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register); 1733 WARN_ON(adev->gmc.sdpif_register != 1734 RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0)); 1735 } 1736 } 1737 1738 /** 1739 * gmc_v9_0_gart_enable - gart enable 1740 * 1741 * @adev: amdgpu_device pointer 1742 */ 1743 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 1744 { 1745 int r; 1746 1747 if (adev->gmc.xgmi.connected_to_cpu) 1748 amdgpu_gmc_init_pdb0(adev); 1749 1750 if (adev->gart.bo == NULL) { 1751 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 1752 return -EINVAL; 1753 } 1754 1755 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 1756 goto skip_pin_bo; 1757 1758 r = amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 1759 if (r) 1760 return r; 1761 1762 skip_pin_bo: 1763 r = adev->gfxhub.funcs->gart_enable(adev); 1764 if (r) 1765 return r; 1766 1767 r = adev->mmhub.funcs->gart_enable(adev); 1768 if (r) 1769 return r; 1770 1771 DRM_INFO("PCIE GART of %uM enabled.\n", 1772 (unsigned)(adev->gmc.gart_size >> 20)); 1773 if (adev->gmc.pdb0_bo) 1774 DRM_INFO("PDB0 located at 0x%016llX\n", 1775 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo)); 1776 DRM_INFO("PTB located at 0x%016llX\n", 1777 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 1778 1779 adev->gart.ready = true; 1780 return 0; 1781 } 1782 1783 static int gmc_v9_0_hw_init(void *handle) 1784 { 1785 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1786 bool value; 1787 int i; 1788 1789 /* The sequence of these two function calls matters.*/ 1790 gmc_v9_0_init_golden_registers(adev); 1791 1792 if (adev->mode_info.num_crtc) { 1793 /* Lockout access through VGA aperture*/ 1794 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 1795 /* disable VGA render */ 1796 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 1797 } 1798 1799 if (adev->mmhub.funcs->update_power_gating) 1800 adev->mmhub.funcs->update_power_gating(adev, true); 1801 1802 adev->hdp.funcs->init_registers(adev); 1803 1804 /* After HDP is initialized, flush HDP.*/ 1805 adev->hdp.funcs->flush_hdp(adev, NULL); 1806 1807 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 1808 value = false; 1809 else 1810 value = true; 1811 1812 if (!amdgpu_sriov_vf(adev)) { 1813 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 1814 adev->mmhub.funcs->set_fault_enable_default(adev, value); 1815 } 1816 for (i = 0; i < adev->num_vmhubs; ++i) 1817 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0); 1818 1819 if (adev->umc.funcs && adev->umc.funcs->init_registers) 1820 adev->umc.funcs->init_registers(adev); 1821 1822 return gmc_v9_0_gart_enable(adev); 1823 } 1824 1825 /** 1826 * gmc_v9_0_gart_disable - gart disable 1827 * 1828 * @adev: amdgpu_device pointer 1829 * 1830 * This disables all VM page table. 1831 */ 1832 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 1833 { 1834 adev->gfxhub.funcs->gart_disable(adev); 1835 adev->mmhub.funcs->gart_disable(adev); 1836 } 1837 1838 static int gmc_v9_0_hw_fini(void *handle) 1839 { 1840 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1841 1842 gmc_v9_0_gart_disable(adev); 1843 1844 if (amdgpu_sriov_vf(adev)) { 1845 /* full access mode, so don't touch any GMC register */ 1846 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 1847 return 0; 1848 } 1849 1850 /* 1851 * Pair the operations did in gmc_v9_0_hw_init and thus maintain 1852 * a correct cached state for GMC. Otherwise, the "gate" again 1853 * operation on S3 resuming will fail due to wrong cached state. 1854 */ 1855 if (adev->mmhub.funcs->update_power_gating) 1856 adev->mmhub.funcs->update_power_gating(adev, false); 1857 1858 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 1859 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1860 1861 return 0; 1862 } 1863 1864 static int gmc_v9_0_suspend(void *handle) 1865 { 1866 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1867 1868 return gmc_v9_0_hw_fini(adev); 1869 } 1870 1871 static int gmc_v9_0_resume(void *handle) 1872 { 1873 int r; 1874 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1875 1876 r = gmc_v9_0_hw_init(adev); 1877 if (r) 1878 return r; 1879 1880 amdgpu_vmid_reset_all(adev); 1881 1882 return 0; 1883 } 1884 1885 static bool gmc_v9_0_is_idle(void *handle) 1886 { 1887 /* MC is always ready in GMC v9.*/ 1888 return true; 1889 } 1890 1891 static int gmc_v9_0_wait_for_idle(void *handle) 1892 { 1893 /* There is no need to wait for MC idle in GMC v9.*/ 1894 return 0; 1895 } 1896 1897 static int gmc_v9_0_soft_reset(void *handle) 1898 { 1899 /* XXX for emulation.*/ 1900 return 0; 1901 } 1902 1903 static int gmc_v9_0_set_clockgating_state(void *handle, 1904 enum amd_clockgating_state state) 1905 { 1906 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1907 1908 adev->mmhub.funcs->set_clockgating(adev, state); 1909 1910 athub_v1_0_set_clockgating(adev, state); 1911 1912 return 0; 1913 } 1914 1915 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags) 1916 { 1917 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1918 1919 adev->mmhub.funcs->get_clockgating(adev, flags); 1920 1921 athub_v1_0_get_clockgating(adev, flags); 1922 } 1923 1924 static int gmc_v9_0_set_powergating_state(void *handle, 1925 enum amd_powergating_state state) 1926 { 1927 return 0; 1928 } 1929 1930 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 1931 .name = "gmc_v9_0", 1932 .early_init = gmc_v9_0_early_init, 1933 .late_init = gmc_v9_0_late_init, 1934 .sw_init = gmc_v9_0_sw_init, 1935 .sw_fini = gmc_v9_0_sw_fini, 1936 .hw_init = gmc_v9_0_hw_init, 1937 .hw_fini = gmc_v9_0_hw_fini, 1938 .suspend = gmc_v9_0_suspend, 1939 .resume = gmc_v9_0_resume, 1940 .is_idle = gmc_v9_0_is_idle, 1941 .wait_for_idle = gmc_v9_0_wait_for_idle, 1942 .soft_reset = gmc_v9_0_soft_reset, 1943 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 1944 .set_powergating_state = gmc_v9_0_set_powergating_state, 1945 .get_clockgating_state = gmc_v9_0_get_clockgating_state, 1946 }; 1947 1948 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = 1949 { 1950 .type = AMD_IP_BLOCK_TYPE_GMC, 1951 .major = 9, 1952 .minor = 0, 1953 .rev = 0, 1954 .funcs = &gmc_v9_0_ip_funcs, 1955 }; 1956