1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/pci.h> 26 27 #include <drm/drm_cache.h> 28 29 #include "amdgpu.h" 30 #include "gmc_v9_0.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_gem.h" 33 34 #include "gc/gc_9_0_sh_mask.h" 35 #include "dce/dce_12_0_offset.h" 36 #include "dce/dce_12_0_sh_mask.h" 37 #include "vega10_enum.h" 38 #include "mmhub/mmhub_1_0_offset.h" 39 #include "athub/athub_1_0_sh_mask.h" 40 #include "athub/athub_1_0_offset.h" 41 #include "oss/osssys_4_0_offset.h" 42 43 #include "soc15.h" 44 #include "soc15d.h" 45 #include "soc15_common.h" 46 #include "umc/umc_6_0_sh_mask.h" 47 48 #include "gfxhub_v1_0.h" 49 #include "mmhub_v1_0.h" 50 #include "athub_v1_0.h" 51 #include "gfxhub_v1_1.h" 52 #include "mmhub_v9_4.h" 53 #include "mmhub_v1_7.h" 54 #include "umc_v6_1.h" 55 #include "umc_v6_0.h" 56 #include "umc_v6_7.h" 57 #include "hdp_v4_0.h" 58 #include "mca_v3_0.h" 59 60 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 61 62 #include "amdgpu_ras.h" 63 #include "amdgpu_xgmi.h" 64 65 #include "amdgpu_reset.h" 66 67 /* add these here since we already include dce12 headers and these are for DCN */ 68 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 69 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 70 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 71 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 72 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL 73 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L 74 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d 75 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2 76 77 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2 0x05ea 78 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX 2 79 80 81 static const char *gfxhub_client_ids[] = { 82 "CB", 83 "DB", 84 "IA", 85 "WD", 86 "CPF", 87 "CPC", 88 "CPG", 89 "RLC", 90 "TCP", 91 "SQC (inst)", 92 "SQC (data)", 93 "SQG", 94 "PA", 95 }; 96 97 static const char *mmhub_client_ids_raven[][2] = { 98 [0][0] = "MP1", 99 [1][0] = "MP0", 100 [2][0] = "VCN", 101 [3][0] = "VCNU", 102 [4][0] = "HDP", 103 [5][0] = "DCE", 104 [13][0] = "UTCL2", 105 [19][0] = "TLS", 106 [26][0] = "OSS", 107 [27][0] = "SDMA0", 108 [0][1] = "MP1", 109 [1][1] = "MP0", 110 [2][1] = "VCN", 111 [3][1] = "VCNU", 112 [4][1] = "HDP", 113 [5][1] = "XDP", 114 [6][1] = "DBGU0", 115 [7][1] = "DCE", 116 [8][1] = "DCEDWB0", 117 [9][1] = "DCEDWB1", 118 [26][1] = "OSS", 119 [27][1] = "SDMA0", 120 }; 121 122 static const char *mmhub_client_ids_renoir[][2] = { 123 [0][0] = "MP1", 124 [1][0] = "MP0", 125 [2][0] = "HDP", 126 [4][0] = "DCEDMC", 127 [5][0] = "DCEVGA", 128 [13][0] = "UTCL2", 129 [19][0] = "TLS", 130 [26][0] = "OSS", 131 [27][0] = "SDMA0", 132 [28][0] = "VCN", 133 [29][0] = "VCNU", 134 [30][0] = "JPEG", 135 [0][1] = "MP1", 136 [1][1] = "MP0", 137 [2][1] = "HDP", 138 [3][1] = "XDP", 139 [6][1] = "DBGU0", 140 [7][1] = "DCEDMC", 141 [8][1] = "DCEVGA", 142 [9][1] = "DCEDWB", 143 [26][1] = "OSS", 144 [27][1] = "SDMA0", 145 [28][1] = "VCN", 146 [29][1] = "VCNU", 147 [30][1] = "JPEG", 148 }; 149 150 static const char *mmhub_client_ids_vega10[][2] = { 151 [0][0] = "MP0", 152 [1][0] = "UVD", 153 [2][0] = "UVDU", 154 [3][0] = "HDP", 155 [13][0] = "UTCL2", 156 [14][0] = "OSS", 157 [15][0] = "SDMA1", 158 [32+0][0] = "VCE0", 159 [32+1][0] = "VCE0U", 160 [32+2][0] = "XDMA", 161 [32+3][0] = "DCE", 162 [32+4][0] = "MP1", 163 [32+14][0] = "SDMA0", 164 [0][1] = "MP0", 165 [1][1] = "UVD", 166 [2][1] = "UVDU", 167 [3][1] = "DBGU0", 168 [4][1] = "HDP", 169 [5][1] = "XDP", 170 [14][1] = "OSS", 171 [15][1] = "SDMA0", 172 [32+0][1] = "VCE0", 173 [32+1][1] = "VCE0U", 174 [32+2][1] = "XDMA", 175 [32+3][1] = "DCE", 176 [32+4][1] = "DCEDWB", 177 [32+5][1] = "MP1", 178 [32+6][1] = "DBGU1", 179 [32+14][1] = "SDMA1", 180 }; 181 182 static const char *mmhub_client_ids_vega12[][2] = { 183 [0][0] = "MP0", 184 [1][0] = "VCE0", 185 [2][0] = "VCE0U", 186 [3][0] = "HDP", 187 [13][0] = "UTCL2", 188 [14][0] = "OSS", 189 [15][0] = "SDMA1", 190 [32+0][0] = "DCE", 191 [32+1][0] = "XDMA", 192 [32+2][0] = "UVD", 193 [32+3][0] = "UVDU", 194 [32+4][0] = "MP1", 195 [32+15][0] = "SDMA0", 196 [0][1] = "MP0", 197 [1][1] = "VCE0", 198 [2][1] = "VCE0U", 199 [3][1] = "DBGU0", 200 [4][1] = "HDP", 201 [5][1] = "XDP", 202 [14][1] = "OSS", 203 [15][1] = "SDMA0", 204 [32+0][1] = "DCE", 205 [32+1][1] = "DCEDWB", 206 [32+2][1] = "XDMA", 207 [32+3][1] = "UVD", 208 [32+4][1] = "UVDU", 209 [32+5][1] = "MP1", 210 [32+6][1] = "DBGU1", 211 [32+15][1] = "SDMA1", 212 }; 213 214 static const char *mmhub_client_ids_vega20[][2] = { 215 [0][0] = "XDMA", 216 [1][0] = "DCE", 217 [2][0] = "VCE0", 218 [3][0] = "VCE0U", 219 [4][0] = "UVD", 220 [5][0] = "UVD1U", 221 [13][0] = "OSS", 222 [14][0] = "HDP", 223 [15][0] = "SDMA0", 224 [32+0][0] = "UVD", 225 [32+1][0] = "UVDU", 226 [32+2][0] = "MP1", 227 [32+3][0] = "MP0", 228 [32+12][0] = "UTCL2", 229 [32+14][0] = "SDMA1", 230 [0][1] = "XDMA", 231 [1][1] = "DCE", 232 [2][1] = "DCEDWB", 233 [3][1] = "VCE0", 234 [4][1] = "VCE0U", 235 [5][1] = "UVD1", 236 [6][1] = "UVD1U", 237 [7][1] = "DBGU0", 238 [8][1] = "XDP", 239 [13][1] = "OSS", 240 [14][1] = "HDP", 241 [15][1] = "SDMA0", 242 [32+0][1] = "UVD", 243 [32+1][1] = "UVDU", 244 [32+2][1] = "DBGU1", 245 [32+3][1] = "MP1", 246 [32+4][1] = "MP0", 247 [32+14][1] = "SDMA1", 248 }; 249 250 static const char *mmhub_client_ids_arcturus[][2] = { 251 [0][0] = "DBGU1", 252 [1][0] = "XDP", 253 [2][0] = "MP1", 254 [14][0] = "HDP", 255 [171][0] = "JPEG", 256 [172][0] = "VCN", 257 [173][0] = "VCNU", 258 [203][0] = "JPEG1", 259 [204][0] = "VCN1", 260 [205][0] = "VCN1U", 261 [256][0] = "SDMA0", 262 [257][0] = "SDMA1", 263 [258][0] = "SDMA2", 264 [259][0] = "SDMA3", 265 [260][0] = "SDMA4", 266 [261][0] = "SDMA5", 267 [262][0] = "SDMA6", 268 [263][0] = "SDMA7", 269 [384][0] = "OSS", 270 [0][1] = "DBGU1", 271 [1][1] = "XDP", 272 [2][1] = "MP1", 273 [14][1] = "HDP", 274 [171][1] = "JPEG", 275 [172][1] = "VCN", 276 [173][1] = "VCNU", 277 [203][1] = "JPEG1", 278 [204][1] = "VCN1", 279 [205][1] = "VCN1U", 280 [256][1] = "SDMA0", 281 [257][1] = "SDMA1", 282 [258][1] = "SDMA2", 283 [259][1] = "SDMA3", 284 [260][1] = "SDMA4", 285 [261][1] = "SDMA5", 286 [262][1] = "SDMA6", 287 [263][1] = "SDMA7", 288 [384][1] = "OSS", 289 }; 290 291 static const char *mmhub_client_ids_aldebaran[][2] = { 292 [2][0] = "MP1", 293 [3][0] = "MP0", 294 [32+1][0] = "DBGU_IO0", 295 [32+2][0] = "DBGU_IO2", 296 [32+4][0] = "MPIO", 297 [96+11][0] = "JPEG0", 298 [96+12][0] = "VCN0", 299 [96+13][0] = "VCNU0", 300 [128+11][0] = "JPEG1", 301 [128+12][0] = "VCN1", 302 [128+13][0] = "VCNU1", 303 [160+1][0] = "XDP", 304 [160+14][0] = "HDP", 305 [256+0][0] = "SDMA0", 306 [256+1][0] = "SDMA1", 307 [256+2][0] = "SDMA2", 308 [256+3][0] = "SDMA3", 309 [256+4][0] = "SDMA4", 310 [384+0][0] = "OSS", 311 [2][1] = "MP1", 312 [3][1] = "MP0", 313 [32+1][1] = "DBGU_IO0", 314 [32+2][1] = "DBGU_IO2", 315 [32+4][1] = "MPIO", 316 [96+11][1] = "JPEG0", 317 [96+12][1] = "VCN0", 318 [96+13][1] = "VCNU0", 319 [128+11][1] = "JPEG1", 320 [128+12][1] = "VCN1", 321 [128+13][1] = "VCNU1", 322 [160+1][1] = "XDP", 323 [160+14][1] = "HDP", 324 [256+0][1] = "SDMA0", 325 [256+1][1] = "SDMA1", 326 [256+2][1] = "SDMA2", 327 [256+3][1] = "SDMA3", 328 [256+4][1] = "SDMA4", 329 [384+0][1] = "OSS", 330 }; 331 332 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = 333 { 334 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), 335 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) 336 }; 337 338 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = 339 { 340 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), 341 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) 342 }; 343 344 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { 345 (0x000143c0 + 0x00000000), 346 (0x000143c0 + 0x00000800), 347 (0x000143c0 + 0x00001000), 348 (0x000143c0 + 0x00001800), 349 (0x000543c0 + 0x00000000), 350 (0x000543c0 + 0x00000800), 351 (0x000543c0 + 0x00001000), 352 (0x000543c0 + 0x00001800), 353 (0x000943c0 + 0x00000000), 354 (0x000943c0 + 0x00000800), 355 (0x000943c0 + 0x00001000), 356 (0x000943c0 + 0x00001800), 357 (0x000d43c0 + 0x00000000), 358 (0x000d43c0 + 0x00000800), 359 (0x000d43c0 + 0x00001000), 360 (0x000d43c0 + 0x00001800), 361 (0x001143c0 + 0x00000000), 362 (0x001143c0 + 0x00000800), 363 (0x001143c0 + 0x00001000), 364 (0x001143c0 + 0x00001800), 365 (0x001543c0 + 0x00000000), 366 (0x001543c0 + 0x00000800), 367 (0x001543c0 + 0x00001000), 368 (0x001543c0 + 0x00001800), 369 (0x001943c0 + 0x00000000), 370 (0x001943c0 + 0x00000800), 371 (0x001943c0 + 0x00001000), 372 (0x001943c0 + 0x00001800), 373 (0x001d43c0 + 0x00000000), 374 (0x001d43c0 + 0x00000800), 375 (0x001d43c0 + 0x00001000), 376 (0x001d43c0 + 0x00001800), 377 }; 378 379 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { 380 (0x000143e0 + 0x00000000), 381 (0x000143e0 + 0x00000800), 382 (0x000143e0 + 0x00001000), 383 (0x000143e0 + 0x00001800), 384 (0x000543e0 + 0x00000000), 385 (0x000543e0 + 0x00000800), 386 (0x000543e0 + 0x00001000), 387 (0x000543e0 + 0x00001800), 388 (0x000943e0 + 0x00000000), 389 (0x000943e0 + 0x00000800), 390 (0x000943e0 + 0x00001000), 391 (0x000943e0 + 0x00001800), 392 (0x000d43e0 + 0x00000000), 393 (0x000d43e0 + 0x00000800), 394 (0x000d43e0 + 0x00001000), 395 (0x000d43e0 + 0x00001800), 396 (0x001143e0 + 0x00000000), 397 (0x001143e0 + 0x00000800), 398 (0x001143e0 + 0x00001000), 399 (0x001143e0 + 0x00001800), 400 (0x001543e0 + 0x00000000), 401 (0x001543e0 + 0x00000800), 402 (0x001543e0 + 0x00001000), 403 (0x001543e0 + 0x00001800), 404 (0x001943e0 + 0x00000000), 405 (0x001943e0 + 0x00000800), 406 (0x001943e0 + 0x00001000), 407 (0x001943e0 + 0x00001800), 408 (0x001d43e0 + 0x00000000), 409 (0x001d43e0 + 0x00000800), 410 (0x001d43e0 + 0x00001000), 411 (0x001d43e0 + 0x00001800), 412 }; 413 414 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, 415 struct amdgpu_irq_src *src, 416 unsigned type, 417 enum amdgpu_interrupt_state state) 418 { 419 u32 bits, i, tmp, reg; 420 421 /* Devices newer then VEGA10/12 shall have these programming 422 sequences performed by PSP BL */ 423 if (adev->asic_type >= CHIP_VEGA20) 424 return 0; 425 426 bits = 0x7f; 427 428 switch (state) { 429 case AMDGPU_IRQ_STATE_DISABLE: 430 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 431 reg = ecc_umc_mcumc_ctrl_addrs[i]; 432 tmp = RREG32(reg); 433 tmp &= ~bits; 434 WREG32(reg, tmp); 435 } 436 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 437 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 438 tmp = RREG32(reg); 439 tmp &= ~bits; 440 WREG32(reg, tmp); 441 } 442 break; 443 case AMDGPU_IRQ_STATE_ENABLE: 444 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 445 reg = ecc_umc_mcumc_ctrl_addrs[i]; 446 tmp = RREG32(reg); 447 tmp |= bits; 448 WREG32(reg, tmp); 449 } 450 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 451 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 452 tmp = RREG32(reg); 453 tmp |= bits; 454 WREG32(reg, tmp); 455 } 456 break; 457 default: 458 break; 459 } 460 461 return 0; 462 } 463 464 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 465 struct amdgpu_irq_src *src, 466 unsigned type, 467 enum amdgpu_interrupt_state state) 468 { 469 struct amdgpu_vmhub *hub; 470 u32 tmp, reg, bits, i, j; 471 472 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 473 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 474 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 475 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 476 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 477 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 478 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 479 480 switch (state) { 481 case AMDGPU_IRQ_STATE_DISABLE: 482 for (j = 0; j < adev->num_vmhubs; j++) { 483 hub = &adev->vmhub[j]; 484 for (i = 0; i < 16; i++) { 485 reg = hub->vm_context0_cntl + i; 486 487 /* This works because this interrupt is only 488 * enabled at init/resume and disabled in 489 * fini/suspend, so the overall state doesn't 490 * change over the course of suspend/resume. 491 */ 492 if (adev->in_s0ix && (j == AMDGPU_GFXHUB_0)) 493 continue; 494 495 if (j == AMDGPU_GFXHUB_0) 496 tmp = RREG32_SOC15_IP(GC, reg); 497 else 498 tmp = RREG32_SOC15_IP(MMHUB, reg); 499 500 tmp &= ~bits; 501 502 if (j == AMDGPU_GFXHUB_0) 503 WREG32_SOC15_IP(GC, reg, tmp); 504 else 505 WREG32_SOC15_IP(MMHUB, reg, tmp); 506 } 507 } 508 break; 509 case AMDGPU_IRQ_STATE_ENABLE: 510 for (j = 0; j < adev->num_vmhubs; j++) { 511 hub = &adev->vmhub[j]; 512 for (i = 0; i < 16; i++) { 513 reg = hub->vm_context0_cntl + i; 514 515 /* This works because this interrupt is only 516 * enabled at init/resume and disabled in 517 * fini/suspend, so the overall state doesn't 518 * change over the course of suspend/resume. 519 */ 520 if (adev->in_s0ix && (j == AMDGPU_GFXHUB_0)) 521 continue; 522 523 if (j == AMDGPU_GFXHUB_0) 524 tmp = RREG32_SOC15_IP(GC, reg); 525 else 526 tmp = RREG32_SOC15_IP(MMHUB, reg); 527 528 tmp |= bits; 529 530 if (j == AMDGPU_GFXHUB_0) 531 WREG32_SOC15_IP(GC, reg, tmp); 532 else 533 WREG32_SOC15_IP(MMHUB, reg, tmp); 534 } 535 } 536 break; 537 default: 538 break; 539 } 540 541 return 0; 542 } 543 544 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 545 struct amdgpu_irq_src *source, 546 struct amdgpu_iv_entry *entry) 547 { 548 bool retry_fault = !!(entry->src_data[1] & 0x80); 549 bool write_fault = !!(entry->src_data[1] & 0x20); 550 uint32_t status = 0, cid = 0, rw = 0; 551 struct amdgpu_task_info task_info; 552 struct amdgpu_vmhub *hub; 553 const char *mmhub_cid; 554 const char *hub_name; 555 u64 addr; 556 557 addr = (u64)entry->src_data[0] << 12; 558 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 559 560 if (retry_fault) { 561 /* Returning 1 here also prevents sending the IV to the KFD */ 562 563 /* Process it onyl if it's the first fault for this address */ 564 if (entry->ih != &adev->irq.ih_soft && 565 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, 566 entry->timestamp)) 567 return 1; 568 569 /* Delegate it to a different ring if the hardware hasn't 570 * already done it. 571 */ 572 if (entry->ih == &adev->irq.ih) { 573 amdgpu_irq_delegate(adev, entry, 8); 574 return 1; 575 } 576 577 /* Try to handle the recoverable page faults by filling page 578 * tables 579 */ 580 if (amdgpu_vm_handle_fault(adev, entry->pasid, addr, write_fault)) 581 return 1; 582 } 583 584 if (!printk_ratelimit()) 585 return 0; 586 587 if (entry->client_id == SOC15_IH_CLIENTID_VMC) { 588 hub_name = "mmhub0"; 589 hub = &adev->vmhub[AMDGPU_MMHUB_0]; 590 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) { 591 hub_name = "mmhub1"; 592 hub = &adev->vmhub[AMDGPU_MMHUB_1]; 593 } else { 594 hub_name = "gfxhub0"; 595 hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 596 } 597 598 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 599 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 600 601 dev_err(adev->dev, 602 "[%s] %s page fault (src_id:%u ring:%u vmid:%u " 603 "pasid:%u, for process %s pid %d thread %s pid %d)\n", 604 hub_name, retry_fault ? "retry" : "no-retry", 605 entry->src_id, entry->ring_id, entry->vmid, 606 entry->pasid, task_info.process_name, task_info.tgid, 607 task_info.task_name, task_info.pid); 608 dev_err(adev->dev, " in page starting at address 0x%016llx from IH client 0x%x (%s)\n", 609 addr, entry->client_id, 610 soc15_ih_clientid_name[entry->client_id]); 611 612 if (amdgpu_sriov_vf(adev)) 613 return 0; 614 615 /* 616 * Issue a dummy read to wait for the status register to 617 * be updated to avoid reading an incorrect value due to 618 * the new fast GRBM interface. 619 */ 620 if ((entry->vmid_src == AMDGPU_GFXHUB_0) && 621 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2))) 622 RREG32(hub->vm_l2_pro_fault_status); 623 624 status = RREG32(hub->vm_l2_pro_fault_status); 625 cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID); 626 rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW); 627 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 628 629 630 dev_err(adev->dev, 631 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 632 status); 633 if (hub == &adev->vmhub[AMDGPU_GFXHUB_0]) { 634 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 635 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : 636 gfxhub_client_ids[cid], 637 cid); 638 } else { 639 switch (adev->ip_versions[MMHUB_HWIP][0]) { 640 case IP_VERSION(9, 0, 0): 641 mmhub_cid = mmhub_client_ids_vega10[cid][rw]; 642 break; 643 case IP_VERSION(9, 3, 0): 644 mmhub_cid = mmhub_client_ids_vega12[cid][rw]; 645 break; 646 case IP_VERSION(9, 4, 0): 647 mmhub_cid = mmhub_client_ids_vega20[cid][rw]; 648 break; 649 case IP_VERSION(9, 4, 1): 650 mmhub_cid = mmhub_client_ids_arcturus[cid][rw]; 651 break; 652 case IP_VERSION(9, 1, 0): 653 case IP_VERSION(9, 2, 0): 654 mmhub_cid = mmhub_client_ids_raven[cid][rw]; 655 break; 656 case IP_VERSION(1, 5, 0): 657 case IP_VERSION(2, 4, 0): 658 mmhub_cid = mmhub_client_ids_renoir[cid][rw]; 659 break; 660 case IP_VERSION(1, 8, 0): 661 case IP_VERSION(9, 4, 2): 662 mmhub_cid = mmhub_client_ids_aldebaran[cid][rw]; 663 break; 664 default: 665 mmhub_cid = NULL; 666 break; 667 } 668 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 669 mmhub_cid ? mmhub_cid : "unknown", cid); 670 } 671 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 672 REG_GET_FIELD(status, 673 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 674 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 675 REG_GET_FIELD(status, 676 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 677 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 678 REG_GET_FIELD(status, 679 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 680 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 681 REG_GET_FIELD(status, 682 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 683 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 684 return 0; 685 } 686 687 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 688 .set = gmc_v9_0_vm_fault_interrupt_state, 689 .process = gmc_v9_0_process_interrupt, 690 }; 691 692 693 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { 694 .set = gmc_v9_0_ecc_interrupt_state, 695 .process = amdgpu_umc_process_ecc_irq, 696 }; 697 698 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 699 { 700 adev->gmc.vm_fault.num_types = 1; 701 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 702 703 if (!amdgpu_sriov_vf(adev) && 704 !adev->gmc.xgmi.connected_to_cpu) { 705 adev->gmc.ecc_irq.num_types = 1; 706 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; 707 } 708 } 709 710 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, 711 uint32_t flush_type) 712 { 713 u32 req = 0; 714 715 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 716 PER_VMID_INVALIDATE_REQ, 1 << vmid); 717 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 718 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 719 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 720 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 721 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 722 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 723 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 724 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 725 726 return req; 727 } 728 729 /** 730 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore 731 * 732 * @adev: amdgpu_device pointer 733 * @vmhub: vmhub type 734 * 735 */ 736 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev, 737 uint32_t vmhub) 738 { 739 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) || 740 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) 741 return false; 742 743 return ((vmhub == AMDGPU_MMHUB_0 || 744 vmhub == AMDGPU_MMHUB_1) && 745 (!amdgpu_sriov_vf(adev)) && 746 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) && 747 (adev->apu_flags & AMD_APU_IS_PICASSO)))); 748 } 749 750 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, 751 uint8_t vmid, uint16_t *p_pasid) 752 { 753 uint32_t value; 754 755 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 756 + vmid); 757 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 758 759 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 760 } 761 762 /* 763 * GART 764 * VMID 0 is the physical GPU addresses as used by the kernel. 765 * VMIDs 1-15 are used for userspace clients and are handled 766 * by the amdgpu vm/hsa code. 767 */ 768 769 /** 770 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type 771 * 772 * @adev: amdgpu_device pointer 773 * @vmid: vm instance to flush 774 * @vmhub: which hub to flush 775 * @flush_type: the flush type 776 * 777 * Flush the TLB for the requested page table using certain type. 778 */ 779 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 780 uint32_t vmhub, uint32_t flush_type) 781 { 782 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub); 783 const unsigned eng = 17; 784 u32 j, inv_req, inv_req2, tmp; 785 struct amdgpu_vmhub *hub; 786 787 BUG_ON(vmhub >= adev->num_vmhubs); 788 789 hub = &adev->vmhub[vmhub]; 790 if (adev->gmc.xgmi.num_physical_nodes && 791 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0)) { 792 /* Vega20+XGMI caches PTEs in TC and TLB. Add a 793 * heavy-weight TLB flush (type 2), which flushes 794 * both. Due to a race condition with concurrent 795 * memory accesses using the same TLB cache line, we 796 * still need a second TLB flush after this. 797 */ 798 inv_req = gmc_v9_0_get_invalidate_req(vmid, 2); 799 inv_req2 = gmc_v9_0_get_invalidate_req(vmid, flush_type); 800 } else { 801 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type); 802 inv_req2 = 0; 803 } 804 805 /* This is necessary for a HW workaround under SRIOV as well 806 * as GFXOFF under bare metal 807 */ 808 if (adev->gfx.kiq.ring.sched.ready && 809 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && 810 down_read_trylock(&adev->reset_domain->sem)) { 811 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 812 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 813 814 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 815 1 << vmid); 816 up_read(&adev->reset_domain->sem); 817 return; 818 } 819 820 spin_lock(&adev->gmc.invalidate_lock); 821 822 /* 823 * It may lose gpuvm invalidate acknowldege state across power-gating 824 * off cycle, add semaphore acquire before invalidation and semaphore 825 * release after invalidation to avoid entering power gated state 826 * to WA the Issue 827 */ 828 829 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 830 if (use_semaphore) { 831 for (j = 0; j < adev->usec_timeout; j++) { 832 /* a read return value of 1 means semaphore acquire */ 833 if (vmhub == AMDGPU_GFXHUB_0) 834 tmp = RREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_sem + hub->eng_distance * eng); 835 else 836 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_sem + hub->eng_distance * eng); 837 838 if (tmp & 0x1) 839 break; 840 udelay(1); 841 } 842 843 if (j >= adev->usec_timeout) 844 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 845 } 846 847 do { 848 if (vmhub == AMDGPU_GFXHUB_0) 849 WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req); 850 else 851 WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req); 852 853 /* 854 * Issue a dummy read to wait for the ACK register to 855 * be cleared to avoid a false ACK due to the new fast 856 * GRBM interface. 857 */ 858 if ((vmhub == AMDGPU_GFXHUB_0) && 859 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2))) 860 RREG32_NO_KIQ(hub->vm_inv_eng0_req + 861 hub->eng_distance * eng); 862 863 for (j = 0; j < adev->usec_timeout; j++) { 864 if (vmhub == AMDGPU_GFXHUB_0) 865 tmp = RREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_ack + hub->eng_distance * eng); 866 else 867 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_ack + hub->eng_distance * eng); 868 869 if (tmp & (1 << vmid)) 870 break; 871 udelay(1); 872 } 873 874 inv_req = inv_req2; 875 inv_req2 = 0; 876 } while (inv_req); 877 878 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 879 if (use_semaphore) { 880 /* 881 * add semaphore release after invalidation, 882 * write with 0 means semaphore release 883 */ 884 if (vmhub == AMDGPU_GFXHUB_0) 885 WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_sem + hub->eng_distance * eng, 0); 886 else 887 WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_sem + hub->eng_distance * eng, 0); 888 } 889 890 spin_unlock(&adev->gmc.invalidate_lock); 891 892 if (j < adev->usec_timeout) 893 return; 894 895 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 896 } 897 898 /** 899 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid 900 * 901 * @adev: amdgpu_device pointer 902 * @pasid: pasid to be flush 903 * @flush_type: the flush type 904 * @all_hub: flush all hubs 905 * 906 * Flush the TLB for the requested pasid. 907 */ 908 static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 909 uint16_t pasid, uint32_t flush_type, 910 bool all_hub) 911 { 912 int vmid, i; 913 signed long r; 914 uint32_t seq; 915 uint16_t queried_pasid; 916 bool ret; 917 u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT : adev->usec_timeout; 918 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 919 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 920 921 if (amdgpu_in_reset(adev)) 922 return -EIO; 923 924 if (ring->sched.ready && down_read_trylock(&adev->reset_domain->sem)) { 925 /* Vega20+XGMI caches PTEs in TC and TLB. Add a 926 * heavy-weight TLB flush (type 2), which flushes 927 * both. Due to a race condition with concurrent 928 * memory accesses using the same TLB cache line, we 929 * still need a second TLB flush after this. 930 */ 931 bool vega20_xgmi_wa = (adev->gmc.xgmi.num_physical_nodes && 932 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0)); 933 /* 2 dwords flush + 8 dwords fence */ 934 unsigned int ndw = kiq->pmf->invalidate_tlbs_size + 8; 935 936 if (vega20_xgmi_wa) 937 ndw += kiq->pmf->invalidate_tlbs_size; 938 939 spin_lock(&adev->gfx.kiq.ring_lock); 940 /* 2 dwords flush + 8 dwords fence */ 941 amdgpu_ring_alloc(ring, ndw); 942 if (vega20_xgmi_wa) 943 kiq->pmf->kiq_invalidate_tlbs(ring, 944 pasid, 2, all_hub); 945 kiq->pmf->kiq_invalidate_tlbs(ring, 946 pasid, flush_type, all_hub); 947 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 948 if (r) { 949 amdgpu_ring_undo(ring); 950 spin_unlock(&adev->gfx.kiq.ring_lock); 951 up_read(&adev->reset_domain->sem); 952 return -ETIME; 953 } 954 955 amdgpu_ring_commit(ring); 956 spin_unlock(&adev->gfx.kiq.ring_lock); 957 r = amdgpu_fence_wait_polling(ring, seq, usec_timeout); 958 if (r < 1) { 959 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r); 960 up_read(&adev->reset_domain->sem); 961 return -ETIME; 962 } 963 up_read(&adev->reset_domain->sem); 964 return 0; 965 } 966 967 for (vmid = 1; vmid < 16; vmid++) { 968 969 ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 970 &queried_pasid); 971 if (ret && queried_pasid == pasid) { 972 if (all_hub) { 973 for (i = 0; i < adev->num_vmhubs; i++) 974 gmc_v9_0_flush_gpu_tlb(adev, vmid, 975 i, flush_type); 976 } else { 977 gmc_v9_0_flush_gpu_tlb(adev, vmid, 978 AMDGPU_GFXHUB_0, flush_type); 979 } 980 break; 981 } 982 } 983 984 return 0; 985 986 } 987 988 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 989 unsigned vmid, uint64_t pd_addr) 990 { 991 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub); 992 struct amdgpu_device *adev = ring->adev; 993 struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub]; 994 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); 995 unsigned eng = ring->vm_inv_eng; 996 997 /* 998 * It may lose gpuvm invalidate acknowldege state across power-gating 999 * off cycle, add semaphore acquire before invalidation and semaphore 1000 * release after invalidation to avoid entering power gated state 1001 * to WA the Issue 1002 */ 1003 1004 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 1005 if (use_semaphore) 1006 /* a read return value of 1 means semaphore acuqire */ 1007 amdgpu_ring_emit_reg_wait(ring, 1008 hub->vm_inv_eng0_sem + 1009 hub->eng_distance * eng, 0x1, 0x1); 1010 1011 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 1012 (hub->ctx_addr_distance * vmid), 1013 lower_32_bits(pd_addr)); 1014 1015 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 1016 (hub->ctx_addr_distance * vmid), 1017 upper_32_bits(pd_addr)); 1018 1019 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 1020 hub->eng_distance * eng, 1021 hub->vm_inv_eng0_ack + 1022 hub->eng_distance * eng, 1023 req, 1 << vmid); 1024 1025 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 1026 if (use_semaphore) 1027 /* 1028 * add semaphore release after invalidation, 1029 * write with 0 means semaphore release 1030 */ 1031 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 1032 hub->eng_distance * eng, 0); 1033 1034 return pd_addr; 1035 } 1036 1037 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 1038 unsigned pasid) 1039 { 1040 struct amdgpu_device *adev = ring->adev; 1041 uint32_t reg; 1042 1043 /* Do nothing because there's no lut register for mmhub1. */ 1044 if (ring->funcs->vmhub == AMDGPU_MMHUB_1) 1045 return; 1046 1047 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) 1048 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 1049 else 1050 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 1051 1052 amdgpu_ring_emit_wreg(ring, reg, pasid); 1053 } 1054 1055 /* 1056 * PTE format on VEGA 10: 1057 * 63:59 reserved 1058 * 58:57 mtype 1059 * 56 F 1060 * 55 L 1061 * 54 P 1062 * 53 SW 1063 * 52 T 1064 * 50:48 reserved 1065 * 47:12 4k physical page base address 1066 * 11:7 fragment 1067 * 6 write 1068 * 5 read 1069 * 4 exe 1070 * 3 Z 1071 * 2 snooped 1072 * 1 system 1073 * 0 valid 1074 * 1075 * PDE format on VEGA 10: 1076 * 63:59 block fragment size 1077 * 58:55 reserved 1078 * 54 P 1079 * 53:48 reserved 1080 * 47:6 physical base address of PD or PTE 1081 * 5:3 reserved 1082 * 2 C 1083 * 1 system 1084 * 0 valid 1085 */ 1086 1087 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 1088 1089 { 1090 switch (flags) { 1091 case AMDGPU_VM_MTYPE_DEFAULT: 1092 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1093 case AMDGPU_VM_MTYPE_NC: 1094 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1095 case AMDGPU_VM_MTYPE_WC: 1096 return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC); 1097 case AMDGPU_VM_MTYPE_RW: 1098 return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW); 1099 case AMDGPU_VM_MTYPE_CC: 1100 return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC); 1101 case AMDGPU_VM_MTYPE_UC: 1102 return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC); 1103 default: 1104 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1105 } 1106 } 1107 1108 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, 1109 uint64_t *addr, uint64_t *flags) 1110 { 1111 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 1112 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 1113 BUG_ON(*addr & 0xFFFF00000000003FULL); 1114 1115 if (!adev->gmc.translate_further) 1116 return; 1117 1118 if (level == AMDGPU_VM_PDB1) { 1119 /* Set the block fragment size */ 1120 if (!(*flags & AMDGPU_PDE_PTE)) 1121 *flags |= AMDGPU_PDE_BFS(0x9); 1122 1123 } else if (level == AMDGPU_VM_PDB0) { 1124 if (*flags & AMDGPU_PDE_PTE) { 1125 *flags &= ~AMDGPU_PDE_PTE; 1126 if (!(*flags & AMDGPU_PTE_VALID)) 1127 *addr |= 1 << PAGE_SHIFT; 1128 } else { 1129 *flags |= AMDGPU_PTE_TF; 1130 } 1131 } 1132 } 1133 1134 static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev, 1135 struct amdgpu_bo *bo, 1136 struct amdgpu_bo_va_mapping *mapping, 1137 uint64_t *flags) 1138 { 1139 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev); 1140 bool is_vram = bo->tbo.resource->mem_type == TTM_PL_VRAM; 1141 bool coherent = bo->flags & AMDGPU_GEM_CREATE_COHERENT; 1142 bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED; 1143 unsigned int mtype; 1144 bool snoop = false; 1145 1146 switch (adev->ip_versions[GC_HWIP][0]) { 1147 case IP_VERSION(9, 4, 1): 1148 case IP_VERSION(9, 4, 2): 1149 case IP_VERSION(9, 4, 3): 1150 if (is_vram) { 1151 if (bo_adev == adev) { 1152 if (uncached) 1153 mtype = MTYPE_UC; 1154 else if (coherent) 1155 mtype = MTYPE_CC; 1156 else 1157 mtype = MTYPE_RW; 1158 /* FIXME: is this still needed? Or does 1159 * amdgpu_ttm_tt_pde_flags already handle this? 1160 */ 1161 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) || 1162 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) && 1163 adev->gmc.xgmi.connected_to_cpu) 1164 snoop = true; 1165 } else { 1166 if (uncached || coherent) 1167 mtype = MTYPE_UC; 1168 else 1169 mtype = MTYPE_NC; 1170 if (mapping->bo_va->is_xgmi) 1171 snoop = true; 1172 } 1173 } else { 1174 if (uncached || coherent) 1175 mtype = MTYPE_UC; 1176 else 1177 mtype = MTYPE_NC; 1178 /* FIXME: is this still needed? Or does 1179 * amdgpu_ttm_tt_pde_flags already handle this? 1180 */ 1181 snoop = true; 1182 } 1183 break; 1184 default: 1185 if (uncached || coherent) 1186 mtype = MTYPE_UC; 1187 else 1188 mtype = MTYPE_NC; 1189 1190 /* FIXME: is this still needed? Or does 1191 * amdgpu_ttm_tt_pde_flags already handle this? 1192 */ 1193 if (!is_vram) 1194 snoop = true; 1195 } 1196 1197 if (mtype != MTYPE_NC) 1198 *flags = (*flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) | 1199 AMDGPU_PTE_MTYPE_VG10(mtype); 1200 *flags |= snoop ? AMDGPU_PTE_SNOOPED : 0; 1201 } 1202 1203 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev, 1204 struct amdgpu_bo_va_mapping *mapping, 1205 uint64_t *flags) 1206 { 1207 struct amdgpu_bo *bo = mapping->bo_va->base.bo; 1208 1209 *flags &= ~AMDGPU_PTE_EXECUTABLE; 1210 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 1211 1212 *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 1213 *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK; 1214 1215 if (mapping->flags & AMDGPU_PTE_PRT) { 1216 *flags |= AMDGPU_PTE_PRT; 1217 *flags &= ~AMDGPU_PTE_VALID; 1218 } 1219 1220 if (bo && bo->tbo.resource) 1221 gmc_v9_0_get_coherence_flags(adev, mapping->bo_va->base.bo, 1222 mapping, flags); 1223 } 1224 1225 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 1226 { 1227 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 1228 unsigned size; 1229 1230 /* TODO move to DC so GMC doesn't need to hard-code DCN registers */ 1231 1232 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1233 size = AMDGPU_VBIOS_VGA_ALLOCATION; 1234 } else { 1235 u32 viewport; 1236 1237 switch (adev->ip_versions[DCE_HWIP][0]) { 1238 case IP_VERSION(1, 0, 0): 1239 case IP_VERSION(1, 0, 1): 1240 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 1241 size = (REG_GET_FIELD(viewport, 1242 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1243 REG_GET_FIELD(viewport, 1244 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1245 4); 1246 break; 1247 case IP_VERSION(2, 1, 0): 1248 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2); 1249 size = (REG_GET_FIELD(viewport, 1250 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1251 REG_GET_FIELD(viewport, 1252 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1253 4); 1254 break; 1255 default: 1256 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); 1257 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1258 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1259 4); 1260 break; 1261 } 1262 } 1263 1264 return size; 1265 } 1266 1267 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { 1268 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, 1269 .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid, 1270 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, 1271 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, 1272 .map_mtype = gmc_v9_0_map_mtype, 1273 .get_vm_pde = gmc_v9_0_get_vm_pde, 1274 .get_vm_pte = gmc_v9_0_get_vm_pte, 1275 .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size, 1276 }; 1277 1278 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) 1279 { 1280 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; 1281 } 1282 1283 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) 1284 { 1285 switch (adev->ip_versions[UMC_HWIP][0]) { 1286 case IP_VERSION(6, 0, 0): 1287 adev->umc.funcs = &umc_v6_0_funcs; 1288 break; 1289 case IP_VERSION(6, 1, 1): 1290 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1291 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1292 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1293 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20; 1294 adev->umc.retire_unit = 1; 1295 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1296 adev->umc.ras = &umc_v6_1_ras; 1297 break; 1298 case IP_VERSION(6, 1, 2): 1299 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1300 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1301 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1302 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT; 1303 adev->umc.retire_unit = 1; 1304 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1305 adev->umc.ras = &umc_v6_1_ras; 1306 break; 1307 case IP_VERSION(6, 7, 0): 1308 adev->umc.max_ras_err_cnt_per_query = 1309 UMC_V6_7_TOTAL_CHANNEL_NUM * UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL; 1310 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM; 1311 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM; 1312 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET; 1313 adev->umc.retire_unit = (UMC_V6_7_NA_MAP_PA_NUM * 2); 1314 if (!adev->gmc.xgmi.connected_to_cpu) 1315 adev->umc.ras = &umc_v6_7_ras; 1316 if (1 & adev->smuio.funcs->get_die_id(adev)) 1317 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0]; 1318 else 1319 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0]; 1320 break; 1321 default: 1322 break; 1323 } 1324 } 1325 1326 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) 1327 { 1328 switch (adev->ip_versions[MMHUB_HWIP][0]) { 1329 case IP_VERSION(9, 4, 1): 1330 adev->mmhub.funcs = &mmhub_v9_4_funcs; 1331 break; 1332 case IP_VERSION(9, 4, 2): 1333 adev->mmhub.funcs = &mmhub_v1_7_funcs; 1334 break; 1335 default: 1336 adev->mmhub.funcs = &mmhub_v1_0_funcs; 1337 break; 1338 } 1339 } 1340 1341 static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev) 1342 { 1343 switch (adev->ip_versions[MMHUB_HWIP][0]) { 1344 case IP_VERSION(9, 4, 0): 1345 adev->mmhub.ras = &mmhub_v1_0_ras; 1346 break; 1347 case IP_VERSION(9, 4, 1): 1348 adev->mmhub.ras = &mmhub_v9_4_ras; 1349 break; 1350 case IP_VERSION(9, 4, 2): 1351 adev->mmhub.ras = &mmhub_v1_7_ras; 1352 break; 1353 default: 1354 /* mmhub ras is not available */ 1355 break; 1356 } 1357 } 1358 1359 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev) 1360 { 1361 adev->gfxhub.funcs = &gfxhub_v1_0_funcs; 1362 } 1363 1364 static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev) 1365 { 1366 adev->hdp.ras = &hdp_v4_0_ras; 1367 } 1368 1369 static void gmc_v9_0_set_mca_ras_funcs(struct amdgpu_device *adev) 1370 { 1371 struct amdgpu_mca *mca = &adev->mca; 1372 1373 /* is UMC the right IP to check for MCA? Maybe DF? */ 1374 switch (adev->ip_versions[UMC_HWIP][0]) { 1375 case IP_VERSION(6, 7, 0): 1376 if (!adev->gmc.xgmi.connected_to_cpu) { 1377 mca->mp0.ras = &mca_v3_0_mp0_ras; 1378 mca->mp1.ras = &mca_v3_0_mp1_ras; 1379 mca->mpio.ras = &mca_v3_0_mpio_ras; 1380 } 1381 break; 1382 default: 1383 break; 1384 } 1385 } 1386 1387 static void gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device *adev) 1388 { 1389 if (!adev->gmc.xgmi.connected_to_cpu) 1390 adev->gmc.xgmi.ras = &xgmi_ras; 1391 } 1392 1393 static int gmc_v9_0_early_init(void *handle) 1394 { 1395 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1396 1397 /* ARCT and VEGA20 don't have XGMI defined in their IP discovery tables */ 1398 if (adev->asic_type == CHIP_VEGA20 || 1399 adev->asic_type == CHIP_ARCTURUS) 1400 adev->gmc.xgmi.supported = true; 1401 1402 if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(6, 1, 0)) { 1403 adev->gmc.xgmi.supported = true; 1404 adev->gmc.xgmi.connected_to_cpu = 1405 adev->smuio.funcs->is_host_gpu_xgmi_supported(adev); 1406 } 1407 1408 gmc_v9_0_set_gmc_funcs(adev); 1409 gmc_v9_0_set_irq_funcs(adev); 1410 gmc_v9_0_set_umc_funcs(adev); 1411 gmc_v9_0_set_mmhub_funcs(adev); 1412 gmc_v9_0_set_mmhub_ras_funcs(adev); 1413 gmc_v9_0_set_gfxhub_funcs(adev); 1414 gmc_v9_0_set_hdp_ras_funcs(adev); 1415 gmc_v9_0_set_mca_ras_funcs(adev); 1416 gmc_v9_0_set_xgmi_ras_funcs(adev); 1417 1418 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1419 adev->gmc.shared_aperture_end = 1420 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1421 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 1422 adev->gmc.private_aperture_end = 1423 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1424 1425 return 0; 1426 } 1427 1428 static int gmc_v9_0_late_init(void *handle) 1429 { 1430 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1431 int r; 1432 1433 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 1434 if (r) 1435 return r; 1436 1437 /* 1438 * Workaround performance drop issue with VBIOS enables partial 1439 * writes, while disables HBM ECC for vega10. 1440 */ 1441 if (!amdgpu_sriov_vf(adev) && 1442 (adev->ip_versions[UMC_HWIP][0] == IP_VERSION(6, 0, 0))) { 1443 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) { 1444 if (adev->df.funcs && 1445 adev->df.funcs->enable_ecc_force_par_wr_rmw) 1446 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false); 1447 } 1448 } 1449 1450 if (!amdgpu_persistent_edc_harvesting_supported(adev)) { 1451 if (adev->mmhub.ras && adev->mmhub.ras->ras_block.hw_ops && 1452 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count) 1453 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(adev); 1454 1455 if (adev->hdp.ras && adev->hdp.ras->ras_block.hw_ops && 1456 adev->hdp.ras->ras_block.hw_ops->reset_ras_error_count) 1457 adev->hdp.ras->ras_block.hw_ops->reset_ras_error_count(adev); 1458 } 1459 1460 r = amdgpu_gmc_ras_late_init(adev); 1461 if (r) 1462 return r; 1463 1464 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1465 } 1466 1467 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 1468 struct amdgpu_gmc *mc) 1469 { 1470 u64 base = adev->mmhub.funcs->get_fb_location(adev); 1471 1472 /* add the xgmi offset of the physical node */ 1473 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1474 if (adev->gmc.xgmi.connected_to_cpu) { 1475 amdgpu_gmc_sysvm_location(adev, mc); 1476 } else { 1477 amdgpu_gmc_vram_location(adev, mc, base); 1478 amdgpu_gmc_gart_location(adev, mc); 1479 amdgpu_gmc_agp_location(adev, mc); 1480 } 1481 /* base offset of vram pages */ 1482 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 1483 1484 /* XXX: add the xgmi offset of the physical node? */ 1485 adev->vm_manager.vram_base_offset += 1486 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1487 } 1488 1489 /** 1490 * gmc_v9_0_mc_init - initialize the memory controller driver params 1491 * 1492 * @adev: amdgpu_device pointer 1493 * 1494 * Look up the amount of vram, vram width, and decide how to place 1495 * vram and gart within the GPU's physical address space. 1496 * Returns 0 for success. 1497 */ 1498 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 1499 { 1500 int r; 1501 1502 /* size in MB on si */ 1503 adev->gmc.mc_vram_size = 1504 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 1505 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 1506 1507 if (!(adev->flags & AMD_IS_APU) && 1508 !adev->gmc.xgmi.connected_to_cpu) { 1509 r = amdgpu_device_resize_fb_bar(adev); 1510 if (r) 1511 return r; 1512 } 1513 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 1514 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 1515 1516 #ifdef CONFIG_X86_64 1517 /* 1518 * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi 1519 * interface can use VRAM through here as it appears system reserved 1520 * memory in host address space. 1521 * 1522 * For APUs, VRAM is just the stolen system memory and can be accessed 1523 * directly. 1524 * 1525 * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR. 1526 */ 1527 1528 /* check whether both host-gpu and gpu-gpu xgmi links exist */ 1529 if (((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) || 1530 (adev->gmc.xgmi.supported && 1531 adev->gmc.xgmi.connected_to_cpu)) { 1532 adev->gmc.aper_base = 1533 adev->gfxhub.funcs->get_mc_fb_offset(adev) + 1534 adev->gmc.xgmi.physical_node_id * 1535 adev->gmc.xgmi.node_segment_size; 1536 adev->gmc.aper_size = adev->gmc.real_vram_size; 1537 } 1538 1539 #endif 1540 adev->gmc.visible_vram_size = adev->gmc.aper_size; 1541 1542 /* set the gart size */ 1543 if (amdgpu_gart_size == -1) { 1544 switch (adev->ip_versions[GC_HWIP][0]) { 1545 case IP_VERSION(9, 0, 1): /* all engines support GPUVM */ 1546 case IP_VERSION(9, 2, 1): /* all engines support GPUVM */ 1547 case IP_VERSION(9, 4, 0): 1548 case IP_VERSION(9, 4, 1): 1549 case IP_VERSION(9, 4, 2): 1550 case IP_VERSION(9, 4, 3): 1551 default: 1552 adev->gmc.gart_size = 512ULL << 20; 1553 break; 1554 case IP_VERSION(9, 1, 0): /* DCE SG support */ 1555 case IP_VERSION(9, 2, 2): /* DCE SG support */ 1556 case IP_VERSION(9, 3, 0): 1557 adev->gmc.gart_size = 1024ULL << 20; 1558 break; 1559 } 1560 } else { 1561 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 1562 } 1563 1564 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; 1565 1566 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); 1567 1568 return 0; 1569 } 1570 1571 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 1572 { 1573 int r; 1574 1575 if (adev->gart.bo) { 1576 WARN(1, "VEGA10 PCIE GART already initialized\n"); 1577 return 0; 1578 } 1579 1580 if (adev->gmc.xgmi.connected_to_cpu) { 1581 adev->gmc.vmid0_page_table_depth = 1; 1582 adev->gmc.vmid0_page_table_block_size = 12; 1583 } else { 1584 adev->gmc.vmid0_page_table_depth = 0; 1585 adev->gmc.vmid0_page_table_block_size = 0; 1586 } 1587 1588 /* Initialize common gart structure */ 1589 r = amdgpu_gart_init(adev); 1590 if (r) 1591 return r; 1592 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 1593 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) | 1594 AMDGPU_PTE_EXECUTABLE; 1595 1596 r = amdgpu_gart_table_vram_alloc(adev); 1597 if (r) 1598 return r; 1599 1600 if (adev->gmc.xgmi.connected_to_cpu) { 1601 r = amdgpu_gmc_pdb0_alloc(adev); 1602 } 1603 1604 return r; 1605 } 1606 1607 /** 1608 * gmc_v9_0_save_registers - saves regs 1609 * 1610 * @adev: amdgpu_device pointer 1611 * 1612 * This saves potential register values that should be 1613 * restored upon resume 1614 */ 1615 static void gmc_v9_0_save_registers(struct amdgpu_device *adev) 1616 { 1617 if ((adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 0)) || 1618 (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 1))) 1619 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); 1620 } 1621 1622 static int gmc_v9_0_sw_init(void *handle) 1623 { 1624 int r, vram_width = 0, vram_type = 0, vram_vendor = 0, dma_addr_bits; 1625 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1626 1627 adev->gfxhub.funcs->init(adev); 1628 1629 adev->mmhub.funcs->init(adev); 1630 1631 spin_lock_init(&adev->gmc.invalidate_lock); 1632 1633 r = amdgpu_atomfirmware_get_vram_info(adev, 1634 &vram_width, &vram_type, &vram_vendor); 1635 if (amdgpu_sriov_vf(adev)) 1636 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, 1637 * and DF related registers is not readable, seems hardcord is the 1638 * only way to set the correct vram_width 1639 */ 1640 adev->gmc.vram_width = 2048; 1641 else if (amdgpu_emu_mode != 1) 1642 adev->gmc.vram_width = vram_width; 1643 1644 if (!adev->gmc.vram_width) { 1645 int chansize, numchan; 1646 1647 /* hbm memory channel size */ 1648 if (adev->flags & AMD_IS_APU) 1649 chansize = 64; 1650 else 1651 chansize = 128; 1652 if (adev->df.funcs && 1653 adev->df.funcs->get_hbm_channel_number) { 1654 numchan = adev->df.funcs->get_hbm_channel_number(adev); 1655 adev->gmc.vram_width = numchan * chansize; 1656 } 1657 } 1658 1659 adev->gmc.vram_type = vram_type; 1660 adev->gmc.vram_vendor = vram_vendor; 1661 switch (adev->ip_versions[GC_HWIP][0]) { 1662 case IP_VERSION(9, 1, 0): 1663 case IP_VERSION(9, 2, 2): 1664 adev->num_vmhubs = 2; 1665 1666 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 1667 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1668 } else { 1669 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 1670 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 1671 adev->gmc.translate_further = 1672 adev->vm_manager.num_level > 1; 1673 } 1674 break; 1675 case IP_VERSION(9, 0, 1): 1676 case IP_VERSION(9, 2, 1): 1677 case IP_VERSION(9, 4, 0): 1678 case IP_VERSION(9, 3, 0): 1679 case IP_VERSION(9, 4, 2): 1680 case IP_VERSION(9, 4, 3): 1681 adev->num_vmhubs = 2; 1682 1683 1684 /* 1685 * To fulfill 4-level page support, 1686 * vm size is 256TB (48bit), maximum size of Vega10, 1687 * block size 512 (9bit) 1688 */ 1689 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */ 1690 if (amdgpu_sriov_vf(adev)) 1691 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47); 1692 else 1693 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1694 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) 1695 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 1696 break; 1697 case IP_VERSION(9, 4, 1): 1698 adev->num_vmhubs = 3; 1699 1700 /* Keep the vm size same with Vega20 */ 1701 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1702 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 1703 break; 1704 default: 1705 break; 1706 } 1707 1708 /* This interrupt is VMC page fault.*/ 1709 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, 1710 &adev->gmc.vm_fault); 1711 if (r) 1712 return r; 1713 1714 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)) { 1715 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT, 1716 &adev->gmc.vm_fault); 1717 if (r) 1718 return r; 1719 } 1720 1721 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, 1722 &adev->gmc.vm_fault); 1723 1724 if (r) 1725 return r; 1726 1727 if (!amdgpu_sriov_vf(adev) && 1728 !adev->gmc.xgmi.connected_to_cpu) { 1729 /* interrupt sent to DF. */ 1730 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 1731 &adev->gmc.ecc_irq); 1732 if (r) 1733 return r; 1734 } 1735 1736 /* Set the internal MC address mask 1737 * This is the max address of the GPU's 1738 * internal address space. 1739 */ 1740 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 1741 1742 dma_addr_bits = adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) ? 48:44; 1743 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(dma_addr_bits)); 1744 if (r) { 1745 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 1746 return r; 1747 } 1748 adev->need_swiotlb = drm_need_swiotlb(dma_addr_bits); 1749 1750 r = gmc_v9_0_mc_init(adev); 1751 if (r) 1752 return r; 1753 1754 amdgpu_gmc_get_vbios_allocations(adev); 1755 1756 /* Memory manager */ 1757 r = amdgpu_bo_init(adev); 1758 if (r) 1759 return r; 1760 1761 r = gmc_v9_0_gart_init(adev); 1762 if (r) 1763 return r; 1764 1765 /* 1766 * number of VMs 1767 * VMID 0 is reserved for System 1768 * amdgpu graphics/compute will use VMIDs 1..n-1 1769 * amdkfd will use VMIDs n..15 1770 * 1771 * The first KFD VMID is 8 for GPUs with graphics, 3 for 1772 * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs 1773 * for video processing. 1774 */ 1775 adev->vm_manager.first_kfd_vmid = 1776 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) || 1777 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) || 1778 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) ? 3 : 8; 1779 1780 amdgpu_vm_manager_init(adev); 1781 1782 gmc_v9_0_save_registers(adev); 1783 1784 r = amdgpu_gmc_ras_sw_init(adev); 1785 if (r) 1786 return r; 1787 1788 return 0; 1789 } 1790 1791 static int gmc_v9_0_sw_fini(void *handle) 1792 { 1793 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1794 1795 amdgpu_gmc_ras_fini(adev); 1796 amdgpu_gem_force_release(adev); 1797 amdgpu_vm_manager_fini(adev); 1798 amdgpu_gart_table_vram_free(adev); 1799 amdgpu_bo_free_kernel(&adev->gmc.pdb0_bo, NULL, &adev->gmc.ptr_pdb0); 1800 amdgpu_bo_fini(adev); 1801 1802 return 0; 1803 } 1804 1805 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 1806 { 1807 1808 switch (adev->ip_versions[MMHUB_HWIP][0]) { 1809 case IP_VERSION(9, 0, 0): 1810 if (amdgpu_sriov_vf(adev)) 1811 break; 1812 fallthrough; 1813 case IP_VERSION(9, 4, 0): 1814 soc15_program_register_sequence(adev, 1815 golden_settings_mmhub_1_0_0, 1816 ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 1817 soc15_program_register_sequence(adev, 1818 golden_settings_athub_1_0_0, 1819 ARRAY_SIZE(golden_settings_athub_1_0_0)); 1820 break; 1821 case IP_VERSION(9, 1, 0): 1822 case IP_VERSION(9, 2, 0): 1823 /* TODO for renoir */ 1824 soc15_program_register_sequence(adev, 1825 golden_settings_athub_1_0_0, 1826 ARRAY_SIZE(golden_settings_athub_1_0_0)); 1827 break; 1828 default: 1829 break; 1830 } 1831 } 1832 1833 /** 1834 * gmc_v9_0_restore_registers - restores regs 1835 * 1836 * @adev: amdgpu_device pointer 1837 * 1838 * This restores register values, saved at suspend. 1839 */ 1840 void gmc_v9_0_restore_registers(struct amdgpu_device *adev) 1841 { 1842 if ((adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 0)) || 1843 (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 1))) { 1844 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register); 1845 WARN_ON(adev->gmc.sdpif_register != 1846 RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0)); 1847 } 1848 } 1849 1850 /** 1851 * gmc_v9_0_gart_enable - gart enable 1852 * 1853 * @adev: amdgpu_device pointer 1854 */ 1855 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 1856 { 1857 int r; 1858 1859 if (adev->gmc.xgmi.connected_to_cpu) 1860 amdgpu_gmc_init_pdb0(adev); 1861 1862 if (adev->gart.bo == NULL) { 1863 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 1864 return -EINVAL; 1865 } 1866 1867 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 1868 1869 if (!adev->in_s0ix) { 1870 r = adev->gfxhub.funcs->gart_enable(adev); 1871 if (r) 1872 return r; 1873 } 1874 1875 r = adev->mmhub.funcs->gart_enable(adev); 1876 if (r) 1877 return r; 1878 1879 DRM_INFO("PCIE GART of %uM enabled.\n", 1880 (unsigned)(adev->gmc.gart_size >> 20)); 1881 if (adev->gmc.pdb0_bo) 1882 DRM_INFO("PDB0 located at 0x%016llX\n", 1883 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo)); 1884 DRM_INFO("PTB located at 0x%016llX\n", 1885 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 1886 1887 return 0; 1888 } 1889 1890 static int gmc_v9_0_hw_init(void *handle) 1891 { 1892 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1893 bool value; 1894 int i, r; 1895 1896 /* The sequence of these two function calls matters.*/ 1897 gmc_v9_0_init_golden_registers(adev); 1898 1899 if (adev->mode_info.num_crtc) { 1900 /* Lockout access through VGA aperture*/ 1901 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 1902 /* disable VGA render */ 1903 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 1904 } 1905 1906 if (adev->mmhub.funcs->update_power_gating) 1907 adev->mmhub.funcs->update_power_gating(adev, true); 1908 1909 adev->hdp.funcs->init_registers(adev); 1910 1911 /* After HDP is initialized, flush HDP.*/ 1912 adev->hdp.funcs->flush_hdp(adev, NULL); 1913 1914 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 1915 value = false; 1916 else 1917 value = true; 1918 1919 if (!amdgpu_sriov_vf(adev)) { 1920 if (!adev->in_s0ix) 1921 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 1922 adev->mmhub.funcs->set_fault_enable_default(adev, value); 1923 } 1924 for (i = 0; i < adev->num_vmhubs; ++i) { 1925 if (adev->in_s0ix && (i == AMDGPU_GFXHUB_0)) 1926 continue; 1927 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0); 1928 } 1929 1930 if (adev->umc.funcs && adev->umc.funcs->init_registers) 1931 adev->umc.funcs->init_registers(adev); 1932 1933 r = gmc_v9_0_gart_enable(adev); 1934 if (r) 1935 return r; 1936 1937 if (amdgpu_emu_mode == 1) 1938 return amdgpu_gmc_vram_checking(adev); 1939 else 1940 return r; 1941 } 1942 1943 /** 1944 * gmc_v9_0_gart_disable - gart disable 1945 * 1946 * @adev: amdgpu_device pointer 1947 * 1948 * This disables all VM page table. 1949 */ 1950 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 1951 { 1952 if (!adev->in_s0ix) 1953 adev->gfxhub.funcs->gart_disable(adev); 1954 adev->mmhub.funcs->gart_disable(adev); 1955 } 1956 1957 static int gmc_v9_0_hw_fini(void *handle) 1958 { 1959 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1960 1961 gmc_v9_0_gart_disable(adev); 1962 1963 if (amdgpu_sriov_vf(adev)) { 1964 /* full access mode, so don't touch any GMC register */ 1965 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 1966 return 0; 1967 } 1968 1969 /* 1970 * Pair the operations did in gmc_v9_0_hw_init and thus maintain 1971 * a correct cached state for GMC. Otherwise, the "gate" again 1972 * operation on S3 resuming will fail due to wrong cached state. 1973 */ 1974 if (adev->mmhub.funcs->update_power_gating) 1975 adev->mmhub.funcs->update_power_gating(adev, false); 1976 1977 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 1978 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1979 1980 return 0; 1981 } 1982 1983 static int gmc_v9_0_suspend(void *handle) 1984 { 1985 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1986 1987 return gmc_v9_0_hw_fini(adev); 1988 } 1989 1990 static int gmc_v9_0_resume(void *handle) 1991 { 1992 int r; 1993 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1994 1995 r = gmc_v9_0_hw_init(adev); 1996 if (r) 1997 return r; 1998 1999 amdgpu_vmid_reset_all(adev); 2000 2001 return 0; 2002 } 2003 2004 static bool gmc_v9_0_is_idle(void *handle) 2005 { 2006 /* MC is always ready in GMC v9.*/ 2007 return true; 2008 } 2009 2010 static int gmc_v9_0_wait_for_idle(void *handle) 2011 { 2012 /* There is no need to wait for MC idle in GMC v9.*/ 2013 return 0; 2014 } 2015 2016 static int gmc_v9_0_soft_reset(void *handle) 2017 { 2018 /* XXX for emulation.*/ 2019 return 0; 2020 } 2021 2022 static int gmc_v9_0_set_clockgating_state(void *handle, 2023 enum amd_clockgating_state state) 2024 { 2025 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2026 2027 adev->mmhub.funcs->set_clockgating(adev, state); 2028 2029 athub_v1_0_set_clockgating(adev, state); 2030 2031 return 0; 2032 } 2033 2034 static void gmc_v9_0_get_clockgating_state(void *handle, u64 *flags) 2035 { 2036 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2037 2038 adev->mmhub.funcs->get_clockgating(adev, flags); 2039 2040 athub_v1_0_get_clockgating(adev, flags); 2041 } 2042 2043 static int gmc_v9_0_set_powergating_state(void *handle, 2044 enum amd_powergating_state state) 2045 { 2046 return 0; 2047 } 2048 2049 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 2050 .name = "gmc_v9_0", 2051 .early_init = gmc_v9_0_early_init, 2052 .late_init = gmc_v9_0_late_init, 2053 .sw_init = gmc_v9_0_sw_init, 2054 .sw_fini = gmc_v9_0_sw_fini, 2055 .hw_init = gmc_v9_0_hw_init, 2056 .hw_fini = gmc_v9_0_hw_fini, 2057 .suspend = gmc_v9_0_suspend, 2058 .resume = gmc_v9_0_resume, 2059 .is_idle = gmc_v9_0_is_idle, 2060 .wait_for_idle = gmc_v9_0_wait_for_idle, 2061 .soft_reset = gmc_v9_0_soft_reset, 2062 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 2063 .set_powergating_state = gmc_v9_0_set_powergating_state, 2064 .get_clockgating_state = gmc_v9_0_get_clockgating_state, 2065 }; 2066 2067 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = 2068 { 2069 .type = AMD_IP_BLOCK_TYPE_GMC, 2070 .major = 9, 2071 .minor = 0, 2072 .rev = 0, 2073 .funcs = &gmc_v9_0_ip_funcs, 2074 }; 2075