1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <drm/drm_cache.h> 25 #include "amdgpu.h" 26 #include "gmc_v9_0.h" 27 #include "amdgpu_atomfirmware.h" 28 #include "amdgpu_gem.h" 29 30 #include "hdp/hdp_4_0_offset.h" 31 #include "hdp/hdp_4_0_sh_mask.h" 32 #include "gc/gc_9_0_sh_mask.h" 33 #include "dce/dce_12_0_offset.h" 34 #include "dce/dce_12_0_sh_mask.h" 35 #include "vega10_enum.h" 36 #include "mmhub/mmhub_1_0_offset.h" 37 #include "athub/athub_1_0_offset.h" 38 #include "oss/osssys_4_0_offset.h" 39 40 #include "soc15.h" 41 #include "soc15_common.h" 42 #include "umc/umc_6_0_sh_mask.h" 43 44 #include "gfxhub_v1_0.h" 45 #include "mmhub_v1_0.h" 46 #include "gfxhub_v1_1.h" 47 48 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 49 50 /* add these here since we already include dce12 headers and these are for DCN */ 51 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 52 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 53 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 54 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 55 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL 56 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L 57 58 /* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/ 59 #define AMDGPU_NUM_OF_VMIDS 8 60 61 static const u32 golden_settings_vega10_hdp[] = 62 { 63 0xf64, 0x0fffffff, 0x00000000, 64 0xf65, 0x0fffffff, 0x00000000, 65 0xf66, 0x0fffffff, 0x00000000, 66 0xf67, 0x0fffffff, 0x00000000, 67 0xf68, 0x0fffffff, 0x00000000, 68 0xf6a, 0x0fffffff, 0x00000000, 69 0xf6b, 0x0fffffff, 0x00000000, 70 0xf6c, 0x0fffffff, 0x00000000, 71 0xf6d, 0x0fffffff, 0x00000000, 72 0xf6e, 0x0fffffff, 0x00000000, 73 }; 74 75 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = 76 { 77 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), 78 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) 79 }; 80 81 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = 82 { 83 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), 84 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) 85 }; 86 87 /* Ecc related register addresses, (BASE + reg offset) */ 88 /* Universal Memory Controller caps (may be fused). */ 89 /* UMCCH:UmcLocalCap */ 90 #define UMCLOCALCAPS_ADDR0 (0x00014306 + 0x00000000) 91 #define UMCLOCALCAPS_ADDR1 (0x00014306 + 0x00000800) 92 #define UMCLOCALCAPS_ADDR2 (0x00014306 + 0x00001000) 93 #define UMCLOCALCAPS_ADDR3 (0x00014306 + 0x00001800) 94 #define UMCLOCALCAPS_ADDR4 (0x00054306 + 0x00000000) 95 #define UMCLOCALCAPS_ADDR5 (0x00054306 + 0x00000800) 96 #define UMCLOCALCAPS_ADDR6 (0x00054306 + 0x00001000) 97 #define UMCLOCALCAPS_ADDR7 (0x00054306 + 0x00001800) 98 #define UMCLOCALCAPS_ADDR8 (0x00094306 + 0x00000000) 99 #define UMCLOCALCAPS_ADDR9 (0x00094306 + 0x00000800) 100 #define UMCLOCALCAPS_ADDR10 (0x00094306 + 0x00001000) 101 #define UMCLOCALCAPS_ADDR11 (0x00094306 + 0x00001800) 102 #define UMCLOCALCAPS_ADDR12 (0x000d4306 + 0x00000000) 103 #define UMCLOCALCAPS_ADDR13 (0x000d4306 + 0x00000800) 104 #define UMCLOCALCAPS_ADDR14 (0x000d4306 + 0x00001000) 105 #define UMCLOCALCAPS_ADDR15 (0x000d4306 + 0x00001800) 106 107 /* Universal Memory Controller Channel config. */ 108 /* UMCCH:UMC_CONFIG */ 109 #define UMCCH_UMC_CONFIG_ADDR0 (0x00014040 + 0x00000000) 110 #define UMCCH_UMC_CONFIG_ADDR1 (0x00014040 + 0x00000800) 111 #define UMCCH_UMC_CONFIG_ADDR2 (0x00014040 + 0x00001000) 112 #define UMCCH_UMC_CONFIG_ADDR3 (0x00014040 + 0x00001800) 113 #define UMCCH_UMC_CONFIG_ADDR4 (0x00054040 + 0x00000000) 114 #define UMCCH_UMC_CONFIG_ADDR5 (0x00054040 + 0x00000800) 115 #define UMCCH_UMC_CONFIG_ADDR6 (0x00054040 + 0x00001000) 116 #define UMCCH_UMC_CONFIG_ADDR7 (0x00054040 + 0x00001800) 117 #define UMCCH_UMC_CONFIG_ADDR8 (0x00094040 + 0x00000000) 118 #define UMCCH_UMC_CONFIG_ADDR9 (0x00094040 + 0x00000800) 119 #define UMCCH_UMC_CONFIG_ADDR10 (0x00094040 + 0x00001000) 120 #define UMCCH_UMC_CONFIG_ADDR11 (0x00094040 + 0x00001800) 121 #define UMCCH_UMC_CONFIG_ADDR12 (0x000d4040 + 0x00000000) 122 #define UMCCH_UMC_CONFIG_ADDR13 (0x000d4040 + 0x00000800) 123 #define UMCCH_UMC_CONFIG_ADDR14 (0x000d4040 + 0x00001000) 124 #define UMCCH_UMC_CONFIG_ADDR15 (0x000d4040 + 0x00001800) 125 126 /* Universal Memory Controller Channel Ecc config. */ 127 /* UMCCH:EccCtrl */ 128 #define UMCCH_ECCCTRL_ADDR0 (0x00014053 + 0x00000000) 129 #define UMCCH_ECCCTRL_ADDR1 (0x00014053 + 0x00000800) 130 #define UMCCH_ECCCTRL_ADDR2 (0x00014053 + 0x00001000) 131 #define UMCCH_ECCCTRL_ADDR3 (0x00014053 + 0x00001800) 132 #define UMCCH_ECCCTRL_ADDR4 (0x00054053 + 0x00000000) 133 #define UMCCH_ECCCTRL_ADDR5 (0x00054053 + 0x00000800) 134 #define UMCCH_ECCCTRL_ADDR6 (0x00054053 + 0x00001000) 135 #define UMCCH_ECCCTRL_ADDR7 (0x00054053 + 0x00001800) 136 #define UMCCH_ECCCTRL_ADDR8 (0x00094053 + 0x00000000) 137 #define UMCCH_ECCCTRL_ADDR9 (0x00094053 + 0x00000800) 138 #define UMCCH_ECCCTRL_ADDR10 (0x00094053 + 0x00001000) 139 #define UMCCH_ECCCTRL_ADDR11 (0x00094053 + 0x00001800) 140 #define UMCCH_ECCCTRL_ADDR12 (0x000d4053 + 0x00000000) 141 #define UMCCH_ECCCTRL_ADDR13 (0x000d4053 + 0x00000800) 142 #define UMCCH_ECCCTRL_ADDR14 (0x000d4053 + 0x00001000) 143 #define UMCCH_ECCCTRL_ADDR15 (0x000d4053 + 0x00001800) 144 145 static const uint32_t ecc_umclocalcap_addrs[] = { 146 UMCLOCALCAPS_ADDR0, 147 UMCLOCALCAPS_ADDR1, 148 UMCLOCALCAPS_ADDR2, 149 UMCLOCALCAPS_ADDR3, 150 UMCLOCALCAPS_ADDR4, 151 UMCLOCALCAPS_ADDR5, 152 UMCLOCALCAPS_ADDR6, 153 UMCLOCALCAPS_ADDR7, 154 UMCLOCALCAPS_ADDR8, 155 UMCLOCALCAPS_ADDR9, 156 UMCLOCALCAPS_ADDR10, 157 UMCLOCALCAPS_ADDR11, 158 UMCLOCALCAPS_ADDR12, 159 UMCLOCALCAPS_ADDR13, 160 UMCLOCALCAPS_ADDR14, 161 UMCLOCALCAPS_ADDR15, 162 }; 163 164 static const uint32_t ecc_umcch_umc_config_addrs[] = { 165 UMCCH_UMC_CONFIG_ADDR0, 166 UMCCH_UMC_CONFIG_ADDR1, 167 UMCCH_UMC_CONFIG_ADDR2, 168 UMCCH_UMC_CONFIG_ADDR3, 169 UMCCH_UMC_CONFIG_ADDR4, 170 UMCCH_UMC_CONFIG_ADDR5, 171 UMCCH_UMC_CONFIG_ADDR6, 172 UMCCH_UMC_CONFIG_ADDR7, 173 UMCCH_UMC_CONFIG_ADDR8, 174 UMCCH_UMC_CONFIG_ADDR9, 175 UMCCH_UMC_CONFIG_ADDR10, 176 UMCCH_UMC_CONFIG_ADDR11, 177 UMCCH_UMC_CONFIG_ADDR12, 178 UMCCH_UMC_CONFIG_ADDR13, 179 UMCCH_UMC_CONFIG_ADDR14, 180 UMCCH_UMC_CONFIG_ADDR15, 181 }; 182 183 static const uint32_t ecc_umcch_eccctrl_addrs[] = { 184 UMCCH_ECCCTRL_ADDR0, 185 UMCCH_ECCCTRL_ADDR1, 186 UMCCH_ECCCTRL_ADDR2, 187 UMCCH_ECCCTRL_ADDR3, 188 UMCCH_ECCCTRL_ADDR4, 189 UMCCH_ECCCTRL_ADDR5, 190 UMCCH_ECCCTRL_ADDR6, 191 UMCCH_ECCCTRL_ADDR7, 192 UMCCH_ECCCTRL_ADDR8, 193 UMCCH_ECCCTRL_ADDR9, 194 UMCCH_ECCCTRL_ADDR10, 195 UMCCH_ECCCTRL_ADDR11, 196 UMCCH_ECCCTRL_ADDR12, 197 UMCCH_ECCCTRL_ADDR13, 198 UMCCH_ECCCTRL_ADDR14, 199 UMCCH_ECCCTRL_ADDR15, 200 }; 201 202 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 203 struct amdgpu_irq_src *src, 204 unsigned type, 205 enum amdgpu_interrupt_state state) 206 { 207 struct amdgpu_vmhub *hub; 208 u32 tmp, reg, bits, i, j; 209 210 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 211 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 212 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 213 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 214 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 215 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 216 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 217 218 switch (state) { 219 case AMDGPU_IRQ_STATE_DISABLE: 220 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) { 221 hub = &adev->vmhub[j]; 222 for (i = 0; i < 16; i++) { 223 reg = hub->vm_context0_cntl + i; 224 tmp = RREG32(reg); 225 tmp &= ~bits; 226 WREG32(reg, tmp); 227 } 228 } 229 break; 230 case AMDGPU_IRQ_STATE_ENABLE: 231 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) { 232 hub = &adev->vmhub[j]; 233 for (i = 0; i < 16; i++) { 234 reg = hub->vm_context0_cntl + i; 235 tmp = RREG32(reg); 236 tmp |= bits; 237 WREG32(reg, tmp); 238 } 239 } 240 default: 241 break; 242 } 243 244 return 0; 245 } 246 247 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 248 struct amdgpu_irq_src *source, 249 struct amdgpu_iv_entry *entry) 250 { 251 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; 252 uint32_t status = 0; 253 u64 addr; 254 255 addr = (u64)entry->src_data[0] << 12; 256 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 257 258 if (!amdgpu_sriov_vf(adev)) { 259 status = RREG32(hub->vm_l2_pro_fault_status); 260 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 261 } 262 263 if (printk_ratelimit()) { 264 struct amdgpu_task_info task_info = { 0 }; 265 266 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 267 268 dev_err(adev->dev, 269 "[%s] VMC page fault (src_id:%u ring:%u vmid:%u pasid:%u, for process %s pid %d thread %s pid %d)\n", 270 entry->vmid_src ? "mmhub" : "gfxhub", 271 entry->src_id, entry->ring_id, entry->vmid, 272 entry->pasid, task_info.process_name, task_info.tgid, 273 task_info.task_name, task_info.pid); 274 dev_err(adev->dev, " in page starting at address 0x%016llx from %d\n", 275 addr, entry->client_id); 276 if (!amdgpu_sriov_vf(adev)) 277 dev_err(adev->dev, 278 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 279 status); 280 } 281 282 return 0; 283 } 284 285 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 286 .set = gmc_v9_0_vm_fault_interrupt_state, 287 .process = gmc_v9_0_process_interrupt, 288 }; 289 290 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 291 { 292 adev->gmc.vm_fault.num_types = 1; 293 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 294 } 295 296 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, 297 uint32_t flush_type) 298 { 299 u32 req = 0; 300 301 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 302 PER_VMID_INVALIDATE_REQ, 1 << vmid); 303 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 304 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 305 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 306 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 307 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 308 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 309 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 310 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 311 312 return req; 313 } 314 315 /* 316 * GART 317 * VMID 0 is the physical GPU addresses as used by the kernel. 318 * VMIDs 1-15 are used for userspace clients and are handled 319 * by the amdgpu vm/hsa code. 320 */ 321 322 /** 323 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type 324 * 325 * @adev: amdgpu_device pointer 326 * @vmid: vm instance to flush 327 * @flush_type: the flush type 328 * 329 * Flush the TLB for the requested page table using certain type. 330 */ 331 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, 332 uint32_t vmid, uint32_t flush_type) 333 { 334 const unsigned eng = 17; 335 unsigned i, j; 336 337 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { 338 struct amdgpu_vmhub *hub = &adev->vmhub[i]; 339 u32 tmp = gmc_v9_0_get_invalidate_req(vmid, flush_type); 340 341 if (i == AMDGPU_GFXHUB && !adev->in_gpu_reset && 342 adev->gfx.kiq.ring.sched.ready && 343 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 344 uint32_t req = hub->vm_inv_eng0_req + eng; 345 uint32_t ack = hub->vm_inv_eng0_ack + eng; 346 347 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, tmp, 348 1 << vmid); 349 continue; 350 } 351 352 spin_lock(&adev->gmc.invalidate_lock); 353 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp); 354 for (j = 0; j < adev->usec_timeout; j++) { 355 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); 356 if (tmp & (1 << vmid)) 357 break; 358 udelay(1); 359 } 360 spin_unlock(&adev->gmc.invalidate_lock); 361 if (j < adev->usec_timeout) 362 continue; 363 364 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 365 } 366 } 367 368 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 369 unsigned vmid, uint64_t pd_addr) 370 { 371 struct amdgpu_device *adev = ring->adev; 372 struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub]; 373 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); 374 unsigned eng = ring->vm_inv_eng; 375 376 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid), 377 lower_32_bits(pd_addr)); 378 379 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid), 380 upper_32_bits(pd_addr)); 381 382 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng, 383 hub->vm_inv_eng0_ack + eng, 384 req, 1 << vmid); 385 386 return pd_addr; 387 } 388 389 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 390 unsigned pasid) 391 { 392 struct amdgpu_device *adev = ring->adev; 393 uint32_t reg; 394 395 if (ring->funcs->vmhub == AMDGPU_GFXHUB) 396 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 397 else 398 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 399 400 amdgpu_ring_emit_wreg(ring, reg, pasid); 401 } 402 403 /** 404 * gmc_v9_0_set_pte_pde - update the page tables using MMIO 405 * 406 * @adev: amdgpu_device pointer 407 * @cpu_pt_addr: cpu address of the page table 408 * @gpu_page_idx: entry in the page table to update 409 * @addr: dst addr to write into pte/pde 410 * @flags: access flags 411 * 412 * Update the page tables using the CPU. 413 */ 414 static int gmc_v9_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 415 uint32_t gpu_page_idx, uint64_t addr, 416 uint64_t flags) 417 { 418 void __iomem *ptr = (void *)cpu_pt_addr; 419 uint64_t value; 420 421 /* 422 * PTE format on VEGA 10: 423 * 63:59 reserved 424 * 58:57 mtype 425 * 56 F 426 * 55 L 427 * 54 P 428 * 53 SW 429 * 52 T 430 * 50:48 reserved 431 * 47:12 4k physical page base address 432 * 11:7 fragment 433 * 6 write 434 * 5 read 435 * 4 exe 436 * 3 Z 437 * 2 snooped 438 * 1 system 439 * 0 valid 440 * 441 * PDE format on VEGA 10: 442 * 63:59 block fragment size 443 * 58:55 reserved 444 * 54 P 445 * 53:48 reserved 446 * 47:6 physical base address of PD or PTE 447 * 5:3 reserved 448 * 2 C 449 * 1 system 450 * 0 valid 451 */ 452 453 /* 454 * The following is for PTE only. GART does not have PDEs. 455 */ 456 value = addr & 0x0000FFFFFFFFF000ULL; 457 value |= flags; 458 writeq(value, ptr + (gpu_page_idx * 8)); 459 return 0; 460 } 461 462 static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev, 463 uint32_t flags) 464 465 { 466 uint64_t pte_flag = 0; 467 468 if (flags & AMDGPU_VM_PAGE_EXECUTABLE) 469 pte_flag |= AMDGPU_PTE_EXECUTABLE; 470 if (flags & AMDGPU_VM_PAGE_READABLE) 471 pte_flag |= AMDGPU_PTE_READABLE; 472 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 473 pte_flag |= AMDGPU_PTE_WRITEABLE; 474 475 switch (flags & AMDGPU_VM_MTYPE_MASK) { 476 case AMDGPU_VM_MTYPE_DEFAULT: 477 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC); 478 break; 479 case AMDGPU_VM_MTYPE_NC: 480 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC); 481 break; 482 case AMDGPU_VM_MTYPE_WC: 483 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_WC); 484 break; 485 case AMDGPU_VM_MTYPE_CC: 486 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_CC); 487 break; 488 case AMDGPU_VM_MTYPE_UC: 489 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_UC); 490 break; 491 default: 492 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC); 493 break; 494 } 495 496 if (flags & AMDGPU_VM_PAGE_PRT) 497 pte_flag |= AMDGPU_PTE_PRT; 498 499 return pte_flag; 500 } 501 502 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, 503 uint64_t *addr, uint64_t *flags) 504 { 505 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 506 *addr = adev->vm_manager.vram_base_offset + *addr - 507 adev->gmc.vram_start; 508 BUG_ON(*addr & 0xFFFF00000000003FULL); 509 510 if (!adev->gmc.translate_further) 511 return; 512 513 if (level == AMDGPU_VM_PDB1) { 514 /* Set the block fragment size */ 515 if (!(*flags & AMDGPU_PDE_PTE)) 516 *flags |= AMDGPU_PDE_BFS(0x9); 517 518 } else if (level == AMDGPU_VM_PDB0) { 519 if (*flags & AMDGPU_PDE_PTE) 520 *flags &= ~AMDGPU_PDE_PTE; 521 else 522 *flags |= AMDGPU_PTE_TF; 523 } 524 } 525 526 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { 527 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, 528 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, 529 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, 530 .set_pte_pde = gmc_v9_0_set_pte_pde, 531 .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags, 532 .get_vm_pde = gmc_v9_0_get_vm_pde 533 }; 534 535 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) 536 { 537 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; 538 } 539 540 static int gmc_v9_0_early_init(void *handle) 541 { 542 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 543 544 gmc_v9_0_set_gmc_funcs(adev); 545 gmc_v9_0_set_irq_funcs(adev); 546 547 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 548 adev->gmc.shared_aperture_end = 549 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 550 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 551 adev->gmc.private_aperture_end = 552 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 553 554 return 0; 555 } 556 557 static int gmc_v9_0_ecc_available(struct amdgpu_device *adev) 558 { 559 uint32_t reg_val; 560 uint32_t reg_addr; 561 uint32_t field_val; 562 size_t i; 563 uint32_t fv2; 564 size_t lost_sheep; 565 566 DRM_DEBUG("ecc: gmc_v9_0_ecc_available()\n"); 567 568 lost_sheep = 0; 569 for (i = 0; i < ARRAY_SIZE(ecc_umclocalcap_addrs); ++i) { 570 reg_addr = ecc_umclocalcap_addrs[i]; 571 DRM_DEBUG("ecc: " 572 "UMCCH_UmcLocalCap[%zu]: reg_addr: 0x%08x\n", 573 i, reg_addr); 574 reg_val = RREG32(reg_addr); 575 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UmcLocalCap, 576 EccDis); 577 DRM_DEBUG("ecc: " 578 "reg_val: 0x%08x, " 579 "EccDis: 0x%08x, ", 580 reg_val, field_val); 581 if (field_val) { 582 DRM_ERROR("ecc: UmcLocalCap:EccDis is set.\n"); 583 ++lost_sheep; 584 } 585 } 586 587 for (i = 0; i < ARRAY_SIZE(ecc_umcch_umc_config_addrs); ++i) { 588 reg_addr = ecc_umcch_umc_config_addrs[i]; 589 DRM_DEBUG("ecc: " 590 "UMCCH0_0_UMC_CONFIG[%zu]: reg_addr: 0x%08x", 591 i, reg_addr); 592 reg_val = RREG32(reg_addr); 593 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UMC_CONFIG, 594 DramReady); 595 DRM_DEBUG("ecc: " 596 "reg_val: 0x%08x, " 597 "DramReady: 0x%08x\n", 598 reg_val, field_val); 599 600 if (!field_val) { 601 DRM_ERROR("ecc: UMC_CONFIG:DramReady is not set.\n"); 602 ++lost_sheep; 603 } 604 } 605 606 for (i = 0; i < ARRAY_SIZE(ecc_umcch_eccctrl_addrs); ++i) { 607 reg_addr = ecc_umcch_eccctrl_addrs[i]; 608 DRM_DEBUG("ecc: " 609 "UMCCH_EccCtrl[%zu]: reg_addr: 0x%08x, ", 610 i, reg_addr); 611 reg_val = RREG32(reg_addr); 612 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl, 613 WrEccEn); 614 fv2 = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl, 615 RdEccEn); 616 DRM_DEBUG("ecc: " 617 "reg_val: 0x%08x, " 618 "WrEccEn: 0x%08x, " 619 "RdEccEn: 0x%08x\n", 620 reg_val, field_val, fv2); 621 622 if (!field_val) { 623 DRM_DEBUG("ecc: WrEccEn is not set\n"); 624 ++lost_sheep; 625 } 626 if (!fv2) { 627 DRM_DEBUG("ecc: RdEccEn is not set\n"); 628 ++lost_sheep; 629 } 630 } 631 632 DRM_DEBUG("ecc: lost_sheep: %zu\n", lost_sheep); 633 return lost_sheep == 0; 634 } 635 636 static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev) 637 { 638 639 /* 640 * TODO: 641 * Currently there is a bug where some memory client outside 642 * of the driver writes to first 8M of VRAM on S3 resume, 643 * this overrides GART which by default gets placed in first 8M and 644 * causes VM_FAULTS once GTT is accessed. 645 * Keep the stolen memory reservation until the while this is not solved. 646 * Also check code in gmc_v9_0_get_vbios_fb_size and gmc_v9_0_late_init 647 */ 648 switch (adev->asic_type) { 649 case CHIP_VEGA10: 650 return true; 651 case CHIP_RAVEN: 652 case CHIP_VEGA12: 653 case CHIP_VEGA20: 654 default: 655 return false; 656 } 657 } 658 659 static int gmc_v9_0_late_init(void *handle) 660 { 661 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 662 /* 663 * The latest engine allocation on gfx9 is: 664 * Engine 0, 1: idle 665 * Engine 2, 3: firmware 666 * Engine 4~13: amdgpu ring, subject to change when ring number changes 667 * Engine 14~15: idle 668 * Engine 16: kfd tlb invalidation 669 * Engine 17: Gart flushes 670 */ 671 unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 }; 672 unsigned i; 673 int r; 674 675 if (!gmc_v9_0_keep_stolen_memory(adev)) 676 amdgpu_bo_late_init(adev); 677 678 for(i = 0; i < adev->num_rings; ++i) { 679 struct amdgpu_ring *ring = adev->rings[i]; 680 unsigned vmhub = ring->funcs->vmhub; 681 682 ring->vm_inv_eng = vm_inv_eng[vmhub]++; 683 dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n", 684 ring->name, ring->vm_inv_eng, ring->funcs->vmhub); 685 } 686 687 /* Engine 16 is used for KFD and 17 for GART flushes */ 688 for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i) 689 BUG_ON(vm_inv_eng[i] > 16); 690 691 if (adev->asic_type == CHIP_VEGA10 && !amdgpu_sriov_vf(adev)) { 692 r = gmc_v9_0_ecc_available(adev); 693 if (r == 1) { 694 DRM_INFO("ECC is active.\n"); 695 } else if (r == 0) { 696 DRM_INFO("ECC is not present.\n"); 697 adev->df_funcs->enable_ecc_force_par_wr_rmw(adev, false); 698 } else { 699 DRM_ERROR("gmc_v9_0_ecc_available() failed. r: %d\n", r); 700 return r; 701 } 702 } 703 704 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 705 } 706 707 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 708 struct amdgpu_gmc *mc) 709 { 710 u64 base = 0; 711 if (!amdgpu_sriov_vf(adev)) 712 base = mmhub_v1_0_get_fb_location(adev); 713 /* add the xgmi offset of the physical node */ 714 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 715 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 716 amdgpu_gmc_gart_location(adev, mc); 717 if (!amdgpu_sriov_vf(adev)) 718 amdgpu_gmc_agp_location(adev, mc); 719 /* base offset of vram pages */ 720 adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev); 721 722 /* XXX: add the xgmi offset of the physical node? */ 723 adev->vm_manager.vram_base_offset += 724 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 725 } 726 727 /** 728 * gmc_v9_0_mc_init - initialize the memory controller driver params 729 * 730 * @adev: amdgpu_device pointer 731 * 732 * Look up the amount of vram, vram width, and decide how to place 733 * vram and gart within the GPU's physical address space. 734 * Returns 0 for success. 735 */ 736 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 737 { 738 int chansize, numchan; 739 int r; 740 741 if (amdgpu_emu_mode != 1) 742 adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev); 743 if (!adev->gmc.vram_width) { 744 /* hbm memory channel size */ 745 if (adev->flags & AMD_IS_APU) 746 chansize = 64; 747 else 748 chansize = 128; 749 750 numchan = adev->df_funcs->get_hbm_channel_number(adev); 751 adev->gmc.vram_width = numchan * chansize; 752 } 753 754 /* size in MB on si */ 755 adev->gmc.mc_vram_size = 756 adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL; 757 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 758 759 if (!(adev->flags & AMD_IS_APU)) { 760 r = amdgpu_device_resize_fb_bar(adev); 761 if (r) 762 return r; 763 } 764 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 765 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 766 767 #ifdef CONFIG_X86_64 768 if (adev->flags & AMD_IS_APU) { 769 adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev); 770 adev->gmc.aper_size = adev->gmc.real_vram_size; 771 } 772 #endif 773 /* In case the PCI BAR is larger than the actual amount of vram */ 774 adev->gmc.visible_vram_size = adev->gmc.aper_size; 775 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 776 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 777 778 /* set the gart size */ 779 if (amdgpu_gart_size == -1) { 780 switch (adev->asic_type) { 781 case CHIP_VEGA10: /* all engines support GPUVM */ 782 case CHIP_VEGA12: /* all engines support GPUVM */ 783 case CHIP_VEGA20: 784 default: 785 adev->gmc.gart_size = 512ULL << 20; 786 break; 787 case CHIP_RAVEN: /* DCE SG support */ 788 adev->gmc.gart_size = 1024ULL << 20; 789 break; 790 } 791 } else { 792 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 793 } 794 795 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); 796 797 return 0; 798 } 799 800 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 801 { 802 int r; 803 804 if (adev->gart.bo) { 805 WARN(1, "VEGA10 PCIE GART already initialized\n"); 806 return 0; 807 } 808 /* Initialize common gart structure */ 809 r = amdgpu_gart_init(adev); 810 if (r) 811 return r; 812 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 813 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE(MTYPE_UC) | 814 AMDGPU_PTE_EXECUTABLE; 815 return amdgpu_gart_table_vram_alloc(adev); 816 } 817 818 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 819 { 820 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 821 unsigned size; 822 823 /* 824 * TODO Remove once GART corruption is resolved 825 * Check related code in gmc_v9_0_sw_fini 826 * */ 827 if (gmc_v9_0_keep_stolen_memory(adev)) 828 return 9 * 1024 * 1024; 829 830 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 831 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */ 832 } else { 833 u32 viewport; 834 835 switch (adev->asic_type) { 836 case CHIP_RAVEN: 837 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 838 size = (REG_GET_FIELD(viewport, 839 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 840 REG_GET_FIELD(viewport, 841 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 842 4); 843 break; 844 case CHIP_VEGA10: 845 case CHIP_VEGA12: 846 case CHIP_VEGA20: 847 default: 848 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); 849 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 850 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * 851 4); 852 break; 853 } 854 } 855 /* return 0 if the pre-OS buffer uses up most of vram */ 856 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 857 return 0; 858 859 return size; 860 } 861 862 static int gmc_v9_0_sw_init(void *handle) 863 { 864 int r; 865 int dma_bits; 866 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 867 868 gfxhub_v1_0_init(adev); 869 mmhub_v1_0_init(adev); 870 871 spin_lock_init(&adev->gmc.invalidate_lock); 872 873 adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev); 874 switch (adev->asic_type) { 875 case CHIP_RAVEN: 876 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 877 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 878 } else { 879 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 880 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 881 adev->gmc.translate_further = 882 adev->vm_manager.num_level > 1; 883 } 884 break; 885 case CHIP_VEGA10: 886 case CHIP_VEGA12: 887 case CHIP_VEGA20: 888 /* 889 * To fulfill 4-level page support, 890 * vm size is 256TB (48bit), maximum size of Vega10, 891 * block size 512 (9bit) 892 */ 893 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 894 break; 895 default: 896 break; 897 } 898 899 /* This interrupt is VMC page fault.*/ 900 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, 901 &adev->gmc.vm_fault); 902 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, 903 &adev->gmc.vm_fault); 904 905 if (r) 906 return r; 907 908 /* Set the internal MC address mask 909 * This is the max address of the GPU's 910 * internal address space. 911 */ 912 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 913 914 /* set DMA mask + need_dma32 flags. 915 * PCIE - can handle 44-bits. 916 * IGP - can handle 44-bits 917 * PCI - dma32 for legacy pci gart, 44 bits on vega10 918 */ 919 adev->need_dma32 = false; 920 dma_bits = adev->need_dma32 ? 32 : 44; 921 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 922 if (r) { 923 adev->need_dma32 = true; 924 dma_bits = 32; 925 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 926 } 927 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 928 if (r) { 929 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); 930 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n"); 931 } 932 adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits); 933 934 if (adev->asic_type == CHIP_VEGA20) { 935 r = gfxhub_v1_1_get_xgmi_info(adev); 936 if (r) 937 return r; 938 } 939 940 r = gmc_v9_0_mc_init(adev); 941 if (r) 942 return r; 943 944 adev->gmc.stolen_size = gmc_v9_0_get_vbios_fb_size(adev); 945 946 /* Memory manager */ 947 r = amdgpu_bo_init(adev); 948 if (r) 949 return r; 950 951 r = gmc_v9_0_gart_init(adev); 952 if (r) 953 return r; 954 955 /* 956 * number of VMs 957 * VMID 0 is reserved for System 958 * amdgpu graphics/compute will use VMIDs 1-7 959 * amdkfd will use VMIDs 8-15 960 */ 961 adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS; 962 adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS; 963 964 amdgpu_vm_manager_init(adev); 965 966 return 0; 967 } 968 969 static int gmc_v9_0_sw_fini(void *handle) 970 { 971 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 972 973 amdgpu_gem_force_release(adev); 974 amdgpu_vm_manager_fini(adev); 975 976 if (gmc_v9_0_keep_stolen_memory(adev)) 977 amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL); 978 979 amdgpu_gart_table_vram_free(adev); 980 amdgpu_bo_fini(adev); 981 amdgpu_gart_fini(adev); 982 983 return 0; 984 } 985 986 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 987 { 988 989 switch (adev->asic_type) { 990 case CHIP_VEGA10: 991 case CHIP_VEGA20: 992 soc15_program_register_sequence(adev, 993 golden_settings_mmhub_1_0_0, 994 ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 995 soc15_program_register_sequence(adev, 996 golden_settings_athub_1_0_0, 997 ARRAY_SIZE(golden_settings_athub_1_0_0)); 998 break; 999 case CHIP_VEGA12: 1000 break; 1001 case CHIP_RAVEN: 1002 soc15_program_register_sequence(adev, 1003 golden_settings_athub_1_0_0, 1004 ARRAY_SIZE(golden_settings_athub_1_0_0)); 1005 break; 1006 default: 1007 break; 1008 } 1009 } 1010 1011 /** 1012 * gmc_v9_0_gart_enable - gart enable 1013 * 1014 * @adev: amdgpu_device pointer 1015 */ 1016 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 1017 { 1018 int r; 1019 bool value; 1020 u32 tmp; 1021 1022 amdgpu_device_program_register_sequence(adev, 1023 golden_settings_vega10_hdp, 1024 ARRAY_SIZE(golden_settings_vega10_hdp)); 1025 1026 if (adev->gart.bo == NULL) { 1027 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 1028 return -EINVAL; 1029 } 1030 r = amdgpu_gart_table_vram_pin(adev); 1031 if (r) 1032 return r; 1033 1034 switch (adev->asic_type) { 1035 case CHIP_RAVEN: 1036 mmhub_v1_0_update_power_gating(adev, true); 1037 break; 1038 default: 1039 break; 1040 } 1041 1042 r = gfxhub_v1_0_gart_enable(adev); 1043 if (r) 1044 return r; 1045 1046 r = mmhub_v1_0_gart_enable(adev); 1047 if (r) 1048 return r; 1049 1050 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1); 1051 1052 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL); 1053 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp); 1054 1055 /* After HDP is initialized, flush HDP.*/ 1056 adev->nbio_funcs->hdp_flush(adev, NULL); 1057 1058 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 1059 value = false; 1060 else 1061 value = true; 1062 1063 gfxhub_v1_0_set_fault_enable_default(adev, value); 1064 mmhub_v1_0_set_fault_enable_default(adev, value); 1065 gmc_v9_0_flush_gpu_tlb(adev, 0, 0); 1066 1067 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1068 (unsigned)(adev->gmc.gart_size >> 20), 1069 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 1070 adev->gart.ready = true; 1071 return 0; 1072 } 1073 1074 static int gmc_v9_0_hw_init(void *handle) 1075 { 1076 int r; 1077 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1078 1079 /* The sequence of these two function calls matters.*/ 1080 gmc_v9_0_init_golden_registers(adev); 1081 1082 if (adev->mode_info.num_crtc) { 1083 /* Lockout access through VGA aperture*/ 1084 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 1085 1086 /* disable VGA render */ 1087 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 1088 } 1089 1090 r = gmc_v9_0_gart_enable(adev); 1091 1092 return r; 1093 } 1094 1095 /** 1096 * gmc_v9_0_gart_disable - gart disable 1097 * 1098 * @adev: amdgpu_device pointer 1099 * 1100 * This disables all VM page table. 1101 */ 1102 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 1103 { 1104 gfxhub_v1_0_gart_disable(adev); 1105 mmhub_v1_0_gart_disable(adev); 1106 amdgpu_gart_table_vram_unpin(adev); 1107 } 1108 1109 static int gmc_v9_0_hw_fini(void *handle) 1110 { 1111 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1112 1113 if (amdgpu_sriov_vf(adev)) { 1114 /* full access mode, so don't touch any GMC register */ 1115 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 1116 return 0; 1117 } 1118 1119 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1120 gmc_v9_0_gart_disable(adev); 1121 1122 return 0; 1123 } 1124 1125 static int gmc_v9_0_suspend(void *handle) 1126 { 1127 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1128 1129 return gmc_v9_0_hw_fini(adev); 1130 } 1131 1132 static int gmc_v9_0_resume(void *handle) 1133 { 1134 int r; 1135 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1136 1137 r = gmc_v9_0_hw_init(adev); 1138 if (r) 1139 return r; 1140 1141 amdgpu_vmid_reset_all(adev); 1142 1143 return 0; 1144 } 1145 1146 static bool gmc_v9_0_is_idle(void *handle) 1147 { 1148 /* MC is always ready in GMC v9.*/ 1149 return true; 1150 } 1151 1152 static int gmc_v9_0_wait_for_idle(void *handle) 1153 { 1154 /* There is no need to wait for MC idle in GMC v9.*/ 1155 return 0; 1156 } 1157 1158 static int gmc_v9_0_soft_reset(void *handle) 1159 { 1160 /* XXX for emulation.*/ 1161 return 0; 1162 } 1163 1164 static int gmc_v9_0_set_clockgating_state(void *handle, 1165 enum amd_clockgating_state state) 1166 { 1167 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1168 1169 return mmhub_v1_0_set_clockgating(adev, state); 1170 } 1171 1172 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags) 1173 { 1174 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1175 1176 mmhub_v1_0_get_clockgating(adev, flags); 1177 } 1178 1179 static int gmc_v9_0_set_powergating_state(void *handle, 1180 enum amd_powergating_state state) 1181 { 1182 return 0; 1183 } 1184 1185 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 1186 .name = "gmc_v9_0", 1187 .early_init = gmc_v9_0_early_init, 1188 .late_init = gmc_v9_0_late_init, 1189 .sw_init = gmc_v9_0_sw_init, 1190 .sw_fini = gmc_v9_0_sw_fini, 1191 .hw_init = gmc_v9_0_hw_init, 1192 .hw_fini = gmc_v9_0_hw_fini, 1193 .suspend = gmc_v9_0_suspend, 1194 .resume = gmc_v9_0_resume, 1195 .is_idle = gmc_v9_0_is_idle, 1196 .wait_for_idle = gmc_v9_0_wait_for_idle, 1197 .soft_reset = gmc_v9_0_soft_reset, 1198 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 1199 .set_powergating_state = gmc_v9_0_set_powergating_state, 1200 .get_clockgating_state = gmc_v9_0_get_clockgating_state, 1201 }; 1202 1203 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = 1204 { 1205 .type = AMD_IP_BLOCK_TYPE_GMC, 1206 .major = 9, 1207 .minor = 0, 1208 .rev = 0, 1209 .funcs = &gmc_v9_0_ip_funcs, 1210 }; 1211