1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/pci.h> 26 27 #include <drm/drm_cache.h> 28 29 #include "amdgpu.h" 30 #include "gmc_v9_0.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_gem.h" 33 34 #include "hdp/hdp_4_0_offset.h" 35 #include "hdp/hdp_4_0_sh_mask.h" 36 #include "gc/gc_9_0_sh_mask.h" 37 #include "dce/dce_12_0_offset.h" 38 #include "dce/dce_12_0_sh_mask.h" 39 #include "vega10_enum.h" 40 #include "mmhub/mmhub_1_0_offset.h" 41 #include "athub/athub_1_0_offset.h" 42 #include "oss/osssys_4_0_offset.h" 43 44 #include "soc15.h" 45 #include "soc15_common.h" 46 #include "umc/umc_6_0_sh_mask.h" 47 48 #include "gfxhub_v1_0.h" 49 #include "mmhub_v1_0.h" 50 #include "athub_v1_0.h" 51 #include "gfxhub_v1_1.h" 52 #include "mmhub_v9_4.h" 53 #include "umc_v6_1.h" 54 #include "umc_v6_0.h" 55 56 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 57 58 #include "amdgpu_ras.h" 59 #include "amdgpu_xgmi.h" 60 61 /* add these here since we already include dce12 headers and these are for DCN */ 62 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 63 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 64 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 65 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 66 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL 67 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L 68 69 /* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/ 70 #define AMDGPU_NUM_OF_VMIDS 8 71 72 static const u32 golden_settings_vega10_hdp[] = 73 { 74 0xf64, 0x0fffffff, 0x00000000, 75 0xf65, 0x0fffffff, 0x00000000, 76 0xf66, 0x0fffffff, 0x00000000, 77 0xf67, 0x0fffffff, 0x00000000, 78 0xf68, 0x0fffffff, 0x00000000, 79 0xf6a, 0x0fffffff, 0x00000000, 80 0xf6b, 0x0fffffff, 0x00000000, 81 0xf6c, 0x0fffffff, 0x00000000, 82 0xf6d, 0x0fffffff, 0x00000000, 83 0xf6e, 0x0fffffff, 0x00000000, 84 }; 85 86 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = 87 { 88 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), 89 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) 90 }; 91 92 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = 93 { 94 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), 95 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) 96 }; 97 98 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { 99 (0x000143c0 + 0x00000000), 100 (0x000143c0 + 0x00000800), 101 (0x000143c0 + 0x00001000), 102 (0x000143c0 + 0x00001800), 103 (0x000543c0 + 0x00000000), 104 (0x000543c0 + 0x00000800), 105 (0x000543c0 + 0x00001000), 106 (0x000543c0 + 0x00001800), 107 (0x000943c0 + 0x00000000), 108 (0x000943c0 + 0x00000800), 109 (0x000943c0 + 0x00001000), 110 (0x000943c0 + 0x00001800), 111 (0x000d43c0 + 0x00000000), 112 (0x000d43c0 + 0x00000800), 113 (0x000d43c0 + 0x00001000), 114 (0x000d43c0 + 0x00001800), 115 (0x001143c0 + 0x00000000), 116 (0x001143c0 + 0x00000800), 117 (0x001143c0 + 0x00001000), 118 (0x001143c0 + 0x00001800), 119 (0x001543c0 + 0x00000000), 120 (0x001543c0 + 0x00000800), 121 (0x001543c0 + 0x00001000), 122 (0x001543c0 + 0x00001800), 123 (0x001943c0 + 0x00000000), 124 (0x001943c0 + 0x00000800), 125 (0x001943c0 + 0x00001000), 126 (0x001943c0 + 0x00001800), 127 (0x001d43c0 + 0x00000000), 128 (0x001d43c0 + 0x00000800), 129 (0x001d43c0 + 0x00001000), 130 (0x001d43c0 + 0x00001800), 131 }; 132 133 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { 134 (0x000143e0 + 0x00000000), 135 (0x000143e0 + 0x00000800), 136 (0x000143e0 + 0x00001000), 137 (0x000143e0 + 0x00001800), 138 (0x000543e0 + 0x00000000), 139 (0x000543e0 + 0x00000800), 140 (0x000543e0 + 0x00001000), 141 (0x000543e0 + 0x00001800), 142 (0x000943e0 + 0x00000000), 143 (0x000943e0 + 0x00000800), 144 (0x000943e0 + 0x00001000), 145 (0x000943e0 + 0x00001800), 146 (0x000d43e0 + 0x00000000), 147 (0x000d43e0 + 0x00000800), 148 (0x000d43e0 + 0x00001000), 149 (0x000d43e0 + 0x00001800), 150 (0x001143e0 + 0x00000000), 151 (0x001143e0 + 0x00000800), 152 (0x001143e0 + 0x00001000), 153 (0x001143e0 + 0x00001800), 154 (0x001543e0 + 0x00000000), 155 (0x001543e0 + 0x00000800), 156 (0x001543e0 + 0x00001000), 157 (0x001543e0 + 0x00001800), 158 (0x001943e0 + 0x00000000), 159 (0x001943e0 + 0x00000800), 160 (0x001943e0 + 0x00001000), 161 (0x001943e0 + 0x00001800), 162 (0x001d43e0 + 0x00000000), 163 (0x001d43e0 + 0x00000800), 164 (0x001d43e0 + 0x00001000), 165 (0x001d43e0 + 0x00001800), 166 }; 167 168 static const uint32_t ecc_umc_mcumc_status_addrs[] = { 169 (0x000143c2 + 0x00000000), 170 (0x000143c2 + 0x00000800), 171 (0x000143c2 + 0x00001000), 172 (0x000143c2 + 0x00001800), 173 (0x000543c2 + 0x00000000), 174 (0x000543c2 + 0x00000800), 175 (0x000543c2 + 0x00001000), 176 (0x000543c2 + 0x00001800), 177 (0x000943c2 + 0x00000000), 178 (0x000943c2 + 0x00000800), 179 (0x000943c2 + 0x00001000), 180 (0x000943c2 + 0x00001800), 181 (0x000d43c2 + 0x00000000), 182 (0x000d43c2 + 0x00000800), 183 (0x000d43c2 + 0x00001000), 184 (0x000d43c2 + 0x00001800), 185 (0x001143c2 + 0x00000000), 186 (0x001143c2 + 0x00000800), 187 (0x001143c2 + 0x00001000), 188 (0x001143c2 + 0x00001800), 189 (0x001543c2 + 0x00000000), 190 (0x001543c2 + 0x00000800), 191 (0x001543c2 + 0x00001000), 192 (0x001543c2 + 0x00001800), 193 (0x001943c2 + 0x00000000), 194 (0x001943c2 + 0x00000800), 195 (0x001943c2 + 0x00001000), 196 (0x001943c2 + 0x00001800), 197 (0x001d43c2 + 0x00000000), 198 (0x001d43c2 + 0x00000800), 199 (0x001d43c2 + 0x00001000), 200 (0x001d43c2 + 0x00001800), 201 }; 202 203 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, 204 struct amdgpu_irq_src *src, 205 unsigned type, 206 enum amdgpu_interrupt_state state) 207 { 208 u32 bits, i, tmp, reg; 209 210 bits = 0x7f; 211 212 switch (state) { 213 case AMDGPU_IRQ_STATE_DISABLE: 214 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 215 reg = ecc_umc_mcumc_ctrl_addrs[i]; 216 tmp = RREG32(reg); 217 tmp &= ~bits; 218 WREG32(reg, tmp); 219 } 220 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 221 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 222 tmp = RREG32(reg); 223 tmp &= ~bits; 224 WREG32(reg, tmp); 225 } 226 break; 227 case AMDGPU_IRQ_STATE_ENABLE: 228 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 229 reg = ecc_umc_mcumc_ctrl_addrs[i]; 230 tmp = RREG32(reg); 231 tmp |= bits; 232 WREG32(reg, tmp); 233 } 234 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 235 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 236 tmp = RREG32(reg); 237 tmp |= bits; 238 WREG32(reg, tmp); 239 } 240 break; 241 default: 242 break; 243 } 244 245 return 0; 246 } 247 248 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 249 struct amdgpu_irq_src *src, 250 unsigned type, 251 enum amdgpu_interrupt_state state) 252 { 253 struct amdgpu_vmhub *hub; 254 u32 tmp, reg, bits, i, j; 255 256 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 257 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 258 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 259 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 260 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 261 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 262 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 263 264 switch (state) { 265 case AMDGPU_IRQ_STATE_DISABLE: 266 for (j = 0; j < adev->num_vmhubs; j++) { 267 hub = &adev->vmhub[j]; 268 for (i = 0; i < 16; i++) { 269 reg = hub->vm_context0_cntl + i; 270 tmp = RREG32(reg); 271 tmp &= ~bits; 272 WREG32(reg, tmp); 273 } 274 } 275 break; 276 case AMDGPU_IRQ_STATE_ENABLE: 277 for (j = 0; j < adev->num_vmhubs; j++) { 278 hub = &adev->vmhub[j]; 279 for (i = 0; i < 16; i++) { 280 reg = hub->vm_context0_cntl + i; 281 tmp = RREG32(reg); 282 tmp |= bits; 283 WREG32(reg, tmp); 284 } 285 } 286 default: 287 break; 288 } 289 290 return 0; 291 } 292 293 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 294 struct amdgpu_irq_src *source, 295 struct amdgpu_iv_entry *entry) 296 { 297 struct amdgpu_vmhub *hub; 298 bool retry_fault = !!(entry->src_data[1] & 0x80); 299 uint32_t status = 0; 300 u64 addr; 301 char hub_name[10]; 302 303 addr = (u64)entry->src_data[0] << 12; 304 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 305 306 if (retry_fault && amdgpu_gmc_filter_faults(adev, addr, entry->pasid, 307 entry->timestamp)) 308 return 1; /* This also prevents sending it to KFD */ 309 310 if (entry->client_id == SOC15_IH_CLIENTID_VMC) { 311 snprintf(hub_name, sizeof(hub_name), "mmhub0"); 312 hub = &adev->vmhub[AMDGPU_MMHUB_0]; 313 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) { 314 snprintf(hub_name, sizeof(hub_name), "mmhub1"); 315 hub = &adev->vmhub[AMDGPU_MMHUB_1]; 316 } else { 317 snprintf(hub_name, sizeof(hub_name), "gfxhub0"); 318 hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 319 } 320 321 /* If it's the first fault for this address, process it normally */ 322 if (retry_fault && !in_interrupt() && 323 amdgpu_vm_handle_fault(adev, entry->pasid, addr)) 324 return 1; /* This also prevents sending it to KFD */ 325 326 if (!amdgpu_sriov_vf(adev)) { 327 /* 328 * Issue a dummy read to wait for the status register to 329 * be updated to avoid reading an incorrect value due to 330 * the new fast GRBM interface. 331 */ 332 if (entry->vmid_src == AMDGPU_GFXHUB_0) 333 RREG32(hub->vm_l2_pro_fault_status); 334 335 status = RREG32(hub->vm_l2_pro_fault_status); 336 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 337 } 338 339 if (printk_ratelimit()) { 340 struct amdgpu_task_info task_info; 341 342 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 343 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 344 345 dev_err(adev->dev, 346 "[%s] %s page fault (src_id:%u ring:%u vmid:%u " 347 "pasid:%u, for process %s pid %d thread %s pid %d)\n", 348 hub_name, retry_fault ? "retry" : "no-retry", 349 entry->src_id, entry->ring_id, entry->vmid, 350 entry->pasid, task_info.process_name, task_info.tgid, 351 task_info.task_name, task_info.pid); 352 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", 353 addr, entry->client_id); 354 if (!amdgpu_sriov_vf(adev)) { 355 dev_err(adev->dev, 356 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 357 status); 358 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 359 REG_GET_FIELD(status, 360 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 361 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 362 REG_GET_FIELD(status, 363 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 364 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 365 REG_GET_FIELD(status, 366 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 367 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 368 REG_GET_FIELD(status, 369 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 370 dev_err(adev->dev, "\t RW: 0x%lx\n", 371 REG_GET_FIELD(status, 372 VM_L2_PROTECTION_FAULT_STATUS, RW)); 373 374 } 375 } 376 377 return 0; 378 } 379 380 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 381 .set = gmc_v9_0_vm_fault_interrupt_state, 382 .process = gmc_v9_0_process_interrupt, 383 }; 384 385 386 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { 387 .set = gmc_v9_0_ecc_interrupt_state, 388 .process = amdgpu_umc_process_ecc_irq, 389 }; 390 391 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 392 { 393 adev->gmc.vm_fault.num_types = 1; 394 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 395 396 adev->gmc.ecc_irq.num_types = 1; 397 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; 398 } 399 400 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, 401 uint32_t flush_type) 402 { 403 u32 req = 0; 404 405 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 406 PER_VMID_INVALIDATE_REQ, 1 << vmid); 407 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 408 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 409 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 410 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 411 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 412 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 413 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 414 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 415 416 return req; 417 } 418 419 /** 420 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore 421 * 422 * @adev: amdgpu_device pointer 423 * @vmhub: vmhub type 424 * 425 */ 426 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev, 427 uint32_t vmhub) 428 { 429 return ((vmhub == AMDGPU_MMHUB_0 || 430 vmhub == AMDGPU_MMHUB_1) && 431 (!amdgpu_sriov_vf(adev)) && 432 (!(adev->asic_type == CHIP_RAVEN && 433 adev->rev_id < 0x8 && 434 adev->pdev->device == 0x15d8))); 435 } 436 437 /* 438 * GART 439 * VMID 0 is the physical GPU addresses as used by the kernel. 440 * VMIDs 1-15 are used for userspace clients and are handled 441 * by the amdgpu vm/hsa code. 442 */ 443 444 /** 445 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type 446 * 447 * @adev: amdgpu_device pointer 448 * @vmid: vm instance to flush 449 * @flush_type: the flush type 450 * 451 * Flush the TLB for the requested page table using certain type. 452 */ 453 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 454 uint32_t vmhub, uint32_t flush_type) 455 { 456 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub); 457 const unsigned eng = 17; 458 u32 j, tmp; 459 struct amdgpu_vmhub *hub; 460 461 BUG_ON(vmhub >= adev->num_vmhubs); 462 463 hub = &adev->vmhub[vmhub]; 464 tmp = gmc_v9_0_get_invalidate_req(vmid, flush_type); 465 466 /* This is necessary for a HW workaround under SRIOV as well 467 * as GFXOFF under bare metal 468 */ 469 if (adev->gfx.kiq.ring.sched.ready && 470 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && 471 !adev->in_gpu_reset) { 472 uint32_t req = hub->vm_inv_eng0_req + eng; 473 uint32_t ack = hub->vm_inv_eng0_ack + eng; 474 475 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, tmp, 476 1 << vmid); 477 return; 478 } 479 480 spin_lock(&adev->gmc.invalidate_lock); 481 482 /* 483 * It may lose gpuvm invalidate acknowldege state across power-gating 484 * off cycle, add semaphore acquire before invalidation and semaphore 485 * release after invalidation to avoid entering power gated state 486 * to WA the Issue 487 */ 488 489 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 490 if (use_semaphore) { 491 for (j = 0; j < adev->usec_timeout; j++) { 492 /* a read return value of 1 means semaphore acuqire */ 493 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng); 494 if (tmp & 0x1) 495 break; 496 udelay(1); 497 } 498 499 if (j >= adev->usec_timeout) 500 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 501 } 502 503 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp); 504 505 /* 506 * Issue a dummy read to wait for the ACK register to be cleared 507 * to avoid a false ACK due to the new fast GRBM interface. 508 */ 509 if (vmhub == AMDGPU_GFXHUB_0) 510 RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng); 511 512 for (j = 0; j < adev->usec_timeout; j++) { 513 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); 514 if (tmp & (1 << vmid)) 515 break; 516 udelay(1); 517 } 518 519 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 520 if (use_semaphore) 521 /* 522 * add semaphore release after invalidation, 523 * write with 0 means semaphore release 524 */ 525 WREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng, 0); 526 527 spin_unlock(&adev->gmc.invalidate_lock); 528 529 if (j < adev->usec_timeout) 530 return; 531 532 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 533 } 534 535 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 536 unsigned vmid, uint64_t pd_addr) 537 { 538 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub); 539 struct amdgpu_device *adev = ring->adev; 540 struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub]; 541 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); 542 unsigned eng = ring->vm_inv_eng; 543 544 /* 545 * It may lose gpuvm invalidate acknowldege state across power-gating 546 * off cycle, add semaphore acquire before invalidation and semaphore 547 * release after invalidation to avoid entering power gated state 548 * to WA the Issue 549 */ 550 551 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 552 if (use_semaphore) 553 /* a read return value of 1 means semaphore acuqire */ 554 amdgpu_ring_emit_reg_wait(ring, 555 hub->vm_inv_eng0_sem + eng, 0x1, 0x1); 556 557 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid), 558 lower_32_bits(pd_addr)); 559 560 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid), 561 upper_32_bits(pd_addr)); 562 563 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng, 564 hub->vm_inv_eng0_ack + eng, 565 req, 1 << vmid); 566 567 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 568 if (use_semaphore) 569 /* 570 * add semaphore release after invalidation, 571 * write with 0 means semaphore release 572 */ 573 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + eng, 0); 574 575 return pd_addr; 576 } 577 578 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 579 unsigned pasid) 580 { 581 struct amdgpu_device *adev = ring->adev; 582 uint32_t reg; 583 584 /* Do nothing because there's no lut register for mmhub1. */ 585 if (ring->funcs->vmhub == AMDGPU_MMHUB_1) 586 return; 587 588 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) 589 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 590 else 591 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 592 593 amdgpu_ring_emit_wreg(ring, reg, pasid); 594 } 595 596 /* 597 * PTE format on VEGA 10: 598 * 63:59 reserved 599 * 58:57 mtype 600 * 56 F 601 * 55 L 602 * 54 P 603 * 53 SW 604 * 52 T 605 * 50:48 reserved 606 * 47:12 4k physical page base address 607 * 11:7 fragment 608 * 6 write 609 * 5 read 610 * 4 exe 611 * 3 Z 612 * 2 snooped 613 * 1 system 614 * 0 valid 615 * 616 * PDE format on VEGA 10: 617 * 63:59 block fragment size 618 * 58:55 reserved 619 * 54 P 620 * 53:48 reserved 621 * 47:6 physical base address of PD or PTE 622 * 5:3 reserved 623 * 2 C 624 * 1 system 625 * 0 valid 626 */ 627 628 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 629 630 { 631 switch (flags) { 632 case AMDGPU_VM_MTYPE_DEFAULT: 633 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 634 case AMDGPU_VM_MTYPE_NC: 635 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 636 case AMDGPU_VM_MTYPE_WC: 637 return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC); 638 case AMDGPU_VM_MTYPE_RW: 639 return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW); 640 case AMDGPU_VM_MTYPE_CC: 641 return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC); 642 case AMDGPU_VM_MTYPE_UC: 643 return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC); 644 default: 645 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 646 } 647 } 648 649 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, 650 uint64_t *addr, uint64_t *flags) 651 { 652 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 653 *addr = adev->vm_manager.vram_base_offset + *addr - 654 adev->gmc.vram_start; 655 BUG_ON(*addr & 0xFFFF00000000003FULL); 656 657 if (!adev->gmc.translate_further) 658 return; 659 660 if (level == AMDGPU_VM_PDB1) { 661 /* Set the block fragment size */ 662 if (!(*flags & AMDGPU_PDE_PTE)) 663 *flags |= AMDGPU_PDE_BFS(0x9); 664 665 } else if (level == AMDGPU_VM_PDB0) { 666 if (*flags & AMDGPU_PDE_PTE) 667 *flags &= ~AMDGPU_PDE_PTE; 668 else 669 *flags |= AMDGPU_PTE_TF; 670 } 671 } 672 673 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev, 674 struct amdgpu_bo_va_mapping *mapping, 675 uint64_t *flags) 676 { 677 *flags &= ~AMDGPU_PTE_EXECUTABLE; 678 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 679 680 *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 681 *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK; 682 683 if (mapping->flags & AMDGPU_PTE_PRT) { 684 *flags |= AMDGPU_PTE_PRT; 685 *flags &= ~AMDGPU_PTE_VALID; 686 } 687 688 if (adev->asic_type == CHIP_ARCTURUS && 689 !(*flags & AMDGPU_PTE_SYSTEM) && 690 mapping->bo_va->is_xgmi) 691 *flags |= AMDGPU_PTE_SNOOPED; 692 } 693 694 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { 695 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, 696 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, 697 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, 698 .map_mtype = gmc_v9_0_map_mtype, 699 .get_vm_pde = gmc_v9_0_get_vm_pde, 700 .get_vm_pte = gmc_v9_0_get_vm_pte 701 }; 702 703 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) 704 { 705 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; 706 } 707 708 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) 709 { 710 switch (adev->asic_type) { 711 case CHIP_VEGA10: 712 adev->umc.funcs = &umc_v6_0_funcs; 713 break; 714 case CHIP_VEGA20: 715 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 716 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 717 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 718 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET; 719 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 720 adev->umc.funcs = &umc_v6_1_funcs; 721 break; 722 default: 723 break; 724 } 725 } 726 727 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) 728 { 729 switch (adev->asic_type) { 730 case CHIP_VEGA20: 731 adev->mmhub.funcs = &mmhub_v1_0_funcs; 732 break; 733 default: 734 break; 735 } 736 } 737 738 static int gmc_v9_0_early_init(void *handle) 739 { 740 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 741 742 gmc_v9_0_set_gmc_funcs(adev); 743 gmc_v9_0_set_irq_funcs(adev); 744 gmc_v9_0_set_umc_funcs(adev); 745 gmc_v9_0_set_mmhub_funcs(adev); 746 747 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 748 adev->gmc.shared_aperture_end = 749 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 750 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 751 adev->gmc.private_aperture_end = 752 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 753 754 return 0; 755 } 756 757 static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev) 758 { 759 760 /* 761 * TODO: 762 * Currently there is a bug where some memory client outside 763 * of the driver writes to first 8M of VRAM on S3 resume, 764 * this overrides GART which by default gets placed in first 8M and 765 * causes VM_FAULTS once GTT is accessed. 766 * Keep the stolen memory reservation until the while this is not solved. 767 * Also check code in gmc_v9_0_get_vbios_fb_size and gmc_v9_0_late_init 768 */ 769 switch (adev->asic_type) { 770 case CHIP_VEGA10: 771 case CHIP_RAVEN: 772 case CHIP_ARCTURUS: 773 case CHIP_RENOIR: 774 return true; 775 case CHIP_VEGA12: 776 case CHIP_VEGA20: 777 default: 778 return false; 779 } 780 } 781 782 static int gmc_v9_0_allocate_vm_inv_eng(struct amdgpu_device *adev) 783 { 784 struct amdgpu_ring *ring; 785 unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] = 786 {GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP, 787 GFXHUB_FREE_VM_INV_ENGS_BITMAP}; 788 unsigned i; 789 unsigned vmhub, inv_eng; 790 791 for (i = 0; i < adev->num_rings; ++i) { 792 ring = adev->rings[i]; 793 vmhub = ring->funcs->vmhub; 794 795 inv_eng = ffs(vm_inv_engs[vmhub]); 796 if (!inv_eng) { 797 dev_err(adev->dev, "no VM inv eng for ring %s\n", 798 ring->name); 799 return -EINVAL; 800 } 801 802 ring->vm_inv_eng = inv_eng - 1; 803 vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng); 804 805 dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n", 806 ring->name, ring->vm_inv_eng, ring->funcs->vmhub); 807 } 808 809 return 0; 810 } 811 812 static int gmc_v9_0_late_init(void *handle) 813 { 814 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 815 int r; 816 817 if (!gmc_v9_0_keep_stolen_memory(adev)) 818 amdgpu_bo_late_init(adev); 819 820 r = gmc_v9_0_allocate_vm_inv_eng(adev); 821 if (r) 822 return r; 823 /* Check if ecc is available */ 824 if (!amdgpu_sriov_vf(adev)) { 825 switch (adev->asic_type) { 826 case CHIP_VEGA10: 827 case CHIP_VEGA20: 828 r = amdgpu_atomfirmware_mem_ecc_supported(adev); 829 if (!r) { 830 DRM_INFO("ECC is not present.\n"); 831 if (adev->df_funcs->enable_ecc_force_par_wr_rmw) 832 adev->df_funcs->enable_ecc_force_par_wr_rmw(adev, false); 833 } else { 834 DRM_INFO("ECC is active.\n"); 835 } 836 837 r = amdgpu_atomfirmware_sram_ecc_supported(adev); 838 if (!r) { 839 DRM_INFO("SRAM ECC is not present.\n"); 840 } else { 841 DRM_INFO("SRAM ECC is active.\n"); 842 } 843 break; 844 default: 845 break; 846 } 847 } 848 849 r = amdgpu_gmc_ras_late_init(adev); 850 if (r) 851 return r; 852 853 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 854 } 855 856 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 857 struct amdgpu_gmc *mc) 858 { 859 u64 base = 0; 860 861 if (adev->asic_type == CHIP_ARCTURUS) 862 base = mmhub_v9_4_get_fb_location(adev); 863 else if (!amdgpu_sriov_vf(adev)) 864 base = mmhub_v1_0_get_fb_location(adev); 865 866 /* add the xgmi offset of the physical node */ 867 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 868 amdgpu_gmc_vram_location(adev, mc, base); 869 amdgpu_gmc_gart_location(adev, mc); 870 amdgpu_gmc_agp_location(adev, mc); 871 /* base offset of vram pages */ 872 adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev); 873 874 /* XXX: add the xgmi offset of the physical node? */ 875 adev->vm_manager.vram_base_offset += 876 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 877 } 878 879 /** 880 * gmc_v9_0_mc_init - initialize the memory controller driver params 881 * 882 * @adev: amdgpu_device pointer 883 * 884 * Look up the amount of vram, vram width, and decide how to place 885 * vram and gart within the GPU's physical address space. 886 * Returns 0 for success. 887 */ 888 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 889 { 890 int r; 891 892 /* size in MB on si */ 893 adev->gmc.mc_vram_size = 894 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 895 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 896 897 if (!(adev->flags & AMD_IS_APU)) { 898 r = amdgpu_device_resize_fb_bar(adev); 899 if (r) 900 return r; 901 } 902 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 903 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 904 905 #ifdef CONFIG_X86_64 906 if (adev->flags & AMD_IS_APU) { 907 adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev); 908 adev->gmc.aper_size = adev->gmc.real_vram_size; 909 } 910 #endif 911 /* In case the PCI BAR is larger than the actual amount of vram */ 912 adev->gmc.visible_vram_size = adev->gmc.aper_size; 913 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 914 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 915 916 /* set the gart size */ 917 if (amdgpu_gart_size == -1) { 918 switch (adev->asic_type) { 919 case CHIP_VEGA10: /* all engines support GPUVM */ 920 case CHIP_VEGA12: /* all engines support GPUVM */ 921 case CHIP_VEGA20: 922 case CHIP_ARCTURUS: 923 default: 924 adev->gmc.gart_size = 512ULL << 20; 925 break; 926 case CHIP_RAVEN: /* DCE SG support */ 927 case CHIP_RENOIR: 928 adev->gmc.gart_size = 1024ULL << 20; 929 break; 930 } 931 } else { 932 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 933 } 934 935 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); 936 937 return 0; 938 } 939 940 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 941 { 942 int r; 943 944 if (adev->gart.bo) { 945 WARN(1, "VEGA10 PCIE GART already initialized\n"); 946 return 0; 947 } 948 /* Initialize common gart structure */ 949 r = amdgpu_gart_init(adev); 950 if (r) 951 return r; 952 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 953 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) | 954 AMDGPU_PTE_EXECUTABLE; 955 return amdgpu_gart_table_vram_alloc(adev); 956 } 957 958 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 959 { 960 u32 d1vga_control; 961 unsigned size; 962 963 /* 964 * TODO Remove once GART corruption is resolved 965 * Check related code in gmc_v9_0_sw_fini 966 * */ 967 if (gmc_v9_0_keep_stolen_memory(adev)) 968 return 9 * 1024 * 1024; 969 970 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 971 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 972 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */ 973 } else { 974 u32 viewport; 975 976 switch (adev->asic_type) { 977 case CHIP_RAVEN: 978 case CHIP_RENOIR: 979 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 980 size = (REG_GET_FIELD(viewport, 981 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 982 REG_GET_FIELD(viewport, 983 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 984 4); 985 break; 986 case CHIP_VEGA10: 987 case CHIP_VEGA12: 988 case CHIP_VEGA20: 989 default: 990 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); 991 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 992 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * 993 4); 994 break; 995 } 996 } 997 /* return 0 if the pre-OS buffer uses up most of vram */ 998 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 999 return 0; 1000 1001 return size; 1002 } 1003 1004 static int gmc_v9_0_sw_init(void *handle) 1005 { 1006 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 1007 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1008 1009 gfxhub_v1_0_init(adev); 1010 if (adev->asic_type == CHIP_ARCTURUS) 1011 mmhub_v9_4_init(adev); 1012 else 1013 mmhub_v1_0_init(adev); 1014 1015 spin_lock_init(&adev->gmc.invalidate_lock); 1016 1017 r = amdgpu_atomfirmware_get_vram_info(adev, 1018 &vram_width, &vram_type, &vram_vendor); 1019 if (amdgpu_sriov_vf(adev)) 1020 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, 1021 * and DF related registers is not readable, seems hardcord is the 1022 * only way to set the correct vram_width 1023 */ 1024 adev->gmc.vram_width = 2048; 1025 else if (amdgpu_emu_mode != 1) 1026 adev->gmc.vram_width = vram_width; 1027 1028 if (!adev->gmc.vram_width) { 1029 int chansize, numchan; 1030 1031 /* hbm memory channel size */ 1032 if (adev->flags & AMD_IS_APU) 1033 chansize = 64; 1034 else 1035 chansize = 128; 1036 1037 numchan = adev->df_funcs->get_hbm_channel_number(adev); 1038 adev->gmc.vram_width = numchan * chansize; 1039 } 1040 1041 adev->gmc.vram_type = vram_type; 1042 adev->gmc.vram_vendor = vram_vendor; 1043 switch (adev->asic_type) { 1044 case CHIP_RAVEN: 1045 adev->num_vmhubs = 2; 1046 1047 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 1048 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1049 } else { 1050 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 1051 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 1052 adev->gmc.translate_further = 1053 adev->vm_manager.num_level > 1; 1054 } 1055 break; 1056 case CHIP_VEGA10: 1057 case CHIP_VEGA12: 1058 case CHIP_VEGA20: 1059 case CHIP_RENOIR: 1060 adev->num_vmhubs = 2; 1061 1062 1063 /* 1064 * To fulfill 4-level page support, 1065 * vm size is 256TB (48bit), maximum size of Vega10, 1066 * block size 512 (9bit) 1067 */ 1068 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */ 1069 if (amdgpu_sriov_vf(adev)) 1070 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47); 1071 else 1072 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1073 break; 1074 case CHIP_ARCTURUS: 1075 adev->num_vmhubs = 3; 1076 1077 /* Keep the vm size same with Vega20 */ 1078 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1079 break; 1080 default: 1081 break; 1082 } 1083 1084 /* This interrupt is VMC page fault.*/ 1085 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, 1086 &adev->gmc.vm_fault); 1087 if (r) 1088 return r; 1089 1090 if (adev->asic_type == CHIP_ARCTURUS) { 1091 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT, 1092 &adev->gmc.vm_fault); 1093 if (r) 1094 return r; 1095 } 1096 1097 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, 1098 &adev->gmc.vm_fault); 1099 1100 if (r) 1101 return r; 1102 1103 /* interrupt sent to DF. */ 1104 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 1105 &adev->gmc.ecc_irq); 1106 if (r) 1107 return r; 1108 1109 /* Set the internal MC address mask 1110 * This is the max address of the GPU's 1111 * internal address space. 1112 */ 1113 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 1114 1115 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 1116 if (r) { 1117 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 1118 return r; 1119 } 1120 adev->need_swiotlb = drm_need_swiotlb(44); 1121 1122 if (adev->gmc.xgmi.supported) { 1123 r = gfxhub_v1_1_get_xgmi_info(adev); 1124 if (r) 1125 return r; 1126 } 1127 1128 r = gmc_v9_0_mc_init(adev); 1129 if (r) 1130 return r; 1131 1132 adev->gmc.stolen_size = gmc_v9_0_get_vbios_fb_size(adev); 1133 1134 /* Memory manager */ 1135 r = amdgpu_bo_init(adev); 1136 if (r) 1137 return r; 1138 1139 r = gmc_v9_0_gart_init(adev); 1140 if (r) 1141 return r; 1142 1143 /* 1144 * number of VMs 1145 * VMID 0 is reserved for System 1146 * amdgpu graphics/compute will use VMIDs 1-7 1147 * amdkfd will use VMIDs 8-15 1148 */ 1149 adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; 1150 adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; 1151 adev->vm_manager.id_mgr[AMDGPU_MMHUB_1].num_ids = AMDGPU_NUM_OF_VMIDS; 1152 1153 amdgpu_vm_manager_init(adev); 1154 1155 return 0; 1156 } 1157 1158 static int gmc_v9_0_sw_fini(void *handle) 1159 { 1160 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1161 void *stolen_vga_buf; 1162 1163 amdgpu_gmc_ras_fini(adev); 1164 amdgpu_gem_force_release(adev); 1165 amdgpu_vm_manager_fini(adev); 1166 1167 if (gmc_v9_0_keep_stolen_memory(adev)) 1168 amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf); 1169 1170 amdgpu_gart_table_vram_free(adev); 1171 amdgpu_bo_fini(adev); 1172 amdgpu_gart_fini(adev); 1173 1174 return 0; 1175 } 1176 1177 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 1178 { 1179 1180 switch (adev->asic_type) { 1181 case CHIP_VEGA10: 1182 if (amdgpu_sriov_vf(adev)) 1183 break; 1184 /* fall through */ 1185 case CHIP_VEGA20: 1186 soc15_program_register_sequence(adev, 1187 golden_settings_mmhub_1_0_0, 1188 ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 1189 soc15_program_register_sequence(adev, 1190 golden_settings_athub_1_0_0, 1191 ARRAY_SIZE(golden_settings_athub_1_0_0)); 1192 break; 1193 case CHIP_VEGA12: 1194 break; 1195 case CHIP_RAVEN: 1196 /* TODO for renoir */ 1197 soc15_program_register_sequence(adev, 1198 golden_settings_athub_1_0_0, 1199 ARRAY_SIZE(golden_settings_athub_1_0_0)); 1200 break; 1201 default: 1202 break; 1203 } 1204 } 1205 1206 /** 1207 * gmc_v9_0_gart_enable - gart enable 1208 * 1209 * @adev: amdgpu_device pointer 1210 */ 1211 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 1212 { 1213 int r; 1214 1215 if (adev->gart.bo == NULL) { 1216 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 1217 return -EINVAL; 1218 } 1219 r = amdgpu_gart_table_vram_pin(adev); 1220 if (r) 1221 return r; 1222 1223 r = gfxhub_v1_0_gart_enable(adev); 1224 if (r) 1225 return r; 1226 1227 if (adev->asic_type == CHIP_ARCTURUS) 1228 r = mmhub_v9_4_gart_enable(adev); 1229 else 1230 r = mmhub_v1_0_gart_enable(adev); 1231 if (r) 1232 return r; 1233 1234 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1235 (unsigned)(adev->gmc.gart_size >> 20), 1236 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 1237 adev->gart.ready = true; 1238 return 0; 1239 } 1240 1241 static int gmc_v9_0_hw_init(void *handle) 1242 { 1243 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1244 bool value; 1245 int r, i; 1246 u32 tmp; 1247 1248 /* The sequence of these two function calls matters.*/ 1249 gmc_v9_0_init_golden_registers(adev); 1250 1251 if (adev->mode_info.num_crtc) { 1252 if (adev->asic_type != CHIP_ARCTURUS) { 1253 /* Lockout access through VGA aperture*/ 1254 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 1255 1256 /* disable VGA render */ 1257 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 1258 } 1259 } 1260 1261 amdgpu_device_program_register_sequence(adev, 1262 golden_settings_vega10_hdp, 1263 ARRAY_SIZE(golden_settings_vega10_hdp)); 1264 1265 switch (adev->asic_type) { 1266 case CHIP_RAVEN: 1267 /* TODO for renoir */ 1268 mmhub_v1_0_update_power_gating(adev, true); 1269 break; 1270 case CHIP_ARCTURUS: 1271 WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1); 1272 break; 1273 default: 1274 break; 1275 } 1276 1277 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1); 1278 1279 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL); 1280 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp); 1281 1282 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); 1283 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40)); 1284 1285 /* After HDP is initialized, flush HDP.*/ 1286 adev->nbio.funcs->hdp_flush(adev, NULL); 1287 1288 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 1289 value = false; 1290 else 1291 value = true; 1292 1293 gfxhub_v1_0_set_fault_enable_default(adev, value); 1294 if (adev->asic_type == CHIP_ARCTURUS) 1295 mmhub_v9_4_set_fault_enable_default(adev, value); 1296 else 1297 mmhub_v1_0_set_fault_enable_default(adev, value); 1298 1299 for (i = 0; i < adev->num_vmhubs; ++i) 1300 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0); 1301 1302 if (adev->umc.funcs && adev->umc.funcs->init_registers) 1303 adev->umc.funcs->init_registers(adev); 1304 1305 r = gmc_v9_0_gart_enable(adev); 1306 1307 return r; 1308 } 1309 1310 /** 1311 * gmc_v9_0_gart_disable - gart disable 1312 * 1313 * @adev: amdgpu_device pointer 1314 * 1315 * This disables all VM page table. 1316 */ 1317 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 1318 { 1319 gfxhub_v1_0_gart_disable(adev); 1320 if (adev->asic_type == CHIP_ARCTURUS) 1321 mmhub_v9_4_gart_disable(adev); 1322 else 1323 mmhub_v1_0_gart_disable(adev); 1324 amdgpu_gart_table_vram_unpin(adev); 1325 } 1326 1327 static int gmc_v9_0_hw_fini(void *handle) 1328 { 1329 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1330 1331 if (amdgpu_sriov_vf(adev)) { 1332 /* full access mode, so don't touch any GMC register */ 1333 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 1334 return 0; 1335 } 1336 1337 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 1338 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1339 gmc_v9_0_gart_disable(adev); 1340 1341 return 0; 1342 } 1343 1344 static int gmc_v9_0_suspend(void *handle) 1345 { 1346 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1347 1348 return gmc_v9_0_hw_fini(adev); 1349 } 1350 1351 static int gmc_v9_0_resume(void *handle) 1352 { 1353 int r; 1354 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1355 1356 r = gmc_v9_0_hw_init(adev); 1357 if (r) 1358 return r; 1359 1360 amdgpu_vmid_reset_all(adev); 1361 1362 return 0; 1363 } 1364 1365 static bool gmc_v9_0_is_idle(void *handle) 1366 { 1367 /* MC is always ready in GMC v9.*/ 1368 return true; 1369 } 1370 1371 static int gmc_v9_0_wait_for_idle(void *handle) 1372 { 1373 /* There is no need to wait for MC idle in GMC v9.*/ 1374 return 0; 1375 } 1376 1377 static int gmc_v9_0_soft_reset(void *handle) 1378 { 1379 /* XXX for emulation.*/ 1380 return 0; 1381 } 1382 1383 static int gmc_v9_0_set_clockgating_state(void *handle, 1384 enum amd_clockgating_state state) 1385 { 1386 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1387 1388 if (adev->asic_type == CHIP_ARCTURUS) 1389 mmhub_v9_4_set_clockgating(adev, state); 1390 else 1391 mmhub_v1_0_set_clockgating(adev, state); 1392 1393 athub_v1_0_set_clockgating(adev, state); 1394 1395 return 0; 1396 } 1397 1398 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags) 1399 { 1400 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1401 1402 if (adev->asic_type == CHIP_ARCTURUS) 1403 mmhub_v9_4_get_clockgating(adev, flags); 1404 else 1405 mmhub_v1_0_get_clockgating(adev, flags); 1406 1407 athub_v1_0_get_clockgating(adev, flags); 1408 } 1409 1410 static int gmc_v9_0_set_powergating_state(void *handle, 1411 enum amd_powergating_state state) 1412 { 1413 return 0; 1414 } 1415 1416 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 1417 .name = "gmc_v9_0", 1418 .early_init = gmc_v9_0_early_init, 1419 .late_init = gmc_v9_0_late_init, 1420 .sw_init = gmc_v9_0_sw_init, 1421 .sw_fini = gmc_v9_0_sw_fini, 1422 .hw_init = gmc_v9_0_hw_init, 1423 .hw_fini = gmc_v9_0_hw_fini, 1424 .suspend = gmc_v9_0_suspend, 1425 .resume = gmc_v9_0_resume, 1426 .is_idle = gmc_v9_0_is_idle, 1427 .wait_for_idle = gmc_v9_0_wait_for_idle, 1428 .soft_reset = gmc_v9_0_soft_reset, 1429 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 1430 .set_powergating_state = gmc_v9_0_set_powergating_state, 1431 .get_clockgating_state = gmc_v9_0_get_clockgating_state, 1432 }; 1433 1434 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = 1435 { 1436 .type = AMD_IP_BLOCK_TYPE_GMC, 1437 .major = 9, 1438 .minor = 0, 1439 .rev = 0, 1440 .funcs = &gmc_v9_0_ip_funcs, 1441 }; 1442