1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/pci.h> 26 27 #include <drm/drm_cache.h> 28 29 #include "amdgpu.h" 30 #include "gmc_v9_0.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_gem.h" 33 34 #include "gc/gc_9_0_sh_mask.h" 35 #include "dce/dce_12_0_offset.h" 36 #include "dce/dce_12_0_sh_mask.h" 37 #include "vega10_enum.h" 38 #include "mmhub/mmhub_1_0_offset.h" 39 #include "athub/athub_1_0_sh_mask.h" 40 #include "athub/athub_1_0_offset.h" 41 #include "oss/osssys_4_0_offset.h" 42 43 #include "soc15.h" 44 #include "soc15d.h" 45 #include "soc15_common.h" 46 #include "umc/umc_6_0_sh_mask.h" 47 48 #include "gfxhub_v1_0.h" 49 #include "mmhub_v1_0.h" 50 #include "athub_v1_0.h" 51 #include "gfxhub_v1_1.h" 52 #include "mmhub_v9_4.h" 53 #include "mmhub_v1_7.h" 54 #include "umc_v6_1.h" 55 #include "umc_v6_0.h" 56 #include "umc_v6_7.h" 57 #include "hdp_v4_0.h" 58 #include "mca_v3_0.h" 59 60 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 61 62 #include "amdgpu_ras.h" 63 #include "amdgpu_xgmi.h" 64 65 #include "amdgpu_reset.h" 66 67 /* add these here since we already include dce12 headers and these are for DCN */ 68 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 69 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 70 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 71 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 72 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL 73 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L 74 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d 75 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2 76 77 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2 0x05ea 78 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX 2 79 80 81 static const char *gfxhub_client_ids[] = { 82 "CB", 83 "DB", 84 "IA", 85 "WD", 86 "CPF", 87 "CPC", 88 "CPG", 89 "RLC", 90 "TCP", 91 "SQC (inst)", 92 "SQC (data)", 93 "SQG", 94 "PA", 95 }; 96 97 static const char *mmhub_client_ids_raven[][2] = { 98 [0][0] = "MP1", 99 [1][0] = "MP0", 100 [2][0] = "VCN", 101 [3][0] = "VCNU", 102 [4][0] = "HDP", 103 [5][0] = "DCE", 104 [13][0] = "UTCL2", 105 [19][0] = "TLS", 106 [26][0] = "OSS", 107 [27][0] = "SDMA0", 108 [0][1] = "MP1", 109 [1][1] = "MP0", 110 [2][1] = "VCN", 111 [3][1] = "VCNU", 112 [4][1] = "HDP", 113 [5][1] = "XDP", 114 [6][1] = "DBGU0", 115 [7][1] = "DCE", 116 [8][1] = "DCEDWB0", 117 [9][1] = "DCEDWB1", 118 [26][1] = "OSS", 119 [27][1] = "SDMA0", 120 }; 121 122 static const char *mmhub_client_ids_renoir[][2] = { 123 [0][0] = "MP1", 124 [1][0] = "MP0", 125 [2][0] = "HDP", 126 [4][0] = "DCEDMC", 127 [5][0] = "DCEVGA", 128 [13][0] = "UTCL2", 129 [19][0] = "TLS", 130 [26][0] = "OSS", 131 [27][0] = "SDMA0", 132 [28][0] = "VCN", 133 [29][0] = "VCNU", 134 [30][0] = "JPEG", 135 [0][1] = "MP1", 136 [1][1] = "MP0", 137 [2][1] = "HDP", 138 [3][1] = "XDP", 139 [6][1] = "DBGU0", 140 [7][1] = "DCEDMC", 141 [8][1] = "DCEVGA", 142 [9][1] = "DCEDWB", 143 [26][1] = "OSS", 144 [27][1] = "SDMA0", 145 [28][1] = "VCN", 146 [29][1] = "VCNU", 147 [30][1] = "JPEG", 148 }; 149 150 static const char *mmhub_client_ids_vega10[][2] = { 151 [0][0] = "MP0", 152 [1][0] = "UVD", 153 [2][0] = "UVDU", 154 [3][0] = "HDP", 155 [13][0] = "UTCL2", 156 [14][0] = "OSS", 157 [15][0] = "SDMA1", 158 [32+0][0] = "VCE0", 159 [32+1][0] = "VCE0U", 160 [32+2][0] = "XDMA", 161 [32+3][0] = "DCE", 162 [32+4][0] = "MP1", 163 [32+14][0] = "SDMA0", 164 [0][1] = "MP0", 165 [1][1] = "UVD", 166 [2][1] = "UVDU", 167 [3][1] = "DBGU0", 168 [4][1] = "HDP", 169 [5][1] = "XDP", 170 [14][1] = "OSS", 171 [15][1] = "SDMA0", 172 [32+0][1] = "VCE0", 173 [32+1][1] = "VCE0U", 174 [32+2][1] = "XDMA", 175 [32+3][1] = "DCE", 176 [32+4][1] = "DCEDWB", 177 [32+5][1] = "MP1", 178 [32+6][1] = "DBGU1", 179 [32+14][1] = "SDMA1", 180 }; 181 182 static const char *mmhub_client_ids_vega12[][2] = { 183 [0][0] = "MP0", 184 [1][0] = "VCE0", 185 [2][0] = "VCE0U", 186 [3][0] = "HDP", 187 [13][0] = "UTCL2", 188 [14][0] = "OSS", 189 [15][0] = "SDMA1", 190 [32+0][0] = "DCE", 191 [32+1][0] = "XDMA", 192 [32+2][0] = "UVD", 193 [32+3][0] = "UVDU", 194 [32+4][0] = "MP1", 195 [32+15][0] = "SDMA0", 196 [0][1] = "MP0", 197 [1][1] = "VCE0", 198 [2][1] = "VCE0U", 199 [3][1] = "DBGU0", 200 [4][1] = "HDP", 201 [5][1] = "XDP", 202 [14][1] = "OSS", 203 [15][1] = "SDMA0", 204 [32+0][1] = "DCE", 205 [32+1][1] = "DCEDWB", 206 [32+2][1] = "XDMA", 207 [32+3][1] = "UVD", 208 [32+4][1] = "UVDU", 209 [32+5][1] = "MP1", 210 [32+6][1] = "DBGU1", 211 [32+15][1] = "SDMA1", 212 }; 213 214 static const char *mmhub_client_ids_vega20[][2] = { 215 [0][0] = "XDMA", 216 [1][0] = "DCE", 217 [2][0] = "VCE0", 218 [3][0] = "VCE0U", 219 [4][0] = "UVD", 220 [5][0] = "UVD1U", 221 [13][0] = "OSS", 222 [14][0] = "HDP", 223 [15][0] = "SDMA0", 224 [32+0][0] = "UVD", 225 [32+1][0] = "UVDU", 226 [32+2][0] = "MP1", 227 [32+3][0] = "MP0", 228 [32+12][0] = "UTCL2", 229 [32+14][0] = "SDMA1", 230 [0][1] = "XDMA", 231 [1][1] = "DCE", 232 [2][1] = "DCEDWB", 233 [3][1] = "VCE0", 234 [4][1] = "VCE0U", 235 [5][1] = "UVD1", 236 [6][1] = "UVD1U", 237 [7][1] = "DBGU0", 238 [8][1] = "XDP", 239 [13][1] = "OSS", 240 [14][1] = "HDP", 241 [15][1] = "SDMA0", 242 [32+0][1] = "UVD", 243 [32+1][1] = "UVDU", 244 [32+2][1] = "DBGU1", 245 [32+3][1] = "MP1", 246 [32+4][1] = "MP0", 247 [32+14][1] = "SDMA1", 248 }; 249 250 static const char *mmhub_client_ids_arcturus[][2] = { 251 [0][0] = "DBGU1", 252 [1][0] = "XDP", 253 [2][0] = "MP1", 254 [14][0] = "HDP", 255 [171][0] = "JPEG", 256 [172][0] = "VCN", 257 [173][0] = "VCNU", 258 [203][0] = "JPEG1", 259 [204][0] = "VCN1", 260 [205][0] = "VCN1U", 261 [256][0] = "SDMA0", 262 [257][0] = "SDMA1", 263 [258][0] = "SDMA2", 264 [259][0] = "SDMA3", 265 [260][0] = "SDMA4", 266 [261][0] = "SDMA5", 267 [262][0] = "SDMA6", 268 [263][0] = "SDMA7", 269 [384][0] = "OSS", 270 [0][1] = "DBGU1", 271 [1][1] = "XDP", 272 [2][1] = "MP1", 273 [14][1] = "HDP", 274 [171][1] = "JPEG", 275 [172][1] = "VCN", 276 [173][1] = "VCNU", 277 [203][1] = "JPEG1", 278 [204][1] = "VCN1", 279 [205][1] = "VCN1U", 280 [256][1] = "SDMA0", 281 [257][1] = "SDMA1", 282 [258][1] = "SDMA2", 283 [259][1] = "SDMA3", 284 [260][1] = "SDMA4", 285 [261][1] = "SDMA5", 286 [262][1] = "SDMA6", 287 [263][1] = "SDMA7", 288 [384][1] = "OSS", 289 }; 290 291 static const char *mmhub_client_ids_aldebaran[][2] = { 292 [2][0] = "MP1", 293 [3][0] = "MP0", 294 [32+1][0] = "DBGU_IO0", 295 [32+2][0] = "DBGU_IO2", 296 [32+4][0] = "MPIO", 297 [96+11][0] = "JPEG0", 298 [96+12][0] = "VCN0", 299 [96+13][0] = "VCNU0", 300 [128+11][0] = "JPEG1", 301 [128+12][0] = "VCN1", 302 [128+13][0] = "VCNU1", 303 [160+1][0] = "XDP", 304 [160+14][0] = "HDP", 305 [256+0][0] = "SDMA0", 306 [256+1][0] = "SDMA1", 307 [256+2][0] = "SDMA2", 308 [256+3][0] = "SDMA3", 309 [256+4][0] = "SDMA4", 310 [384+0][0] = "OSS", 311 [2][1] = "MP1", 312 [3][1] = "MP0", 313 [32+1][1] = "DBGU_IO0", 314 [32+2][1] = "DBGU_IO2", 315 [32+4][1] = "MPIO", 316 [96+11][1] = "JPEG0", 317 [96+12][1] = "VCN0", 318 [96+13][1] = "VCNU0", 319 [128+11][1] = "JPEG1", 320 [128+12][1] = "VCN1", 321 [128+13][1] = "VCNU1", 322 [160+1][1] = "XDP", 323 [160+14][1] = "HDP", 324 [256+0][1] = "SDMA0", 325 [256+1][1] = "SDMA1", 326 [256+2][1] = "SDMA2", 327 [256+3][1] = "SDMA3", 328 [256+4][1] = "SDMA4", 329 [384+0][1] = "OSS", 330 }; 331 332 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = 333 { 334 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), 335 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) 336 }; 337 338 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = 339 { 340 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), 341 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) 342 }; 343 344 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { 345 (0x000143c0 + 0x00000000), 346 (0x000143c0 + 0x00000800), 347 (0x000143c0 + 0x00001000), 348 (0x000143c0 + 0x00001800), 349 (0x000543c0 + 0x00000000), 350 (0x000543c0 + 0x00000800), 351 (0x000543c0 + 0x00001000), 352 (0x000543c0 + 0x00001800), 353 (0x000943c0 + 0x00000000), 354 (0x000943c0 + 0x00000800), 355 (0x000943c0 + 0x00001000), 356 (0x000943c0 + 0x00001800), 357 (0x000d43c0 + 0x00000000), 358 (0x000d43c0 + 0x00000800), 359 (0x000d43c0 + 0x00001000), 360 (0x000d43c0 + 0x00001800), 361 (0x001143c0 + 0x00000000), 362 (0x001143c0 + 0x00000800), 363 (0x001143c0 + 0x00001000), 364 (0x001143c0 + 0x00001800), 365 (0x001543c0 + 0x00000000), 366 (0x001543c0 + 0x00000800), 367 (0x001543c0 + 0x00001000), 368 (0x001543c0 + 0x00001800), 369 (0x001943c0 + 0x00000000), 370 (0x001943c0 + 0x00000800), 371 (0x001943c0 + 0x00001000), 372 (0x001943c0 + 0x00001800), 373 (0x001d43c0 + 0x00000000), 374 (0x001d43c0 + 0x00000800), 375 (0x001d43c0 + 0x00001000), 376 (0x001d43c0 + 0x00001800), 377 }; 378 379 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { 380 (0x000143e0 + 0x00000000), 381 (0x000143e0 + 0x00000800), 382 (0x000143e0 + 0x00001000), 383 (0x000143e0 + 0x00001800), 384 (0x000543e0 + 0x00000000), 385 (0x000543e0 + 0x00000800), 386 (0x000543e0 + 0x00001000), 387 (0x000543e0 + 0x00001800), 388 (0x000943e0 + 0x00000000), 389 (0x000943e0 + 0x00000800), 390 (0x000943e0 + 0x00001000), 391 (0x000943e0 + 0x00001800), 392 (0x000d43e0 + 0x00000000), 393 (0x000d43e0 + 0x00000800), 394 (0x000d43e0 + 0x00001000), 395 (0x000d43e0 + 0x00001800), 396 (0x001143e0 + 0x00000000), 397 (0x001143e0 + 0x00000800), 398 (0x001143e0 + 0x00001000), 399 (0x001143e0 + 0x00001800), 400 (0x001543e0 + 0x00000000), 401 (0x001543e0 + 0x00000800), 402 (0x001543e0 + 0x00001000), 403 (0x001543e0 + 0x00001800), 404 (0x001943e0 + 0x00000000), 405 (0x001943e0 + 0x00000800), 406 (0x001943e0 + 0x00001000), 407 (0x001943e0 + 0x00001800), 408 (0x001d43e0 + 0x00000000), 409 (0x001d43e0 + 0x00000800), 410 (0x001d43e0 + 0x00001000), 411 (0x001d43e0 + 0x00001800), 412 }; 413 414 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, 415 struct amdgpu_irq_src *src, 416 unsigned type, 417 enum amdgpu_interrupt_state state) 418 { 419 u32 bits, i, tmp, reg; 420 421 /* Devices newer then VEGA10/12 shall have these programming 422 sequences performed by PSP BL */ 423 if (adev->asic_type >= CHIP_VEGA20) 424 return 0; 425 426 bits = 0x7f; 427 428 switch (state) { 429 case AMDGPU_IRQ_STATE_DISABLE: 430 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 431 reg = ecc_umc_mcumc_ctrl_addrs[i]; 432 tmp = RREG32(reg); 433 tmp &= ~bits; 434 WREG32(reg, tmp); 435 } 436 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 437 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 438 tmp = RREG32(reg); 439 tmp &= ~bits; 440 WREG32(reg, tmp); 441 } 442 break; 443 case AMDGPU_IRQ_STATE_ENABLE: 444 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 445 reg = ecc_umc_mcumc_ctrl_addrs[i]; 446 tmp = RREG32(reg); 447 tmp |= bits; 448 WREG32(reg, tmp); 449 } 450 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 451 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 452 tmp = RREG32(reg); 453 tmp |= bits; 454 WREG32(reg, tmp); 455 } 456 break; 457 default: 458 break; 459 } 460 461 return 0; 462 } 463 464 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 465 struct amdgpu_irq_src *src, 466 unsigned type, 467 enum amdgpu_interrupt_state state) 468 { 469 struct amdgpu_vmhub *hub; 470 u32 tmp, reg, bits, i, j; 471 472 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 473 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 474 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 475 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 476 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 477 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 478 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 479 480 switch (state) { 481 case AMDGPU_IRQ_STATE_DISABLE: 482 for (j = 0; j < adev->num_vmhubs; j++) { 483 hub = &adev->vmhub[j]; 484 for (i = 0; i < 16; i++) { 485 reg = hub->vm_context0_cntl + i; 486 487 /* This works because this interrupt is only 488 * enabled at init/resume and disabled in 489 * fini/suspend, so the overall state doesn't 490 * change over the course of suspend/resume. 491 */ 492 if (adev->in_s0ix && (j == AMDGPU_GFXHUB_0)) 493 continue; 494 495 if (j == AMDGPU_GFXHUB_0) 496 tmp = RREG32_SOC15_IP(GC, reg); 497 else 498 tmp = RREG32_SOC15_IP(MMHUB, reg); 499 500 tmp &= ~bits; 501 502 if (j == AMDGPU_GFXHUB_0) 503 WREG32_SOC15_IP(GC, reg, tmp); 504 else 505 WREG32_SOC15_IP(MMHUB, reg, tmp); 506 } 507 } 508 break; 509 case AMDGPU_IRQ_STATE_ENABLE: 510 for (j = 0; j < adev->num_vmhubs; j++) { 511 hub = &adev->vmhub[j]; 512 for (i = 0; i < 16; i++) { 513 reg = hub->vm_context0_cntl + i; 514 515 /* This works because this interrupt is only 516 * enabled at init/resume and disabled in 517 * fini/suspend, so the overall state doesn't 518 * change over the course of suspend/resume. 519 */ 520 if (adev->in_s0ix && (j == AMDGPU_GFXHUB_0)) 521 continue; 522 523 if (j == AMDGPU_GFXHUB_0) 524 tmp = RREG32_SOC15_IP(GC, reg); 525 else 526 tmp = RREG32_SOC15_IP(MMHUB, reg); 527 528 tmp |= bits; 529 530 if (j == AMDGPU_GFXHUB_0) 531 WREG32_SOC15_IP(GC, reg, tmp); 532 else 533 WREG32_SOC15_IP(MMHUB, reg, tmp); 534 } 535 } 536 break; 537 default: 538 break; 539 } 540 541 return 0; 542 } 543 544 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 545 struct amdgpu_irq_src *source, 546 struct amdgpu_iv_entry *entry) 547 { 548 bool retry_fault = !!(entry->src_data[1] & 0x80); 549 bool write_fault = !!(entry->src_data[1] & 0x20); 550 uint32_t status = 0, cid = 0, rw = 0; 551 struct amdgpu_task_info task_info; 552 struct amdgpu_vmhub *hub; 553 const char *mmhub_cid; 554 const char *hub_name; 555 u64 addr; 556 557 addr = (u64)entry->src_data[0] << 12; 558 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 559 560 if (retry_fault) { 561 /* Returning 1 here also prevents sending the IV to the KFD */ 562 563 /* Process it onyl if it's the first fault for this address */ 564 if (entry->ih != &adev->irq.ih_soft && 565 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, 566 entry->timestamp)) 567 return 1; 568 569 /* Delegate it to a different ring if the hardware hasn't 570 * already done it. 571 */ 572 if (entry->ih == &adev->irq.ih) { 573 amdgpu_irq_delegate(adev, entry, 8); 574 return 1; 575 } 576 577 /* Try to handle the recoverable page faults by filling page 578 * tables 579 */ 580 if (amdgpu_vm_handle_fault(adev, entry->pasid, addr, write_fault)) 581 return 1; 582 } 583 584 if (!printk_ratelimit()) 585 return 0; 586 587 if (entry->client_id == SOC15_IH_CLIENTID_VMC) { 588 hub_name = "mmhub0"; 589 hub = &adev->vmhub[AMDGPU_MMHUB_0]; 590 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) { 591 hub_name = "mmhub1"; 592 hub = &adev->vmhub[AMDGPU_MMHUB_1]; 593 } else { 594 hub_name = "gfxhub0"; 595 hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 596 } 597 598 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 599 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 600 601 dev_err(adev->dev, 602 "[%s] %s page fault (src_id:%u ring:%u vmid:%u " 603 "pasid:%u, for process %s pid %d thread %s pid %d)\n", 604 hub_name, retry_fault ? "retry" : "no-retry", 605 entry->src_id, entry->ring_id, entry->vmid, 606 entry->pasid, task_info.process_name, task_info.tgid, 607 task_info.task_name, task_info.pid); 608 dev_err(adev->dev, " in page starting at address 0x%016llx from IH client 0x%x (%s)\n", 609 addr, entry->client_id, 610 soc15_ih_clientid_name[entry->client_id]); 611 612 if (amdgpu_sriov_vf(adev)) 613 return 0; 614 615 /* 616 * Issue a dummy read to wait for the status register to 617 * be updated to avoid reading an incorrect value due to 618 * the new fast GRBM interface. 619 */ 620 if ((entry->vmid_src == AMDGPU_GFXHUB_0) && 621 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2))) 622 RREG32(hub->vm_l2_pro_fault_status); 623 624 status = RREG32(hub->vm_l2_pro_fault_status); 625 cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID); 626 rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW); 627 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 628 629 630 dev_err(adev->dev, 631 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 632 status); 633 if (hub == &adev->vmhub[AMDGPU_GFXHUB_0]) { 634 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 635 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : 636 gfxhub_client_ids[cid], 637 cid); 638 } else { 639 switch (adev->ip_versions[MMHUB_HWIP][0]) { 640 case IP_VERSION(9, 0, 0): 641 mmhub_cid = mmhub_client_ids_vega10[cid][rw]; 642 break; 643 case IP_VERSION(9, 3, 0): 644 mmhub_cid = mmhub_client_ids_vega12[cid][rw]; 645 break; 646 case IP_VERSION(9, 4, 0): 647 mmhub_cid = mmhub_client_ids_vega20[cid][rw]; 648 break; 649 case IP_VERSION(9, 4, 1): 650 mmhub_cid = mmhub_client_ids_arcturus[cid][rw]; 651 break; 652 case IP_VERSION(9, 1, 0): 653 case IP_VERSION(9, 2, 0): 654 mmhub_cid = mmhub_client_ids_raven[cid][rw]; 655 break; 656 case IP_VERSION(1, 5, 0): 657 case IP_VERSION(2, 4, 0): 658 mmhub_cid = mmhub_client_ids_renoir[cid][rw]; 659 break; 660 case IP_VERSION(9, 4, 2): 661 mmhub_cid = mmhub_client_ids_aldebaran[cid][rw]; 662 break; 663 default: 664 mmhub_cid = NULL; 665 break; 666 } 667 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 668 mmhub_cid ? mmhub_cid : "unknown", cid); 669 } 670 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 671 REG_GET_FIELD(status, 672 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 673 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 674 REG_GET_FIELD(status, 675 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 676 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 677 REG_GET_FIELD(status, 678 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 679 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 680 REG_GET_FIELD(status, 681 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 682 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 683 return 0; 684 } 685 686 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 687 .set = gmc_v9_0_vm_fault_interrupt_state, 688 .process = gmc_v9_0_process_interrupt, 689 }; 690 691 692 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { 693 .set = gmc_v9_0_ecc_interrupt_state, 694 .process = amdgpu_umc_process_ecc_irq, 695 }; 696 697 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 698 { 699 adev->gmc.vm_fault.num_types = 1; 700 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 701 702 if (!amdgpu_sriov_vf(adev) && 703 !adev->gmc.xgmi.connected_to_cpu) { 704 adev->gmc.ecc_irq.num_types = 1; 705 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; 706 } 707 } 708 709 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, 710 uint32_t flush_type) 711 { 712 u32 req = 0; 713 714 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 715 PER_VMID_INVALIDATE_REQ, 1 << vmid); 716 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 717 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 718 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 719 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 720 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 721 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 722 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 723 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 724 725 return req; 726 } 727 728 /** 729 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore 730 * 731 * @adev: amdgpu_device pointer 732 * @vmhub: vmhub type 733 * 734 */ 735 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev, 736 uint32_t vmhub) 737 { 738 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) 739 return false; 740 741 return ((vmhub == AMDGPU_MMHUB_0 || 742 vmhub == AMDGPU_MMHUB_1) && 743 (!amdgpu_sriov_vf(adev)) && 744 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) && 745 (adev->apu_flags & AMD_APU_IS_PICASSO)))); 746 } 747 748 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, 749 uint8_t vmid, uint16_t *p_pasid) 750 { 751 uint32_t value; 752 753 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 754 + vmid); 755 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 756 757 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 758 } 759 760 /* 761 * GART 762 * VMID 0 is the physical GPU addresses as used by the kernel. 763 * VMIDs 1-15 are used for userspace clients and are handled 764 * by the amdgpu vm/hsa code. 765 */ 766 767 /** 768 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type 769 * 770 * @adev: amdgpu_device pointer 771 * @vmid: vm instance to flush 772 * @vmhub: which hub to flush 773 * @flush_type: the flush type 774 * 775 * Flush the TLB for the requested page table using certain type. 776 */ 777 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 778 uint32_t vmhub, uint32_t flush_type) 779 { 780 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub); 781 const unsigned eng = 17; 782 u32 j, inv_req, inv_req2, tmp; 783 struct amdgpu_vmhub *hub; 784 785 BUG_ON(vmhub >= adev->num_vmhubs); 786 787 hub = &adev->vmhub[vmhub]; 788 if (adev->gmc.xgmi.num_physical_nodes && 789 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0)) { 790 /* Vega20+XGMI caches PTEs in TC and TLB. Add a 791 * heavy-weight TLB flush (type 2), which flushes 792 * both. Due to a race condition with concurrent 793 * memory accesses using the same TLB cache line, we 794 * still need a second TLB flush after this. 795 */ 796 inv_req = gmc_v9_0_get_invalidate_req(vmid, 2); 797 inv_req2 = gmc_v9_0_get_invalidate_req(vmid, flush_type); 798 } else { 799 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type); 800 inv_req2 = 0; 801 } 802 803 /* This is necessary for a HW workaround under SRIOV as well 804 * as GFXOFF under bare metal 805 */ 806 if (adev->gfx.kiq.ring.sched.ready && 807 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && 808 down_read_trylock(&adev->reset_domain->sem)) { 809 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 810 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 811 812 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 813 1 << vmid); 814 up_read(&adev->reset_domain->sem); 815 return; 816 } 817 818 spin_lock(&adev->gmc.invalidate_lock); 819 820 /* 821 * It may lose gpuvm invalidate acknowldege state across power-gating 822 * off cycle, add semaphore acquire before invalidation and semaphore 823 * release after invalidation to avoid entering power gated state 824 * to WA the Issue 825 */ 826 827 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 828 if (use_semaphore) { 829 for (j = 0; j < adev->usec_timeout; j++) { 830 /* a read return value of 1 means semaphore acquire */ 831 if (vmhub == AMDGPU_GFXHUB_0) 832 tmp = RREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_sem + hub->eng_distance * eng); 833 else 834 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_sem + hub->eng_distance * eng); 835 836 if (tmp & 0x1) 837 break; 838 udelay(1); 839 } 840 841 if (j >= adev->usec_timeout) 842 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 843 } 844 845 do { 846 if (vmhub == AMDGPU_GFXHUB_0) 847 WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req); 848 else 849 WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req); 850 851 /* 852 * Issue a dummy read to wait for the ACK register to 853 * be cleared to avoid a false ACK due to the new fast 854 * GRBM interface. 855 */ 856 if ((vmhub == AMDGPU_GFXHUB_0) && 857 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2))) 858 RREG32_NO_KIQ(hub->vm_inv_eng0_req + 859 hub->eng_distance * eng); 860 861 for (j = 0; j < adev->usec_timeout; j++) { 862 if (vmhub == AMDGPU_GFXHUB_0) 863 tmp = RREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_ack + hub->eng_distance * eng); 864 else 865 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_ack + hub->eng_distance * eng); 866 867 if (tmp & (1 << vmid)) 868 break; 869 udelay(1); 870 } 871 872 inv_req = inv_req2; 873 inv_req2 = 0; 874 } while (inv_req); 875 876 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 877 if (use_semaphore) { 878 /* 879 * add semaphore release after invalidation, 880 * write with 0 means semaphore release 881 */ 882 if (vmhub == AMDGPU_GFXHUB_0) 883 WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_sem + hub->eng_distance * eng, 0); 884 else 885 WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_sem + hub->eng_distance * eng, 0); 886 } 887 888 spin_unlock(&adev->gmc.invalidate_lock); 889 890 if (j < adev->usec_timeout) 891 return; 892 893 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 894 } 895 896 /** 897 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid 898 * 899 * @adev: amdgpu_device pointer 900 * @pasid: pasid to be flush 901 * @flush_type: the flush type 902 * @all_hub: flush all hubs 903 * 904 * Flush the TLB for the requested pasid. 905 */ 906 static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 907 uint16_t pasid, uint32_t flush_type, 908 bool all_hub) 909 { 910 int vmid, i; 911 signed long r; 912 uint32_t seq; 913 uint16_t queried_pasid; 914 bool ret; 915 u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT : adev->usec_timeout; 916 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 917 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 918 919 if (amdgpu_in_reset(adev)) 920 return -EIO; 921 922 if (ring->sched.ready && down_read_trylock(&adev->reset_domain->sem)) { 923 /* Vega20+XGMI caches PTEs in TC and TLB. Add a 924 * heavy-weight TLB flush (type 2), which flushes 925 * both. Due to a race condition with concurrent 926 * memory accesses using the same TLB cache line, we 927 * still need a second TLB flush after this. 928 */ 929 bool vega20_xgmi_wa = (adev->gmc.xgmi.num_physical_nodes && 930 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0)); 931 /* 2 dwords flush + 8 dwords fence */ 932 unsigned int ndw = kiq->pmf->invalidate_tlbs_size + 8; 933 934 if (vega20_xgmi_wa) 935 ndw += kiq->pmf->invalidate_tlbs_size; 936 937 spin_lock(&adev->gfx.kiq.ring_lock); 938 /* 2 dwords flush + 8 dwords fence */ 939 amdgpu_ring_alloc(ring, ndw); 940 if (vega20_xgmi_wa) 941 kiq->pmf->kiq_invalidate_tlbs(ring, 942 pasid, 2, all_hub); 943 kiq->pmf->kiq_invalidate_tlbs(ring, 944 pasid, flush_type, all_hub); 945 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 946 if (r) { 947 amdgpu_ring_undo(ring); 948 spin_unlock(&adev->gfx.kiq.ring_lock); 949 up_read(&adev->reset_domain->sem); 950 return -ETIME; 951 } 952 953 amdgpu_ring_commit(ring); 954 spin_unlock(&adev->gfx.kiq.ring_lock); 955 r = amdgpu_fence_wait_polling(ring, seq, usec_timeout); 956 if (r < 1) { 957 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r); 958 up_read(&adev->reset_domain->sem); 959 return -ETIME; 960 } 961 up_read(&adev->reset_domain->sem); 962 return 0; 963 } 964 965 for (vmid = 1; vmid < 16; vmid++) { 966 967 ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 968 &queried_pasid); 969 if (ret && queried_pasid == pasid) { 970 if (all_hub) { 971 for (i = 0; i < adev->num_vmhubs; i++) 972 gmc_v9_0_flush_gpu_tlb(adev, vmid, 973 i, flush_type); 974 } else { 975 gmc_v9_0_flush_gpu_tlb(adev, vmid, 976 AMDGPU_GFXHUB_0, flush_type); 977 } 978 break; 979 } 980 } 981 982 return 0; 983 984 } 985 986 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 987 unsigned vmid, uint64_t pd_addr) 988 { 989 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub); 990 struct amdgpu_device *adev = ring->adev; 991 struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub]; 992 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); 993 unsigned eng = ring->vm_inv_eng; 994 995 /* 996 * It may lose gpuvm invalidate acknowldege state across power-gating 997 * off cycle, add semaphore acquire before invalidation and semaphore 998 * release after invalidation to avoid entering power gated state 999 * to WA the Issue 1000 */ 1001 1002 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 1003 if (use_semaphore) 1004 /* a read return value of 1 means semaphore acuqire */ 1005 amdgpu_ring_emit_reg_wait(ring, 1006 hub->vm_inv_eng0_sem + 1007 hub->eng_distance * eng, 0x1, 0x1); 1008 1009 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 1010 (hub->ctx_addr_distance * vmid), 1011 lower_32_bits(pd_addr)); 1012 1013 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 1014 (hub->ctx_addr_distance * vmid), 1015 upper_32_bits(pd_addr)); 1016 1017 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 1018 hub->eng_distance * eng, 1019 hub->vm_inv_eng0_ack + 1020 hub->eng_distance * eng, 1021 req, 1 << vmid); 1022 1023 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 1024 if (use_semaphore) 1025 /* 1026 * add semaphore release after invalidation, 1027 * write with 0 means semaphore release 1028 */ 1029 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 1030 hub->eng_distance * eng, 0); 1031 1032 return pd_addr; 1033 } 1034 1035 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 1036 unsigned pasid) 1037 { 1038 struct amdgpu_device *adev = ring->adev; 1039 uint32_t reg; 1040 1041 /* Do nothing because there's no lut register for mmhub1. */ 1042 if (ring->funcs->vmhub == AMDGPU_MMHUB_1) 1043 return; 1044 1045 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) 1046 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 1047 else 1048 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 1049 1050 amdgpu_ring_emit_wreg(ring, reg, pasid); 1051 } 1052 1053 /* 1054 * PTE format on VEGA 10: 1055 * 63:59 reserved 1056 * 58:57 mtype 1057 * 56 F 1058 * 55 L 1059 * 54 P 1060 * 53 SW 1061 * 52 T 1062 * 50:48 reserved 1063 * 47:12 4k physical page base address 1064 * 11:7 fragment 1065 * 6 write 1066 * 5 read 1067 * 4 exe 1068 * 3 Z 1069 * 2 snooped 1070 * 1 system 1071 * 0 valid 1072 * 1073 * PDE format on VEGA 10: 1074 * 63:59 block fragment size 1075 * 58:55 reserved 1076 * 54 P 1077 * 53:48 reserved 1078 * 47:6 physical base address of PD or PTE 1079 * 5:3 reserved 1080 * 2 C 1081 * 1 system 1082 * 0 valid 1083 */ 1084 1085 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 1086 1087 { 1088 switch (flags) { 1089 case AMDGPU_VM_MTYPE_DEFAULT: 1090 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1091 case AMDGPU_VM_MTYPE_NC: 1092 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1093 case AMDGPU_VM_MTYPE_WC: 1094 return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC); 1095 case AMDGPU_VM_MTYPE_RW: 1096 return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW); 1097 case AMDGPU_VM_MTYPE_CC: 1098 return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC); 1099 case AMDGPU_VM_MTYPE_UC: 1100 return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC); 1101 default: 1102 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1103 } 1104 } 1105 1106 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, 1107 uint64_t *addr, uint64_t *flags) 1108 { 1109 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 1110 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 1111 BUG_ON(*addr & 0xFFFF00000000003FULL); 1112 1113 if (!adev->gmc.translate_further) 1114 return; 1115 1116 if (level == AMDGPU_VM_PDB1) { 1117 /* Set the block fragment size */ 1118 if (!(*flags & AMDGPU_PDE_PTE)) 1119 *flags |= AMDGPU_PDE_BFS(0x9); 1120 1121 } else if (level == AMDGPU_VM_PDB0) { 1122 if (*flags & AMDGPU_PDE_PTE) { 1123 *flags &= ~AMDGPU_PDE_PTE; 1124 if (!(*flags & AMDGPU_PTE_VALID)) 1125 *addr |= 1 << PAGE_SHIFT; 1126 } else { 1127 *flags |= AMDGPU_PTE_TF; 1128 } 1129 } 1130 } 1131 1132 static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev, 1133 struct amdgpu_bo *bo, 1134 struct amdgpu_bo_va_mapping *mapping, 1135 uint64_t *flags) 1136 { 1137 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev); 1138 bool is_vram = bo->tbo.resource->mem_type == TTM_PL_VRAM; 1139 bool coherent = bo->flags & AMDGPU_GEM_CREATE_COHERENT; 1140 bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED; 1141 unsigned int mtype; 1142 bool snoop = false; 1143 1144 switch (adev->ip_versions[GC_HWIP][0]) { 1145 case IP_VERSION(9, 4, 1): 1146 case IP_VERSION(9, 4, 2): 1147 if (is_vram) { 1148 if (bo_adev == adev) { 1149 if (uncached) 1150 mtype = MTYPE_UC; 1151 else if (coherent) 1152 mtype = MTYPE_CC; 1153 else 1154 mtype = MTYPE_RW; 1155 /* FIXME: is this still needed? Or does 1156 * amdgpu_ttm_tt_pde_flags already handle this? 1157 */ 1158 if (adev->ip_versions[GC_HWIP][0] == 1159 IP_VERSION(9, 4, 2) && 1160 adev->gmc.xgmi.connected_to_cpu) 1161 snoop = true; 1162 } else { 1163 if (uncached || coherent) 1164 mtype = MTYPE_UC; 1165 else 1166 mtype = MTYPE_NC; 1167 if (mapping->bo_va->is_xgmi) 1168 snoop = true; 1169 } 1170 } else { 1171 if (uncached || coherent) 1172 mtype = MTYPE_UC; 1173 else 1174 mtype = MTYPE_NC; 1175 /* FIXME: is this still needed? Or does 1176 * amdgpu_ttm_tt_pde_flags already handle this? 1177 */ 1178 snoop = true; 1179 } 1180 break; 1181 default: 1182 if (uncached || coherent) 1183 mtype = MTYPE_UC; 1184 else 1185 mtype = MTYPE_NC; 1186 1187 /* FIXME: is this still needed? Or does 1188 * amdgpu_ttm_tt_pde_flags already handle this? 1189 */ 1190 if (!is_vram) 1191 snoop = true; 1192 } 1193 1194 if (mtype != MTYPE_NC) 1195 *flags = (*flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) | 1196 AMDGPU_PTE_MTYPE_VG10(mtype); 1197 *flags |= snoop ? AMDGPU_PTE_SNOOPED : 0; 1198 } 1199 1200 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev, 1201 struct amdgpu_bo_va_mapping *mapping, 1202 uint64_t *flags) 1203 { 1204 struct amdgpu_bo *bo = mapping->bo_va->base.bo; 1205 1206 *flags &= ~AMDGPU_PTE_EXECUTABLE; 1207 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 1208 1209 *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 1210 *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK; 1211 1212 if (mapping->flags & AMDGPU_PTE_PRT) { 1213 *flags |= AMDGPU_PTE_PRT; 1214 *flags &= ~AMDGPU_PTE_VALID; 1215 } 1216 1217 if (bo && bo->tbo.resource) 1218 gmc_v9_0_get_coherence_flags(adev, mapping->bo_va->base.bo, 1219 mapping, flags); 1220 } 1221 1222 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 1223 { 1224 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 1225 unsigned size; 1226 1227 /* TODO move to DC so GMC doesn't need to hard-code DCN registers */ 1228 1229 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1230 size = AMDGPU_VBIOS_VGA_ALLOCATION; 1231 } else { 1232 u32 viewport; 1233 1234 switch (adev->ip_versions[DCE_HWIP][0]) { 1235 case IP_VERSION(1, 0, 0): 1236 case IP_VERSION(1, 0, 1): 1237 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 1238 size = (REG_GET_FIELD(viewport, 1239 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1240 REG_GET_FIELD(viewport, 1241 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1242 4); 1243 break; 1244 case IP_VERSION(2, 1, 0): 1245 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2); 1246 size = (REG_GET_FIELD(viewport, 1247 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1248 REG_GET_FIELD(viewport, 1249 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1250 4); 1251 break; 1252 default: 1253 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); 1254 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1255 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1256 4); 1257 break; 1258 } 1259 } 1260 1261 return size; 1262 } 1263 1264 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { 1265 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, 1266 .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid, 1267 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, 1268 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, 1269 .map_mtype = gmc_v9_0_map_mtype, 1270 .get_vm_pde = gmc_v9_0_get_vm_pde, 1271 .get_vm_pte = gmc_v9_0_get_vm_pte, 1272 .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size, 1273 }; 1274 1275 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) 1276 { 1277 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; 1278 } 1279 1280 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) 1281 { 1282 switch (adev->ip_versions[UMC_HWIP][0]) { 1283 case IP_VERSION(6, 0, 0): 1284 adev->umc.funcs = &umc_v6_0_funcs; 1285 break; 1286 case IP_VERSION(6, 1, 1): 1287 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1288 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1289 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1290 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20; 1291 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1292 adev->umc.ras = &umc_v6_1_ras; 1293 break; 1294 case IP_VERSION(6, 1, 2): 1295 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1296 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1297 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1298 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT; 1299 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1300 adev->umc.ras = &umc_v6_1_ras; 1301 break; 1302 case IP_VERSION(6, 7, 0): 1303 adev->umc.max_ras_err_cnt_per_query = 1304 UMC_V6_7_TOTAL_CHANNEL_NUM * UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL; 1305 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM; 1306 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM; 1307 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET; 1308 if (!adev->gmc.xgmi.connected_to_cpu) 1309 adev->umc.ras = &umc_v6_7_ras; 1310 if (1 & adev->smuio.funcs->get_die_id(adev)) 1311 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0]; 1312 else 1313 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0]; 1314 break; 1315 default: 1316 break; 1317 } 1318 1319 if (adev->umc.ras) { 1320 amdgpu_ras_register_ras_block(adev, &adev->umc.ras->ras_block); 1321 1322 strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc"); 1323 adev->umc.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC; 1324 adev->umc.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; 1325 adev->umc.ras_if = &adev->umc.ras->ras_block.ras_comm; 1326 1327 /* If don't define special ras_late_init function, use default ras_late_init */ 1328 if (!adev->umc.ras->ras_block.ras_late_init) 1329 adev->umc.ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init; 1330 1331 /* If not defined special ras_cb function, use default ras_cb */ 1332 if (!adev->umc.ras->ras_block.ras_cb) 1333 adev->umc.ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb; 1334 } 1335 } 1336 1337 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) 1338 { 1339 switch (adev->ip_versions[MMHUB_HWIP][0]) { 1340 case IP_VERSION(9, 4, 1): 1341 adev->mmhub.funcs = &mmhub_v9_4_funcs; 1342 break; 1343 case IP_VERSION(9, 4, 2): 1344 adev->mmhub.funcs = &mmhub_v1_7_funcs; 1345 break; 1346 default: 1347 adev->mmhub.funcs = &mmhub_v1_0_funcs; 1348 break; 1349 } 1350 } 1351 1352 static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev) 1353 { 1354 switch (adev->ip_versions[MMHUB_HWIP][0]) { 1355 case IP_VERSION(9, 4, 0): 1356 adev->mmhub.ras = &mmhub_v1_0_ras; 1357 break; 1358 case IP_VERSION(9, 4, 1): 1359 adev->mmhub.ras = &mmhub_v9_4_ras; 1360 break; 1361 case IP_VERSION(9, 4, 2): 1362 adev->mmhub.ras = &mmhub_v1_7_ras; 1363 break; 1364 default: 1365 /* mmhub ras is not available */ 1366 break; 1367 } 1368 1369 if (adev->mmhub.ras) { 1370 amdgpu_ras_register_ras_block(adev, &adev->mmhub.ras->ras_block); 1371 1372 strcpy(adev->mmhub.ras->ras_block.ras_comm.name, "mmhub"); 1373 adev->mmhub.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MMHUB; 1374 adev->mmhub.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; 1375 adev->mmhub.ras_if = &adev->mmhub.ras->ras_block.ras_comm; 1376 } 1377 } 1378 1379 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev) 1380 { 1381 adev->gfxhub.funcs = &gfxhub_v1_0_funcs; 1382 } 1383 1384 static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev) 1385 { 1386 adev->hdp.ras = &hdp_v4_0_ras; 1387 amdgpu_ras_register_ras_block(adev, &adev->hdp.ras->ras_block); 1388 adev->hdp.ras_if = &adev->hdp.ras->ras_block.ras_comm; 1389 } 1390 1391 static void gmc_v9_0_set_mca_funcs(struct amdgpu_device *adev) 1392 { 1393 /* is UMC the right IP to check for MCA? Maybe DF? */ 1394 switch (adev->ip_versions[UMC_HWIP][0]) { 1395 case IP_VERSION(6, 7, 0): 1396 if (!adev->gmc.xgmi.connected_to_cpu) 1397 adev->mca.funcs = &mca_v3_0_funcs; 1398 break; 1399 default: 1400 break; 1401 } 1402 } 1403 1404 static int gmc_v9_0_early_init(void *handle) 1405 { 1406 int r; 1407 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1408 1409 /* ARCT and VEGA20 don't have XGMI defined in their IP discovery tables */ 1410 if (adev->asic_type == CHIP_VEGA20 || 1411 adev->asic_type == CHIP_ARCTURUS) 1412 adev->gmc.xgmi.supported = true; 1413 1414 if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(6, 1, 0)) { 1415 adev->gmc.xgmi.supported = true; 1416 adev->gmc.xgmi.connected_to_cpu = 1417 adev->smuio.funcs->is_host_gpu_xgmi_supported(adev); 1418 } 1419 1420 gmc_v9_0_set_gmc_funcs(adev); 1421 gmc_v9_0_set_irq_funcs(adev); 1422 gmc_v9_0_set_umc_funcs(adev); 1423 gmc_v9_0_set_mmhub_funcs(adev); 1424 gmc_v9_0_set_mmhub_ras_funcs(adev); 1425 gmc_v9_0_set_gfxhub_funcs(adev); 1426 gmc_v9_0_set_hdp_ras_funcs(adev); 1427 gmc_v9_0_set_mca_funcs(adev); 1428 1429 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1430 adev->gmc.shared_aperture_end = 1431 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1432 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 1433 adev->gmc.private_aperture_end = 1434 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1435 1436 r = amdgpu_gmc_ras_early_init(adev); 1437 if (r) 1438 return r; 1439 1440 return 0; 1441 } 1442 1443 static int gmc_v9_0_late_init(void *handle) 1444 { 1445 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1446 int r; 1447 1448 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 1449 if (r) 1450 return r; 1451 1452 /* 1453 * Workaround performance drop issue with VBIOS enables partial 1454 * writes, while disables HBM ECC for vega10. 1455 */ 1456 if (!amdgpu_sriov_vf(adev) && 1457 (adev->ip_versions[UMC_HWIP][0] == IP_VERSION(6, 0, 0))) { 1458 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) { 1459 if (adev->df.funcs && 1460 adev->df.funcs->enable_ecc_force_par_wr_rmw) 1461 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false); 1462 } 1463 } 1464 1465 if (!amdgpu_persistent_edc_harvesting_supported(adev)) { 1466 if (adev->mmhub.ras && adev->mmhub.ras->ras_block.hw_ops && 1467 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count) 1468 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(adev); 1469 1470 if (adev->hdp.ras && adev->hdp.ras->ras_block.hw_ops && 1471 adev->hdp.ras->ras_block.hw_ops->reset_ras_error_count) 1472 adev->hdp.ras->ras_block.hw_ops->reset_ras_error_count(adev); 1473 } 1474 1475 r = amdgpu_gmc_ras_late_init(adev); 1476 if (r) 1477 return r; 1478 1479 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1480 } 1481 1482 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 1483 struct amdgpu_gmc *mc) 1484 { 1485 u64 base = adev->mmhub.funcs->get_fb_location(adev); 1486 1487 /* add the xgmi offset of the physical node */ 1488 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1489 if (adev->gmc.xgmi.connected_to_cpu) { 1490 amdgpu_gmc_sysvm_location(adev, mc); 1491 } else { 1492 amdgpu_gmc_vram_location(adev, mc, base); 1493 amdgpu_gmc_gart_location(adev, mc); 1494 amdgpu_gmc_agp_location(adev, mc); 1495 } 1496 /* base offset of vram pages */ 1497 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 1498 1499 /* XXX: add the xgmi offset of the physical node? */ 1500 adev->vm_manager.vram_base_offset += 1501 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1502 } 1503 1504 /** 1505 * gmc_v9_0_mc_init - initialize the memory controller driver params 1506 * 1507 * @adev: amdgpu_device pointer 1508 * 1509 * Look up the amount of vram, vram width, and decide how to place 1510 * vram and gart within the GPU's physical address space. 1511 * Returns 0 for success. 1512 */ 1513 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 1514 { 1515 int r; 1516 1517 /* size in MB on si */ 1518 adev->gmc.mc_vram_size = 1519 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 1520 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 1521 1522 if (!(adev->flags & AMD_IS_APU) && 1523 !adev->gmc.xgmi.connected_to_cpu) { 1524 r = amdgpu_device_resize_fb_bar(adev); 1525 if (r) 1526 return r; 1527 } 1528 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 1529 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 1530 1531 #ifdef CONFIG_X86_64 1532 /* 1533 * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi 1534 * interface can use VRAM through here as it appears system reserved 1535 * memory in host address space. 1536 * 1537 * For APUs, VRAM is just the stolen system memory and can be accessed 1538 * directly. 1539 * 1540 * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR. 1541 */ 1542 1543 /* check whether both host-gpu and gpu-gpu xgmi links exist */ 1544 if (((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) || 1545 (adev->gmc.xgmi.supported && 1546 adev->gmc.xgmi.connected_to_cpu)) { 1547 adev->gmc.aper_base = 1548 adev->gfxhub.funcs->get_mc_fb_offset(adev) + 1549 adev->gmc.xgmi.physical_node_id * 1550 adev->gmc.xgmi.node_segment_size; 1551 adev->gmc.aper_size = adev->gmc.real_vram_size; 1552 } 1553 1554 #endif 1555 adev->gmc.visible_vram_size = adev->gmc.aper_size; 1556 1557 /* set the gart size */ 1558 if (amdgpu_gart_size == -1) { 1559 switch (adev->ip_versions[GC_HWIP][0]) { 1560 case IP_VERSION(9, 0, 1): /* all engines support GPUVM */ 1561 case IP_VERSION(9, 2, 1): /* all engines support GPUVM */ 1562 case IP_VERSION(9, 4, 0): 1563 case IP_VERSION(9, 4, 1): 1564 case IP_VERSION(9, 4, 2): 1565 default: 1566 adev->gmc.gart_size = 512ULL << 20; 1567 break; 1568 case IP_VERSION(9, 1, 0): /* DCE SG support */ 1569 case IP_VERSION(9, 2, 2): /* DCE SG support */ 1570 case IP_VERSION(9, 3, 0): 1571 adev->gmc.gart_size = 1024ULL << 20; 1572 break; 1573 } 1574 } else { 1575 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 1576 } 1577 1578 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; 1579 1580 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); 1581 1582 return 0; 1583 } 1584 1585 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 1586 { 1587 int r; 1588 1589 if (adev->gart.bo) { 1590 WARN(1, "VEGA10 PCIE GART already initialized\n"); 1591 return 0; 1592 } 1593 1594 if (adev->gmc.xgmi.connected_to_cpu) { 1595 adev->gmc.vmid0_page_table_depth = 1; 1596 adev->gmc.vmid0_page_table_block_size = 12; 1597 } else { 1598 adev->gmc.vmid0_page_table_depth = 0; 1599 adev->gmc.vmid0_page_table_block_size = 0; 1600 } 1601 1602 /* Initialize common gart structure */ 1603 r = amdgpu_gart_init(adev); 1604 if (r) 1605 return r; 1606 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 1607 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) | 1608 AMDGPU_PTE_EXECUTABLE; 1609 1610 r = amdgpu_gart_table_vram_alloc(adev); 1611 if (r) 1612 return r; 1613 1614 if (adev->gmc.xgmi.connected_to_cpu) { 1615 r = amdgpu_gmc_pdb0_alloc(adev); 1616 } 1617 1618 return r; 1619 } 1620 1621 /** 1622 * gmc_v9_0_save_registers - saves regs 1623 * 1624 * @adev: amdgpu_device pointer 1625 * 1626 * This saves potential register values that should be 1627 * restored upon resume 1628 */ 1629 static void gmc_v9_0_save_registers(struct amdgpu_device *adev) 1630 { 1631 if ((adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 0)) || 1632 (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 1))) 1633 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); 1634 } 1635 1636 static int gmc_v9_0_sw_init(void *handle) 1637 { 1638 int r, vram_width = 0, vram_type = 0, vram_vendor = 0, dma_addr_bits; 1639 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1640 1641 adev->gfxhub.funcs->init(adev); 1642 1643 adev->mmhub.funcs->init(adev); 1644 if (adev->mca.funcs) 1645 adev->mca.funcs->init(adev); 1646 1647 spin_lock_init(&adev->gmc.invalidate_lock); 1648 1649 r = amdgpu_atomfirmware_get_vram_info(adev, 1650 &vram_width, &vram_type, &vram_vendor); 1651 if (amdgpu_sriov_vf(adev)) 1652 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, 1653 * and DF related registers is not readable, seems hardcord is the 1654 * only way to set the correct vram_width 1655 */ 1656 adev->gmc.vram_width = 2048; 1657 else if (amdgpu_emu_mode != 1) 1658 adev->gmc.vram_width = vram_width; 1659 1660 if (!adev->gmc.vram_width) { 1661 int chansize, numchan; 1662 1663 /* hbm memory channel size */ 1664 if (adev->flags & AMD_IS_APU) 1665 chansize = 64; 1666 else 1667 chansize = 128; 1668 if (adev->df.funcs && 1669 adev->df.funcs->get_hbm_channel_number) { 1670 numchan = adev->df.funcs->get_hbm_channel_number(adev); 1671 adev->gmc.vram_width = numchan * chansize; 1672 } 1673 } 1674 1675 adev->gmc.vram_type = vram_type; 1676 adev->gmc.vram_vendor = vram_vendor; 1677 switch (adev->ip_versions[GC_HWIP][0]) { 1678 case IP_VERSION(9, 1, 0): 1679 case IP_VERSION(9, 2, 2): 1680 adev->num_vmhubs = 2; 1681 1682 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 1683 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1684 } else { 1685 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 1686 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 1687 adev->gmc.translate_further = 1688 adev->vm_manager.num_level > 1; 1689 } 1690 break; 1691 case IP_VERSION(9, 0, 1): 1692 case IP_VERSION(9, 2, 1): 1693 case IP_VERSION(9, 4, 0): 1694 case IP_VERSION(9, 3, 0): 1695 case IP_VERSION(9, 4, 2): 1696 adev->num_vmhubs = 2; 1697 1698 1699 /* 1700 * To fulfill 4-level page support, 1701 * vm size is 256TB (48bit), maximum size of Vega10, 1702 * block size 512 (9bit) 1703 */ 1704 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */ 1705 if (amdgpu_sriov_vf(adev)) 1706 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47); 1707 else 1708 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1709 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) 1710 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 1711 break; 1712 case IP_VERSION(9, 4, 1): 1713 adev->num_vmhubs = 3; 1714 1715 /* Keep the vm size same with Vega20 */ 1716 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1717 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 1718 break; 1719 default: 1720 break; 1721 } 1722 1723 /* This interrupt is VMC page fault.*/ 1724 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, 1725 &adev->gmc.vm_fault); 1726 if (r) 1727 return r; 1728 1729 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)) { 1730 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT, 1731 &adev->gmc.vm_fault); 1732 if (r) 1733 return r; 1734 } 1735 1736 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, 1737 &adev->gmc.vm_fault); 1738 1739 if (r) 1740 return r; 1741 1742 if (!amdgpu_sriov_vf(adev) && 1743 !adev->gmc.xgmi.connected_to_cpu) { 1744 /* interrupt sent to DF. */ 1745 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 1746 &adev->gmc.ecc_irq); 1747 if (r) 1748 return r; 1749 } 1750 1751 /* Set the internal MC address mask 1752 * This is the max address of the GPU's 1753 * internal address space. 1754 */ 1755 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 1756 1757 dma_addr_bits = adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) ? 48:44; 1758 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(dma_addr_bits)); 1759 if (r) { 1760 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 1761 return r; 1762 } 1763 adev->need_swiotlb = drm_need_swiotlb(dma_addr_bits); 1764 1765 r = gmc_v9_0_mc_init(adev); 1766 if (r) 1767 return r; 1768 1769 amdgpu_gmc_get_vbios_allocations(adev); 1770 1771 /* Memory manager */ 1772 r = amdgpu_bo_init(adev); 1773 if (r) 1774 return r; 1775 1776 r = gmc_v9_0_gart_init(adev); 1777 if (r) 1778 return r; 1779 1780 /* 1781 * number of VMs 1782 * VMID 0 is reserved for System 1783 * amdgpu graphics/compute will use VMIDs 1..n-1 1784 * amdkfd will use VMIDs n..15 1785 * 1786 * The first KFD VMID is 8 for GPUs with graphics, 3 for 1787 * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs 1788 * for video processing. 1789 */ 1790 adev->vm_manager.first_kfd_vmid = 1791 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) || 1792 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) ? 3 : 8; 1793 1794 amdgpu_vm_manager_init(adev); 1795 1796 gmc_v9_0_save_registers(adev); 1797 1798 return 0; 1799 } 1800 1801 static int gmc_v9_0_sw_fini(void *handle) 1802 { 1803 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1804 1805 amdgpu_gmc_ras_fini(adev); 1806 amdgpu_gem_force_release(adev); 1807 amdgpu_vm_manager_fini(adev); 1808 amdgpu_gart_table_vram_free(adev); 1809 amdgpu_bo_free_kernel(&adev->gmc.pdb0_bo, NULL, &adev->gmc.ptr_pdb0); 1810 amdgpu_bo_fini(adev); 1811 1812 return 0; 1813 } 1814 1815 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 1816 { 1817 1818 switch (adev->ip_versions[MMHUB_HWIP][0]) { 1819 case IP_VERSION(9, 0, 0): 1820 if (amdgpu_sriov_vf(adev)) 1821 break; 1822 fallthrough; 1823 case IP_VERSION(9, 4, 0): 1824 soc15_program_register_sequence(adev, 1825 golden_settings_mmhub_1_0_0, 1826 ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 1827 soc15_program_register_sequence(adev, 1828 golden_settings_athub_1_0_0, 1829 ARRAY_SIZE(golden_settings_athub_1_0_0)); 1830 break; 1831 case IP_VERSION(9, 1, 0): 1832 case IP_VERSION(9, 2, 0): 1833 /* TODO for renoir */ 1834 soc15_program_register_sequence(adev, 1835 golden_settings_athub_1_0_0, 1836 ARRAY_SIZE(golden_settings_athub_1_0_0)); 1837 break; 1838 default: 1839 break; 1840 } 1841 } 1842 1843 /** 1844 * gmc_v9_0_restore_registers - restores regs 1845 * 1846 * @adev: amdgpu_device pointer 1847 * 1848 * This restores register values, saved at suspend. 1849 */ 1850 void gmc_v9_0_restore_registers(struct amdgpu_device *adev) 1851 { 1852 if ((adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 0)) || 1853 (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 1))) { 1854 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register); 1855 WARN_ON(adev->gmc.sdpif_register != 1856 RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0)); 1857 } 1858 } 1859 1860 /** 1861 * gmc_v9_0_gart_enable - gart enable 1862 * 1863 * @adev: amdgpu_device pointer 1864 */ 1865 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 1866 { 1867 int r; 1868 1869 if (adev->gmc.xgmi.connected_to_cpu) 1870 amdgpu_gmc_init_pdb0(adev); 1871 1872 if (adev->gart.bo == NULL) { 1873 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 1874 return -EINVAL; 1875 } 1876 1877 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 1878 1879 if (!adev->in_s0ix) { 1880 r = adev->gfxhub.funcs->gart_enable(adev); 1881 if (r) 1882 return r; 1883 } 1884 1885 r = adev->mmhub.funcs->gart_enable(adev); 1886 if (r) 1887 return r; 1888 1889 DRM_INFO("PCIE GART of %uM enabled.\n", 1890 (unsigned)(adev->gmc.gart_size >> 20)); 1891 if (adev->gmc.pdb0_bo) 1892 DRM_INFO("PDB0 located at 0x%016llX\n", 1893 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo)); 1894 DRM_INFO("PTB located at 0x%016llX\n", 1895 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 1896 1897 return 0; 1898 } 1899 1900 static int gmc_v9_0_hw_init(void *handle) 1901 { 1902 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1903 bool value; 1904 int i, r; 1905 1906 /* The sequence of these two function calls matters.*/ 1907 gmc_v9_0_init_golden_registers(adev); 1908 1909 if (adev->mode_info.num_crtc) { 1910 /* Lockout access through VGA aperture*/ 1911 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 1912 /* disable VGA render */ 1913 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 1914 } 1915 1916 if (adev->mmhub.funcs->update_power_gating) 1917 adev->mmhub.funcs->update_power_gating(adev, true); 1918 1919 adev->hdp.funcs->init_registers(adev); 1920 1921 /* After HDP is initialized, flush HDP.*/ 1922 adev->hdp.funcs->flush_hdp(adev, NULL); 1923 1924 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 1925 value = false; 1926 else 1927 value = true; 1928 1929 if (!amdgpu_sriov_vf(adev)) { 1930 if (!adev->in_s0ix) 1931 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 1932 adev->mmhub.funcs->set_fault_enable_default(adev, value); 1933 } 1934 for (i = 0; i < adev->num_vmhubs; ++i) { 1935 if (adev->in_s0ix && (i == AMDGPU_GFXHUB_0)) 1936 continue; 1937 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0); 1938 } 1939 1940 if (adev->umc.funcs && adev->umc.funcs->init_registers) 1941 adev->umc.funcs->init_registers(adev); 1942 1943 r = gmc_v9_0_gart_enable(adev); 1944 if (r) 1945 return r; 1946 1947 if (amdgpu_emu_mode == 1) 1948 return amdgpu_gmc_vram_checking(adev); 1949 else 1950 return r; 1951 } 1952 1953 /** 1954 * gmc_v9_0_gart_disable - gart disable 1955 * 1956 * @adev: amdgpu_device pointer 1957 * 1958 * This disables all VM page table. 1959 */ 1960 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 1961 { 1962 if (!adev->in_s0ix) 1963 adev->gfxhub.funcs->gart_disable(adev); 1964 adev->mmhub.funcs->gart_disable(adev); 1965 } 1966 1967 static int gmc_v9_0_hw_fini(void *handle) 1968 { 1969 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1970 1971 gmc_v9_0_gart_disable(adev); 1972 1973 if (amdgpu_sriov_vf(adev)) { 1974 /* full access mode, so don't touch any GMC register */ 1975 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 1976 return 0; 1977 } 1978 1979 /* 1980 * Pair the operations did in gmc_v9_0_hw_init and thus maintain 1981 * a correct cached state for GMC. Otherwise, the "gate" again 1982 * operation on S3 resuming will fail due to wrong cached state. 1983 */ 1984 if (adev->mmhub.funcs->update_power_gating) 1985 adev->mmhub.funcs->update_power_gating(adev, false); 1986 1987 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 1988 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1989 1990 return 0; 1991 } 1992 1993 static int gmc_v9_0_suspend(void *handle) 1994 { 1995 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1996 1997 return gmc_v9_0_hw_fini(adev); 1998 } 1999 2000 static int gmc_v9_0_resume(void *handle) 2001 { 2002 int r; 2003 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2004 2005 r = gmc_v9_0_hw_init(adev); 2006 if (r) 2007 return r; 2008 2009 amdgpu_vmid_reset_all(adev); 2010 2011 return 0; 2012 } 2013 2014 static bool gmc_v9_0_is_idle(void *handle) 2015 { 2016 /* MC is always ready in GMC v9.*/ 2017 return true; 2018 } 2019 2020 static int gmc_v9_0_wait_for_idle(void *handle) 2021 { 2022 /* There is no need to wait for MC idle in GMC v9.*/ 2023 return 0; 2024 } 2025 2026 static int gmc_v9_0_soft_reset(void *handle) 2027 { 2028 /* XXX for emulation.*/ 2029 return 0; 2030 } 2031 2032 static int gmc_v9_0_set_clockgating_state(void *handle, 2033 enum amd_clockgating_state state) 2034 { 2035 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2036 2037 adev->mmhub.funcs->set_clockgating(adev, state); 2038 2039 athub_v1_0_set_clockgating(adev, state); 2040 2041 return 0; 2042 } 2043 2044 static void gmc_v9_0_get_clockgating_state(void *handle, u64 *flags) 2045 { 2046 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2047 2048 adev->mmhub.funcs->get_clockgating(adev, flags); 2049 2050 athub_v1_0_get_clockgating(adev, flags); 2051 } 2052 2053 static int gmc_v9_0_set_powergating_state(void *handle, 2054 enum amd_powergating_state state) 2055 { 2056 return 0; 2057 } 2058 2059 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 2060 .name = "gmc_v9_0", 2061 .early_init = gmc_v9_0_early_init, 2062 .late_init = gmc_v9_0_late_init, 2063 .sw_init = gmc_v9_0_sw_init, 2064 .sw_fini = gmc_v9_0_sw_fini, 2065 .hw_init = gmc_v9_0_hw_init, 2066 .hw_fini = gmc_v9_0_hw_fini, 2067 .suspend = gmc_v9_0_suspend, 2068 .resume = gmc_v9_0_resume, 2069 .is_idle = gmc_v9_0_is_idle, 2070 .wait_for_idle = gmc_v9_0_wait_for_idle, 2071 .soft_reset = gmc_v9_0_soft_reset, 2072 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 2073 .set_powergating_state = gmc_v9_0_set_powergating_state, 2074 .get_clockgating_state = gmc_v9_0_get_clockgating_state, 2075 }; 2076 2077 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = 2078 { 2079 .type = AMD_IP_BLOCK_TYPE_GMC, 2080 .major = 9, 2081 .minor = 0, 2082 .rev = 0, 2083 .funcs = &gmc_v9_0_ip_funcs, 2084 }; 2085