1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/pci.h> 26 27 #include <drm/drm_cache.h> 28 29 #include "amdgpu.h" 30 #include "gmc_v9_0.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_gem.h" 33 34 #include "gc/gc_9_0_sh_mask.h" 35 #include "dce/dce_12_0_offset.h" 36 #include "dce/dce_12_0_sh_mask.h" 37 #include "vega10_enum.h" 38 #include "mmhub/mmhub_1_0_offset.h" 39 #include "athub/athub_1_0_sh_mask.h" 40 #include "athub/athub_1_0_offset.h" 41 #include "oss/osssys_4_0_offset.h" 42 43 #include "soc15.h" 44 #include "soc15d.h" 45 #include "soc15_common.h" 46 #include "umc/umc_6_0_sh_mask.h" 47 48 #include "gfxhub_v1_0.h" 49 #include "mmhub_v1_0.h" 50 #include "athub_v1_0.h" 51 #include "gfxhub_v1_1.h" 52 #include "mmhub_v9_4.h" 53 #include "mmhub_v1_7.h" 54 #include "umc_v6_1.h" 55 #include "umc_v6_0.h" 56 57 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 58 59 #include "amdgpu_ras.h" 60 #include "amdgpu_xgmi.h" 61 62 /* add these here since we already include dce12 headers and these are for DCN */ 63 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 64 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 65 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 66 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 67 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL 68 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L 69 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d 70 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2 71 72 73 static const char *gfxhub_client_ids[] = { 74 "CB", 75 "DB", 76 "IA", 77 "WD", 78 "CPF", 79 "CPC", 80 "CPG", 81 "RLC", 82 "TCP", 83 "SQC (inst)", 84 "SQC (data)", 85 "SQG", 86 "PA", 87 }; 88 89 static const char *mmhub_client_ids_raven[][2] = { 90 [0][0] = "MP1", 91 [1][0] = "MP0", 92 [2][0] = "VCN", 93 [3][0] = "VCNU", 94 [4][0] = "HDP", 95 [5][0] = "DCE", 96 [13][0] = "UTCL2", 97 [19][0] = "TLS", 98 [26][0] = "OSS", 99 [27][0] = "SDMA0", 100 [0][1] = "MP1", 101 [1][1] = "MP0", 102 [2][1] = "VCN", 103 [3][1] = "VCNU", 104 [4][1] = "HDP", 105 [5][1] = "XDP", 106 [6][1] = "DBGU0", 107 [7][1] = "DCE", 108 [8][1] = "DCEDWB0", 109 [9][1] = "DCEDWB1", 110 [26][1] = "OSS", 111 [27][1] = "SDMA0", 112 }; 113 114 static const char *mmhub_client_ids_renoir[][2] = { 115 [0][0] = "MP1", 116 [1][0] = "MP0", 117 [2][0] = "HDP", 118 [4][0] = "DCEDMC", 119 [5][0] = "DCEVGA", 120 [13][0] = "UTCL2", 121 [19][0] = "TLS", 122 [26][0] = "OSS", 123 [27][0] = "SDMA0", 124 [28][0] = "VCN", 125 [29][0] = "VCNU", 126 [30][0] = "JPEG", 127 [0][1] = "MP1", 128 [1][1] = "MP0", 129 [2][1] = "HDP", 130 [3][1] = "XDP", 131 [6][1] = "DBGU0", 132 [7][1] = "DCEDMC", 133 [8][1] = "DCEVGA", 134 [9][1] = "DCEDWB", 135 [26][1] = "OSS", 136 [27][1] = "SDMA0", 137 [28][1] = "VCN", 138 [29][1] = "VCNU", 139 [30][1] = "JPEG", 140 }; 141 142 static const char *mmhub_client_ids_vega10[][2] = { 143 [0][0] = "MP0", 144 [1][0] = "UVD", 145 [2][0] = "UVDU", 146 [3][0] = "HDP", 147 [13][0] = "UTCL2", 148 [14][0] = "OSS", 149 [15][0] = "SDMA1", 150 [32+0][0] = "VCE0", 151 [32+1][0] = "VCE0U", 152 [32+2][0] = "XDMA", 153 [32+3][0] = "DCE", 154 [32+4][0] = "MP1", 155 [32+14][0] = "SDMA0", 156 [0][1] = "MP0", 157 [1][1] = "UVD", 158 [2][1] = "UVDU", 159 [3][1] = "DBGU0", 160 [4][1] = "HDP", 161 [5][1] = "XDP", 162 [14][1] = "OSS", 163 [15][1] = "SDMA0", 164 [32+0][1] = "VCE0", 165 [32+1][1] = "VCE0U", 166 [32+2][1] = "XDMA", 167 [32+3][1] = "DCE", 168 [32+4][1] = "DCEDWB", 169 [32+5][1] = "MP1", 170 [32+6][1] = "DBGU1", 171 [32+14][1] = "SDMA1", 172 }; 173 174 static const char *mmhub_client_ids_vega12[][2] = { 175 [0][0] = "MP0", 176 [1][0] = "VCE0", 177 [2][0] = "VCE0U", 178 [3][0] = "HDP", 179 [13][0] = "UTCL2", 180 [14][0] = "OSS", 181 [15][0] = "SDMA1", 182 [32+0][0] = "DCE", 183 [32+1][0] = "XDMA", 184 [32+2][0] = "UVD", 185 [32+3][0] = "UVDU", 186 [32+4][0] = "MP1", 187 [32+15][0] = "SDMA0", 188 [0][1] = "MP0", 189 [1][1] = "VCE0", 190 [2][1] = "VCE0U", 191 [3][1] = "DBGU0", 192 [4][1] = "HDP", 193 [5][1] = "XDP", 194 [14][1] = "OSS", 195 [15][1] = "SDMA0", 196 [32+0][1] = "DCE", 197 [32+1][1] = "DCEDWB", 198 [32+2][1] = "XDMA", 199 [32+3][1] = "UVD", 200 [32+4][1] = "UVDU", 201 [32+5][1] = "MP1", 202 [32+6][1] = "DBGU1", 203 [32+15][1] = "SDMA1", 204 }; 205 206 static const char *mmhub_client_ids_vega20[][2] = { 207 [0][0] = "XDMA", 208 [1][0] = "DCE", 209 [2][0] = "VCE0", 210 [3][0] = "VCE0U", 211 [4][0] = "UVD", 212 [5][0] = "UVD1U", 213 [13][0] = "OSS", 214 [14][0] = "HDP", 215 [15][0] = "SDMA0", 216 [32+0][0] = "UVD", 217 [32+1][0] = "UVDU", 218 [32+2][0] = "MP1", 219 [32+3][0] = "MP0", 220 [32+12][0] = "UTCL2", 221 [32+14][0] = "SDMA1", 222 [0][1] = "XDMA", 223 [1][1] = "DCE", 224 [2][1] = "DCEDWB", 225 [3][1] = "VCE0", 226 [4][1] = "VCE0U", 227 [5][1] = "UVD1", 228 [6][1] = "UVD1U", 229 [7][1] = "DBGU0", 230 [8][1] = "XDP", 231 [13][1] = "OSS", 232 [14][1] = "HDP", 233 [15][1] = "SDMA0", 234 [32+0][1] = "UVD", 235 [32+1][1] = "UVDU", 236 [32+2][1] = "DBGU1", 237 [32+3][1] = "MP1", 238 [32+4][1] = "MP0", 239 [32+14][1] = "SDMA1", 240 }; 241 242 static const char *mmhub_client_ids_arcturus[][2] = { 243 [0][0] = "DBGU1", 244 [1][0] = "XDP", 245 [2][0] = "MP1", 246 [14][0] = "HDP", 247 [171][0] = "JPEG", 248 [172][0] = "VCN", 249 [173][0] = "VCNU", 250 [203][0] = "JPEG1", 251 [204][0] = "VCN1", 252 [205][0] = "VCN1U", 253 [256][0] = "SDMA0", 254 [257][0] = "SDMA1", 255 [258][0] = "SDMA2", 256 [259][0] = "SDMA3", 257 [260][0] = "SDMA4", 258 [261][0] = "SDMA5", 259 [262][0] = "SDMA6", 260 [263][0] = "SDMA7", 261 [384][0] = "OSS", 262 [0][1] = "DBGU1", 263 [1][1] = "XDP", 264 [2][1] = "MP1", 265 [14][1] = "HDP", 266 [171][1] = "JPEG", 267 [172][1] = "VCN", 268 [173][1] = "VCNU", 269 [203][1] = "JPEG1", 270 [204][1] = "VCN1", 271 [205][1] = "VCN1U", 272 [256][1] = "SDMA0", 273 [257][1] = "SDMA1", 274 [258][1] = "SDMA2", 275 [259][1] = "SDMA3", 276 [260][1] = "SDMA4", 277 [261][1] = "SDMA5", 278 [262][1] = "SDMA6", 279 [263][1] = "SDMA7", 280 [384][1] = "OSS", 281 }; 282 283 static const char *mmhub_client_ids_aldebaran[][2] = { 284 [2][0] = "MP1", 285 [3][0] = "MP0", 286 [32+1][0] = "DBGU_IO0", 287 [32+2][0] = "DBGU_IO2", 288 [32+4][0] = "MPIO", 289 [96+11][0] = "JPEG0", 290 [96+12][0] = "VCN0", 291 [96+13][0] = "VCNU0", 292 [128+11][0] = "JPEG1", 293 [128+12][0] = "VCN1", 294 [128+13][0] = "VCNU1", 295 [160+1][0] = "XDP", 296 [160+14][0] = "HDP", 297 [256+0][0] = "SDMA0", 298 [256+1][0] = "SDMA1", 299 [256+2][0] = "SDMA2", 300 [256+3][0] = "SDMA3", 301 [256+4][0] = "SDMA4", 302 [384+0][0] = "OSS", 303 [2][1] = "MP1", 304 [3][1] = "MP0", 305 [32+1][1] = "DBGU_IO0", 306 [32+2][1] = "DBGU_IO2", 307 [32+4][1] = "MPIO", 308 [96+11][1] = "JPEG0", 309 [96+12][1] = "VCN0", 310 [96+13][1] = "VCNU0", 311 [128+11][1] = "JPEG1", 312 [128+12][1] = "VCN1", 313 [128+13][1] = "VCNU1", 314 [160+1][1] = "XDP", 315 [160+14][1] = "HDP", 316 [256+0][1] = "SDMA0", 317 [256+1][1] = "SDMA1", 318 [256+2][1] = "SDMA2", 319 [256+3][1] = "SDMA3", 320 [256+4][1] = "SDMA4", 321 [384+0][1] = "OSS", 322 }; 323 324 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = 325 { 326 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), 327 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) 328 }; 329 330 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = 331 { 332 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), 333 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) 334 }; 335 336 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { 337 (0x000143c0 + 0x00000000), 338 (0x000143c0 + 0x00000800), 339 (0x000143c0 + 0x00001000), 340 (0x000143c0 + 0x00001800), 341 (0x000543c0 + 0x00000000), 342 (0x000543c0 + 0x00000800), 343 (0x000543c0 + 0x00001000), 344 (0x000543c0 + 0x00001800), 345 (0x000943c0 + 0x00000000), 346 (0x000943c0 + 0x00000800), 347 (0x000943c0 + 0x00001000), 348 (0x000943c0 + 0x00001800), 349 (0x000d43c0 + 0x00000000), 350 (0x000d43c0 + 0x00000800), 351 (0x000d43c0 + 0x00001000), 352 (0x000d43c0 + 0x00001800), 353 (0x001143c0 + 0x00000000), 354 (0x001143c0 + 0x00000800), 355 (0x001143c0 + 0x00001000), 356 (0x001143c0 + 0x00001800), 357 (0x001543c0 + 0x00000000), 358 (0x001543c0 + 0x00000800), 359 (0x001543c0 + 0x00001000), 360 (0x001543c0 + 0x00001800), 361 (0x001943c0 + 0x00000000), 362 (0x001943c0 + 0x00000800), 363 (0x001943c0 + 0x00001000), 364 (0x001943c0 + 0x00001800), 365 (0x001d43c0 + 0x00000000), 366 (0x001d43c0 + 0x00000800), 367 (0x001d43c0 + 0x00001000), 368 (0x001d43c0 + 0x00001800), 369 }; 370 371 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { 372 (0x000143e0 + 0x00000000), 373 (0x000143e0 + 0x00000800), 374 (0x000143e0 + 0x00001000), 375 (0x000143e0 + 0x00001800), 376 (0x000543e0 + 0x00000000), 377 (0x000543e0 + 0x00000800), 378 (0x000543e0 + 0x00001000), 379 (0x000543e0 + 0x00001800), 380 (0x000943e0 + 0x00000000), 381 (0x000943e0 + 0x00000800), 382 (0x000943e0 + 0x00001000), 383 (0x000943e0 + 0x00001800), 384 (0x000d43e0 + 0x00000000), 385 (0x000d43e0 + 0x00000800), 386 (0x000d43e0 + 0x00001000), 387 (0x000d43e0 + 0x00001800), 388 (0x001143e0 + 0x00000000), 389 (0x001143e0 + 0x00000800), 390 (0x001143e0 + 0x00001000), 391 (0x001143e0 + 0x00001800), 392 (0x001543e0 + 0x00000000), 393 (0x001543e0 + 0x00000800), 394 (0x001543e0 + 0x00001000), 395 (0x001543e0 + 0x00001800), 396 (0x001943e0 + 0x00000000), 397 (0x001943e0 + 0x00000800), 398 (0x001943e0 + 0x00001000), 399 (0x001943e0 + 0x00001800), 400 (0x001d43e0 + 0x00000000), 401 (0x001d43e0 + 0x00000800), 402 (0x001d43e0 + 0x00001000), 403 (0x001d43e0 + 0x00001800), 404 }; 405 406 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, 407 struct amdgpu_irq_src *src, 408 unsigned type, 409 enum amdgpu_interrupt_state state) 410 { 411 u32 bits, i, tmp, reg; 412 413 /* Devices newer then VEGA10/12 shall have these programming 414 sequences performed by PSP BL */ 415 if (adev->asic_type >= CHIP_VEGA20) 416 return 0; 417 418 bits = 0x7f; 419 420 switch (state) { 421 case AMDGPU_IRQ_STATE_DISABLE: 422 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 423 reg = ecc_umc_mcumc_ctrl_addrs[i]; 424 tmp = RREG32(reg); 425 tmp &= ~bits; 426 WREG32(reg, tmp); 427 } 428 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 429 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 430 tmp = RREG32(reg); 431 tmp &= ~bits; 432 WREG32(reg, tmp); 433 } 434 break; 435 case AMDGPU_IRQ_STATE_ENABLE: 436 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 437 reg = ecc_umc_mcumc_ctrl_addrs[i]; 438 tmp = RREG32(reg); 439 tmp |= bits; 440 WREG32(reg, tmp); 441 } 442 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 443 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 444 tmp = RREG32(reg); 445 tmp |= bits; 446 WREG32(reg, tmp); 447 } 448 break; 449 default: 450 break; 451 } 452 453 return 0; 454 } 455 456 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 457 struct amdgpu_irq_src *src, 458 unsigned type, 459 enum amdgpu_interrupt_state state) 460 { 461 struct amdgpu_vmhub *hub; 462 u32 tmp, reg, bits, i, j; 463 464 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 465 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 466 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 467 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 468 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 469 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 470 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 471 472 switch (state) { 473 case AMDGPU_IRQ_STATE_DISABLE: 474 for (j = 0; j < adev->num_vmhubs; j++) { 475 hub = &adev->vmhub[j]; 476 for (i = 0; i < 16; i++) { 477 reg = hub->vm_context0_cntl + i; 478 tmp = RREG32(reg); 479 tmp &= ~bits; 480 WREG32(reg, tmp); 481 } 482 } 483 break; 484 case AMDGPU_IRQ_STATE_ENABLE: 485 for (j = 0; j < adev->num_vmhubs; j++) { 486 hub = &adev->vmhub[j]; 487 for (i = 0; i < 16; i++) { 488 reg = hub->vm_context0_cntl + i; 489 tmp = RREG32(reg); 490 tmp |= bits; 491 WREG32(reg, tmp); 492 } 493 } 494 break; 495 default: 496 break; 497 } 498 499 return 0; 500 } 501 502 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 503 struct amdgpu_irq_src *source, 504 struct amdgpu_iv_entry *entry) 505 { 506 bool retry_fault = !!(entry->src_data[1] & 0x80); 507 uint32_t status = 0, cid = 0, rw = 0; 508 struct amdgpu_task_info task_info; 509 struct amdgpu_vmhub *hub; 510 const char *mmhub_cid; 511 const char *hub_name; 512 u64 addr; 513 514 addr = (u64)entry->src_data[0] << 12; 515 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 516 517 if (retry_fault) { 518 /* Returning 1 here also prevents sending the IV to the KFD */ 519 520 /* Process it onyl if it's the first fault for this address */ 521 if (entry->ih != &adev->irq.ih_soft && 522 amdgpu_gmc_filter_faults(adev, addr, entry->pasid, 523 entry->timestamp)) 524 return 1; 525 526 /* Delegate it to a different ring if the hardware hasn't 527 * already done it. 528 */ 529 if (entry->ih == &adev->irq.ih) { 530 amdgpu_irq_delegate(adev, entry, 8); 531 return 1; 532 } 533 534 /* Try to handle the recoverable page faults by filling page 535 * tables 536 */ 537 if (amdgpu_vm_handle_fault(adev, entry->pasid, addr)) 538 return 1; 539 } 540 541 if (!printk_ratelimit()) 542 return 0; 543 544 if (entry->client_id == SOC15_IH_CLIENTID_VMC) { 545 hub_name = "mmhub0"; 546 hub = &adev->vmhub[AMDGPU_MMHUB_0]; 547 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) { 548 hub_name = "mmhub1"; 549 hub = &adev->vmhub[AMDGPU_MMHUB_1]; 550 } else { 551 hub_name = "gfxhub0"; 552 hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 553 } 554 555 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 556 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 557 558 dev_err(adev->dev, 559 "[%s] %s page fault (src_id:%u ring:%u vmid:%u " 560 "pasid:%u, for process %s pid %d thread %s pid %d)\n", 561 hub_name, retry_fault ? "retry" : "no-retry", 562 entry->src_id, entry->ring_id, entry->vmid, 563 entry->pasid, task_info.process_name, task_info.tgid, 564 task_info.task_name, task_info.pid); 565 dev_err(adev->dev, " in page starting at address 0x%016llx from IH client 0x%x (%s)\n", 566 addr, entry->client_id, 567 soc15_ih_clientid_name[entry->client_id]); 568 569 if (amdgpu_sriov_vf(adev)) 570 return 0; 571 572 /* 573 * Issue a dummy read to wait for the status register to 574 * be updated to avoid reading an incorrect value due to 575 * the new fast GRBM interface. 576 */ 577 if (entry->vmid_src == AMDGPU_GFXHUB_0) 578 RREG32(hub->vm_l2_pro_fault_status); 579 580 status = RREG32(hub->vm_l2_pro_fault_status); 581 cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID); 582 rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW); 583 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 584 585 586 dev_err(adev->dev, 587 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 588 status); 589 if (hub == &adev->vmhub[AMDGPU_GFXHUB_0]) { 590 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 591 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : 592 gfxhub_client_ids[cid], 593 cid); 594 } else { 595 switch (adev->asic_type) { 596 case CHIP_VEGA10: 597 mmhub_cid = mmhub_client_ids_vega10[cid][rw]; 598 break; 599 case CHIP_VEGA12: 600 mmhub_cid = mmhub_client_ids_vega12[cid][rw]; 601 break; 602 case CHIP_VEGA20: 603 mmhub_cid = mmhub_client_ids_vega20[cid][rw]; 604 break; 605 case CHIP_ARCTURUS: 606 mmhub_cid = mmhub_client_ids_arcturus[cid][rw]; 607 break; 608 case CHIP_RAVEN: 609 mmhub_cid = mmhub_client_ids_raven[cid][rw]; 610 break; 611 case CHIP_RENOIR: 612 mmhub_cid = mmhub_client_ids_renoir[cid][rw]; 613 break; 614 case CHIP_ALDEBARAN: 615 mmhub_cid = mmhub_client_ids_aldebaran[cid][rw]; 616 break; 617 default: 618 mmhub_cid = NULL; 619 break; 620 } 621 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 622 mmhub_cid ? mmhub_cid : "unknown", cid); 623 } 624 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 625 REG_GET_FIELD(status, 626 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 627 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 628 REG_GET_FIELD(status, 629 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 630 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 631 REG_GET_FIELD(status, 632 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 633 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 634 REG_GET_FIELD(status, 635 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 636 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 637 return 0; 638 } 639 640 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 641 .set = gmc_v9_0_vm_fault_interrupt_state, 642 .process = gmc_v9_0_process_interrupt, 643 }; 644 645 646 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { 647 .set = gmc_v9_0_ecc_interrupt_state, 648 .process = amdgpu_umc_process_ecc_irq, 649 }; 650 651 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 652 { 653 adev->gmc.vm_fault.num_types = 1; 654 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 655 656 if (!amdgpu_sriov_vf(adev) && 657 !adev->gmc.xgmi.connected_to_cpu) { 658 adev->gmc.ecc_irq.num_types = 1; 659 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; 660 } 661 } 662 663 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, 664 uint32_t flush_type) 665 { 666 u32 req = 0; 667 668 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 669 PER_VMID_INVALIDATE_REQ, 1 << vmid); 670 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 671 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 672 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 673 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 674 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 675 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 676 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 677 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 678 679 return req; 680 } 681 682 /** 683 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore 684 * 685 * @adev: amdgpu_device pointer 686 * @vmhub: vmhub type 687 * 688 */ 689 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev, 690 uint32_t vmhub) 691 { 692 if (adev->asic_type == CHIP_ALDEBARAN) 693 return false; 694 695 return ((vmhub == AMDGPU_MMHUB_0 || 696 vmhub == AMDGPU_MMHUB_1) && 697 (!amdgpu_sriov_vf(adev)) && 698 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) && 699 (adev->apu_flags & AMD_APU_IS_PICASSO)))); 700 } 701 702 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, 703 uint8_t vmid, uint16_t *p_pasid) 704 { 705 uint32_t value; 706 707 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 708 + vmid); 709 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 710 711 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 712 } 713 714 /* 715 * GART 716 * VMID 0 is the physical GPU addresses as used by the kernel. 717 * VMIDs 1-15 are used for userspace clients and are handled 718 * by the amdgpu vm/hsa code. 719 */ 720 721 /** 722 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type 723 * 724 * @adev: amdgpu_device pointer 725 * @vmid: vm instance to flush 726 * @vmhub: which hub to flush 727 * @flush_type: the flush type 728 * 729 * Flush the TLB for the requested page table using certain type. 730 */ 731 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 732 uint32_t vmhub, uint32_t flush_type) 733 { 734 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub); 735 const unsigned eng = 17; 736 u32 j, inv_req, inv_req2, tmp; 737 struct amdgpu_vmhub *hub; 738 739 BUG_ON(vmhub >= adev->num_vmhubs); 740 741 hub = &adev->vmhub[vmhub]; 742 if (adev->gmc.xgmi.num_physical_nodes && 743 adev->asic_type == CHIP_VEGA20) { 744 /* Vega20+XGMI caches PTEs in TC and TLB. Add a 745 * heavy-weight TLB flush (type 2), which flushes 746 * both. Due to a race condition with concurrent 747 * memory accesses using the same TLB cache line, we 748 * still need a second TLB flush after this. 749 */ 750 inv_req = gmc_v9_0_get_invalidate_req(vmid, 2); 751 inv_req2 = gmc_v9_0_get_invalidate_req(vmid, flush_type); 752 } else { 753 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type); 754 inv_req2 = 0; 755 } 756 757 /* This is necessary for a HW workaround under SRIOV as well 758 * as GFXOFF under bare metal 759 */ 760 if (adev->gfx.kiq.ring.sched.ready && 761 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && 762 down_read_trylock(&adev->reset_sem)) { 763 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 764 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 765 766 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 767 1 << vmid); 768 up_read(&adev->reset_sem); 769 return; 770 } 771 772 spin_lock(&adev->gmc.invalidate_lock); 773 774 /* 775 * It may lose gpuvm invalidate acknowldege state across power-gating 776 * off cycle, add semaphore acquire before invalidation and semaphore 777 * release after invalidation to avoid entering power gated state 778 * to WA the Issue 779 */ 780 781 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 782 if (use_semaphore) { 783 for (j = 0; j < adev->usec_timeout; j++) { 784 /* a read return value of 1 means semaphore acuqire */ 785 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + 786 hub->eng_distance * eng); 787 if (tmp & 0x1) 788 break; 789 udelay(1); 790 } 791 792 if (j >= adev->usec_timeout) 793 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 794 } 795 796 do { 797 WREG32_NO_KIQ(hub->vm_inv_eng0_req + 798 hub->eng_distance * eng, inv_req); 799 800 /* 801 * Issue a dummy read to wait for the ACK register to 802 * be cleared to avoid a false ACK due to the new fast 803 * GRBM interface. 804 */ 805 if (vmhub == AMDGPU_GFXHUB_0) 806 RREG32_NO_KIQ(hub->vm_inv_eng0_req + 807 hub->eng_distance * eng); 808 809 for (j = 0; j < adev->usec_timeout; j++) { 810 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + 811 hub->eng_distance * eng); 812 if (tmp & (1 << vmid)) 813 break; 814 udelay(1); 815 } 816 817 inv_req = inv_req2; 818 inv_req2 = 0; 819 } while (inv_req); 820 821 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 822 if (use_semaphore) 823 /* 824 * add semaphore release after invalidation, 825 * write with 0 means semaphore release 826 */ 827 WREG32_NO_KIQ(hub->vm_inv_eng0_sem + 828 hub->eng_distance * eng, 0); 829 830 spin_unlock(&adev->gmc.invalidate_lock); 831 832 if (j < adev->usec_timeout) 833 return; 834 835 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 836 } 837 838 /** 839 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid 840 * 841 * @adev: amdgpu_device pointer 842 * @pasid: pasid to be flush 843 * @flush_type: the flush type 844 * @all_hub: flush all hubs 845 * 846 * Flush the TLB for the requested pasid. 847 */ 848 static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 849 uint16_t pasid, uint32_t flush_type, 850 bool all_hub) 851 { 852 int vmid, i; 853 signed long r; 854 uint32_t seq; 855 uint16_t queried_pasid; 856 bool ret; 857 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 858 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 859 860 if (amdgpu_in_reset(adev)) 861 return -EIO; 862 863 if (ring->sched.ready && down_read_trylock(&adev->reset_sem)) { 864 /* Vega20+XGMI caches PTEs in TC and TLB. Add a 865 * heavy-weight TLB flush (type 2), which flushes 866 * both. Due to a race condition with concurrent 867 * memory accesses using the same TLB cache line, we 868 * still need a second TLB flush after this. 869 */ 870 bool vega20_xgmi_wa = (adev->gmc.xgmi.num_physical_nodes && 871 adev->asic_type == CHIP_VEGA20); 872 /* 2 dwords flush + 8 dwords fence */ 873 unsigned int ndw = kiq->pmf->invalidate_tlbs_size + 8; 874 875 if (vega20_xgmi_wa) 876 ndw += kiq->pmf->invalidate_tlbs_size; 877 878 spin_lock(&adev->gfx.kiq.ring_lock); 879 /* 2 dwords flush + 8 dwords fence */ 880 amdgpu_ring_alloc(ring, ndw); 881 if (vega20_xgmi_wa) 882 kiq->pmf->kiq_invalidate_tlbs(ring, 883 pasid, 2, all_hub); 884 kiq->pmf->kiq_invalidate_tlbs(ring, 885 pasid, flush_type, all_hub); 886 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 887 if (r) { 888 amdgpu_ring_undo(ring); 889 spin_unlock(&adev->gfx.kiq.ring_lock); 890 up_read(&adev->reset_sem); 891 return -ETIME; 892 } 893 894 amdgpu_ring_commit(ring); 895 spin_unlock(&adev->gfx.kiq.ring_lock); 896 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); 897 if (r < 1) { 898 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r); 899 up_read(&adev->reset_sem); 900 return -ETIME; 901 } 902 up_read(&adev->reset_sem); 903 return 0; 904 } 905 906 for (vmid = 1; vmid < 16; vmid++) { 907 908 ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 909 &queried_pasid); 910 if (ret && queried_pasid == pasid) { 911 if (all_hub) { 912 for (i = 0; i < adev->num_vmhubs; i++) 913 gmc_v9_0_flush_gpu_tlb(adev, vmid, 914 i, flush_type); 915 } else { 916 gmc_v9_0_flush_gpu_tlb(adev, vmid, 917 AMDGPU_GFXHUB_0, flush_type); 918 } 919 break; 920 } 921 } 922 923 return 0; 924 925 } 926 927 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 928 unsigned vmid, uint64_t pd_addr) 929 { 930 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub); 931 struct amdgpu_device *adev = ring->adev; 932 struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub]; 933 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); 934 unsigned eng = ring->vm_inv_eng; 935 936 /* 937 * It may lose gpuvm invalidate acknowldege state across power-gating 938 * off cycle, add semaphore acquire before invalidation and semaphore 939 * release after invalidation to avoid entering power gated state 940 * to WA the Issue 941 */ 942 943 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 944 if (use_semaphore) 945 /* a read return value of 1 means semaphore acuqire */ 946 amdgpu_ring_emit_reg_wait(ring, 947 hub->vm_inv_eng0_sem + 948 hub->eng_distance * eng, 0x1, 0x1); 949 950 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 951 (hub->ctx_addr_distance * vmid), 952 lower_32_bits(pd_addr)); 953 954 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 955 (hub->ctx_addr_distance * vmid), 956 upper_32_bits(pd_addr)); 957 958 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 959 hub->eng_distance * eng, 960 hub->vm_inv_eng0_ack + 961 hub->eng_distance * eng, 962 req, 1 << vmid); 963 964 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 965 if (use_semaphore) 966 /* 967 * add semaphore release after invalidation, 968 * write with 0 means semaphore release 969 */ 970 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 971 hub->eng_distance * eng, 0); 972 973 return pd_addr; 974 } 975 976 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 977 unsigned pasid) 978 { 979 struct amdgpu_device *adev = ring->adev; 980 uint32_t reg; 981 982 /* Do nothing because there's no lut register for mmhub1. */ 983 if (ring->funcs->vmhub == AMDGPU_MMHUB_1) 984 return; 985 986 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) 987 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 988 else 989 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 990 991 amdgpu_ring_emit_wreg(ring, reg, pasid); 992 } 993 994 /* 995 * PTE format on VEGA 10: 996 * 63:59 reserved 997 * 58:57 mtype 998 * 56 F 999 * 55 L 1000 * 54 P 1001 * 53 SW 1002 * 52 T 1003 * 50:48 reserved 1004 * 47:12 4k physical page base address 1005 * 11:7 fragment 1006 * 6 write 1007 * 5 read 1008 * 4 exe 1009 * 3 Z 1010 * 2 snooped 1011 * 1 system 1012 * 0 valid 1013 * 1014 * PDE format on VEGA 10: 1015 * 63:59 block fragment size 1016 * 58:55 reserved 1017 * 54 P 1018 * 53:48 reserved 1019 * 47:6 physical base address of PD or PTE 1020 * 5:3 reserved 1021 * 2 C 1022 * 1 system 1023 * 0 valid 1024 */ 1025 1026 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 1027 1028 { 1029 switch (flags) { 1030 case AMDGPU_VM_MTYPE_DEFAULT: 1031 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1032 case AMDGPU_VM_MTYPE_NC: 1033 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1034 case AMDGPU_VM_MTYPE_WC: 1035 return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC); 1036 case AMDGPU_VM_MTYPE_RW: 1037 return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW); 1038 case AMDGPU_VM_MTYPE_CC: 1039 return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC); 1040 case AMDGPU_VM_MTYPE_UC: 1041 return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC); 1042 default: 1043 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1044 } 1045 } 1046 1047 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, 1048 uint64_t *addr, uint64_t *flags) 1049 { 1050 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 1051 *addr = adev->vm_manager.vram_base_offset + *addr - 1052 adev->gmc.vram_start; 1053 BUG_ON(*addr & 0xFFFF00000000003FULL); 1054 1055 if (!adev->gmc.translate_further) 1056 return; 1057 1058 if (level == AMDGPU_VM_PDB1) { 1059 /* Set the block fragment size */ 1060 if (!(*flags & AMDGPU_PDE_PTE)) 1061 *flags |= AMDGPU_PDE_BFS(0x9); 1062 1063 } else if (level == AMDGPU_VM_PDB0) { 1064 if (*flags & AMDGPU_PDE_PTE) 1065 *flags &= ~AMDGPU_PDE_PTE; 1066 else 1067 *flags |= AMDGPU_PTE_TF; 1068 } 1069 } 1070 1071 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev, 1072 struct amdgpu_bo_va_mapping *mapping, 1073 uint64_t *flags) 1074 { 1075 *flags &= ~AMDGPU_PTE_EXECUTABLE; 1076 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 1077 1078 *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 1079 *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK; 1080 1081 if (mapping->flags & AMDGPU_PTE_PRT) { 1082 *flags |= AMDGPU_PTE_PRT; 1083 *flags &= ~AMDGPU_PTE_VALID; 1084 } 1085 1086 if ((adev->asic_type == CHIP_ARCTURUS || 1087 adev->asic_type == CHIP_ALDEBARAN) && 1088 !(*flags & AMDGPU_PTE_SYSTEM) && 1089 mapping->bo_va->is_xgmi) 1090 *flags |= AMDGPU_PTE_SNOOPED; 1091 1092 if (adev->asic_type == CHIP_ALDEBARAN) 1093 *flags |= mapping->flags & AMDGPU_PTE_SNOOPED; 1094 } 1095 1096 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 1097 { 1098 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 1099 unsigned size; 1100 1101 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1102 size = AMDGPU_VBIOS_VGA_ALLOCATION; 1103 } else { 1104 u32 viewport; 1105 1106 switch (adev->asic_type) { 1107 case CHIP_RAVEN: 1108 case CHIP_RENOIR: 1109 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 1110 size = (REG_GET_FIELD(viewport, 1111 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1112 REG_GET_FIELD(viewport, 1113 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1114 4); 1115 break; 1116 case CHIP_VEGA10: 1117 case CHIP_VEGA12: 1118 case CHIP_VEGA20: 1119 default: 1120 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); 1121 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1122 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1123 4); 1124 break; 1125 } 1126 } 1127 1128 return size; 1129 } 1130 1131 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { 1132 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, 1133 .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid, 1134 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, 1135 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, 1136 .map_mtype = gmc_v9_0_map_mtype, 1137 .get_vm_pde = gmc_v9_0_get_vm_pde, 1138 .get_vm_pte = gmc_v9_0_get_vm_pte, 1139 .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size, 1140 }; 1141 1142 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) 1143 { 1144 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; 1145 } 1146 1147 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) 1148 { 1149 switch (adev->asic_type) { 1150 case CHIP_VEGA10: 1151 adev->umc.funcs = &umc_v6_0_funcs; 1152 break; 1153 case CHIP_VEGA20: 1154 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1155 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1156 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1157 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20; 1158 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1159 adev->umc.ras_funcs = &umc_v6_1_ras_funcs; 1160 break; 1161 case CHIP_ARCTURUS: 1162 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1163 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1164 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1165 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT; 1166 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1167 adev->umc.ras_funcs = &umc_v6_1_ras_funcs; 1168 break; 1169 default: 1170 break; 1171 } 1172 } 1173 1174 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) 1175 { 1176 switch (adev->asic_type) { 1177 case CHIP_ARCTURUS: 1178 adev->mmhub.funcs = &mmhub_v9_4_funcs; 1179 break; 1180 case CHIP_ALDEBARAN: 1181 adev->mmhub.funcs = &mmhub_v1_7_funcs; 1182 break; 1183 default: 1184 adev->mmhub.funcs = &mmhub_v1_0_funcs; 1185 break; 1186 } 1187 } 1188 1189 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev) 1190 { 1191 adev->gfxhub.funcs = &gfxhub_v1_0_funcs; 1192 } 1193 1194 static int gmc_v9_0_early_init(void *handle) 1195 { 1196 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1197 1198 if (adev->asic_type == CHIP_VEGA20 || 1199 adev->asic_type == CHIP_ARCTURUS) 1200 adev->gmc.xgmi.supported = true; 1201 1202 if (adev->asic_type == CHIP_ALDEBARAN) { 1203 adev->gmc.xgmi.supported = true; 1204 adev->gmc.xgmi.connected_to_cpu = 1205 adev->smuio.funcs->is_host_gpu_xgmi_supported(adev); 1206 } 1207 1208 gmc_v9_0_set_gmc_funcs(adev); 1209 gmc_v9_0_set_irq_funcs(adev); 1210 gmc_v9_0_set_umc_funcs(adev); 1211 gmc_v9_0_set_mmhub_funcs(adev); 1212 gmc_v9_0_set_gfxhub_funcs(adev); 1213 1214 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1215 adev->gmc.shared_aperture_end = 1216 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1217 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 1218 adev->gmc.private_aperture_end = 1219 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1220 1221 return 0; 1222 } 1223 1224 static int gmc_v9_0_late_init(void *handle) 1225 { 1226 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1227 int r; 1228 1229 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 1230 if (r) 1231 return r; 1232 1233 /* 1234 * Workaround performance drop issue with VBIOS enables partial 1235 * writes, while disables HBM ECC for vega10. 1236 */ 1237 if (!amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_VEGA10)) { 1238 if (!(adev->ras_features & (1 << AMDGPU_RAS_BLOCK__UMC))) { 1239 if (adev->df.funcs->enable_ecc_force_par_wr_rmw) 1240 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false); 1241 } 1242 } 1243 1244 if (adev->mmhub.ras_funcs && 1245 adev->mmhub.ras_funcs->reset_ras_error_count) 1246 adev->mmhub.ras_funcs->reset_ras_error_count(adev); 1247 1248 r = amdgpu_gmc_ras_late_init(adev); 1249 if (r) 1250 return r; 1251 1252 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1253 } 1254 1255 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 1256 struct amdgpu_gmc *mc) 1257 { 1258 u64 base = 0; 1259 1260 if (!amdgpu_sriov_vf(adev)) 1261 base = adev->mmhub.funcs->get_fb_location(adev); 1262 1263 /* add the xgmi offset of the physical node */ 1264 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1265 if (adev->gmc.xgmi.connected_to_cpu) { 1266 amdgpu_gmc_sysvm_location(adev, mc); 1267 } else { 1268 amdgpu_gmc_vram_location(adev, mc, base); 1269 amdgpu_gmc_gart_location(adev, mc); 1270 amdgpu_gmc_agp_location(adev, mc); 1271 } 1272 /* base offset of vram pages */ 1273 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 1274 1275 /* XXX: add the xgmi offset of the physical node? */ 1276 adev->vm_manager.vram_base_offset += 1277 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1278 } 1279 1280 /** 1281 * gmc_v9_0_mc_init - initialize the memory controller driver params 1282 * 1283 * @adev: amdgpu_device pointer 1284 * 1285 * Look up the amount of vram, vram width, and decide how to place 1286 * vram and gart within the GPU's physical address space. 1287 * Returns 0 for success. 1288 */ 1289 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 1290 { 1291 int r; 1292 1293 /* size in MB on si */ 1294 adev->gmc.mc_vram_size = 1295 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 1296 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 1297 1298 if (!(adev->flags & AMD_IS_APU) && 1299 !adev->gmc.xgmi.connected_to_cpu) { 1300 r = amdgpu_device_resize_fb_bar(adev); 1301 if (r) 1302 return r; 1303 } 1304 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 1305 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 1306 1307 #ifdef CONFIG_X86_64 1308 /* 1309 * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi 1310 * interface can use VRAM through here as it appears system reserved 1311 * memory in host address space. 1312 * 1313 * For APUs, VRAM is just the stolen system memory and can be accessed 1314 * directly. 1315 * 1316 * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR. 1317 */ 1318 1319 /* check whether both host-gpu and gpu-gpu xgmi links exist */ 1320 if ((adev->flags & AMD_IS_APU) || 1321 (adev->gmc.xgmi.supported && 1322 adev->gmc.xgmi.connected_to_cpu)) { 1323 adev->gmc.aper_base = 1324 adev->gfxhub.funcs->get_mc_fb_offset(adev) + 1325 adev->gmc.xgmi.physical_node_id * 1326 adev->gmc.xgmi.node_segment_size; 1327 adev->gmc.aper_size = adev->gmc.real_vram_size; 1328 } 1329 1330 #endif 1331 /* In case the PCI BAR is larger than the actual amount of vram */ 1332 adev->gmc.visible_vram_size = adev->gmc.aper_size; 1333 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 1334 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 1335 1336 /* set the gart size */ 1337 if (amdgpu_gart_size == -1) { 1338 switch (adev->asic_type) { 1339 case CHIP_VEGA10: /* all engines support GPUVM */ 1340 case CHIP_VEGA12: /* all engines support GPUVM */ 1341 case CHIP_VEGA20: 1342 case CHIP_ARCTURUS: 1343 case CHIP_ALDEBARAN: 1344 default: 1345 adev->gmc.gart_size = 512ULL << 20; 1346 break; 1347 case CHIP_RAVEN: /* DCE SG support */ 1348 case CHIP_RENOIR: 1349 adev->gmc.gart_size = 1024ULL << 20; 1350 break; 1351 } 1352 } else { 1353 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 1354 } 1355 1356 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; 1357 1358 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); 1359 1360 return 0; 1361 } 1362 1363 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 1364 { 1365 int r; 1366 1367 if (adev->gart.bo) { 1368 WARN(1, "VEGA10 PCIE GART already initialized\n"); 1369 return 0; 1370 } 1371 1372 if (adev->gmc.xgmi.connected_to_cpu) { 1373 adev->gmc.vmid0_page_table_depth = 1; 1374 adev->gmc.vmid0_page_table_block_size = 12; 1375 } else { 1376 adev->gmc.vmid0_page_table_depth = 0; 1377 adev->gmc.vmid0_page_table_block_size = 0; 1378 } 1379 1380 /* Initialize common gart structure */ 1381 r = amdgpu_gart_init(adev); 1382 if (r) 1383 return r; 1384 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 1385 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) | 1386 AMDGPU_PTE_EXECUTABLE; 1387 1388 r = amdgpu_gart_table_vram_alloc(adev); 1389 if (r) 1390 return r; 1391 1392 if (adev->gmc.xgmi.connected_to_cpu) { 1393 r = amdgpu_gmc_pdb0_alloc(adev); 1394 } 1395 1396 return r; 1397 } 1398 1399 /** 1400 * gmc_v9_0_save_registers - saves regs 1401 * 1402 * @adev: amdgpu_device pointer 1403 * 1404 * This saves potential register values that should be 1405 * restored upon resume 1406 */ 1407 static void gmc_v9_0_save_registers(struct amdgpu_device *adev) 1408 { 1409 if (adev->asic_type == CHIP_RAVEN) 1410 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); 1411 } 1412 1413 static int gmc_v9_0_sw_init(void *handle) 1414 { 1415 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 1416 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1417 1418 adev->gfxhub.funcs->init(adev); 1419 1420 adev->mmhub.funcs->init(adev); 1421 1422 spin_lock_init(&adev->gmc.invalidate_lock); 1423 1424 r = amdgpu_atomfirmware_get_vram_info(adev, 1425 &vram_width, &vram_type, &vram_vendor); 1426 if (amdgpu_sriov_vf(adev)) 1427 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, 1428 * and DF related registers is not readable, seems hardcord is the 1429 * only way to set the correct vram_width 1430 */ 1431 adev->gmc.vram_width = 2048; 1432 else if (amdgpu_emu_mode != 1) 1433 adev->gmc.vram_width = vram_width; 1434 1435 if (!adev->gmc.vram_width) { 1436 int chansize, numchan; 1437 1438 /* hbm memory channel size */ 1439 if (adev->flags & AMD_IS_APU) 1440 chansize = 64; 1441 else 1442 chansize = 128; 1443 1444 numchan = adev->df.funcs->get_hbm_channel_number(adev); 1445 adev->gmc.vram_width = numchan * chansize; 1446 } 1447 1448 adev->gmc.vram_type = vram_type; 1449 adev->gmc.vram_vendor = vram_vendor; 1450 switch (adev->asic_type) { 1451 case CHIP_RAVEN: 1452 adev->num_vmhubs = 2; 1453 1454 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 1455 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1456 } else { 1457 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 1458 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 1459 adev->gmc.translate_further = 1460 adev->vm_manager.num_level > 1; 1461 } 1462 break; 1463 case CHIP_VEGA10: 1464 case CHIP_VEGA12: 1465 case CHIP_VEGA20: 1466 case CHIP_RENOIR: 1467 case CHIP_ALDEBARAN: 1468 adev->num_vmhubs = 2; 1469 1470 1471 /* 1472 * To fulfill 4-level page support, 1473 * vm size is 256TB (48bit), maximum size of Vega10, 1474 * block size 512 (9bit) 1475 */ 1476 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */ 1477 if (amdgpu_sriov_vf(adev)) 1478 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47); 1479 else 1480 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1481 break; 1482 case CHIP_ARCTURUS: 1483 adev->num_vmhubs = 3; 1484 1485 /* Keep the vm size same with Vega20 */ 1486 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1487 break; 1488 default: 1489 break; 1490 } 1491 1492 /* This interrupt is VMC page fault.*/ 1493 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, 1494 &adev->gmc.vm_fault); 1495 if (r) 1496 return r; 1497 1498 if (adev->asic_type == CHIP_ARCTURUS) { 1499 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT, 1500 &adev->gmc.vm_fault); 1501 if (r) 1502 return r; 1503 } 1504 1505 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, 1506 &adev->gmc.vm_fault); 1507 1508 if (r) 1509 return r; 1510 1511 if (!amdgpu_sriov_vf(adev) && 1512 !adev->gmc.xgmi.connected_to_cpu) { 1513 /* interrupt sent to DF. */ 1514 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 1515 &adev->gmc.ecc_irq); 1516 if (r) 1517 return r; 1518 } 1519 1520 /* Set the internal MC address mask 1521 * This is the max address of the GPU's 1522 * internal address space. 1523 */ 1524 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 1525 1526 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 1527 if (r) { 1528 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 1529 return r; 1530 } 1531 adev->need_swiotlb = drm_need_swiotlb(44); 1532 1533 if (adev->gmc.xgmi.supported) { 1534 r = adev->gfxhub.funcs->get_xgmi_info(adev); 1535 if (r) 1536 return r; 1537 } 1538 1539 r = gmc_v9_0_mc_init(adev); 1540 if (r) 1541 return r; 1542 1543 amdgpu_gmc_get_vbios_allocations(adev); 1544 1545 /* Memory manager */ 1546 r = amdgpu_bo_init(adev); 1547 if (r) 1548 return r; 1549 1550 r = gmc_v9_0_gart_init(adev); 1551 if (r) 1552 return r; 1553 1554 /* 1555 * number of VMs 1556 * VMID 0 is reserved for System 1557 * amdgpu graphics/compute will use VMIDs 1..n-1 1558 * amdkfd will use VMIDs n..15 1559 * 1560 * The first KFD VMID is 8 for GPUs with graphics, 3 for 1561 * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs 1562 * for video processing. 1563 */ 1564 adev->vm_manager.first_kfd_vmid = 1565 (adev->asic_type == CHIP_ARCTURUS || 1566 adev->asic_type == CHIP_ALDEBARAN) ? 3 : 8; 1567 1568 amdgpu_vm_manager_init(adev); 1569 1570 gmc_v9_0_save_registers(adev); 1571 1572 return 0; 1573 } 1574 1575 static int gmc_v9_0_sw_fini(void *handle) 1576 { 1577 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1578 1579 amdgpu_gmc_ras_fini(adev); 1580 amdgpu_gem_force_release(adev); 1581 amdgpu_vm_manager_fini(adev); 1582 amdgpu_gart_table_vram_free(adev); 1583 amdgpu_bo_unref(&adev->gmc.pdb0_bo); 1584 amdgpu_bo_fini(adev); 1585 amdgpu_gart_fini(adev); 1586 1587 return 0; 1588 } 1589 1590 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 1591 { 1592 1593 switch (adev->asic_type) { 1594 case CHIP_VEGA10: 1595 if (amdgpu_sriov_vf(adev)) 1596 break; 1597 fallthrough; 1598 case CHIP_VEGA20: 1599 soc15_program_register_sequence(adev, 1600 golden_settings_mmhub_1_0_0, 1601 ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 1602 soc15_program_register_sequence(adev, 1603 golden_settings_athub_1_0_0, 1604 ARRAY_SIZE(golden_settings_athub_1_0_0)); 1605 break; 1606 case CHIP_VEGA12: 1607 break; 1608 case CHIP_RAVEN: 1609 /* TODO for renoir */ 1610 soc15_program_register_sequence(adev, 1611 golden_settings_athub_1_0_0, 1612 ARRAY_SIZE(golden_settings_athub_1_0_0)); 1613 break; 1614 default: 1615 break; 1616 } 1617 } 1618 1619 /** 1620 * gmc_v9_0_restore_registers - restores regs 1621 * 1622 * @adev: amdgpu_device pointer 1623 * 1624 * This restores register values, saved at suspend. 1625 */ 1626 void gmc_v9_0_restore_registers(struct amdgpu_device *adev) 1627 { 1628 if (adev->asic_type == CHIP_RAVEN) { 1629 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register); 1630 WARN_ON(adev->gmc.sdpif_register != 1631 RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0)); 1632 } 1633 } 1634 1635 /** 1636 * gmc_v9_0_gart_enable - gart enable 1637 * 1638 * @adev: amdgpu_device pointer 1639 */ 1640 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 1641 { 1642 int r; 1643 1644 if (adev->gmc.xgmi.connected_to_cpu) 1645 amdgpu_gmc_init_pdb0(adev); 1646 1647 if (adev->gart.bo == NULL) { 1648 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 1649 return -EINVAL; 1650 } 1651 1652 r = amdgpu_gart_table_vram_pin(adev); 1653 if (r) 1654 return r; 1655 1656 r = adev->gfxhub.funcs->gart_enable(adev); 1657 if (r) 1658 return r; 1659 1660 r = adev->mmhub.funcs->gart_enable(adev); 1661 if (r) 1662 return r; 1663 1664 DRM_INFO("PCIE GART of %uM enabled.\n", 1665 (unsigned)(adev->gmc.gart_size >> 20)); 1666 if (adev->gmc.pdb0_bo) 1667 DRM_INFO("PDB0 located at 0x%016llX\n", 1668 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo)); 1669 DRM_INFO("PTB located at 0x%016llX\n", 1670 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 1671 1672 adev->gart.ready = true; 1673 return 0; 1674 } 1675 1676 static int gmc_v9_0_hw_init(void *handle) 1677 { 1678 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1679 bool value; 1680 int r, i; 1681 1682 /* The sequence of these two function calls matters.*/ 1683 gmc_v9_0_init_golden_registers(adev); 1684 1685 if (adev->mode_info.num_crtc) { 1686 /* Lockout access through VGA aperture*/ 1687 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 1688 /* disable VGA render */ 1689 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 1690 } 1691 1692 if (adev->mmhub.funcs->update_power_gating) 1693 adev->mmhub.funcs->update_power_gating(adev, true); 1694 1695 adev->hdp.funcs->init_registers(adev); 1696 1697 /* After HDP is initialized, flush HDP.*/ 1698 adev->hdp.funcs->flush_hdp(adev, NULL); 1699 1700 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 1701 value = false; 1702 else 1703 value = true; 1704 1705 if (!amdgpu_sriov_vf(adev)) { 1706 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 1707 adev->mmhub.funcs->set_fault_enable_default(adev, value); 1708 } 1709 for (i = 0; i < adev->num_vmhubs; ++i) 1710 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0); 1711 1712 if (adev->umc.funcs && adev->umc.funcs->init_registers) 1713 adev->umc.funcs->init_registers(adev); 1714 1715 r = gmc_v9_0_gart_enable(adev); 1716 1717 return r; 1718 } 1719 1720 /** 1721 * gmc_v9_0_gart_disable - gart disable 1722 * 1723 * @adev: amdgpu_device pointer 1724 * 1725 * This disables all VM page table. 1726 */ 1727 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 1728 { 1729 adev->gfxhub.funcs->gart_disable(adev); 1730 adev->mmhub.funcs->gart_disable(adev); 1731 amdgpu_gart_table_vram_unpin(adev); 1732 } 1733 1734 static int gmc_v9_0_hw_fini(void *handle) 1735 { 1736 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1737 1738 if (amdgpu_sriov_vf(adev)) { 1739 /* full access mode, so don't touch any GMC register */ 1740 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 1741 return 0; 1742 } 1743 1744 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 1745 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1746 gmc_v9_0_gart_disable(adev); 1747 1748 return 0; 1749 } 1750 1751 static int gmc_v9_0_suspend(void *handle) 1752 { 1753 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1754 1755 return gmc_v9_0_hw_fini(adev); 1756 } 1757 1758 static int gmc_v9_0_resume(void *handle) 1759 { 1760 int r; 1761 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1762 1763 r = gmc_v9_0_hw_init(adev); 1764 if (r) 1765 return r; 1766 1767 amdgpu_vmid_reset_all(adev); 1768 1769 return 0; 1770 } 1771 1772 static bool gmc_v9_0_is_idle(void *handle) 1773 { 1774 /* MC is always ready in GMC v9.*/ 1775 return true; 1776 } 1777 1778 static int gmc_v9_0_wait_for_idle(void *handle) 1779 { 1780 /* There is no need to wait for MC idle in GMC v9.*/ 1781 return 0; 1782 } 1783 1784 static int gmc_v9_0_soft_reset(void *handle) 1785 { 1786 /* XXX for emulation.*/ 1787 return 0; 1788 } 1789 1790 static int gmc_v9_0_set_clockgating_state(void *handle, 1791 enum amd_clockgating_state state) 1792 { 1793 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1794 1795 adev->mmhub.funcs->set_clockgating(adev, state); 1796 1797 athub_v1_0_set_clockgating(adev, state); 1798 1799 return 0; 1800 } 1801 1802 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags) 1803 { 1804 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1805 1806 adev->mmhub.funcs->get_clockgating(adev, flags); 1807 1808 athub_v1_0_get_clockgating(adev, flags); 1809 } 1810 1811 static int gmc_v9_0_set_powergating_state(void *handle, 1812 enum amd_powergating_state state) 1813 { 1814 return 0; 1815 } 1816 1817 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 1818 .name = "gmc_v9_0", 1819 .early_init = gmc_v9_0_early_init, 1820 .late_init = gmc_v9_0_late_init, 1821 .sw_init = gmc_v9_0_sw_init, 1822 .sw_fini = gmc_v9_0_sw_fini, 1823 .hw_init = gmc_v9_0_hw_init, 1824 .hw_fini = gmc_v9_0_hw_fini, 1825 .suspend = gmc_v9_0_suspend, 1826 .resume = gmc_v9_0_resume, 1827 .is_idle = gmc_v9_0_is_idle, 1828 .wait_for_idle = gmc_v9_0_wait_for_idle, 1829 .soft_reset = gmc_v9_0_soft_reset, 1830 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 1831 .set_powergating_state = gmc_v9_0_set_powergating_state, 1832 .get_clockgating_state = gmc_v9_0_get_clockgating_state, 1833 }; 1834 1835 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = 1836 { 1837 .type = AMD_IP_BLOCK_TYPE_GMC, 1838 .major = 9, 1839 .minor = 0, 1840 .rev = 0, 1841 .funcs = &gmc_v9_0_ip_funcs, 1842 }; 1843