1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/pci.h> 26 27 #include <drm/drm_cache.h> 28 29 #include "amdgpu.h" 30 #include "gmc_v9_0.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_gem.h" 33 34 #include "gc/gc_9_0_sh_mask.h" 35 #include "dce/dce_12_0_offset.h" 36 #include "dce/dce_12_0_sh_mask.h" 37 #include "vega10_enum.h" 38 #include "mmhub/mmhub_1_0_offset.h" 39 #include "athub/athub_1_0_sh_mask.h" 40 #include "athub/athub_1_0_offset.h" 41 #include "oss/osssys_4_0_offset.h" 42 43 #include "soc15.h" 44 #include "soc15d.h" 45 #include "soc15_common.h" 46 #include "umc/umc_6_0_sh_mask.h" 47 48 #include "gfxhub_v1_0.h" 49 #include "mmhub_v1_0.h" 50 #include "athub_v1_0.h" 51 #include "gfxhub_v1_1.h" 52 #include "gfxhub_v1_2.h" 53 #include "mmhub_v9_4.h" 54 #include "mmhub_v1_7.h" 55 #include "mmhub_v1_8.h" 56 #include "umc_v6_1.h" 57 #include "umc_v6_0.h" 58 #include "umc_v6_7.h" 59 #include "hdp_v4_0.h" 60 #include "mca_v3_0.h" 61 62 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 63 64 #include "amdgpu_ras.h" 65 #include "amdgpu_xgmi.h" 66 67 #include "amdgpu_reset.h" 68 69 /* add these here since we already include dce12 headers and these are for DCN */ 70 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 71 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 72 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 73 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 74 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL 75 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L 76 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d 77 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2 78 79 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2 0x05ea 80 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX 2 81 82 83 static const char *gfxhub_client_ids[] = { 84 "CB", 85 "DB", 86 "IA", 87 "WD", 88 "CPF", 89 "CPC", 90 "CPG", 91 "RLC", 92 "TCP", 93 "SQC (inst)", 94 "SQC (data)", 95 "SQG", 96 "PA", 97 }; 98 99 static const char *mmhub_client_ids_raven[][2] = { 100 [0][0] = "MP1", 101 [1][0] = "MP0", 102 [2][0] = "VCN", 103 [3][0] = "VCNU", 104 [4][0] = "HDP", 105 [5][0] = "DCE", 106 [13][0] = "UTCL2", 107 [19][0] = "TLS", 108 [26][0] = "OSS", 109 [27][0] = "SDMA0", 110 [0][1] = "MP1", 111 [1][1] = "MP0", 112 [2][1] = "VCN", 113 [3][1] = "VCNU", 114 [4][1] = "HDP", 115 [5][1] = "XDP", 116 [6][1] = "DBGU0", 117 [7][1] = "DCE", 118 [8][1] = "DCEDWB0", 119 [9][1] = "DCEDWB1", 120 [26][1] = "OSS", 121 [27][1] = "SDMA0", 122 }; 123 124 static const char *mmhub_client_ids_renoir[][2] = { 125 [0][0] = "MP1", 126 [1][0] = "MP0", 127 [2][0] = "HDP", 128 [4][0] = "DCEDMC", 129 [5][0] = "DCEVGA", 130 [13][0] = "UTCL2", 131 [19][0] = "TLS", 132 [26][0] = "OSS", 133 [27][0] = "SDMA0", 134 [28][0] = "VCN", 135 [29][0] = "VCNU", 136 [30][0] = "JPEG", 137 [0][1] = "MP1", 138 [1][1] = "MP0", 139 [2][1] = "HDP", 140 [3][1] = "XDP", 141 [6][1] = "DBGU0", 142 [7][1] = "DCEDMC", 143 [8][1] = "DCEVGA", 144 [9][1] = "DCEDWB", 145 [26][1] = "OSS", 146 [27][1] = "SDMA0", 147 [28][1] = "VCN", 148 [29][1] = "VCNU", 149 [30][1] = "JPEG", 150 }; 151 152 static const char *mmhub_client_ids_vega10[][2] = { 153 [0][0] = "MP0", 154 [1][0] = "UVD", 155 [2][0] = "UVDU", 156 [3][0] = "HDP", 157 [13][0] = "UTCL2", 158 [14][0] = "OSS", 159 [15][0] = "SDMA1", 160 [32+0][0] = "VCE0", 161 [32+1][0] = "VCE0U", 162 [32+2][0] = "XDMA", 163 [32+3][0] = "DCE", 164 [32+4][0] = "MP1", 165 [32+14][0] = "SDMA0", 166 [0][1] = "MP0", 167 [1][1] = "UVD", 168 [2][1] = "UVDU", 169 [3][1] = "DBGU0", 170 [4][1] = "HDP", 171 [5][1] = "XDP", 172 [14][1] = "OSS", 173 [15][1] = "SDMA0", 174 [32+0][1] = "VCE0", 175 [32+1][1] = "VCE0U", 176 [32+2][1] = "XDMA", 177 [32+3][1] = "DCE", 178 [32+4][1] = "DCEDWB", 179 [32+5][1] = "MP1", 180 [32+6][1] = "DBGU1", 181 [32+14][1] = "SDMA1", 182 }; 183 184 static const char *mmhub_client_ids_vega12[][2] = { 185 [0][0] = "MP0", 186 [1][0] = "VCE0", 187 [2][0] = "VCE0U", 188 [3][0] = "HDP", 189 [13][0] = "UTCL2", 190 [14][0] = "OSS", 191 [15][0] = "SDMA1", 192 [32+0][0] = "DCE", 193 [32+1][0] = "XDMA", 194 [32+2][0] = "UVD", 195 [32+3][0] = "UVDU", 196 [32+4][0] = "MP1", 197 [32+15][0] = "SDMA0", 198 [0][1] = "MP0", 199 [1][1] = "VCE0", 200 [2][1] = "VCE0U", 201 [3][1] = "DBGU0", 202 [4][1] = "HDP", 203 [5][1] = "XDP", 204 [14][1] = "OSS", 205 [15][1] = "SDMA0", 206 [32+0][1] = "DCE", 207 [32+1][1] = "DCEDWB", 208 [32+2][1] = "XDMA", 209 [32+3][1] = "UVD", 210 [32+4][1] = "UVDU", 211 [32+5][1] = "MP1", 212 [32+6][1] = "DBGU1", 213 [32+15][1] = "SDMA1", 214 }; 215 216 static const char *mmhub_client_ids_vega20[][2] = { 217 [0][0] = "XDMA", 218 [1][0] = "DCE", 219 [2][0] = "VCE0", 220 [3][0] = "VCE0U", 221 [4][0] = "UVD", 222 [5][0] = "UVD1U", 223 [13][0] = "OSS", 224 [14][0] = "HDP", 225 [15][0] = "SDMA0", 226 [32+0][0] = "UVD", 227 [32+1][0] = "UVDU", 228 [32+2][0] = "MP1", 229 [32+3][0] = "MP0", 230 [32+12][0] = "UTCL2", 231 [32+14][0] = "SDMA1", 232 [0][1] = "XDMA", 233 [1][1] = "DCE", 234 [2][1] = "DCEDWB", 235 [3][1] = "VCE0", 236 [4][1] = "VCE0U", 237 [5][1] = "UVD1", 238 [6][1] = "UVD1U", 239 [7][1] = "DBGU0", 240 [8][1] = "XDP", 241 [13][1] = "OSS", 242 [14][1] = "HDP", 243 [15][1] = "SDMA0", 244 [32+0][1] = "UVD", 245 [32+1][1] = "UVDU", 246 [32+2][1] = "DBGU1", 247 [32+3][1] = "MP1", 248 [32+4][1] = "MP0", 249 [32+14][1] = "SDMA1", 250 }; 251 252 static const char *mmhub_client_ids_arcturus[][2] = { 253 [0][0] = "DBGU1", 254 [1][0] = "XDP", 255 [2][0] = "MP1", 256 [14][0] = "HDP", 257 [171][0] = "JPEG", 258 [172][0] = "VCN", 259 [173][0] = "VCNU", 260 [203][0] = "JPEG1", 261 [204][0] = "VCN1", 262 [205][0] = "VCN1U", 263 [256][0] = "SDMA0", 264 [257][0] = "SDMA1", 265 [258][0] = "SDMA2", 266 [259][0] = "SDMA3", 267 [260][0] = "SDMA4", 268 [261][0] = "SDMA5", 269 [262][0] = "SDMA6", 270 [263][0] = "SDMA7", 271 [384][0] = "OSS", 272 [0][1] = "DBGU1", 273 [1][1] = "XDP", 274 [2][1] = "MP1", 275 [14][1] = "HDP", 276 [171][1] = "JPEG", 277 [172][1] = "VCN", 278 [173][1] = "VCNU", 279 [203][1] = "JPEG1", 280 [204][1] = "VCN1", 281 [205][1] = "VCN1U", 282 [256][1] = "SDMA0", 283 [257][1] = "SDMA1", 284 [258][1] = "SDMA2", 285 [259][1] = "SDMA3", 286 [260][1] = "SDMA4", 287 [261][1] = "SDMA5", 288 [262][1] = "SDMA6", 289 [263][1] = "SDMA7", 290 [384][1] = "OSS", 291 }; 292 293 static const char *mmhub_client_ids_aldebaran[][2] = { 294 [2][0] = "MP1", 295 [3][0] = "MP0", 296 [32+1][0] = "DBGU_IO0", 297 [32+2][0] = "DBGU_IO2", 298 [32+4][0] = "MPIO", 299 [96+11][0] = "JPEG0", 300 [96+12][0] = "VCN0", 301 [96+13][0] = "VCNU0", 302 [128+11][0] = "JPEG1", 303 [128+12][0] = "VCN1", 304 [128+13][0] = "VCNU1", 305 [160+1][0] = "XDP", 306 [160+14][0] = "HDP", 307 [256+0][0] = "SDMA0", 308 [256+1][0] = "SDMA1", 309 [256+2][0] = "SDMA2", 310 [256+3][0] = "SDMA3", 311 [256+4][0] = "SDMA4", 312 [384+0][0] = "OSS", 313 [2][1] = "MP1", 314 [3][1] = "MP0", 315 [32+1][1] = "DBGU_IO0", 316 [32+2][1] = "DBGU_IO2", 317 [32+4][1] = "MPIO", 318 [96+11][1] = "JPEG0", 319 [96+12][1] = "VCN0", 320 [96+13][1] = "VCNU0", 321 [128+11][1] = "JPEG1", 322 [128+12][1] = "VCN1", 323 [128+13][1] = "VCNU1", 324 [160+1][1] = "XDP", 325 [160+14][1] = "HDP", 326 [256+0][1] = "SDMA0", 327 [256+1][1] = "SDMA1", 328 [256+2][1] = "SDMA2", 329 [256+3][1] = "SDMA3", 330 [256+4][1] = "SDMA4", 331 [384+0][1] = "OSS", 332 }; 333 334 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = 335 { 336 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), 337 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) 338 }; 339 340 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = 341 { 342 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), 343 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) 344 }; 345 346 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { 347 (0x000143c0 + 0x00000000), 348 (0x000143c0 + 0x00000800), 349 (0x000143c0 + 0x00001000), 350 (0x000143c0 + 0x00001800), 351 (0x000543c0 + 0x00000000), 352 (0x000543c0 + 0x00000800), 353 (0x000543c0 + 0x00001000), 354 (0x000543c0 + 0x00001800), 355 (0x000943c0 + 0x00000000), 356 (0x000943c0 + 0x00000800), 357 (0x000943c0 + 0x00001000), 358 (0x000943c0 + 0x00001800), 359 (0x000d43c0 + 0x00000000), 360 (0x000d43c0 + 0x00000800), 361 (0x000d43c0 + 0x00001000), 362 (0x000d43c0 + 0x00001800), 363 (0x001143c0 + 0x00000000), 364 (0x001143c0 + 0x00000800), 365 (0x001143c0 + 0x00001000), 366 (0x001143c0 + 0x00001800), 367 (0x001543c0 + 0x00000000), 368 (0x001543c0 + 0x00000800), 369 (0x001543c0 + 0x00001000), 370 (0x001543c0 + 0x00001800), 371 (0x001943c0 + 0x00000000), 372 (0x001943c0 + 0x00000800), 373 (0x001943c0 + 0x00001000), 374 (0x001943c0 + 0x00001800), 375 (0x001d43c0 + 0x00000000), 376 (0x001d43c0 + 0x00000800), 377 (0x001d43c0 + 0x00001000), 378 (0x001d43c0 + 0x00001800), 379 }; 380 381 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { 382 (0x000143e0 + 0x00000000), 383 (0x000143e0 + 0x00000800), 384 (0x000143e0 + 0x00001000), 385 (0x000143e0 + 0x00001800), 386 (0x000543e0 + 0x00000000), 387 (0x000543e0 + 0x00000800), 388 (0x000543e0 + 0x00001000), 389 (0x000543e0 + 0x00001800), 390 (0x000943e0 + 0x00000000), 391 (0x000943e0 + 0x00000800), 392 (0x000943e0 + 0x00001000), 393 (0x000943e0 + 0x00001800), 394 (0x000d43e0 + 0x00000000), 395 (0x000d43e0 + 0x00000800), 396 (0x000d43e0 + 0x00001000), 397 (0x000d43e0 + 0x00001800), 398 (0x001143e0 + 0x00000000), 399 (0x001143e0 + 0x00000800), 400 (0x001143e0 + 0x00001000), 401 (0x001143e0 + 0x00001800), 402 (0x001543e0 + 0x00000000), 403 (0x001543e0 + 0x00000800), 404 (0x001543e0 + 0x00001000), 405 (0x001543e0 + 0x00001800), 406 (0x001943e0 + 0x00000000), 407 (0x001943e0 + 0x00000800), 408 (0x001943e0 + 0x00001000), 409 (0x001943e0 + 0x00001800), 410 (0x001d43e0 + 0x00000000), 411 (0x001d43e0 + 0x00000800), 412 (0x001d43e0 + 0x00001000), 413 (0x001d43e0 + 0x00001800), 414 }; 415 416 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, 417 struct amdgpu_irq_src *src, 418 unsigned type, 419 enum amdgpu_interrupt_state state) 420 { 421 u32 bits, i, tmp, reg; 422 423 /* Devices newer then VEGA10/12 shall have these programming 424 sequences performed by PSP BL */ 425 if (adev->asic_type >= CHIP_VEGA20) 426 return 0; 427 428 bits = 0x7f; 429 430 switch (state) { 431 case AMDGPU_IRQ_STATE_DISABLE: 432 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 433 reg = ecc_umc_mcumc_ctrl_addrs[i]; 434 tmp = RREG32(reg); 435 tmp &= ~bits; 436 WREG32(reg, tmp); 437 } 438 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 439 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 440 tmp = RREG32(reg); 441 tmp &= ~bits; 442 WREG32(reg, tmp); 443 } 444 break; 445 case AMDGPU_IRQ_STATE_ENABLE: 446 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 447 reg = ecc_umc_mcumc_ctrl_addrs[i]; 448 tmp = RREG32(reg); 449 tmp |= bits; 450 WREG32(reg, tmp); 451 } 452 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 453 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 454 tmp = RREG32(reg); 455 tmp |= bits; 456 WREG32(reg, tmp); 457 } 458 break; 459 default: 460 break; 461 } 462 463 return 0; 464 } 465 466 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 467 struct amdgpu_irq_src *src, 468 unsigned type, 469 enum amdgpu_interrupt_state state) 470 { 471 struct amdgpu_vmhub *hub; 472 u32 tmp, reg, bits, i, j; 473 474 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 475 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 476 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 477 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 478 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 479 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 480 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 481 482 switch (state) { 483 case AMDGPU_IRQ_STATE_DISABLE: 484 for (j = 0; j < adev->num_vmhubs; j++) { 485 hub = &adev->vmhub[j]; 486 for (i = 0; i < 16; i++) { 487 reg = hub->vm_context0_cntl + i; 488 489 /* This works because this interrupt is only 490 * enabled at init/resume and disabled in 491 * fini/suspend, so the overall state doesn't 492 * change over the course of suspend/resume. 493 */ 494 if (adev->in_s0ix && (j == AMDGPU_GFXHUB_0)) 495 continue; 496 497 if (j == AMDGPU_GFXHUB_0) 498 tmp = RREG32_SOC15_IP(GC, reg); 499 else 500 tmp = RREG32_SOC15_IP(MMHUB, reg); 501 502 tmp &= ~bits; 503 504 if (j == AMDGPU_GFXHUB_0) 505 WREG32_SOC15_IP(GC, reg, tmp); 506 else 507 WREG32_SOC15_IP(MMHUB, reg, tmp); 508 } 509 } 510 break; 511 case AMDGPU_IRQ_STATE_ENABLE: 512 for (j = 0; j < adev->num_vmhubs; j++) { 513 hub = &adev->vmhub[j]; 514 for (i = 0; i < 16; i++) { 515 reg = hub->vm_context0_cntl + i; 516 517 /* This works because this interrupt is only 518 * enabled at init/resume and disabled in 519 * fini/suspend, so the overall state doesn't 520 * change over the course of suspend/resume. 521 */ 522 if (adev->in_s0ix && (j == AMDGPU_GFXHUB_0)) 523 continue; 524 525 if (j == AMDGPU_GFXHUB_0) 526 tmp = RREG32_SOC15_IP(GC, reg); 527 else 528 tmp = RREG32_SOC15_IP(MMHUB, reg); 529 530 tmp |= bits; 531 532 if (j == AMDGPU_GFXHUB_0) 533 WREG32_SOC15_IP(GC, reg, tmp); 534 else 535 WREG32_SOC15_IP(MMHUB, reg, tmp); 536 } 537 } 538 break; 539 default: 540 break; 541 } 542 543 return 0; 544 } 545 546 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 547 struct amdgpu_irq_src *source, 548 struct amdgpu_iv_entry *entry) 549 { 550 bool retry_fault = !!(entry->src_data[1] & 0x80); 551 bool write_fault = !!(entry->src_data[1] & 0x20); 552 uint32_t status = 0, cid = 0, rw = 0; 553 struct amdgpu_task_info task_info; 554 struct amdgpu_vmhub *hub; 555 const char *mmhub_cid; 556 const char *hub_name; 557 u64 addr; 558 559 addr = (u64)entry->src_data[0] << 12; 560 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 561 562 if (retry_fault) { 563 /* Returning 1 here also prevents sending the IV to the KFD */ 564 565 /* Process it onyl if it's the first fault for this address */ 566 if (entry->ih != &adev->irq.ih_soft && 567 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, 568 entry->timestamp)) 569 return 1; 570 571 /* Delegate it to a different ring if the hardware hasn't 572 * already done it. 573 */ 574 if (entry->ih == &adev->irq.ih) { 575 amdgpu_irq_delegate(adev, entry, 8); 576 return 1; 577 } 578 579 /* Try to handle the recoverable page faults by filling page 580 * tables 581 */ 582 if (amdgpu_vm_handle_fault(adev, entry->pasid, addr, write_fault)) 583 return 1; 584 } 585 586 if (!printk_ratelimit()) 587 return 0; 588 589 if (entry->client_id == SOC15_IH_CLIENTID_VMC) { 590 hub_name = "mmhub0"; 591 hub = &adev->vmhub[AMDGPU_MMHUB_0]; 592 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) { 593 hub_name = "mmhub1"; 594 hub = &adev->vmhub[AMDGPU_MMHUB_1]; 595 } else { 596 hub_name = "gfxhub0"; 597 hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 598 } 599 600 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 601 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 602 603 dev_err(adev->dev, 604 "[%s] %s page fault (src_id:%u ring:%u vmid:%u " 605 "pasid:%u, for process %s pid %d thread %s pid %d)\n", 606 hub_name, retry_fault ? "retry" : "no-retry", 607 entry->src_id, entry->ring_id, entry->vmid, 608 entry->pasid, task_info.process_name, task_info.tgid, 609 task_info.task_name, task_info.pid); 610 dev_err(adev->dev, " in page starting at address 0x%016llx from IH client 0x%x (%s)\n", 611 addr, entry->client_id, 612 soc15_ih_clientid_name[entry->client_id]); 613 614 if (amdgpu_sriov_vf(adev)) 615 return 0; 616 617 /* 618 * Issue a dummy read to wait for the status register to 619 * be updated to avoid reading an incorrect value due to 620 * the new fast GRBM interface. 621 */ 622 if ((entry->vmid_src == AMDGPU_GFXHUB_0) && 623 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2))) 624 RREG32(hub->vm_l2_pro_fault_status); 625 626 status = RREG32(hub->vm_l2_pro_fault_status); 627 cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID); 628 rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW); 629 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 630 631 632 dev_err(adev->dev, 633 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 634 status); 635 if (hub == &adev->vmhub[AMDGPU_GFXHUB_0]) { 636 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 637 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : 638 gfxhub_client_ids[cid], 639 cid); 640 } else { 641 switch (adev->ip_versions[MMHUB_HWIP][0]) { 642 case IP_VERSION(9, 0, 0): 643 mmhub_cid = mmhub_client_ids_vega10[cid][rw]; 644 break; 645 case IP_VERSION(9, 3, 0): 646 mmhub_cid = mmhub_client_ids_vega12[cid][rw]; 647 break; 648 case IP_VERSION(9, 4, 0): 649 mmhub_cid = mmhub_client_ids_vega20[cid][rw]; 650 break; 651 case IP_VERSION(9, 4, 1): 652 mmhub_cid = mmhub_client_ids_arcturus[cid][rw]; 653 break; 654 case IP_VERSION(9, 1, 0): 655 case IP_VERSION(9, 2, 0): 656 mmhub_cid = mmhub_client_ids_raven[cid][rw]; 657 break; 658 case IP_VERSION(1, 5, 0): 659 case IP_VERSION(2, 4, 0): 660 mmhub_cid = mmhub_client_ids_renoir[cid][rw]; 661 break; 662 case IP_VERSION(1, 8, 0): 663 case IP_VERSION(9, 4, 2): 664 mmhub_cid = mmhub_client_ids_aldebaran[cid][rw]; 665 break; 666 default: 667 mmhub_cid = NULL; 668 break; 669 } 670 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 671 mmhub_cid ? mmhub_cid : "unknown", cid); 672 } 673 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 674 REG_GET_FIELD(status, 675 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 676 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 677 REG_GET_FIELD(status, 678 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 679 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 680 REG_GET_FIELD(status, 681 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 682 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 683 REG_GET_FIELD(status, 684 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 685 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 686 return 0; 687 } 688 689 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 690 .set = gmc_v9_0_vm_fault_interrupt_state, 691 .process = gmc_v9_0_process_interrupt, 692 }; 693 694 695 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { 696 .set = gmc_v9_0_ecc_interrupt_state, 697 .process = amdgpu_umc_process_ecc_irq, 698 }; 699 700 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 701 { 702 adev->gmc.vm_fault.num_types = 1; 703 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 704 705 if (!amdgpu_sriov_vf(adev) && 706 !adev->gmc.xgmi.connected_to_cpu) { 707 adev->gmc.ecc_irq.num_types = 1; 708 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; 709 } 710 } 711 712 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, 713 uint32_t flush_type) 714 { 715 u32 req = 0; 716 717 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 718 PER_VMID_INVALIDATE_REQ, 1 << vmid); 719 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 720 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 721 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 722 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 723 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 724 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 725 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 726 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 727 728 return req; 729 } 730 731 /** 732 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore 733 * 734 * @adev: amdgpu_device pointer 735 * @vmhub: vmhub type 736 * 737 */ 738 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev, 739 uint32_t vmhub) 740 { 741 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) || 742 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) 743 return false; 744 745 return ((vmhub == AMDGPU_MMHUB_0 || 746 vmhub == AMDGPU_MMHUB_1) && 747 (!amdgpu_sriov_vf(adev)) && 748 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) && 749 (adev->apu_flags & AMD_APU_IS_PICASSO)))); 750 } 751 752 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, 753 uint8_t vmid, uint16_t *p_pasid) 754 { 755 uint32_t value; 756 757 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 758 + vmid); 759 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 760 761 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 762 } 763 764 /* 765 * GART 766 * VMID 0 is the physical GPU addresses as used by the kernel. 767 * VMIDs 1-15 are used for userspace clients and are handled 768 * by the amdgpu vm/hsa code. 769 */ 770 771 /** 772 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type 773 * 774 * @adev: amdgpu_device pointer 775 * @vmid: vm instance to flush 776 * @vmhub: which hub to flush 777 * @flush_type: the flush type 778 * 779 * Flush the TLB for the requested page table using certain type. 780 */ 781 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 782 uint32_t vmhub, uint32_t flush_type) 783 { 784 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub); 785 const unsigned eng = 17; 786 u32 j, inv_req, inv_req2, tmp; 787 struct amdgpu_vmhub *hub; 788 789 BUG_ON(vmhub >= adev->num_vmhubs); 790 791 hub = &adev->vmhub[vmhub]; 792 if (adev->gmc.xgmi.num_physical_nodes && 793 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0)) { 794 /* Vega20+XGMI caches PTEs in TC and TLB. Add a 795 * heavy-weight TLB flush (type 2), which flushes 796 * both. Due to a race condition with concurrent 797 * memory accesses using the same TLB cache line, we 798 * still need a second TLB flush after this. 799 */ 800 inv_req = gmc_v9_0_get_invalidate_req(vmid, 2); 801 inv_req2 = gmc_v9_0_get_invalidate_req(vmid, flush_type); 802 } else { 803 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type); 804 inv_req2 = 0; 805 } 806 807 /* This is necessary for a HW workaround under SRIOV as well 808 * as GFXOFF under bare metal 809 */ 810 if (adev->gfx.kiq.ring.sched.ready && 811 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && 812 down_read_trylock(&adev->reset_domain->sem)) { 813 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 814 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 815 816 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 817 1 << vmid); 818 up_read(&adev->reset_domain->sem); 819 return; 820 } 821 822 spin_lock(&adev->gmc.invalidate_lock); 823 824 /* 825 * It may lose gpuvm invalidate acknowldege state across power-gating 826 * off cycle, add semaphore acquire before invalidation and semaphore 827 * release after invalidation to avoid entering power gated state 828 * to WA the Issue 829 */ 830 831 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 832 if (use_semaphore) { 833 for (j = 0; j < adev->usec_timeout; j++) { 834 /* a read return value of 1 means semaphore acquire */ 835 if (vmhub == AMDGPU_GFXHUB_0) 836 tmp = RREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_sem + hub->eng_distance * eng); 837 else 838 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_sem + hub->eng_distance * eng); 839 840 if (tmp & 0x1) 841 break; 842 udelay(1); 843 } 844 845 if (j >= adev->usec_timeout) 846 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 847 } 848 849 do { 850 if (vmhub == AMDGPU_GFXHUB_0) 851 WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req); 852 else 853 WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req); 854 855 /* 856 * Issue a dummy read to wait for the ACK register to 857 * be cleared to avoid a false ACK due to the new fast 858 * GRBM interface. 859 */ 860 if ((vmhub == AMDGPU_GFXHUB_0) && 861 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2))) 862 RREG32_NO_KIQ(hub->vm_inv_eng0_req + 863 hub->eng_distance * eng); 864 865 for (j = 0; j < adev->usec_timeout; j++) { 866 if (vmhub == AMDGPU_GFXHUB_0) 867 tmp = RREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_ack + hub->eng_distance * eng); 868 else 869 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_ack + hub->eng_distance * eng); 870 871 if (tmp & (1 << vmid)) 872 break; 873 udelay(1); 874 } 875 876 inv_req = inv_req2; 877 inv_req2 = 0; 878 } while (inv_req); 879 880 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 881 if (use_semaphore) { 882 /* 883 * add semaphore release after invalidation, 884 * write with 0 means semaphore release 885 */ 886 if (vmhub == AMDGPU_GFXHUB_0) 887 WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_sem + hub->eng_distance * eng, 0); 888 else 889 WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_sem + hub->eng_distance * eng, 0); 890 } 891 892 spin_unlock(&adev->gmc.invalidate_lock); 893 894 if (j < adev->usec_timeout) 895 return; 896 897 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 898 } 899 900 /** 901 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid 902 * 903 * @adev: amdgpu_device pointer 904 * @pasid: pasid to be flush 905 * @flush_type: the flush type 906 * @all_hub: flush all hubs 907 * 908 * Flush the TLB for the requested pasid. 909 */ 910 static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 911 uint16_t pasid, uint32_t flush_type, 912 bool all_hub) 913 { 914 int vmid, i; 915 signed long r; 916 uint32_t seq; 917 uint16_t queried_pasid; 918 bool ret; 919 u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT : adev->usec_timeout; 920 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 921 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 922 923 if (amdgpu_in_reset(adev)) 924 return -EIO; 925 926 if (ring->sched.ready && down_read_trylock(&adev->reset_domain->sem)) { 927 /* Vega20+XGMI caches PTEs in TC and TLB. Add a 928 * heavy-weight TLB flush (type 2), which flushes 929 * both. Due to a race condition with concurrent 930 * memory accesses using the same TLB cache line, we 931 * still need a second TLB flush after this. 932 */ 933 bool vega20_xgmi_wa = (adev->gmc.xgmi.num_physical_nodes && 934 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0)); 935 /* 2 dwords flush + 8 dwords fence */ 936 unsigned int ndw = kiq->pmf->invalidate_tlbs_size + 8; 937 938 if (vega20_xgmi_wa) 939 ndw += kiq->pmf->invalidate_tlbs_size; 940 941 spin_lock(&adev->gfx.kiq.ring_lock); 942 /* 2 dwords flush + 8 dwords fence */ 943 amdgpu_ring_alloc(ring, ndw); 944 if (vega20_xgmi_wa) 945 kiq->pmf->kiq_invalidate_tlbs(ring, 946 pasid, 2, all_hub); 947 kiq->pmf->kiq_invalidate_tlbs(ring, 948 pasid, flush_type, all_hub); 949 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 950 if (r) { 951 amdgpu_ring_undo(ring); 952 spin_unlock(&adev->gfx.kiq.ring_lock); 953 up_read(&adev->reset_domain->sem); 954 return -ETIME; 955 } 956 957 amdgpu_ring_commit(ring); 958 spin_unlock(&adev->gfx.kiq.ring_lock); 959 r = amdgpu_fence_wait_polling(ring, seq, usec_timeout); 960 if (r < 1) { 961 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r); 962 up_read(&adev->reset_domain->sem); 963 return -ETIME; 964 } 965 up_read(&adev->reset_domain->sem); 966 return 0; 967 } 968 969 for (vmid = 1; vmid < 16; vmid++) { 970 971 ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 972 &queried_pasid); 973 if (ret && queried_pasid == pasid) { 974 if (all_hub) { 975 for (i = 0; i < adev->num_vmhubs; i++) 976 gmc_v9_0_flush_gpu_tlb(adev, vmid, 977 i, flush_type); 978 } else { 979 gmc_v9_0_flush_gpu_tlb(adev, vmid, 980 AMDGPU_GFXHUB_0, flush_type); 981 } 982 break; 983 } 984 } 985 986 return 0; 987 988 } 989 990 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 991 unsigned vmid, uint64_t pd_addr) 992 { 993 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub); 994 struct amdgpu_device *adev = ring->adev; 995 struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub]; 996 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); 997 unsigned eng = ring->vm_inv_eng; 998 999 /* 1000 * It may lose gpuvm invalidate acknowldege state across power-gating 1001 * off cycle, add semaphore acquire before invalidation and semaphore 1002 * release after invalidation to avoid entering power gated state 1003 * to WA the Issue 1004 */ 1005 1006 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 1007 if (use_semaphore) 1008 /* a read return value of 1 means semaphore acuqire */ 1009 amdgpu_ring_emit_reg_wait(ring, 1010 hub->vm_inv_eng0_sem + 1011 hub->eng_distance * eng, 0x1, 0x1); 1012 1013 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 1014 (hub->ctx_addr_distance * vmid), 1015 lower_32_bits(pd_addr)); 1016 1017 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 1018 (hub->ctx_addr_distance * vmid), 1019 upper_32_bits(pd_addr)); 1020 1021 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 1022 hub->eng_distance * eng, 1023 hub->vm_inv_eng0_ack + 1024 hub->eng_distance * eng, 1025 req, 1 << vmid); 1026 1027 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 1028 if (use_semaphore) 1029 /* 1030 * add semaphore release after invalidation, 1031 * write with 0 means semaphore release 1032 */ 1033 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 1034 hub->eng_distance * eng, 0); 1035 1036 return pd_addr; 1037 } 1038 1039 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 1040 unsigned pasid) 1041 { 1042 struct amdgpu_device *adev = ring->adev; 1043 uint32_t reg; 1044 1045 /* Do nothing because there's no lut register for mmhub1. */ 1046 if (ring->funcs->vmhub == AMDGPU_MMHUB_1) 1047 return; 1048 1049 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) 1050 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 1051 else 1052 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 1053 1054 amdgpu_ring_emit_wreg(ring, reg, pasid); 1055 } 1056 1057 /* 1058 * PTE format on VEGA 10: 1059 * 63:59 reserved 1060 * 58:57 mtype 1061 * 56 F 1062 * 55 L 1063 * 54 P 1064 * 53 SW 1065 * 52 T 1066 * 50:48 reserved 1067 * 47:12 4k physical page base address 1068 * 11:7 fragment 1069 * 6 write 1070 * 5 read 1071 * 4 exe 1072 * 3 Z 1073 * 2 snooped 1074 * 1 system 1075 * 0 valid 1076 * 1077 * PDE format on VEGA 10: 1078 * 63:59 block fragment size 1079 * 58:55 reserved 1080 * 54 P 1081 * 53:48 reserved 1082 * 47:6 physical base address of PD or PTE 1083 * 5:3 reserved 1084 * 2 C 1085 * 1 system 1086 * 0 valid 1087 */ 1088 1089 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 1090 1091 { 1092 switch (flags) { 1093 case AMDGPU_VM_MTYPE_DEFAULT: 1094 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1095 case AMDGPU_VM_MTYPE_NC: 1096 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1097 case AMDGPU_VM_MTYPE_WC: 1098 return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC); 1099 case AMDGPU_VM_MTYPE_RW: 1100 return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW); 1101 case AMDGPU_VM_MTYPE_CC: 1102 return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC); 1103 case AMDGPU_VM_MTYPE_UC: 1104 return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC); 1105 default: 1106 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1107 } 1108 } 1109 1110 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, 1111 uint64_t *addr, uint64_t *flags) 1112 { 1113 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 1114 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 1115 BUG_ON(*addr & 0xFFFF00000000003FULL); 1116 1117 if (!adev->gmc.translate_further) 1118 return; 1119 1120 if (level == AMDGPU_VM_PDB1) { 1121 /* Set the block fragment size */ 1122 if (!(*flags & AMDGPU_PDE_PTE)) 1123 *flags |= AMDGPU_PDE_BFS(0x9); 1124 1125 } else if (level == AMDGPU_VM_PDB0) { 1126 if (*flags & AMDGPU_PDE_PTE) { 1127 *flags &= ~AMDGPU_PDE_PTE; 1128 if (!(*flags & AMDGPU_PTE_VALID)) 1129 *addr |= 1 << PAGE_SHIFT; 1130 } else { 1131 *flags |= AMDGPU_PTE_TF; 1132 } 1133 } 1134 } 1135 1136 static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev, 1137 struct amdgpu_bo *bo, 1138 struct amdgpu_bo_va_mapping *mapping, 1139 uint64_t *flags) 1140 { 1141 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev); 1142 bool is_vram = bo->tbo.resource->mem_type == TTM_PL_VRAM; 1143 bool coherent = bo->flags & AMDGPU_GEM_CREATE_COHERENT; 1144 bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED; 1145 unsigned int mtype; 1146 bool snoop = false; 1147 1148 switch (adev->ip_versions[GC_HWIP][0]) { 1149 case IP_VERSION(9, 4, 1): 1150 case IP_VERSION(9, 4, 2): 1151 case IP_VERSION(9, 4, 3): 1152 if (is_vram) { 1153 if (bo_adev == adev) { 1154 if (uncached) 1155 mtype = MTYPE_UC; 1156 else if (coherent) 1157 mtype = MTYPE_CC; 1158 else 1159 mtype = MTYPE_RW; 1160 /* FIXME: is this still needed? Or does 1161 * amdgpu_ttm_tt_pde_flags already handle this? 1162 */ 1163 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) || 1164 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) && 1165 adev->gmc.xgmi.connected_to_cpu) 1166 snoop = true; 1167 } else { 1168 if (uncached || coherent) 1169 mtype = MTYPE_UC; 1170 else 1171 mtype = MTYPE_NC; 1172 if (mapping->bo_va->is_xgmi) 1173 snoop = true; 1174 } 1175 } else { 1176 if (uncached || coherent) 1177 mtype = MTYPE_UC; 1178 else 1179 mtype = MTYPE_NC; 1180 /* FIXME: is this still needed? Or does 1181 * amdgpu_ttm_tt_pde_flags already handle this? 1182 */ 1183 snoop = true; 1184 } 1185 break; 1186 default: 1187 if (uncached || coherent) 1188 mtype = MTYPE_UC; 1189 else 1190 mtype = MTYPE_NC; 1191 1192 /* FIXME: is this still needed? Or does 1193 * amdgpu_ttm_tt_pde_flags already handle this? 1194 */ 1195 if (!is_vram) 1196 snoop = true; 1197 } 1198 1199 if (mtype != MTYPE_NC) 1200 *flags = (*flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) | 1201 AMDGPU_PTE_MTYPE_VG10(mtype); 1202 *flags |= snoop ? AMDGPU_PTE_SNOOPED : 0; 1203 } 1204 1205 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev, 1206 struct amdgpu_bo_va_mapping *mapping, 1207 uint64_t *flags) 1208 { 1209 struct amdgpu_bo *bo = mapping->bo_va->base.bo; 1210 1211 *flags &= ~AMDGPU_PTE_EXECUTABLE; 1212 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 1213 1214 *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 1215 *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK; 1216 1217 if (mapping->flags & AMDGPU_PTE_PRT) { 1218 *flags |= AMDGPU_PTE_PRT; 1219 *flags &= ~AMDGPU_PTE_VALID; 1220 } 1221 1222 if (bo && bo->tbo.resource) 1223 gmc_v9_0_get_coherence_flags(adev, mapping->bo_va->base.bo, 1224 mapping, flags); 1225 } 1226 1227 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 1228 { 1229 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 1230 unsigned size; 1231 1232 /* TODO move to DC so GMC doesn't need to hard-code DCN registers */ 1233 1234 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1235 size = AMDGPU_VBIOS_VGA_ALLOCATION; 1236 } else { 1237 u32 viewport; 1238 1239 switch (adev->ip_versions[DCE_HWIP][0]) { 1240 case IP_VERSION(1, 0, 0): 1241 case IP_VERSION(1, 0, 1): 1242 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 1243 size = (REG_GET_FIELD(viewport, 1244 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1245 REG_GET_FIELD(viewport, 1246 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1247 4); 1248 break; 1249 case IP_VERSION(2, 1, 0): 1250 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2); 1251 size = (REG_GET_FIELD(viewport, 1252 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1253 REG_GET_FIELD(viewport, 1254 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1255 4); 1256 break; 1257 default: 1258 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); 1259 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1260 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1261 4); 1262 break; 1263 } 1264 } 1265 1266 return size; 1267 } 1268 1269 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { 1270 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, 1271 .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid, 1272 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, 1273 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, 1274 .map_mtype = gmc_v9_0_map_mtype, 1275 .get_vm_pde = gmc_v9_0_get_vm_pde, 1276 .get_vm_pte = gmc_v9_0_get_vm_pte, 1277 .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size, 1278 }; 1279 1280 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) 1281 { 1282 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; 1283 } 1284 1285 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) 1286 { 1287 switch (adev->ip_versions[UMC_HWIP][0]) { 1288 case IP_VERSION(6, 0, 0): 1289 adev->umc.funcs = &umc_v6_0_funcs; 1290 break; 1291 case IP_VERSION(6, 1, 1): 1292 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1293 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1294 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1295 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20; 1296 adev->umc.retire_unit = 1; 1297 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1298 adev->umc.ras = &umc_v6_1_ras; 1299 break; 1300 case IP_VERSION(6, 1, 2): 1301 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1302 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1303 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1304 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT; 1305 adev->umc.retire_unit = 1; 1306 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1307 adev->umc.ras = &umc_v6_1_ras; 1308 break; 1309 case IP_VERSION(6, 7, 0): 1310 adev->umc.max_ras_err_cnt_per_query = 1311 UMC_V6_7_TOTAL_CHANNEL_NUM * UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL; 1312 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM; 1313 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM; 1314 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET; 1315 adev->umc.retire_unit = (UMC_V6_7_NA_MAP_PA_NUM * 2); 1316 if (!adev->gmc.xgmi.connected_to_cpu) 1317 adev->umc.ras = &umc_v6_7_ras; 1318 if (1 & adev->smuio.funcs->get_die_id(adev)) 1319 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0]; 1320 else 1321 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0]; 1322 break; 1323 default: 1324 break; 1325 } 1326 } 1327 1328 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) 1329 { 1330 switch (adev->ip_versions[MMHUB_HWIP][0]) { 1331 case IP_VERSION(9, 4, 1): 1332 adev->mmhub.funcs = &mmhub_v9_4_funcs; 1333 break; 1334 case IP_VERSION(9, 4, 2): 1335 adev->mmhub.funcs = &mmhub_v1_7_funcs; 1336 break; 1337 case IP_VERSION(1, 8, 0): 1338 adev->mmhub.funcs = &mmhub_v1_8_funcs; 1339 break; 1340 default: 1341 adev->mmhub.funcs = &mmhub_v1_0_funcs; 1342 break; 1343 } 1344 } 1345 1346 static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev) 1347 { 1348 switch (adev->ip_versions[MMHUB_HWIP][0]) { 1349 case IP_VERSION(9, 4, 0): 1350 adev->mmhub.ras = &mmhub_v1_0_ras; 1351 break; 1352 case IP_VERSION(9, 4, 1): 1353 adev->mmhub.ras = &mmhub_v9_4_ras; 1354 break; 1355 case IP_VERSION(9, 4, 2): 1356 adev->mmhub.ras = &mmhub_v1_7_ras; 1357 break; 1358 default: 1359 /* mmhub ras is not available */ 1360 break; 1361 } 1362 } 1363 1364 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev) 1365 { 1366 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) 1367 adev->gfxhub.funcs = &gfxhub_v1_2_funcs; 1368 else 1369 adev->gfxhub.funcs = &gfxhub_v1_0_funcs; 1370 } 1371 1372 static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev) 1373 { 1374 adev->hdp.ras = &hdp_v4_0_ras; 1375 } 1376 1377 static void gmc_v9_0_set_mca_ras_funcs(struct amdgpu_device *adev) 1378 { 1379 struct amdgpu_mca *mca = &adev->mca; 1380 1381 /* is UMC the right IP to check for MCA? Maybe DF? */ 1382 switch (adev->ip_versions[UMC_HWIP][0]) { 1383 case IP_VERSION(6, 7, 0): 1384 if (!adev->gmc.xgmi.connected_to_cpu) { 1385 mca->mp0.ras = &mca_v3_0_mp0_ras; 1386 mca->mp1.ras = &mca_v3_0_mp1_ras; 1387 mca->mpio.ras = &mca_v3_0_mpio_ras; 1388 } 1389 break; 1390 default: 1391 break; 1392 } 1393 } 1394 1395 static void gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device *adev) 1396 { 1397 if (!adev->gmc.xgmi.connected_to_cpu) 1398 adev->gmc.xgmi.ras = &xgmi_ras; 1399 } 1400 1401 static int gmc_v9_0_early_init(void *handle) 1402 { 1403 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1404 1405 /* ARCT and VEGA20 don't have XGMI defined in their IP discovery tables */ 1406 if (adev->asic_type == CHIP_VEGA20 || 1407 adev->asic_type == CHIP_ARCTURUS) 1408 adev->gmc.xgmi.supported = true; 1409 1410 if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(6, 1, 0)) { 1411 adev->gmc.xgmi.supported = true; 1412 adev->gmc.xgmi.connected_to_cpu = 1413 adev->smuio.funcs->is_host_gpu_xgmi_supported(adev); 1414 } 1415 1416 gmc_v9_0_set_gmc_funcs(adev); 1417 gmc_v9_0_set_irq_funcs(adev); 1418 gmc_v9_0_set_umc_funcs(adev); 1419 gmc_v9_0_set_mmhub_funcs(adev); 1420 gmc_v9_0_set_mmhub_ras_funcs(adev); 1421 gmc_v9_0_set_gfxhub_funcs(adev); 1422 gmc_v9_0_set_hdp_ras_funcs(adev); 1423 gmc_v9_0_set_mca_ras_funcs(adev); 1424 gmc_v9_0_set_xgmi_ras_funcs(adev); 1425 1426 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1427 adev->gmc.shared_aperture_end = 1428 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1429 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 1430 adev->gmc.private_aperture_end = 1431 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1432 1433 return 0; 1434 } 1435 1436 static int gmc_v9_0_late_init(void *handle) 1437 { 1438 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1439 int r; 1440 1441 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 1442 if (r) 1443 return r; 1444 1445 /* 1446 * Workaround performance drop issue with VBIOS enables partial 1447 * writes, while disables HBM ECC for vega10. 1448 */ 1449 if (!amdgpu_sriov_vf(adev) && 1450 (adev->ip_versions[UMC_HWIP][0] == IP_VERSION(6, 0, 0))) { 1451 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) { 1452 if (adev->df.funcs && 1453 adev->df.funcs->enable_ecc_force_par_wr_rmw) 1454 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false); 1455 } 1456 } 1457 1458 if (!amdgpu_persistent_edc_harvesting_supported(adev)) { 1459 if (adev->mmhub.ras && adev->mmhub.ras->ras_block.hw_ops && 1460 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count) 1461 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(adev); 1462 1463 if (adev->hdp.ras && adev->hdp.ras->ras_block.hw_ops && 1464 adev->hdp.ras->ras_block.hw_ops->reset_ras_error_count) 1465 adev->hdp.ras->ras_block.hw_ops->reset_ras_error_count(adev); 1466 } 1467 1468 r = amdgpu_gmc_ras_late_init(adev); 1469 if (r) 1470 return r; 1471 1472 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1473 } 1474 1475 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 1476 struct amdgpu_gmc *mc) 1477 { 1478 u64 base = adev->mmhub.funcs->get_fb_location(adev); 1479 1480 /* add the xgmi offset of the physical node */ 1481 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1482 if (adev->gmc.xgmi.connected_to_cpu) { 1483 amdgpu_gmc_sysvm_location(adev, mc); 1484 } else { 1485 amdgpu_gmc_vram_location(adev, mc, base); 1486 amdgpu_gmc_gart_location(adev, mc); 1487 amdgpu_gmc_agp_location(adev, mc); 1488 } 1489 /* base offset of vram pages */ 1490 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 1491 1492 /* XXX: add the xgmi offset of the physical node? */ 1493 adev->vm_manager.vram_base_offset += 1494 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1495 } 1496 1497 /** 1498 * gmc_v9_0_mc_init - initialize the memory controller driver params 1499 * 1500 * @adev: amdgpu_device pointer 1501 * 1502 * Look up the amount of vram, vram width, and decide how to place 1503 * vram and gart within the GPU's physical address space. 1504 * Returns 0 for success. 1505 */ 1506 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 1507 { 1508 int r; 1509 1510 /* size in MB on si */ 1511 adev->gmc.mc_vram_size = 1512 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 1513 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 1514 1515 if (!(adev->flags & AMD_IS_APU) && 1516 !adev->gmc.xgmi.connected_to_cpu) { 1517 r = amdgpu_device_resize_fb_bar(adev); 1518 if (r) 1519 return r; 1520 } 1521 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 1522 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 1523 1524 #ifdef CONFIG_X86_64 1525 /* 1526 * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi 1527 * interface can use VRAM through here as it appears system reserved 1528 * memory in host address space. 1529 * 1530 * For APUs, VRAM is just the stolen system memory and can be accessed 1531 * directly. 1532 * 1533 * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR. 1534 */ 1535 1536 /* check whether both host-gpu and gpu-gpu xgmi links exist */ 1537 if (((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) || 1538 (adev->gmc.xgmi.supported && 1539 adev->gmc.xgmi.connected_to_cpu)) { 1540 adev->gmc.aper_base = 1541 adev->gfxhub.funcs->get_mc_fb_offset(adev) + 1542 adev->gmc.xgmi.physical_node_id * 1543 adev->gmc.xgmi.node_segment_size; 1544 adev->gmc.aper_size = adev->gmc.real_vram_size; 1545 } 1546 1547 #endif 1548 adev->gmc.visible_vram_size = adev->gmc.aper_size; 1549 1550 /* set the gart size */ 1551 if (amdgpu_gart_size == -1) { 1552 switch (adev->ip_versions[GC_HWIP][0]) { 1553 case IP_VERSION(9, 0, 1): /* all engines support GPUVM */ 1554 case IP_VERSION(9, 2, 1): /* all engines support GPUVM */ 1555 case IP_VERSION(9, 4, 0): 1556 case IP_VERSION(9, 4, 1): 1557 case IP_VERSION(9, 4, 2): 1558 case IP_VERSION(9, 4, 3): 1559 default: 1560 adev->gmc.gart_size = 512ULL << 20; 1561 break; 1562 case IP_VERSION(9, 1, 0): /* DCE SG support */ 1563 case IP_VERSION(9, 2, 2): /* DCE SG support */ 1564 case IP_VERSION(9, 3, 0): 1565 adev->gmc.gart_size = 1024ULL << 20; 1566 break; 1567 } 1568 } else { 1569 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 1570 } 1571 1572 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; 1573 1574 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); 1575 1576 return 0; 1577 } 1578 1579 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 1580 { 1581 int r; 1582 1583 if (adev->gart.bo) { 1584 WARN(1, "VEGA10 PCIE GART already initialized\n"); 1585 return 0; 1586 } 1587 1588 if (adev->gmc.xgmi.connected_to_cpu) { 1589 adev->gmc.vmid0_page_table_depth = 1; 1590 adev->gmc.vmid0_page_table_block_size = 12; 1591 } else { 1592 adev->gmc.vmid0_page_table_depth = 0; 1593 adev->gmc.vmid0_page_table_block_size = 0; 1594 } 1595 1596 /* Initialize common gart structure */ 1597 r = amdgpu_gart_init(adev); 1598 if (r) 1599 return r; 1600 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 1601 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) | 1602 AMDGPU_PTE_EXECUTABLE; 1603 1604 r = amdgpu_gart_table_vram_alloc(adev); 1605 if (r) 1606 return r; 1607 1608 if (adev->gmc.xgmi.connected_to_cpu) { 1609 r = amdgpu_gmc_pdb0_alloc(adev); 1610 } 1611 1612 return r; 1613 } 1614 1615 /** 1616 * gmc_v9_0_save_registers - saves regs 1617 * 1618 * @adev: amdgpu_device pointer 1619 * 1620 * This saves potential register values that should be 1621 * restored upon resume 1622 */ 1623 static void gmc_v9_0_save_registers(struct amdgpu_device *adev) 1624 { 1625 if ((adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 0)) || 1626 (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 1))) 1627 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); 1628 } 1629 1630 static int gmc_v9_0_sw_init(void *handle) 1631 { 1632 int r, vram_width = 0, vram_type = 0, vram_vendor = 0, dma_addr_bits; 1633 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1634 1635 adev->gfxhub.funcs->init(adev); 1636 1637 adev->mmhub.funcs->init(adev); 1638 1639 spin_lock_init(&adev->gmc.invalidate_lock); 1640 1641 r = amdgpu_atomfirmware_get_vram_info(adev, 1642 &vram_width, &vram_type, &vram_vendor); 1643 if (amdgpu_sriov_vf(adev)) 1644 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, 1645 * and DF related registers is not readable, seems hardcord is the 1646 * only way to set the correct vram_width 1647 */ 1648 adev->gmc.vram_width = 2048; 1649 else if (amdgpu_emu_mode != 1) 1650 adev->gmc.vram_width = vram_width; 1651 1652 if (!adev->gmc.vram_width) { 1653 int chansize, numchan; 1654 1655 /* hbm memory channel size */ 1656 if (adev->flags & AMD_IS_APU) 1657 chansize = 64; 1658 else 1659 chansize = 128; 1660 if (adev->df.funcs && 1661 adev->df.funcs->get_hbm_channel_number) { 1662 numchan = adev->df.funcs->get_hbm_channel_number(adev); 1663 adev->gmc.vram_width = numchan * chansize; 1664 } 1665 } 1666 1667 adev->gmc.vram_type = vram_type; 1668 adev->gmc.vram_vendor = vram_vendor; 1669 switch (adev->ip_versions[GC_HWIP][0]) { 1670 case IP_VERSION(9, 1, 0): 1671 case IP_VERSION(9, 2, 2): 1672 adev->num_vmhubs = 2; 1673 1674 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 1675 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1676 } else { 1677 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 1678 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 1679 adev->gmc.translate_further = 1680 adev->vm_manager.num_level > 1; 1681 } 1682 break; 1683 case IP_VERSION(9, 0, 1): 1684 case IP_VERSION(9, 2, 1): 1685 case IP_VERSION(9, 4, 0): 1686 case IP_VERSION(9, 3, 0): 1687 case IP_VERSION(9, 4, 2): 1688 case IP_VERSION(9, 4, 3): 1689 adev->num_vmhubs = 2; 1690 1691 1692 /* 1693 * To fulfill 4-level page support, 1694 * vm size is 256TB (48bit), maximum size of Vega10, 1695 * block size 512 (9bit) 1696 */ 1697 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */ 1698 if (amdgpu_sriov_vf(adev)) 1699 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47); 1700 else 1701 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1702 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) 1703 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 1704 break; 1705 case IP_VERSION(9, 4, 1): 1706 adev->num_vmhubs = 3; 1707 1708 /* Keep the vm size same with Vega20 */ 1709 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1710 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 1711 break; 1712 default: 1713 break; 1714 } 1715 1716 /* This interrupt is VMC page fault.*/ 1717 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, 1718 &adev->gmc.vm_fault); 1719 if (r) 1720 return r; 1721 1722 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)) { 1723 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT, 1724 &adev->gmc.vm_fault); 1725 if (r) 1726 return r; 1727 } 1728 1729 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, 1730 &adev->gmc.vm_fault); 1731 1732 if (r) 1733 return r; 1734 1735 if (!amdgpu_sriov_vf(adev) && 1736 !adev->gmc.xgmi.connected_to_cpu) { 1737 /* interrupt sent to DF. */ 1738 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 1739 &adev->gmc.ecc_irq); 1740 if (r) 1741 return r; 1742 } 1743 1744 /* Set the internal MC address mask 1745 * This is the max address of the GPU's 1746 * internal address space. 1747 */ 1748 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 1749 1750 dma_addr_bits = adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) ? 48:44; 1751 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(dma_addr_bits)); 1752 if (r) { 1753 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 1754 return r; 1755 } 1756 adev->need_swiotlb = drm_need_swiotlb(dma_addr_bits); 1757 1758 r = gmc_v9_0_mc_init(adev); 1759 if (r) 1760 return r; 1761 1762 amdgpu_gmc_get_vbios_allocations(adev); 1763 1764 /* Memory manager */ 1765 r = amdgpu_bo_init(adev); 1766 if (r) 1767 return r; 1768 1769 r = gmc_v9_0_gart_init(adev); 1770 if (r) 1771 return r; 1772 1773 /* 1774 * number of VMs 1775 * VMID 0 is reserved for System 1776 * amdgpu graphics/compute will use VMIDs 1..n-1 1777 * amdkfd will use VMIDs n..15 1778 * 1779 * The first KFD VMID is 8 for GPUs with graphics, 3 for 1780 * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs 1781 * for video processing. 1782 */ 1783 adev->vm_manager.first_kfd_vmid = 1784 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) || 1785 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) || 1786 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) ? 3 : 8; 1787 1788 amdgpu_vm_manager_init(adev); 1789 1790 gmc_v9_0_save_registers(adev); 1791 1792 r = amdgpu_gmc_ras_sw_init(adev); 1793 if (r) 1794 return r; 1795 1796 return 0; 1797 } 1798 1799 static int gmc_v9_0_sw_fini(void *handle) 1800 { 1801 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1802 1803 amdgpu_gmc_ras_fini(adev); 1804 amdgpu_gem_force_release(adev); 1805 amdgpu_vm_manager_fini(adev); 1806 amdgpu_gart_table_vram_free(adev); 1807 amdgpu_bo_free_kernel(&adev->gmc.pdb0_bo, NULL, &adev->gmc.ptr_pdb0); 1808 amdgpu_bo_fini(adev); 1809 1810 return 0; 1811 } 1812 1813 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 1814 { 1815 1816 switch (adev->ip_versions[MMHUB_HWIP][0]) { 1817 case IP_VERSION(9, 0, 0): 1818 if (amdgpu_sriov_vf(adev)) 1819 break; 1820 fallthrough; 1821 case IP_VERSION(9, 4, 0): 1822 soc15_program_register_sequence(adev, 1823 golden_settings_mmhub_1_0_0, 1824 ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 1825 soc15_program_register_sequence(adev, 1826 golden_settings_athub_1_0_0, 1827 ARRAY_SIZE(golden_settings_athub_1_0_0)); 1828 break; 1829 case IP_VERSION(9, 1, 0): 1830 case IP_VERSION(9, 2, 0): 1831 /* TODO for renoir */ 1832 soc15_program_register_sequence(adev, 1833 golden_settings_athub_1_0_0, 1834 ARRAY_SIZE(golden_settings_athub_1_0_0)); 1835 break; 1836 default: 1837 break; 1838 } 1839 } 1840 1841 /** 1842 * gmc_v9_0_restore_registers - restores regs 1843 * 1844 * @adev: amdgpu_device pointer 1845 * 1846 * This restores register values, saved at suspend. 1847 */ 1848 void gmc_v9_0_restore_registers(struct amdgpu_device *adev) 1849 { 1850 if ((adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 0)) || 1851 (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 1))) { 1852 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register); 1853 WARN_ON(adev->gmc.sdpif_register != 1854 RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0)); 1855 } 1856 } 1857 1858 /** 1859 * gmc_v9_0_gart_enable - gart enable 1860 * 1861 * @adev: amdgpu_device pointer 1862 */ 1863 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 1864 { 1865 int r; 1866 1867 if (adev->gmc.xgmi.connected_to_cpu) 1868 amdgpu_gmc_init_pdb0(adev); 1869 1870 if (adev->gart.bo == NULL) { 1871 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 1872 return -EINVAL; 1873 } 1874 1875 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 1876 1877 if (!adev->in_s0ix) { 1878 r = adev->gfxhub.funcs->gart_enable(adev); 1879 if (r) 1880 return r; 1881 } 1882 1883 r = adev->mmhub.funcs->gart_enable(adev); 1884 if (r) 1885 return r; 1886 1887 DRM_INFO("PCIE GART of %uM enabled.\n", 1888 (unsigned)(adev->gmc.gart_size >> 20)); 1889 if (adev->gmc.pdb0_bo) 1890 DRM_INFO("PDB0 located at 0x%016llX\n", 1891 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo)); 1892 DRM_INFO("PTB located at 0x%016llX\n", 1893 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 1894 1895 return 0; 1896 } 1897 1898 static int gmc_v9_0_hw_init(void *handle) 1899 { 1900 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1901 bool value; 1902 int i, r; 1903 1904 /* The sequence of these two function calls matters.*/ 1905 gmc_v9_0_init_golden_registers(adev); 1906 1907 if (adev->mode_info.num_crtc) { 1908 /* Lockout access through VGA aperture*/ 1909 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 1910 /* disable VGA render */ 1911 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 1912 } 1913 1914 if (adev->mmhub.funcs->update_power_gating) 1915 adev->mmhub.funcs->update_power_gating(adev, true); 1916 1917 adev->hdp.funcs->init_registers(adev); 1918 1919 /* After HDP is initialized, flush HDP.*/ 1920 adev->hdp.funcs->flush_hdp(adev, NULL); 1921 1922 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 1923 value = false; 1924 else 1925 value = true; 1926 1927 if (!amdgpu_sriov_vf(adev)) { 1928 if (!adev->in_s0ix) 1929 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 1930 adev->mmhub.funcs->set_fault_enable_default(adev, value); 1931 } 1932 for (i = 0; i < adev->num_vmhubs; ++i) { 1933 if (adev->in_s0ix && (i == AMDGPU_GFXHUB_0)) 1934 continue; 1935 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0); 1936 } 1937 1938 if (adev->umc.funcs && adev->umc.funcs->init_registers) 1939 adev->umc.funcs->init_registers(adev); 1940 1941 r = gmc_v9_0_gart_enable(adev); 1942 if (r) 1943 return r; 1944 1945 if (amdgpu_emu_mode == 1) 1946 return amdgpu_gmc_vram_checking(adev); 1947 else 1948 return r; 1949 } 1950 1951 /** 1952 * gmc_v9_0_gart_disable - gart disable 1953 * 1954 * @adev: amdgpu_device pointer 1955 * 1956 * This disables all VM page table. 1957 */ 1958 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 1959 { 1960 if (!adev->in_s0ix) 1961 adev->gfxhub.funcs->gart_disable(adev); 1962 adev->mmhub.funcs->gart_disable(adev); 1963 } 1964 1965 static int gmc_v9_0_hw_fini(void *handle) 1966 { 1967 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1968 1969 gmc_v9_0_gart_disable(adev); 1970 1971 if (amdgpu_sriov_vf(adev)) { 1972 /* full access mode, so don't touch any GMC register */ 1973 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 1974 return 0; 1975 } 1976 1977 /* 1978 * Pair the operations did in gmc_v9_0_hw_init and thus maintain 1979 * a correct cached state for GMC. Otherwise, the "gate" again 1980 * operation on S3 resuming will fail due to wrong cached state. 1981 */ 1982 if (adev->mmhub.funcs->update_power_gating) 1983 adev->mmhub.funcs->update_power_gating(adev, false); 1984 1985 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 1986 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1987 1988 return 0; 1989 } 1990 1991 static int gmc_v9_0_suspend(void *handle) 1992 { 1993 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1994 1995 return gmc_v9_0_hw_fini(adev); 1996 } 1997 1998 static int gmc_v9_0_resume(void *handle) 1999 { 2000 int r; 2001 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2002 2003 r = gmc_v9_0_hw_init(adev); 2004 if (r) 2005 return r; 2006 2007 amdgpu_vmid_reset_all(adev); 2008 2009 return 0; 2010 } 2011 2012 static bool gmc_v9_0_is_idle(void *handle) 2013 { 2014 /* MC is always ready in GMC v9.*/ 2015 return true; 2016 } 2017 2018 static int gmc_v9_0_wait_for_idle(void *handle) 2019 { 2020 /* There is no need to wait for MC idle in GMC v9.*/ 2021 return 0; 2022 } 2023 2024 static int gmc_v9_0_soft_reset(void *handle) 2025 { 2026 /* XXX for emulation.*/ 2027 return 0; 2028 } 2029 2030 static int gmc_v9_0_set_clockgating_state(void *handle, 2031 enum amd_clockgating_state state) 2032 { 2033 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2034 2035 adev->mmhub.funcs->set_clockgating(adev, state); 2036 2037 athub_v1_0_set_clockgating(adev, state); 2038 2039 return 0; 2040 } 2041 2042 static void gmc_v9_0_get_clockgating_state(void *handle, u64 *flags) 2043 { 2044 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2045 2046 adev->mmhub.funcs->get_clockgating(adev, flags); 2047 2048 athub_v1_0_get_clockgating(adev, flags); 2049 } 2050 2051 static int gmc_v9_0_set_powergating_state(void *handle, 2052 enum amd_powergating_state state) 2053 { 2054 return 0; 2055 } 2056 2057 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 2058 .name = "gmc_v9_0", 2059 .early_init = gmc_v9_0_early_init, 2060 .late_init = gmc_v9_0_late_init, 2061 .sw_init = gmc_v9_0_sw_init, 2062 .sw_fini = gmc_v9_0_sw_fini, 2063 .hw_init = gmc_v9_0_hw_init, 2064 .hw_fini = gmc_v9_0_hw_fini, 2065 .suspend = gmc_v9_0_suspend, 2066 .resume = gmc_v9_0_resume, 2067 .is_idle = gmc_v9_0_is_idle, 2068 .wait_for_idle = gmc_v9_0_wait_for_idle, 2069 .soft_reset = gmc_v9_0_soft_reset, 2070 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 2071 .set_powergating_state = gmc_v9_0_set_powergating_state, 2072 .get_clockgating_state = gmc_v9_0_get_clockgating_state, 2073 }; 2074 2075 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = 2076 { 2077 .type = AMD_IP_BLOCK_TYPE_GMC, 2078 .major = 9, 2079 .minor = 0, 2080 .rev = 0, 2081 .funcs = &gmc_v9_0_ip_funcs, 2082 }; 2083