1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <drm/drm_cache.h> 25 #include "amdgpu.h" 26 #include "gmc_v9_0.h" 27 #include "amdgpu_atomfirmware.h" 28 #include "amdgpu_gem.h" 29 30 #include "hdp/hdp_4_0_offset.h" 31 #include "hdp/hdp_4_0_sh_mask.h" 32 #include "gc/gc_9_0_sh_mask.h" 33 #include "dce/dce_12_0_offset.h" 34 #include "dce/dce_12_0_sh_mask.h" 35 #include "vega10_enum.h" 36 #include "mmhub/mmhub_1_0_offset.h" 37 #include "athub/athub_1_0_offset.h" 38 #include "oss/osssys_4_0_offset.h" 39 40 #include "soc15.h" 41 #include "soc15_common.h" 42 #include "umc/umc_6_0_sh_mask.h" 43 44 #include "gfxhub_v1_0.h" 45 #include "mmhub_v1_0.h" 46 #include "gfxhub_v1_1.h" 47 48 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 49 50 #include "amdgpu_ras.h" 51 52 /* add these here since we already include dce12 headers and these are for DCN */ 53 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 54 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 55 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 56 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 57 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL 58 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L 59 60 /* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/ 61 #define AMDGPU_NUM_OF_VMIDS 8 62 63 static const u32 golden_settings_vega10_hdp[] = 64 { 65 0xf64, 0x0fffffff, 0x00000000, 66 0xf65, 0x0fffffff, 0x00000000, 67 0xf66, 0x0fffffff, 0x00000000, 68 0xf67, 0x0fffffff, 0x00000000, 69 0xf68, 0x0fffffff, 0x00000000, 70 0xf6a, 0x0fffffff, 0x00000000, 71 0xf6b, 0x0fffffff, 0x00000000, 72 0xf6c, 0x0fffffff, 0x00000000, 73 0xf6d, 0x0fffffff, 0x00000000, 74 0xf6e, 0x0fffffff, 0x00000000, 75 }; 76 77 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = 78 { 79 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), 80 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) 81 }; 82 83 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = 84 { 85 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), 86 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) 87 }; 88 89 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { 90 (0x000143c0 + 0x00000000), 91 (0x000143c0 + 0x00000800), 92 (0x000143c0 + 0x00001000), 93 (0x000143c0 + 0x00001800), 94 (0x000543c0 + 0x00000000), 95 (0x000543c0 + 0x00000800), 96 (0x000543c0 + 0x00001000), 97 (0x000543c0 + 0x00001800), 98 (0x000943c0 + 0x00000000), 99 (0x000943c0 + 0x00000800), 100 (0x000943c0 + 0x00001000), 101 (0x000943c0 + 0x00001800), 102 (0x000d43c0 + 0x00000000), 103 (0x000d43c0 + 0x00000800), 104 (0x000d43c0 + 0x00001000), 105 (0x000d43c0 + 0x00001800), 106 (0x001143c0 + 0x00000000), 107 (0x001143c0 + 0x00000800), 108 (0x001143c0 + 0x00001000), 109 (0x001143c0 + 0x00001800), 110 (0x001543c0 + 0x00000000), 111 (0x001543c0 + 0x00000800), 112 (0x001543c0 + 0x00001000), 113 (0x001543c0 + 0x00001800), 114 (0x001943c0 + 0x00000000), 115 (0x001943c0 + 0x00000800), 116 (0x001943c0 + 0x00001000), 117 (0x001943c0 + 0x00001800), 118 (0x001d43c0 + 0x00000000), 119 (0x001d43c0 + 0x00000800), 120 (0x001d43c0 + 0x00001000), 121 (0x001d43c0 + 0x00001800), 122 }; 123 124 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { 125 (0x000143e0 + 0x00000000), 126 (0x000143e0 + 0x00000800), 127 (0x000143e0 + 0x00001000), 128 (0x000143e0 + 0x00001800), 129 (0x000543e0 + 0x00000000), 130 (0x000543e0 + 0x00000800), 131 (0x000543e0 + 0x00001000), 132 (0x000543e0 + 0x00001800), 133 (0x000943e0 + 0x00000000), 134 (0x000943e0 + 0x00000800), 135 (0x000943e0 + 0x00001000), 136 (0x000943e0 + 0x00001800), 137 (0x000d43e0 + 0x00000000), 138 (0x000d43e0 + 0x00000800), 139 (0x000d43e0 + 0x00001000), 140 (0x000d43e0 + 0x00001800), 141 (0x001143e0 + 0x00000000), 142 (0x001143e0 + 0x00000800), 143 (0x001143e0 + 0x00001000), 144 (0x001143e0 + 0x00001800), 145 (0x001543e0 + 0x00000000), 146 (0x001543e0 + 0x00000800), 147 (0x001543e0 + 0x00001000), 148 (0x001543e0 + 0x00001800), 149 (0x001943e0 + 0x00000000), 150 (0x001943e0 + 0x00000800), 151 (0x001943e0 + 0x00001000), 152 (0x001943e0 + 0x00001800), 153 (0x001d43e0 + 0x00000000), 154 (0x001d43e0 + 0x00000800), 155 (0x001d43e0 + 0x00001000), 156 (0x001d43e0 + 0x00001800), 157 }; 158 159 static const uint32_t ecc_umc_mcumc_status_addrs[] = { 160 (0x000143c2 + 0x00000000), 161 (0x000143c2 + 0x00000800), 162 (0x000143c2 + 0x00001000), 163 (0x000143c2 + 0x00001800), 164 (0x000543c2 + 0x00000000), 165 (0x000543c2 + 0x00000800), 166 (0x000543c2 + 0x00001000), 167 (0x000543c2 + 0x00001800), 168 (0x000943c2 + 0x00000000), 169 (0x000943c2 + 0x00000800), 170 (0x000943c2 + 0x00001000), 171 (0x000943c2 + 0x00001800), 172 (0x000d43c2 + 0x00000000), 173 (0x000d43c2 + 0x00000800), 174 (0x000d43c2 + 0x00001000), 175 (0x000d43c2 + 0x00001800), 176 (0x001143c2 + 0x00000000), 177 (0x001143c2 + 0x00000800), 178 (0x001143c2 + 0x00001000), 179 (0x001143c2 + 0x00001800), 180 (0x001543c2 + 0x00000000), 181 (0x001543c2 + 0x00000800), 182 (0x001543c2 + 0x00001000), 183 (0x001543c2 + 0x00001800), 184 (0x001943c2 + 0x00000000), 185 (0x001943c2 + 0x00000800), 186 (0x001943c2 + 0x00001000), 187 (0x001943c2 + 0x00001800), 188 (0x001d43c2 + 0x00000000), 189 (0x001d43c2 + 0x00000800), 190 (0x001d43c2 + 0x00001000), 191 (0x001d43c2 + 0x00001800), 192 }; 193 194 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, 195 struct amdgpu_irq_src *src, 196 unsigned type, 197 enum amdgpu_interrupt_state state) 198 { 199 u32 bits, i, tmp, reg; 200 201 bits = 0x7f; 202 203 switch (state) { 204 case AMDGPU_IRQ_STATE_DISABLE: 205 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 206 reg = ecc_umc_mcumc_ctrl_addrs[i]; 207 tmp = RREG32(reg); 208 tmp &= ~bits; 209 WREG32(reg, tmp); 210 } 211 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 212 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 213 tmp = RREG32(reg); 214 tmp &= ~bits; 215 WREG32(reg, tmp); 216 } 217 break; 218 case AMDGPU_IRQ_STATE_ENABLE: 219 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 220 reg = ecc_umc_mcumc_ctrl_addrs[i]; 221 tmp = RREG32(reg); 222 tmp |= bits; 223 WREG32(reg, tmp); 224 } 225 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 226 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 227 tmp = RREG32(reg); 228 tmp |= bits; 229 WREG32(reg, tmp); 230 } 231 break; 232 default: 233 break; 234 } 235 236 return 0; 237 } 238 239 static int gmc_v9_0_process_ras_data_cb(struct amdgpu_device *adev, 240 struct amdgpu_iv_entry *entry) 241 { 242 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); 243 amdgpu_ras_reset_gpu(adev, 0); 244 return AMDGPU_RAS_UE; 245 } 246 247 static int gmc_v9_0_process_ecc_irq(struct amdgpu_device *adev, 248 struct amdgpu_irq_src *source, 249 struct amdgpu_iv_entry *entry) 250 { 251 struct ras_dispatch_if ih_data = { 252 .head = *adev->gmc.ras_if, 253 .entry = entry, 254 }; 255 amdgpu_ras_interrupt_dispatch(adev, &ih_data); 256 return 0; 257 } 258 259 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 260 struct amdgpu_irq_src *src, 261 unsigned type, 262 enum amdgpu_interrupt_state state) 263 { 264 struct amdgpu_vmhub *hub; 265 u32 tmp, reg, bits, i, j; 266 267 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 268 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 269 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 270 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 271 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 272 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 273 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 274 275 switch (state) { 276 case AMDGPU_IRQ_STATE_DISABLE: 277 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) { 278 hub = &adev->vmhub[j]; 279 for (i = 0; i < 16; i++) { 280 reg = hub->vm_context0_cntl + i; 281 tmp = RREG32(reg); 282 tmp &= ~bits; 283 WREG32(reg, tmp); 284 } 285 } 286 break; 287 case AMDGPU_IRQ_STATE_ENABLE: 288 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) { 289 hub = &adev->vmhub[j]; 290 for (i = 0; i < 16; i++) { 291 reg = hub->vm_context0_cntl + i; 292 tmp = RREG32(reg); 293 tmp |= bits; 294 WREG32(reg, tmp); 295 } 296 } 297 default: 298 break; 299 } 300 301 return 0; 302 } 303 304 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 305 struct amdgpu_irq_src *source, 306 struct amdgpu_iv_entry *entry) 307 { 308 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; 309 bool retry_fault = !!(entry->src_data[1] & 0x80); 310 uint32_t status = 0; 311 u64 addr; 312 313 addr = (u64)entry->src_data[0] << 12; 314 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 315 316 if (retry_fault && amdgpu_gmc_filter_faults(adev, addr, entry->pasid, 317 entry->timestamp)) 318 return 1; /* This also prevents sending it to KFD */ 319 320 /* If it's the first fault for this address, process it normally */ 321 if (!amdgpu_sriov_vf(adev)) { 322 status = RREG32(hub->vm_l2_pro_fault_status); 323 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 324 } 325 326 if (printk_ratelimit()) { 327 struct amdgpu_task_info task_info; 328 329 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 330 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 331 332 dev_err(adev->dev, 333 "[%s] %s page fault (src_id:%u ring:%u vmid:%u " 334 "pasid:%u, for process %s pid %d thread %s pid %d)\n", 335 entry->vmid_src ? "mmhub" : "gfxhub", 336 retry_fault ? "retry" : "no-retry", 337 entry->src_id, entry->ring_id, entry->vmid, 338 entry->pasid, task_info.process_name, task_info.tgid, 339 task_info.task_name, task_info.pid); 340 dev_err(adev->dev, " in page starting at address 0x%016llx from %d\n", 341 addr, entry->client_id); 342 if (!amdgpu_sriov_vf(adev)) 343 dev_err(adev->dev, 344 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 345 status); 346 } 347 348 return 0; 349 } 350 351 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 352 .set = gmc_v9_0_vm_fault_interrupt_state, 353 .process = gmc_v9_0_process_interrupt, 354 }; 355 356 357 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { 358 .set = gmc_v9_0_ecc_interrupt_state, 359 .process = gmc_v9_0_process_ecc_irq, 360 }; 361 362 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 363 { 364 adev->gmc.vm_fault.num_types = 1; 365 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 366 367 adev->gmc.ecc_irq.num_types = 1; 368 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; 369 } 370 371 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, 372 uint32_t flush_type) 373 { 374 u32 req = 0; 375 376 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 377 PER_VMID_INVALIDATE_REQ, 1 << vmid); 378 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 379 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 380 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 381 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 382 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 383 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 384 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 385 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 386 387 return req; 388 } 389 390 /* 391 * GART 392 * VMID 0 is the physical GPU addresses as used by the kernel. 393 * VMIDs 1-15 are used for userspace clients and are handled 394 * by the amdgpu vm/hsa code. 395 */ 396 397 /** 398 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type 399 * 400 * @adev: amdgpu_device pointer 401 * @vmid: vm instance to flush 402 * @flush_type: the flush type 403 * 404 * Flush the TLB for the requested page table using certain type. 405 */ 406 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, 407 uint32_t vmid, uint32_t flush_type) 408 { 409 const unsigned eng = 17; 410 unsigned i, j; 411 412 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { 413 struct amdgpu_vmhub *hub = &adev->vmhub[i]; 414 u32 tmp = gmc_v9_0_get_invalidate_req(vmid, flush_type); 415 416 /* This is necessary for a HW workaround under SRIOV as well 417 * as GFXOFF under bare metal 418 */ 419 if (adev->gfx.kiq.ring.sched.ready && 420 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && 421 !adev->in_gpu_reset) { 422 uint32_t req = hub->vm_inv_eng0_req + eng; 423 uint32_t ack = hub->vm_inv_eng0_ack + eng; 424 425 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, tmp, 426 1 << vmid); 427 continue; 428 } 429 430 spin_lock(&adev->gmc.invalidate_lock); 431 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp); 432 for (j = 0; j < adev->usec_timeout; j++) { 433 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); 434 if (tmp & (1 << vmid)) 435 break; 436 udelay(1); 437 } 438 spin_unlock(&adev->gmc.invalidate_lock); 439 if (j < adev->usec_timeout) 440 continue; 441 442 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 443 } 444 } 445 446 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 447 unsigned vmid, uint64_t pd_addr) 448 { 449 struct amdgpu_device *adev = ring->adev; 450 struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub]; 451 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); 452 unsigned eng = ring->vm_inv_eng; 453 454 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid), 455 lower_32_bits(pd_addr)); 456 457 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid), 458 upper_32_bits(pd_addr)); 459 460 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng, 461 hub->vm_inv_eng0_ack + eng, 462 req, 1 << vmid); 463 464 return pd_addr; 465 } 466 467 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 468 unsigned pasid) 469 { 470 struct amdgpu_device *adev = ring->adev; 471 uint32_t reg; 472 473 if (ring->funcs->vmhub == AMDGPU_GFXHUB) 474 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 475 else 476 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 477 478 amdgpu_ring_emit_wreg(ring, reg, pasid); 479 } 480 481 /* 482 * PTE format on VEGA 10: 483 * 63:59 reserved 484 * 58:57 mtype 485 * 56 F 486 * 55 L 487 * 54 P 488 * 53 SW 489 * 52 T 490 * 50:48 reserved 491 * 47:12 4k physical page base address 492 * 11:7 fragment 493 * 6 write 494 * 5 read 495 * 4 exe 496 * 3 Z 497 * 2 snooped 498 * 1 system 499 * 0 valid 500 * 501 * PDE format on VEGA 10: 502 * 63:59 block fragment size 503 * 58:55 reserved 504 * 54 P 505 * 53:48 reserved 506 * 47:6 physical base address of PD or PTE 507 * 5:3 reserved 508 * 2 C 509 * 1 system 510 * 0 valid 511 */ 512 513 static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev, 514 uint32_t flags) 515 516 { 517 uint64_t pte_flag = 0; 518 519 if (flags & AMDGPU_VM_PAGE_EXECUTABLE) 520 pte_flag |= AMDGPU_PTE_EXECUTABLE; 521 if (flags & AMDGPU_VM_PAGE_READABLE) 522 pte_flag |= AMDGPU_PTE_READABLE; 523 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 524 pte_flag |= AMDGPU_PTE_WRITEABLE; 525 526 switch (flags & AMDGPU_VM_MTYPE_MASK) { 527 case AMDGPU_VM_MTYPE_DEFAULT: 528 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC); 529 break; 530 case AMDGPU_VM_MTYPE_NC: 531 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC); 532 break; 533 case AMDGPU_VM_MTYPE_WC: 534 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_WC); 535 break; 536 case AMDGPU_VM_MTYPE_CC: 537 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_CC); 538 break; 539 case AMDGPU_VM_MTYPE_UC: 540 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_UC); 541 break; 542 default: 543 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC); 544 break; 545 } 546 547 if (flags & AMDGPU_VM_PAGE_PRT) 548 pte_flag |= AMDGPU_PTE_PRT; 549 550 return pte_flag; 551 } 552 553 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, 554 uint64_t *addr, uint64_t *flags) 555 { 556 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 557 *addr = adev->vm_manager.vram_base_offset + *addr - 558 adev->gmc.vram_start; 559 BUG_ON(*addr & 0xFFFF00000000003FULL); 560 561 if (!adev->gmc.translate_further) 562 return; 563 564 if (level == AMDGPU_VM_PDB1) { 565 /* Set the block fragment size */ 566 if (!(*flags & AMDGPU_PDE_PTE)) 567 *flags |= AMDGPU_PDE_BFS(0x9); 568 569 } else if (level == AMDGPU_VM_PDB0) { 570 if (*flags & AMDGPU_PDE_PTE) 571 *flags &= ~AMDGPU_PDE_PTE; 572 else 573 *flags |= AMDGPU_PTE_TF; 574 } 575 } 576 577 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { 578 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, 579 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, 580 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, 581 .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags, 582 .get_vm_pde = gmc_v9_0_get_vm_pde 583 }; 584 585 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) 586 { 587 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; 588 } 589 590 static int gmc_v9_0_early_init(void *handle) 591 { 592 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 593 594 gmc_v9_0_set_gmc_funcs(adev); 595 gmc_v9_0_set_irq_funcs(adev); 596 597 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 598 adev->gmc.shared_aperture_end = 599 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 600 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 601 adev->gmc.private_aperture_end = 602 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 603 604 return 0; 605 } 606 607 static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev) 608 { 609 610 /* 611 * TODO: 612 * Currently there is a bug where some memory client outside 613 * of the driver writes to first 8M of VRAM on S3 resume, 614 * this overrides GART which by default gets placed in first 8M and 615 * causes VM_FAULTS once GTT is accessed. 616 * Keep the stolen memory reservation until the while this is not solved. 617 * Also check code in gmc_v9_0_get_vbios_fb_size and gmc_v9_0_late_init 618 */ 619 switch (adev->asic_type) { 620 case CHIP_VEGA10: 621 return true; 622 case CHIP_RAVEN: 623 case CHIP_VEGA12: 624 case CHIP_VEGA20: 625 default: 626 return false; 627 } 628 } 629 630 static int gmc_v9_0_allocate_vm_inv_eng(struct amdgpu_device *adev) 631 { 632 struct amdgpu_ring *ring; 633 unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] = 634 {GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP}; 635 unsigned i; 636 unsigned vmhub, inv_eng; 637 638 for (i = 0; i < adev->num_rings; ++i) { 639 ring = adev->rings[i]; 640 vmhub = ring->funcs->vmhub; 641 642 inv_eng = ffs(vm_inv_engs[vmhub]); 643 if (!inv_eng) { 644 dev_err(adev->dev, "no VM inv eng for ring %s\n", 645 ring->name); 646 return -EINVAL; 647 } 648 649 ring->vm_inv_eng = inv_eng - 1; 650 vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng); 651 652 dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n", 653 ring->name, ring->vm_inv_eng, ring->funcs->vmhub); 654 } 655 656 return 0; 657 } 658 659 static int gmc_v9_0_ecc_late_init(void *handle) 660 { 661 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 662 struct ras_common_if **ras_if = &adev->gmc.ras_if; 663 struct ras_ih_if ih_info = { 664 .cb = gmc_v9_0_process_ras_data_cb, 665 }; 666 struct ras_fs_if fs_info = { 667 .sysfs_name = "umc_err_count", 668 .debugfs_name = "umc_err_inject", 669 }; 670 struct ras_common_if ras_block = { 671 .block = AMDGPU_RAS_BLOCK__UMC, 672 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 673 .sub_block_index = 0, 674 .name = "umc", 675 }; 676 int r; 677 678 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) { 679 amdgpu_ras_feature_enable(adev, &ras_block, 0); 680 return 0; 681 } 682 /* handle resume path. */ 683 if (*ras_if) 684 goto resume; 685 686 *ras_if = kmalloc(sizeof(**ras_if), GFP_KERNEL); 687 if (!*ras_if) 688 return -ENOMEM; 689 690 **ras_if = ras_block; 691 692 r = amdgpu_ras_feature_enable(adev, *ras_if, 1); 693 if (r) 694 goto feature; 695 696 ih_info.head = **ras_if; 697 fs_info.head = **ras_if; 698 699 r = amdgpu_ras_interrupt_add_handler(adev, &ih_info); 700 if (r) 701 goto interrupt; 702 703 r = amdgpu_ras_debugfs_create(adev, &fs_info); 704 if (r) 705 goto debugfs; 706 707 r = amdgpu_ras_sysfs_create(adev, &fs_info); 708 if (r) 709 goto sysfs; 710 resume: 711 r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0); 712 if (r) 713 goto irq; 714 715 return 0; 716 irq: 717 amdgpu_ras_sysfs_remove(adev, *ras_if); 718 sysfs: 719 amdgpu_ras_debugfs_remove(adev, *ras_if); 720 debugfs: 721 amdgpu_ras_interrupt_remove_handler(adev, &ih_info); 722 interrupt: 723 amdgpu_ras_feature_enable(adev, *ras_if, 0); 724 feature: 725 kfree(*ras_if); 726 *ras_if = NULL; 727 return -EINVAL; 728 } 729 730 731 static int gmc_v9_0_late_init(void *handle) 732 { 733 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 734 bool r; 735 736 if (!gmc_v9_0_keep_stolen_memory(adev)) 737 amdgpu_bo_late_init(adev); 738 739 r = gmc_v9_0_allocate_vm_inv_eng(adev); 740 if (r) 741 return r; 742 /* Check if ecc is available */ 743 if (!amdgpu_sriov_vf(adev)) { 744 switch (adev->asic_type) { 745 case CHIP_VEGA10: 746 case CHIP_VEGA20: 747 r = amdgpu_atomfirmware_mem_ecc_supported(adev); 748 if (!r) { 749 DRM_INFO("ECC is not present.\n"); 750 if (adev->df_funcs->enable_ecc_force_par_wr_rmw) 751 adev->df_funcs->enable_ecc_force_par_wr_rmw(adev, false); 752 } else { 753 DRM_INFO("ECC is active.\n"); 754 } 755 756 r = amdgpu_atomfirmware_sram_ecc_supported(adev); 757 if (!r) { 758 DRM_INFO("SRAM ECC is not present.\n"); 759 } else { 760 DRM_INFO("SRAM ECC is active.\n"); 761 } 762 break; 763 default: 764 break; 765 } 766 } 767 768 r = gmc_v9_0_ecc_late_init(handle); 769 if (r) 770 return r; 771 772 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 773 } 774 775 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 776 struct amdgpu_gmc *mc) 777 { 778 u64 base = 0; 779 if (!amdgpu_sriov_vf(adev)) 780 base = mmhub_v1_0_get_fb_location(adev); 781 /* add the xgmi offset of the physical node */ 782 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 783 amdgpu_gmc_vram_location(adev, mc, base); 784 amdgpu_gmc_gart_location(adev, mc); 785 if (!amdgpu_sriov_vf(adev)) 786 amdgpu_gmc_agp_location(adev, mc); 787 /* base offset of vram pages */ 788 adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev); 789 790 /* XXX: add the xgmi offset of the physical node? */ 791 adev->vm_manager.vram_base_offset += 792 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 793 } 794 795 /** 796 * gmc_v9_0_mc_init - initialize the memory controller driver params 797 * 798 * @adev: amdgpu_device pointer 799 * 800 * Look up the amount of vram, vram width, and decide how to place 801 * vram and gart within the GPU's physical address space. 802 * Returns 0 for success. 803 */ 804 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 805 { 806 int chansize, numchan; 807 int r; 808 809 if (amdgpu_emu_mode != 1) 810 adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev); 811 if (!adev->gmc.vram_width) { 812 /* hbm memory channel size */ 813 if (adev->flags & AMD_IS_APU) 814 chansize = 64; 815 else 816 chansize = 128; 817 818 numchan = adev->df_funcs->get_hbm_channel_number(adev); 819 adev->gmc.vram_width = numchan * chansize; 820 } 821 822 /* size in MB on si */ 823 adev->gmc.mc_vram_size = 824 adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL; 825 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 826 827 if (!(adev->flags & AMD_IS_APU)) { 828 r = amdgpu_device_resize_fb_bar(adev); 829 if (r) 830 return r; 831 } 832 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 833 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 834 835 #ifdef CONFIG_X86_64 836 if (adev->flags & AMD_IS_APU) { 837 adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev); 838 adev->gmc.aper_size = adev->gmc.real_vram_size; 839 } 840 #endif 841 /* In case the PCI BAR is larger than the actual amount of vram */ 842 adev->gmc.visible_vram_size = adev->gmc.aper_size; 843 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 844 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 845 846 /* set the gart size */ 847 if (amdgpu_gart_size == -1) { 848 switch (adev->asic_type) { 849 case CHIP_VEGA10: /* all engines support GPUVM */ 850 case CHIP_VEGA12: /* all engines support GPUVM */ 851 case CHIP_VEGA20: 852 default: 853 adev->gmc.gart_size = 512ULL << 20; 854 break; 855 case CHIP_RAVEN: /* DCE SG support */ 856 adev->gmc.gart_size = 1024ULL << 20; 857 break; 858 } 859 } else { 860 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 861 } 862 863 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); 864 865 return 0; 866 } 867 868 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 869 { 870 int r; 871 872 if (adev->gart.bo) { 873 WARN(1, "VEGA10 PCIE GART already initialized\n"); 874 return 0; 875 } 876 /* Initialize common gart structure */ 877 r = amdgpu_gart_init(adev); 878 if (r) 879 return r; 880 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 881 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE(MTYPE_UC) | 882 AMDGPU_PTE_EXECUTABLE; 883 return amdgpu_gart_table_vram_alloc(adev); 884 } 885 886 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 887 { 888 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 889 unsigned size; 890 891 /* 892 * TODO Remove once GART corruption is resolved 893 * Check related code in gmc_v9_0_sw_fini 894 * */ 895 if (gmc_v9_0_keep_stolen_memory(adev)) 896 return 9 * 1024 * 1024; 897 898 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 899 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */ 900 } else { 901 u32 viewport; 902 903 switch (adev->asic_type) { 904 case CHIP_RAVEN: 905 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 906 size = (REG_GET_FIELD(viewport, 907 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 908 REG_GET_FIELD(viewport, 909 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 910 4); 911 break; 912 case CHIP_VEGA10: 913 case CHIP_VEGA12: 914 case CHIP_VEGA20: 915 default: 916 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); 917 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 918 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * 919 4); 920 break; 921 } 922 } 923 /* return 0 if the pre-OS buffer uses up most of vram */ 924 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 925 return 0; 926 927 return size; 928 } 929 930 static int gmc_v9_0_sw_init(void *handle) 931 { 932 int r; 933 int dma_bits; 934 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 935 936 gfxhub_v1_0_init(adev); 937 mmhub_v1_0_init(adev); 938 939 spin_lock_init(&adev->gmc.invalidate_lock); 940 941 adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev); 942 switch (adev->asic_type) { 943 case CHIP_RAVEN: 944 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 945 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 946 } else { 947 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 948 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 949 adev->gmc.translate_further = 950 adev->vm_manager.num_level > 1; 951 } 952 break; 953 case CHIP_VEGA10: 954 case CHIP_VEGA12: 955 case CHIP_VEGA20: 956 /* 957 * To fulfill 4-level page support, 958 * vm size is 256TB (48bit), maximum size of Vega10, 959 * block size 512 (9bit) 960 */ 961 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */ 962 if (amdgpu_sriov_vf(adev)) 963 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47); 964 else 965 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 966 break; 967 default: 968 break; 969 } 970 971 /* This interrupt is VMC page fault.*/ 972 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, 973 &adev->gmc.vm_fault); 974 if (r) 975 return r; 976 977 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, 978 &adev->gmc.vm_fault); 979 980 if (r) 981 return r; 982 983 /* interrupt sent to DF. */ 984 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 985 &adev->gmc.ecc_irq); 986 if (r) 987 return r; 988 989 /* Set the internal MC address mask 990 * This is the max address of the GPU's 991 * internal address space. 992 */ 993 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 994 995 /* set DMA mask + need_dma32 flags. 996 * PCIE - can handle 44-bits. 997 * IGP - can handle 44-bits 998 * PCI - dma32 for legacy pci gart, 44 bits on vega10 999 */ 1000 adev->need_dma32 = false; 1001 dma_bits = adev->need_dma32 ? 32 : 44; 1002 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 1003 if (r) { 1004 adev->need_dma32 = true; 1005 dma_bits = 32; 1006 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 1007 } 1008 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 1009 if (r) { 1010 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); 1011 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n"); 1012 } 1013 adev->need_swiotlb = drm_need_swiotlb(dma_bits); 1014 1015 if (adev->gmc.xgmi.supported) { 1016 r = gfxhub_v1_1_get_xgmi_info(adev); 1017 if (r) 1018 return r; 1019 } 1020 1021 r = gmc_v9_0_mc_init(adev); 1022 if (r) 1023 return r; 1024 1025 adev->gmc.stolen_size = gmc_v9_0_get_vbios_fb_size(adev); 1026 1027 /* Memory manager */ 1028 r = amdgpu_bo_init(adev); 1029 if (r) 1030 return r; 1031 1032 r = gmc_v9_0_gart_init(adev); 1033 if (r) 1034 return r; 1035 1036 /* 1037 * number of VMs 1038 * VMID 0 is reserved for System 1039 * amdgpu graphics/compute will use VMIDs 1-7 1040 * amdkfd will use VMIDs 8-15 1041 */ 1042 adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS; 1043 adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS; 1044 1045 amdgpu_vm_manager_init(adev); 1046 1047 return 0; 1048 } 1049 1050 static int gmc_v9_0_sw_fini(void *handle) 1051 { 1052 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1053 1054 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) && 1055 adev->gmc.ras_if) { 1056 struct ras_common_if *ras_if = adev->gmc.ras_if; 1057 struct ras_ih_if ih_info = { 1058 .head = *ras_if, 1059 }; 1060 1061 /*remove fs first*/ 1062 amdgpu_ras_debugfs_remove(adev, ras_if); 1063 amdgpu_ras_sysfs_remove(adev, ras_if); 1064 /*remove the IH*/ 1065 amdgpu_ras_interrupt_remove_handler(adev, &ih_info); 1066 amdgpu_ras_feature_enable(adev, ras_if, 0); 1067 kfree(ras_if); 1068 } 1069 1070 amdgpu_gem_force_release(adev); 1071 amdgpu_vm_manager_fini(adev); 1072 1073 if (gmc_v9_0_keep_stolen_memory(adev)) 1074 amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL); 1075 1076 amdgpu_gart_table_vram_free(adev); 1077 amdgpu_bo_fini(adev); 1078 amdgpu_gart_fini(adev); 1079 1080 return 0; 1081 } 1082 1083 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 1084 { 1085 1086 switch (adev->asic_type) { 1087 case CHIP_VEGA10: 1088 case CHIP_VEGA20: 1089 soc15_program_register_sequence(adev, 1090 golden_settings_mmhub_1_0_0, 1091 ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 1092 soc15_program_register_sequence(adev, 1093 golden_settings_athub_1_0_0, 1094 ARRAY_SIZE(golden_settings_athub_1_0_0)); 1095 break; 1096 case CHIP_VEGA12: 1097 break; 1098 case CHIP_RAVEN: 1099 soc15_program_register_sequence(adev, 1100 golden_settings_athub_1_0_0, 1101 ARRAY_SIZE(golden_settings_athub_1_0_0)); 1102 break; 1103 default: 1104 break; 1105 } 1106 } 1107 1108 /** 1109 * gmc_v9_0_gart_enable - gart enable 1110 * 1111 * @adev: amdgpu_device pointer 1112 */ 1113 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 1114 { 1115 int r; 1116 bool value; 1117 u32 tmp; 1118 1119 amdgpu_device_program_register_sequence(adev, 1120 golden_settings_vega10_hdp, 1121 ARRAY_SIZE(golden_settings_vega10_hdp)); 1122 1123 if (adev->gart.bo == NULL) { 1124 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 1125 return -EINVAL; 1126 } 1127 r = amdgpu_gart_table_vram_pin(adev); 1128 if (r) 1129 return r; 1130 1131 switch (adev->asic_type) { 1132 case CHIP_RAVEN: 1133 mmhub_v1_0_update_power_gating(adev, true); 1134 break; 1135 default: 1136 break; 1137 } 1138 1139 r = gfxhub_v1_0_gart_enable(adev); 1140 if (r) 1141 return r; 1142 1143 r = mmhub_v1_0_gart_enable(adev); 1144 if (r) 1145 return r; 1146 1147 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1); 1148 1149 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL); 1150 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp); 1151 1152 /* After HDP is initialized, flush HDP.*/ 1153 adev->nbio_funcs->hdp_flush(adev, NULL); 1154 1155 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 1156 value = false; 1157 else 1158 value = true; 1159 1160 gfxhub_v1_0_set_fault_enable_default(adev, value); 1161 mmhub_v1_0_set_fault_enable_default(adev, value); 1162 gmc_v9_0_flush_gpu_tlb(adev, 0, 0); 1163 1164 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1165 (unsigned)(adev->gmc.gart_size >> 20), 1166 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 1167 adev->gart.ready = true; 1168 return 0; 1169 } 1170 1171 static int gmc_v9_0_hw_init(void *handle) 1172 { 1173 int r; 1174 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1175 1176 /* The sequence of these two function calls matters.*/ 1177 gmc_v9_0_init_golden_registers(adev); 1178 1179 if (adev->mode_info.num_crtc) { 1180 /* Lockout access through VGA aperture*/ 1181 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 1182 1183 /* disable VGA render */ 1184 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 1185 } 1186 1187 r = gmc_v9_0_gart_enable(adev); 1188 1189 return r; 1190 } 1191 1192 /** 1193 * gmc_v9_0_gart_disable - gart disable 1194 * 1195 * @adev: amdgpu_device pointer 1196 * 1197 * This disables all VM page table. 1198 */ 1199 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 1200 { 1201 gfxhub_v1_0_gart_disable(adev); 1202 mmhub_v1_0_gart_disable(adev); 1203 amdgpu_gart_table_vram_unpin(adev); 1204 } 1205 1206 static int gmc_v9_0_hw_fini(void *handle) 1207 { 1208 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1209 1210 if (amdgpu_sriov_vf(adev)) { 1211 /* full access mode, so don't touch any GMC register */ 1212 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 1213 return 0; 1214 } 1215 1216 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 1217 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1218 gmc_v9_0_gart_disable(adev); 1219 1220 return 0; 1221 } 1222 1223 static int gmc_v9_0_suspend(void *handle) 1224 { 1225 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1226 1227 return gmc_v9_0_hw_fini(adev); 1228 } 1229 1230 static int gmc_v9_0_resume(void *handle) 1231 { 1232 int r; 1233 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1234 1235 r = gmc_v9_0_hw_init(adev); 1236 if (r) 1237 return r; 1238 1239 amdgpu_vmid_reset_all(adev); 1240 1241 return 0; 1242 } 1243 1244 static bool gmc_v9_0_is_idle(void *handle) 1245 { 1246 /* MC is always ready in GMC v9.*/ 1247 return true; 1248 } 1249 1250 static int gmc_v9_0_wait_for_idle(void *handle) 1251 { 1252 /* There is no need to wait for MC idle in GMC v9.*/ 1253 return 0; 1254 } 1255 1256 static int gmc_v9_0_soft_reset(void *handle) 1257 { 1258 /* XXX for emulation.*/ 1259 return 0; 1260 } 1261 1262 static int gmc_v9_0_set_clockgating_state(void *handle, 1263 enum amd_clockgating_state state) 1264 { 1265 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1266 1267 return mmhub_v1_0_set_clockgating(adev, state); 1268 } 1269 1270 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags) 1271 { 1272 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1273 1274 mmhub_v1_0_get_clockgating(adev, flags); 1275 } 1276 1277 static int gmc_v9_0_set_powergating_state(void *handle, 1278 enum amd_powergating_state state) 1279 { 1280 return 0; 1281 } 1282 1283 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 1284 .name = "gmc_v9_0", 1285 .early_init = gmc_v9_0_early_init, 1286 .late_init = gmc_v9_0_late_init, 1287 .sw_init = gmc_v9_0_sw_init, 1288 .sw_fini = gmc_v9_0_sw_fini, 1289 .hw_init = gmc_v9_0_hw_init, 1290 .hw_fini = gmc_v9_0_hw_fini, 1291 .suspend = gmc_v9_0_suspend, 1292 .resume = gmc_v9_0_resume, 1293 .is_idle = gmc_v9_0_is_idle, 1294 .wait_for_idle = gmc_v9_0_wait_for_idle, 1295 .soft_reset = gmc_v9_0_soft_reset, 1296 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 1297 .set_powergating_state = gmc_v9_0_set_powergating_state, 1298 .get_clockgating_state = gmc_v9_0_get_clockgating_state, 1299 }; 1300 1301 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = 1302 { 1303 .type = AMD_IP_BLOCK_TYPE_GMC, 1304 .major = 9, 1305 .minor = 0, 1306 .rev = 0, 1307 .funcs = &gmc_v9_0_ip_funcs, 1308 }; 1309