1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/pci.h> 26 27 #include <drm/drm_cache.h> 28 29 #include "amdgpu.h" 30 #include "gmc_v9_0.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_gem.h" 33 34 #include "hdp/hdp_4_0_offset.h" 35 #include "hdp/hdp_4_0_sh_mask.h" 36 #include "gc/gc_9_0_sh_mask.h" 37 #include "dce/dce_12_0_offset.h" 38 #include "dce/dce_12_0_sh_mask.h" 39 #include "vega10_enum.h" 40 #include "mmhub/mmhub_1_0_offset.h" 41 #include "athub/athub_1_0_sh_mask.h" 42 #include "athub/athub_1_0_offset.h" 43 #include "oss/osssys_4_0_offset.h" 44 45 #include "soc15.h" 46 #include "soc15d.h" 47 #include "soc15_common.h" 48 #include "umc/umc_6_0_sh_mask.h" 49 50 #include "gfxhub_v1_0.h" 51 #include "mmhub_v1_0.h" 52 #include "athub_v1_0.h" 53 #include "gfxhub_v1_1.h" 54 #include "mmhub_v9_4.h" 55 #include "umc_v6_1.h" 56 #include "umc_v6_0.h" 57 58 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 59 60 #include "amdgpu_ras.h" 61 #include "amdgpu_xgmi.h" 62 63 /* add these here since we already include dce12 headers and these are for DCN */ 64 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 65 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 66 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 67 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 68 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL 69 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L 70 71 /* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/ 72 #define AMDGPU_NUM_OF_VMIDS 8 73 74 static const u32 golden_settings_vega10_hdp[] = 75 { 76 0xf64, 0x0fffffff, 0x00000000, 77 0xf65, 0x0fffffff, 0x00000000, 78 0xf66, 0x0fffffff, 0x00000000, 79 0xf67, 0x0fffffff, 0x00000000, 80 0xf68, 0x0fffffff, 0x00000000, 81 0xf6a, 0x0fffffff, 0x00000000, 82 0xf6b, 0x0fffffff, 0x00000000, 83 0xf6c, 0x0fffffff, 0x00000000, 84 0xf6d, 0x0fffffff, 0x00000000, 85 0xf6e, 0x0fffffff, 0x00000000, 86 }; 87 88 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = 89 { 90 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), 91 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) 92 }; 93 94 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = 95 { 96 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), 97 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) 98 }; 99 100 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { 101 (0x000143c0 + 0x00000000), 102 (0x000143c0 + 0x00000800), 103 (0x000143c0 + 0x00001000), 104 (0x000143c0 + 0x00001800), 105 (0x000543c0 + 0x00000000), 106 (0x000543c0 + 0x00000800), 107 (0x000543c0 + 0x00001000), 108 (0x000543c0 + 0x00001800), 109 (0x000943c0 + 0x00000000), 110 (0x000943c0 + 0x00000800), 111 (0x000943c0 + 0x00001000), 112 (0x000943c0 + 0x00001800), 113 (0x000d43c0 + 0x00000000), 114 (0x000d43c0 + 0x00000800), 115 (0x000d43c0 + 0x00001000), 116 (0x000d43c0 + 0x00001800), 117 (0x001143c0 + 0x00000000), 118 (0x001143c0 + 0x00000800), 119 (0x001143c0 + 0x00001000), 120 (0x001143c0 + 0x00001800), 121 (0x001543c0 + 0x00000000), 122 (0x001543c0 + 0x00000800), 123 (0x001543c0 + 0x00001000), 124 (0x001543c0 + 0x00001800), 125 (0x001943c0 + 0x00000000), 126 (0x001943c0 + 0x00000800), 127 (0x001943c0 + 0x00001000), 128 (0x001943c0 + 0x00001800), 129 (0x001d43c0 + 0x00000000), 130 (0x001d43c0 + 0x00000800), 131 (0x001d43c0 + 0x00001000), 132 (0x001d43c0 + 0x00001800), 133 }; 134 135 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { 136 (0x000143e0 + 0x00000000), 137 (0x000143e0 + 0x00000800), 138 (0x000143e0 + 0x00001000), 139 (0x000143e0 + 0x00001800), 140 (0x000543e0 + 0x00000000), 141 (0x000543e0 + 0x00000800), 142 (0x000543e0 + 0x00001000), 143 (0x000543e0 + 0x00001800), 144 (0x000943e0 + 0x00000000), 145 (0x000943e0 + 0x00000800), 146 (0x000943e0 + 0x00001000), 147 (0x000943e0 + 0x00001800), 148 (0x000d43e0 + 0x00000000), 149 (0x000d43e0 + 0x00000800), 150 (0x000d43e0 + 0x00001000), 151 (0x000d43e0 + 0x00001800), 152 (0x001143e0 + 0x00000000), 153 (0x001143e0 + 0x00000800), 154 (0x001143e0 + 0x00001000), 155 (0x001143e0 + 0x00001800), 156 (0x001543e0 + 0x00000000), 157 (0x001543e0 + 0x00000800), 158 (0x001543e0 + 0x00001000), 159 (0x001543e0 + 0x00001800), 160 (0x001943e0 + 0x00000000), 161 (0x001943e0 + 0x00000800), 162 (0x001943e0 + 0x00001000), 163 (0x001943e0 + 0x00001800), 164 (0x001d43e0 + 0x00000000), 165 (0x001d43e0 + 0x00000800), 166 (0x001d43e0 + 0x00001000), 167 (0x001d43e0 + 0x00001800), 168 }; 169 170 static const uint32_t ecc_umc_mcumc_status_addrs[] = { 171 (0x000143c2 + 0x00000000), 172 (0x000143c2 + 0x00000800), 173 (0x000143c2 + 0x00001000), 174 (0x000143c2 + 0x00001800), 175 (0x000543c2 + 0x00000000), 176 (0x000543c2 + 0x00000800), 177 (0x000543c2 + 0x00001000), 178 (0x000543c2 + 0x00001800), 179 (0x000943c2 + 0x00000000), 180 (0x000943c2 + 0x00000800), 181 (0x000943c2 + 0x00001000), 182 (0x000943c2 + 0x00001800), 183 (0x000d43c2 + 0x00000000), 184 (0x000d43c2 + 0x00000800), 185 (0x000d43c2 + 0x00001000), 186 (0x000d43c2 + 0x00001800), 187 (0x001143c2 + 0x00000000), 188 (0x001143c2 + 0x00000800), 189 (0x001143c2 + 0x00001000), 190 (0x001143c2 + 0x00001800), 191 (0x001543c2 + 0x00000000), 192 (0x001543c2 + 0x00000800), 193 (0x001543c2 + 0x00001000), 194 (0x001543c2 + 0x00001800), 195 (0x001943c2 + 0x00000000), 196 (0x001943c2 + 0x00000800), 197 (0x001943c2 + 0x00001000), 198 (0x001943c2 + 0x00001800), 199 (0x001d43c2 + 0x00000000), 200 (0x001d43c2 + 0x00000800), 201 (0x001d43c2 + 0x00001000), 202 (0x001d43c2 + 0x00001800), 203 }; 204 205 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, 206 struct amdgpu_irq_src *src, 207 unsigned type, 208 enum amdgpu_interrupt_state state) 209 { 210 u32 bits, i, tmp, reg; 211 212 /* Devices newer then VEGA10/12 shall have these programming 213 sequences performed by PSP BL */ 214 if (adev->asic_type >= CHIP_VEGA20) 215 return 0; 216 217 bits = 0x7f; 218 219 switch (state) { 220 case AMDGPU_IRQ_STATE_DISABLE: 221 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 222 reg = ecc_umc_mcumc_ctrl_addrs[i]; 223 tmp = RREG32(reg); 224 tmp &= ~bits; 225 WREG32(reg, tmp); 226 } 227 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 228 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 229 tmp = RREG32(reg); 230 tmp &= ~bits; 231 WREG32(reg, tmp); 232 } 233 break; 234 case AMDGPU_IRQ_STATE_ENABLE: 235 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 236 reg = ecc_umc_mcumc_ctrl_addrs[i]; 237 tmp = RREG32(reg); 238 tmp |= bits; 239 WREG32(reg, tmp); 240 } 241 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 242 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 243 tmp = RREG32(reg); 244 tmp |= bits; 245 WREG32(reg, tmp); 246 } 247 break; 248 default: 249 break; 250 } 251 252 return 0; 253 } 254 255 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 256 struct amdgpu_irq_src *src, 257 unsigned type, 258 enum amdgpu_interrupt_state state) 259 { 260 struct amdgpu_vmhub *hub; 261 u32 tmp, reg, bits, i, j; 262 263 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 264 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 265 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 266 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 267 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 268 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 269 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 270 271 switch (state) { 272 case AMDGPU_IRQ_STATE_DISABLE: 273 for (j = 0; j < adev->num_vmhubs; j++) { 274 hub = &adev->vmhub[j]; 275 for (i = 0; i < 16; i++) { 276 reg = hub->vm_context0_cntl + i; 277 tmp = RREG32(reg); 278 tmp &= ~bits; 279 WREG32(reg, tmp); 280 } 281 } 282 break; 283 case AMDGPU_IRQ_STATE_ENABLE: 284 for (j = 0; j < adev->num_vmhubs; j++) { 285 hub = &adev->vmhub[j]; 286 for (i = 0; i < 16; i++) { 287 reg = hub->vm_context0_cntl + i; 288 tmp = RREG32(reg); 289 tmp |= bits; 290 WREG32(reg, tmp); 291 } 292 } 293 default: 294 break; 295 } 296 297 return 0; 298 } 299 300 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 301 struct amdgpu_irq_src *source, 302 struct amdgpu_iv_entry *entry) 303 { 304 struct amdgpu_vmhub *hub; 305 bool retry_fault = !!(entry->src_data[1] & 0x80); 306 uint32_t status = 0; 307 u64 addr; 308 char hub_name[10]; 309 310 addr = (u64)entry->src_data[0] << 12; 311 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 312 313 if (retry_fault && amdgpu_gmc_filter_faults(adev, addr, entry->pasid, 314 entry->timestamp)) 315 return 1; /* This also prevents sending it to KFD */ 316 317 if (entry->client_id == SOC15_IH_CLIENTID_VMC) { 318 snprintf(hub_name, sizeof(hub_name), "mmhub0"); 319 hub = &adev->vmhub[AMDGPU_MMHUB_0]; 320 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) { 321 snprintf(hub_name, sizeof(hub_name), "mmhub1"); 322 hub = &adev->vmhub[AMDGPU_MMHUB_1]; 323 } else { 324 snprintf(hub_name, sizeof(hub_name), "gfxhub0"); 325 hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 326 } 327 328 /* If it's the first fault for this address, process it normally */ 329 if (retry_fault && !in_interrupt() && 330 amdgpu_vm_handle_fault(adev, entry->pasid, addr)) 331 return 1; /* This also prevents sending it to KFD */ 332 333 if (!amdgpu_sriov_vf(adev)) { 334 /* 335 * Issue a dummy read to wait for the status register to 336 * be updated to avoid reading an incorrect value due to 337 * the new fast GRBM interface. 338 */ 339 if (entry->vmid_src == AMDGPU_GFXHUB_0) 340 RREG32(hub->vm_l2_pro_fault_status); 341 342 status = RREG32(hub->vm_l2_pro_fault_status); 343 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 344 } 345 346 if (printk_ratelimit()) { 347 struct amdgpu_task_info task_info; 348 349 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 350 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 351 352 dev_err(adev->dev, 353 "[%s] %s page fault (src_id:%u ring:%u vmid:%u " 354 "pasid:%u, for process %s pid %d thread %s pid %d)\n", 355 hub_name, retry_fault ? "retry" : "no-retry", 356 entry->src_id, entry->ring_id, entry->vmid, 357 entry->pasid, task_info.process_name, task_info.tgid, 358 task_info.task_name, task_info.pid); 359 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", 360 addr, entry->client_id); 361 if (!amdgpu_sriov_vf(adev)) { 362 dev_err(adev->dev, 363 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 364 status); 365 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 366 REG_GET_FIELD(status, 367 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 368 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 369 REG_GET_FIELD(status, 370 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 371 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 372 REG_GET_FIELD(status, 373 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 374 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 375 REG_GET_FIELD(status, 376 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 377 dev_err(adev->dev, "\t RW: 0x%lx\n", 378 REG_GET_FIELD(status, 379 VM_L2_PROTECTION_FAULT_STATUS, RW)); 380 381 } 382 } 383 384 return 0; 385 } 386 387 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 388 .set = gmc_v9_0_vm_fault_interrupt_state, 389 .process = gmc_v9_0_process_interrupt, 390 }; 391 392 393 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { 394 .set = gmc_v9_0_ecc_interrupt_state, 395 .process = amdgpu_umc_process_ecc_irq, 396 }; 397 398 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 399 { 400 adev->gmc.vm_fault.num_types = 1; 401 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 402 403 if (!amdgpu_sriov_vf(adev)) { 404 adev->gmc.ecc_irq.num_types = 1; 405 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; 406 } 407 } 408 409 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, 410 uint32_t flush_type) 411 { 412 u32 req = 0; 413 414 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 415 PER_VMID_INVALIDATE_REQ, 1 << vmid); 416 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 417 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 418 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 419 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 420 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 421 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 422 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 423 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 424 425 return req; 426 } 427 428 /** 429 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore 430 * 431 * @adev: amdgpu_device pointer 432 * @vmhub: vmhub type 433 * 434 */ 435 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev, 436 uint32_t vmhub) 437 { 438 return ((vmhub == AMDGPU_MMHUB_0 || 439 vmhub == AMDGPU_MMHUB_1) && 440 (!amdgpu_sriov_vf(adev)) && 441 (!(adev->asic_type == CHIP_RAVEN && 442 adev->rev_id < 0x8 && 443 adev->pdev->device == 0x15d8))); 444 } 445 446 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, 447 uint8_t vmid, uint16_t *p_pasid) 448 { 449 uint32_t value; 450 451 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 452 + vmid); 453 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 454 455 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 456 } 457 458 /* 459 * GART 460 * VMID 0 is the physical GPU addresses as used by the kernel. 461 * VMIDs 1-15 are used for userspace clients and are handled 462 * by the amdgpu vm/hsa code. 463 */ 464 465 /** 466 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type 467 * 468 * @adev: amdgpu_device pointer 469 * @vmid: vm instance to flush 470 * @flush_type: the flush type 471 * 472 * Flush the TLB for the requested page table using certain type. 473 */ 474 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 475 uint32_t vmhub, uint32_t flush_type) 476 { 477 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub); 478 const unsigned eng = 17; 479 u32 j, inv_req, inv_req2, tmp; 480 struct amdgpu_vmhub *hub; 481 482 BUG_ON(vmhub >= adev->num_vmhubs); 483 484 hub = &adev->vmhub[vmhub]; 485 if (adev->gmc.xgmi.num_physical_nodes && 486 adev->asic_type == CHIP_VEGA20) { 487 /* Vega20+XGMI caches PTEs in TC and TLB. Add a 488 * heavy-weight TLB flush (type 2), which flushes 489 * both. Due to a race condition with concurrent 490 * memory accesses using the same TLB cache line, we 491 * still need a second TLB flush after this. 492 */ 493 inv_req = gmc_v9_0_get_invalidate_req(vmid, 2); 494 inv_req2 = gmc_v9_0_get_invalidate_req(vmid, flush_type); 495 } else { 496 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type); 497 inv_req2 = 0; 498 } 499 500 /* This is necessary for a HW workaround under SRIOV as well 501 * as GFXOFF under bare metal 502 */ 503 if (adev->gfx.kiq.ring.sched.ready && 504 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && 505 !adev->in_gpu_reset) { 506 uint32_t req = hub->vm_inv_eng0_req + eng; 507 uint32_t ack = hub->vm_inv_eng0_ack + eng; 508 509 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 510 1 << vmid); 511 return; 512 } 513 514 spin_lock(&adev->gmc.invalidate_lock); 515 516 /* 517 * It may lose gpuvm invalidate acknowldege state across power-gating 518 * off cycle, add semaphore acquire before invalidation and semaphore 519 * release after invalidation to avoid entering power gated state 520 * to WA the Issue 521 */ 522 523 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 524 if (use_semaphore) { 525 for (j = 0; j < adev->usec_timeout; j++) { 526 /* a read return value of 1 means semaphore acuqire */ 527 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng); 528 if (tmp & 0x1) 529 break; 530 udelay(1); 531 } 532 533 if (j >= adev->usec_timeout) 534 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 535 } 536 537 do { 538 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, inv_req); 539 540 /* 541 * Issue a dummy read to wait for the ACK register to 542 * be cleared to avoid a false ACK due to the new fast 543 * GRBM interface. 544 */ 545 if (vmhub == AMDGPU_GFXHUB_0) 546 RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng); 547 548 for (j = 0; j < adev->usec_timeout; j++) { 549 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); 550 if (tmp & (1 << vmid)) 551 break; 552 udelay(1); 553 } 554 555 inv_req = inv_req2; 556 inv_req2 = 0; 557 } while (inv_req); 558 559 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 560 if (use_semaphore) 561 /* 562 * add semaphore release after invalidation, 563 * write with 0 means semaphore release 564 */ 565 WREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng, 0); 566 567 spin_unlock(&adev->gmc.invalidate_lock); 568 569 if (j < adev->usec_timeout) 570 return; 571 572 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 573 } 574 575 /** 576 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid 577 * 578 * @adev: amdgpu_device pointer 579 * @pasid: pasid to be flush 580 * 581 * Flush the TLB for the requested pasid. 582 */ 583 static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 584 uint16_t pasid, uint32_t flush_type, 585 bool all_hub) 586 { 587 int vmid, i; 588 signed long r; 589 uint32_t seq; 590 uint16_t queried_pasid; 591 bool ret; 592 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 593 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 594 595 if (adev->in_gpu_reset) 596 return -EIO; 597 598 if (ring->sched.ready) { 599 /* Vega20+XGMI caches PTEs in TC and TLB. Add a 600 * heavy-weight TLB flush (type 2), which flushes 601 * both. Due to a race condition with concurrent 602 * memory accesses using the same TLB cache line, we 603 * still need a second TLB flush after this. 604 */ 605 bool vega20_xgmi_wa = (adev->gmc.xgmi.num_physical_nodes && 606 adev->asic_type == CHIP_VEGA20); 607 /* 2 dwords flush + 8 dwords fence */ 608 unsigned int ndw = kiq->pmf->invalidate_tlbs_size + 8; 609 610 if (vega20_xgmi_wa) 611 ndw += kiq->pmf->invalidate_tlbs_size; 612 613 spin_lock(&adev->gfx.kiq.ring_lock); 614 /* 2 dwords flush + 8 dwords fence */ 615 amdgpu_ring_alloc(ring, ndw); 616 if (vega20_xgmi_wa) 617 kiq->pmf->kiq_invalidate_tlbs(ring, 618 pasid, 2, all_hub); 619 kiq->pmf->kiq_invalidate_tlbs(ring, 620 pasid, flush_type, all_hub); 621 amdgpu_fence_emit_polling(ring, &seq); 622 amdgpu_ring_commit(ring); 623 spin_unlock(&adev->gfx.kiq.ring_lock); 624 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); 625 if (r < 1) { 626 DRM_ERROR("wait for kiq fence error: %ld.\n", r); 627 return -ETIME; 628 } 629 630 return 0; 631 } 632 633 for (vmid = 1; vmid < 16; vmid++) { 634 635 ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 636 &queried_pasid); 637 if (ret && queried_pasid == pasid) { 638 if (all_hub) { 639 for (i = 0; i < adev->num_vmhubs; i++) 640 gmc_v9_0_flush_gpu_tlb(adev, vmid, 641 i, flush_type); 642 } else { 643 gmc_v9_0_flush_gpu_tlb(adev, vmid, 644 AMDGPU_GFXHUB_0, flush_type); 645 } 646 break; 647 } 648 } 649 650 return 0; 651 652 } 653 654 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 655 unsigned vmid, uint64_t pd_addr) 656 { 657 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub); 658 struct amdgpu_device *adev = ring->adev; 659 struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub]; 660 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); 661 unsigned eng = ring->vm_inv_eng; 662 663 /* 664 * It may lose gpuvm invalidate acknowldege state across power-gating 665 * off cycle, add semaphore acquire before invalidation and semaphore 666 * release after invalidation to avoid entering power gated state 667 * to WA the Issue 668 */ 669 670 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 671 if (use_semaphore) 672 /* a read return value of 1 means semaphore acuqire */ 673 amdgpu_ring_emit_reg_wait(ring, 674 hub->vm_inv_eng0_sem + eng, 0x1, 0x1); 675 676 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid), 677 lower_32_bits(pd_addr)); 678 679 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid), 680 upper_32_bits(pd_addr)); 681 682 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng, 683 hub->vm_inv_eng0_ack + eng, 684 req, 1 << vmid); 685 686 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 687 if (use_semaphore) 688 /* 689 * add semaphore release after invalidation, 690 * write with 0 means semaphore release 691 */ 692 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + eng, 0); 693 694 return pd_addr; 695 } 696 697 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 698 unsigned pasid) 699 { 700 struct amdgpu_device *adev = ring->adev; 701 uint32_t reg; 702 703 /* Do nothing because there's no lut register for mmhub1. */ 704 if (ring->funcs->vmhub == AMDGPU_MMHUB_1) 705 return; 706 707 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) 708 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 709 else 710 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 711 712 amdgpu_ring_emit_wreg(ring, reg, pasid); 713 } 714 715 /* 716 * PTE format on VEGA 10: 717 * 63:59 reserved 718 * 58:57 mtype 719 * 56 F 720 * 55 L 721 * 54 P 722 * 53 SW 723 * 52 T 724 * 50:48 reserved 725 * 47:12 4k physical page base address 726 * 11:7 fragment 727 * 6 write 728 * 5 read 729 * 4 exe 730 * 3 Z 731 * 2 snooped 732 * 1 system 733 * 0 valid 734 * 735 * PDE format on VEGA 10: 736 * 63:59 block fragment size 737 * 58:55 reserved 738 * 54 P 739 * 53:48 reserved 740 * 47:6 physical base address of PD or PTE 741 * 5:3 reserved 742 * 2 C 743 * 1 system 744 * 0 valid 745 */ 746 747 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 748 749 { 750 switch (flags) { 751 case AMDGPU_VM_MTYPE_DEFAULT: 752 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 753 case AMDGPU_VM_MTYPE_NC: 754 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 755 case AMDGPU_VM_MTYPE_WC: 756 return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC); 757 case AMDGPU_VM_MTYPE_RW: 758 return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW); 759 case AMDGPU_VM_MTYPE_CC: 760 return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC); 761 case AMDGPU_VM_MTYPE_UC: 762 return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC); 763 default: 764 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 765 } 766 } 767 768 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, 769 uint64_t *addr, uint64_t *flags) 770 { 771 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 772 *addr = adev->vm_manager.vram_base_offset + *addr - 773 adev->gmc.vram_start; 774 BUG_ON(*addr & 0xFFFF00000000003FULL); 775 776 if (!adev->gmc.translate_further) 777 return; 778 779 if (level == AMDGPU_VM_PDB1) { 780 /* Set the block fragment size */ 781 if (!(*flags & AMDGPU_PDE_PTE)) 782 *flags |= AMDGPU_PDE_BFS(0x9); 783 784 } else if (level == AMDGPU_VM_PDB0) { 785 if (*flags & AMDGPU_PDE_PTE) 786 *flags &= ~AMDGPU_PDE_PTE; 787 else 788 *flags |= AMDGPU_PTE_TF; 789 } 790 } 791 792 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev, 793 struct amdgpu_bo_va_mapping *mapping, 794 uint64_t *flags) 795 { 796 *flags &= ~AMDGPU_PTE_EXECUTABLE; 797 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 798 799 *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 800 *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK; 801 802 if (mapping->flags & AMDGPU_PTE_PRT) { 803 *flags |= AMDGPU_PTE_PRT; 804 *flags &= ~AMDGPU_PTE_VALID; 805 } 806 807 if (adev->asic_type == CHIP_ARCTURUS && 808 !(*flags & AMDGPU_PTE_SYSTEM) && 809 mapping->bo_va->is_xgmi) 810 *flags |= AMDGPU_PTE_SNOOPED; 811 } 812 813 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { 814 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, 815 .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid, 816 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, 817 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, 818 .map_mtype = gmc_v9_0_map_mtype, 819 .get_vm_pde = gmc_v9_0_get_vm_pde, 820 .get_vm_pte = gmc_v9_0_get_vm_pte 821 }; 822 823 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) 824 { 825 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; 826 } 827 828 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) 829 { 830 switch (adev->asic_type) { 831 case CHIP_VEGA10: 832 adev->umc.funcs = &umc_v6_0_funcs; 833 break; 834 case CHIP_VEGA20: 835 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 836 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 837 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 838 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20; 839 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 840 adev->umc.funcs = &umc_v6_1_funcs; 841 break; 842 case CHIP_ARCTURUS: 843 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 844 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 845 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 846 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT; 847 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 848 adev->umc.funcs = &umc_v6_1_funcs; 849 break; 850 default: 851 break; 852 } 853 } 854 855 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) 856 { 857 switch (adev->asic_type) { 858 case CHIP_VEGA20: 859 adev->mmhub.funcs = &mmhub_v1_0_funcs; 860 break; 861 case CHIP_ARCTURUS: 862 adev->mmhub.funcs = &mmhub_v9_4_funcs; 863 break; 864 default: 865 break; 866 } 867 } 868 869 static int gmc_v9_0_early_init(void *handle) 870 { 871 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 872 873 gmc_v9_0_set_gmc_funcs(adev); 874 gmc_v9_0_set_irq_funcs(adev); 875 gmc_v9_0_set_umc_funcs(adev); 876 gmc_v9_0_set_mmhub_funcs(adev); 877 878 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 879 adev->gmc.shared_aperture_end = 880 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 881 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 882 adev->gmc.private_aperture_end = 883 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 884 885 return 0; 886 } 887 888 static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev) 889 { 890 891 /* 892 * TODO: 893 * Currently there is a bug where some memory client outside 894 * of the driver writes to first 8M of VRAM on S3 resume, 895 * this overrides GART which by default gets placed in first 8M and 896 * causes VM_FAULTS once GTT is accessed. 897 * Keep the stolen memory reservation until the while this is not solved. 898 * Also check code in gmc_v9_0_get_vbios_fb_size and gmc_v9_0_late_init 899 */ 900 switch (adev->asic_type) { 901 case CHIP_VEGA10: 902 case CHIP_RAVEN: 903 case CHIP_ARCTURUS: 904 case CHIP_RENOIR: 905 return true; 906 case CHIP_VEGA12: 907 case CHIP_VEGA20: 908 default: 909 return false; 910 } 911 } 912 913 static int gmc_v9_0_late_init(void *handle) 914 { 915 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 916 int r; 917 918 if (!gmc_v9_0_keep_stolen_memory(adev)) 919 amdgpu_bo_late_init(adev); 920 921 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 922 if (r) 923 return r; 924 /* Check if ecc is available */ 925 if (!amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_VEGA10)) { 926 r = amdgpu_atomfirmware_mem_ecc_supported(adev); 927 if (!r) { 928 DRM_INFO("ECC is not present.\n"); 929 if (adev->df.funcs->enable_ecc_force_par_wr_rmw) 930 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false); 931 } else 932 DRM_INFO("ECC is active.\n"); 933 934 r = amdgpu_atomfirmware_sram_ecc_supported(adev); 935 if (!r) 936 DRM_INFO("SRAM ECC is not present.\n"); 937 else 938 DRM_INFO("SRAM ECC is active.\n"); 939 } 940 941 if (adev->mmhub.funcs && adev->mmhub.funcs->reset_ras_error_count) 942 adev->mmhub.funcs->reset_ras_error_count(adev); 943 944 r = amdgpu_gmc_ras_late_init(adev); 945 if (r) 946 return r; 947 948 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 949 } 950 951 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 952 struct amdgpu_gmc *mc) 953 { 954 u64 base = 0; 955 956 if (adev->asic_type == CHIP_ARCTURUS) 957 base = mmhub_v9_4_get_fb_location(adev); 958 else if (!amdgpu_sriov_vf(adev)) 959 base = mmhub_v1_0_get_fb_location(adev); 960 961 /* add the xgmi offset of the physical node */ 962 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 963 amdgpu_gmc_vram_location(adev, mc, base); 964 amdgpu_gmc_gart_location(adev, mc); 965 amdgpu_gmc_agp_location(adev, mc); 966 /* base offset of vram pages */ 967 adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev); 968 969 /* XXX: add the xgmi offset of the physical node? */ 970 adev->vm_manager.vram_base_offset += 971 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 972 } 973 974 /** 975 * gmc_v9_0_mc_init - initialize the memory controller driver params 976 * 977 * @adev: amdgpu_device pointer 978 * 979 * Look up the amount of vram, vram width, and decide how to place 980 * vram and gart within the GPU's physical address space. 981 * Returns 0 for success. 982 */ 983 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 984 { 985 int r; 986 987 /* size in MB on si */ 988 adev->gmc.mc_vram_size = 989 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 990 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 991 992 if (!(adev->flags & AMD_IS_APU)) { 993 r = amdgpu_device_resize_fb_bar(adev); 994 if (r) 995 return r; 996 } 997 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 998 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 999 1000 #ifdef CONFIG_X86_64 1001 if (adev->flags & AMD_IS_APU) { 1002 adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev); 1003 adev->gmc.aper_size = adev->gmc.real_vram_size; 1004 } 1005 #endif 1006 /* In case the PCI BAR is larger than the actual amount of vram */ 1007 adev->gmc.visible_vram_size = adev->gmc.aper_size; 1008 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 1009 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 1010 1011 /* set the gart size */ 1012 if (amdgpu_gart_size == -1) { 1013 switch (adev->asic_type) { 1014 case CHIP_VEGA10: /* all engines support GPUVM */ 1015 case CHIP_VEGA12: /* all engines support GPUVM */ 1016 case CHIP_VEGA20: 1017 case CHIP_ARCTURUS: 1018 default: 1019 adev->gmc.gart_size = 512ULL << 20; 1020 break; 1021 case CHIP_RAVEN: /* DCE SG support */ 1022 case CHIP_RENOIR: 1023 adev->gmc.gart_size = 1024ULL << 20; 1024 break; 1025 } 1026 } else { 1027 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 1028 } 1029 1030 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); 1031 1032 return 0; 1033 } 1034 1035 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 1036 { 1037 int r; 1038 1039 if (adev->gart.bo) { 1040 WARN(1, "VEGA10 PCIE GART already initialized\n"); 1041 return 0; 1042 } 1043 /* Initialize common gart structure */ 1044 r = amdgpu_gart_init(adev); 1045 if (r) 1046 return r; 1047 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 1048 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) | 1049 AMDGPU_PTE_EXECUTABLE; 1050 return amdgpu_gart_table_vram_alloc(adev); 1051 } 1052 1053 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 1054 { 1055 u32 d1vga_control; 1056 unsigned size; 1057 1058 /* 1059 * TODO Remove once GART corruption is resolved 1060 * Check related code in gmc_v9_0_sw_fini 1061 * */ 1062 if (gmc_v9_0_keep_stolen_memory(adev)) 1063 return 9 * 1024 * 1024; 1064 1065 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 1066 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1067 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */ 1068 } else { 1069 u32 viewport; 1070 1071 switch (adev->asic_type) { 1072 case CHIP_RAVEN: 1073 case CHIP_RENOIR: 1074 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 1075 size = (REG_GET_FIELD(viewport, 1076 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1077 REG_GET_FIELD(viewport, 1078 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1079 4); 1080 break; 1081 case CHIP_VEGA10: 1082 case CHIP_VEGA12: 1083 case CHIP_VEGA20: 1084 default: 1085 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); 1086 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1087 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1088 4); 1089 break; 1090 } 1091 } 1092 /* return 0 if the pre-OS buffer uses up most of vram */ 1093 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 1094 return 0; 1095 1096 return size; 1097 } 1098 1099 static int gmc_v9_0_sw_init(void *handle) 1100 { 1101 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 1102 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1103 1104 gfxhub_v1_0_init(adev); 1105 if (adev->asic_type == CHIP_ARCTURUS) 1106 mmhub_v9_4_init(adev); 1107 else 1108 mmhub_v1_0_init(adev); 1109 1110 spin_lock_init(&adev->gmc.invalidate_lock); 1111 1112 r = amdgpu_atomfirmware_get_vram_info(adev, 1113 &vram_width, &vram_type, &vram_vendor); 1114 if (amdgpu_sriov_vf(adev)) 1115 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, 1116 * and DF related registers is not readable, seems hardcord is the 1117 * only way to set the correct vram_width 1118 */ 1119 adev->gmc.vram_width = 2048; 1120 else if (amdgpu_emu_mode != 1) 1121 adev->gmc.vram_width = vram_width; 1122 1123 if (!adev->gmc.vram_width) { 1124 int chansize, numchan; 1125 1126 /* hbm memory channel size */ 1127 if (adev->flags & AMD_IS_APU) 1128 chansize = 64; 1129 else 1130 chansize = 128; 1131 1132 numchan = adev->df.funcs->get_hbm_channel_number(adev); 1133 adev->gmc.vram_width = numchan * chansize; 1134 } 1135 1136 adev->gmc.vram_type = vram_type; 1137 adev->gmc.vram_vendor = vram_vendor; 1138 switch (adev->asic_type) { 1139 case CHIP_RAVEN: 1140 adev->num_vmhubs = 2; 1141 1142 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 1143 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1144 } else { 1145 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 1146 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 1147 adev->gmc.translate_further = 1148 adev->vm_manager.num_level > 1; 1149 } 1150 break; 1151 case CHIP_VEGA10: 1152 case CHIP_VEGA12: 1153 case CHIP_VEGA20: 1154 case CHIP_RENOIR: 1155 adev->num_vmhubs = 2; 1156 1157 1158 /* 1159 * To fulfill 4-level page support, 1160 * vm size is 256TB (48bit), maximum size of Vega10, 1161 * block size 512 (9bit) 1162 */ 1163 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */ 1164 if (amdgpu_sriov_vf(adev)) 1165 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47); 1166 else 1167 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1168 break; 1169 case CHIP_ARCTURUS: 1170 adev->num_vmhubs = 3; 1171 1172 /* Keep the vm size same with Vega20 */ 1173 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1174 break; 1175 default: 1176 break; 1177 } 1178 1179 /* This interrupt is VMC page fault.*/ 1180 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, 1181 &adev->gmc.vm_fault); 1182 if (r) 1183 return r; 1184 1185 if (adev->asic_type == CHIP_ARCTURUS) { 1186 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT, 1187 &adev->gmc.vm_fault); 1188 if (r) 1189 return r; 1190 } 1191 1192 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, 1193 &adev->gmc.vm_fault); 1194 1195 if (r) 1196 return r; 1197 1198 if (!amdgpu_sriov_vf(adev)) { 1199 /* interrupt sent to DF. */ 1200 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 1201 &adev->gmc.ecc_irq); 1202 if (r) 1203 return r; 1204 } 1205 1206 /* Set the internal MC address mask 1207 * This is the max address of the GPU's 1208 * internal address space. 1209 */ 1210 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 1211 1212 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 1213 if (r) { 1214 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 1215 return r; 1216 } 1217 adev->need_swiotlb = drm_need_swiotlb(44); 1218 1219 if (adev->gmc.xgmi.supported) { 1220 r = gfxhub_v1_1_get_xgmi_info(adev); 1221 if (r) 1222 return r; 1223 } 1224 1225 r = gmc_v9_0_mc_init(adev); 1226 if (r) 1227 return r; 1228 1229 adev->gmc.stolen_size = gmc_v9_0_get_vbios_fb_size(adev); 1230 1231 /* Memory manager */ 1232 r = amdgpu_bo_init(adev); 1233 if (r) 1234 return r; 1235 1236 r = gmc_v9_0_gart_init(adev); 1237 if (r) 1238 return r; 1239 1240 /* 1241 * number of VMs 1242 * VMID 0 is reserved for System 1243 * amdgpu graphics/compute will use VMIDs 1-7 1244 * amdkfd will use VMIDs 8-15 1245 */ 1246 adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; 1247 adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; 1248 adev->vm_manager.id_mgr[AMDGPU_MMHUB_1].num_ids = AMDGPU_NUM_OF_VMIDS; 1249 1250 amdgpu_vm_manager_init(adev); 1251 1252 return 0; 1253 } 1254 1255 static int gmc_v9_0_sw_fini(void *handle) 1256 { 1257 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1258 void *stolen_vga_buf; 1259 1260 amdgpu_gmc_ras_fini(adev); 1261 amdgpu_gem_force_release(adev); 1262 amdgpu_vm_manager_fini(adev); 1263 1264 if (gmc_v9_0_keep_stolen_memory(adev)) 1265 amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf); 1266 1267 amdgpu_gart_table_vram_free(adev); 1268 amdgpu_bo_fini(adev); 1269 amdgpu_gart_fini(adev); 1270 1271 return 0; 1272 } 1273 1274 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 1275 { 1276 1277 switch (adev->asic_type) { 1278 case CHIP_VEGA10: 1279 if (amdgpu_sriov_vf(adev)) 1280 break; 1281 /* fall through */ 1282 case CHIP_VEGA20: 1283 soc15_program_register_sequence(adev, 1284 golden_settings_mmhub_1_0_0, 1285 ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 1286 soc15_program_register_sequence(adev, 1287 golden_settings_athub_1_0_0, 1288 ARRAY_SIZE(golden_settings_athub_1_0_0)); 1289 break; 1290 case CHIP_VEGA12: 1291 break; 1292 case CHIP_RAVEN: 1293 /* TODO for renoir */ 1294 soc15_program_register_sequence(adev, 1295 golden_settings_athub_1_0_0, 1296 ARRAY_SIZE(golden_settings_athub_1_0_0)); 1297 break; 1298 default: 1299 break; 1300 } 1301 } 1302 1303 /** 1304 * gmc_v9_0_restore_registers - restores regs 1305 * 1306 * @adev: amdgpu_device pointer 1307 * 1308 * This restores register values, saved at suspend. 1309 */ 1310 static void gmc_v9_0_restore_registers(struct amdgpu_device *adev) 1311 { 1312 if (adev->asic_type == CHIP_RAVEN) 1313 WREG32(mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register); 1314 } 1315 1316 /** 1317 * gmc_v9_0_gart_enable - gart enable 1318 * 1319 * @adev: amdgpu_device pointer 1320 */ 1321 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 1322 { 1323 int r; 1324 1325 if (adev->gart.bo == NULL) { 1326 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 1327 return -EINVAL; 1328 } 1329 r = amdgpu_gart_table_vram_pin(adev); 1330 if (r) 1331 return r; 1332 1333 r = gfxhub_v1_0_gart_enable(adev); 1334 if (r) 1335 return r; 1336 1337 if (adev->asic_type == CHIP_ARCTURUS) 1338 r = mmhub_v9_4_gart_enable(adev); 1339 else 1340 r = mmhub_v1_0_gart_enable(adev); 1341 if (r) 1342 return r; 1343 1344 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1345 (unsigned)(adev->gmc.gart_size >> 20), 1346 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 1347 adev->gart.ready = true; 1348 return 0; 1349 } 1350 1351 static int gmc_v9_0_hw_init(void *handle) 1352 { 1353 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1354 bool value; 1355 int r, i; 1356 u32 tmp; 1357 1358 /* The sequence of these two function calls matters.*/ 1359 gmc_v9_0_init_golden_registers(adev); 1360 1361 if (adev->mode_info.num_crtc) { 1362 if (adev->asic_type != CHIP_ARCTURUS) { 1363 /* Lockout access through VGA aperture*/ 1364 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 1365 1366 /* disable VGA render */ 1367 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 1368 } 1369 } 1370 1371 amdgpu_device_program_register_sequence(adev, 1372 golden_settings_vega10_hdp, 1373 ARRAY_SIZE(golden_settings_vega10_hdp)); 1374 1375 switch (adev->asic_type) { 1376 case CHIP_RAVEN: 1377 /* TODO for renoir */ 1378 mmhub_v1_0_update_power_gating(adev, true); 1379 break; 1380 case CHIP_ARCTURUS: 1381 WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1); 1382 break; 1383 default: 1384 break; 1385 } 1386 1387 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1); 1388 1389 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL); 1390 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp); 1391 1392 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); 1393 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40)); 1394 1395 /* After HDP is initialized, flush HDP.*/ 1396 adev->nbio.funcs->hdp_flush(adev, NULL); 1397 1398 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 1399 value = false; 1400 else 1401 value = true; 1402 1403 if (!amdgpu_sriov_vf(adev)) { 1404 gfxhub_v1_0_set_fault_enable_default(adev, value); 1405 if (adev->asic_type == CHIP_ARCTURUS) 1406 mmhub_v9_4_set_fault_enable_default(adev, value); 1407 else 1408 mmhub_v1_0_set_fault_enable_default(adev, value); 1409 } 1410 for (i = 0; i < adev->num_vmhubs; ++i) 1411 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0); 1412 1413 if (adev->umc.funcs && adev->umc.funcs->init_registers) 1414 adev->umc.funcs->init_registers(adev); 1415 1416 r = gmc_v9_0_gart_enable(adev); 1417 1418 return r; 1419 } 1420 1421 /** 1422 * gmc_v9_0_save_registers - saves regs 1423 * 1424 * @adev: amdgpu_device pointer 1425 * 1426 * This saves potential register values that should be 1427 * restored upon resume 1428 */ 1429 static void gmc_v9_0_save_registers(struct amdgpu_device *adev) 1430 { 1431 if (adev->asic_type == CHIP_RAVEN) 1432 adev->gmc.sdpif_register = RREG32(mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); 1433 } 1434 1435 /** 1436 * gmc_v9_0_gart_disable - gart disable 1437 * 1438 * @adev: amdgpu_device pointer 1439 * 1440 * This disables all VM page table. 1441 */ 1442 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 1443 { 1444 gfxhub_v1_0_gart_disable(adev); 1445 if (adev->asic_type == CHIP_ARCTURUS) 1446 mmhub_v9_4_gart_disable(adev); 1447 else 1448 mmhub_v1_0_gart_disable(adev); 1449 amdgpu_gart_table_vram_unpin(adev); 1450 } 1451 1452 static int gmc_v9_0_hw_fini(void *handle) 1453 { 1454 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1455 1456 if (amdgpu_sriov_vf(adev)) { 1457 /* full access mode, so don't touch any GMC register */ 1458 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 1459 return 0; 1460 } 1461 1462 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 1463 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1464 gmc_v9_0_gart_disable(adev); 1465 1466 return 0; 1467 } 1468 1469 static int gmc_v9_0_suspend(void *handle) 1470 { 1471 int r; 1472 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1473 1474 r = gmc_v9_0_hw_fini(adev); 1475 if (r) 1476 return r; 1477 1478 gmc_v9_0_save_registers(adev); 1479 1480 return 0; 1481 } 1482 1483 static int gmc_v9_0_resume(void *handle) 1484 { 1485 int r; 1486 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1487 1488 gmc_v9_0_restore_registers(adev); 1489 r = gmc_v9_0_hw_init(adev); 1490 if (r) 1491 return r; 1492 1493 amdgpu_vmid_reset_all(adev); 1494 1495 return 0; 1496 } 1497 1498 static bool gmc_v9_0_is_idle(void *handle) 1499 { 1500 /* MC is always ready in GMC v9.*/ 1501 return true; 1502 } 1503 1504 static int gmc_v9_0_wait_for_idle(void *handle) 1505 { 1506 /* There is no need to wait for MC idle in GMC v9.*/ 1507 return 0; 1508 } 1509 1510 static int gmc_v9_0_soft_reset(void *handle) 1511 { 1512 /* XXX for emulation.*/ 1513 return 0; 1514 } 1515 1516 static int gmc_v9_0_set_clockgating_state(void *handle, 1517 enum amd_clockgating_state state) 1518 { 1519 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1520 1521 if (adev->asic_type == CHIP_ARCTURUS) 1522 mmhub_v9_4_set_clockgating(adev, state); 1523 else 1524 mmhub_v1_0_set_clockgating(adev, state); 1525 1526 athub_v1_0_set_clockgating(adev, state); 1527 1528 return 0; 1529 } 1530 1531 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags) 1532 { 1533 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1534 1535 if (adev->asic_type == CHIP_ARCTURUS) 1536 mmhub_v9_4_get_clockgating(adev, flags); 1537 else 1538 mmhub_v1_0_get_clockgating(adev, flags); 1539 1540 athub_v1_0_get_clockgating(adev, flags); 1541 } 1542 1543 static int gmc_v9_0_set_powergating_state(void *handle, 1544 enum amd_powergating_state state) 1545 { 1546 return 0; 1547 } 1548 1549 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 1550 .name = "gmc_v9_0", 1551 .early_init = gmc_v9_0_early_init, 1552 .late_init = gmc_v9_0_late_init, 1553 .sw_init = gmc_v9_0_sw_init, 1554 .sw_fini = gmc_v9_0_sw_fini, 1555 .hw_init = gmc_v9_0_hw_init, 1556 .hw_fini = gmc_v9_0_hw_fini, 1557 .suspend = gmc_v9_0_suspend, 1558 .resume = gmc_v9_0_resume, 1559 .is_idle = gmc_v9_0_is_idle, 1560 .wait_for_idle = gmc_v9_0_wait_for_idle, 1561 .soft_reset = gmc_v9_0_soft_reset, 1562 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 1563 .set_powergating_state = gmc_v9_0_set_powergating_state, 1564 .get_clockgating_state = gmc_v9_0_get_clockgating_state, 1565 }; 1566 1567 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = 1568 { 1569 .type = AMD_IP_BLOCK_TYPE_GMC, 1570 .major = 9, 1571 .minor = 0, 1572 .rev = 0, 1573 .funcs = &gmc_v9_0_ip_funcs, 1574 }; 1575