1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include "drmP.h" 25 #include "amdgpu.h" 26 #include "gmc_v8_0.h" 27 #include "amdgpu_ucode.h" 28 29 #include "gmc/gmc_8_1_d.h" 30 #include "gmc/gmc_8_1_sh_mask.h" 31 32 #include "bif/bif_5_0_d.h" 33 #include "bif/bif_5_0_sh_mask.h" 34 35 #include "oss/oss_3_0_d.h" 36 #include "oss/oss_3_0_sh_mask.h" 37 38 #include "vid.h" 39 #include "vi.h" 40 41 42 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev); 43 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev); 44 static int gmc_v8_0_wait_for_idle(void *handle); 45 46 MODULE_FIRMWARE("amdgpu/tonga_mc.bin"); 47 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin"); 48 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin"); 49 MODULE_FIRMWARE("amdgpu/polaris12_mc.bin"); 50 51 static const u32 golden_settings_tonga_a11[] = 52 { 53 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, 54 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028, 55 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991, 56 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 57 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 58 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 59 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 60 }; 61 62 static const u32 tonga_mgcg_cgcg_init[] = 63 { 64 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 65 }; 66 67 static const u32 golden_settings_fiji_a10[] = 68 { 69 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 70 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 71 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 72 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 73 }; 74 75 static const u32 fiji_mgcg_cgcg_init[] = 76 { 77 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 78 }; 79 80 static const u32 golden_settings_polaris11_a11[] = 81 { 82 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 83 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 84 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 85 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 86 }; 87 88 static const u32 golden_settings_polaris10_a11[] = 89 { 90 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, 91 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 92 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 93 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 94 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 95 }; 96 97 static const u32 cz_mgcg_cgcg_init[] = 98 { 99 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 100 }; 101 102 static const u32 stoney_mgcg_cgcg_init[] = 103 { 104 mmATC_MISC_CG, 0xffffffff, 0x000c0200, 105 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 106 }; 107 108 static const u32 golden_settings_stoney_common[] = 109 { 110 mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004, 111 mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000 112 }; 113 114 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) 115 { 116 switch (adev->asic_type) { 117 case CHIP_FIJI: 118 amdgpu_program_register_sequence(adev, 119 fiji_mgcg_cgcg_init, 120 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); 121 amdgpu_program_register_sequence(adev, 122 golden_settings_fiji_a10, 123 (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); 124 break; 125 case CHIP_TONGA: 126 amdgpu_program_register_sequence(adev, 127 tonga_mgcg_cgcg_init, 128 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); 129 amdgpu_program_register_sequence(adev, 130 golden_settings_tonga_a11, 131 (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); 132 break; 133 case CHIP_POLARIS11: 134 case CHIP_POLARIS12: 135 amdgpu_program_register_sequence(adev, 136 golden_settings_polaris11_a11, 137 (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); 138 break; 139 case CHIP_POLARIS10: 140 amdgpu_program_register_sequence(adev, 141 golden_settings_polaris10_a11, 142 (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); 143 break; 144 case CHIP_CARRIZO: 145 amdgpu_program_register_sequence(adev, 146 cz_mgcg_cgcg_init, 147 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); 148 break; 149 case CHIP_STONEY: 150 amdgpu_program_register_sequence(adev, 151 stoney_mgcg_cgcg_init, 152 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); 153 amdgpu_program_register_sequence(adev, 154 golden_settings_stoney_common, 155 (const u32)ARRAY_SIZE(golden_settings_stoney_common)); 156 break; 157 default: 158 break; 159 } 160 } 161 162 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev, 163 struct amdgpu_mode_mc_save *save) 164 { 165 u32 blackout; 166 167 if (adev->mode_info.num_crtc) 168 amdgpu_display_stop_mc_access(adev, save); 169 170 gmc_v8_0_wait_for_idle(adev); 171 172 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 173 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 174 /* Block CPU access */ 175 WREG32(mmBIF_FB_EN, 0); 176 /* blackout the MC */ 177 blackout = REG_SET_FIELD(blackout, 178 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1); 179 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout); 180 } 181 /* wait for the MC to settle */ 182 udelay(100); 183 } 184 185 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev, 186 struct amdgpu_mode_mc_save *save) 187 { 188 u32 tmp; 189 190 /* unblackout the MC */ 191 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 192 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 193 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 194 /* allow CPU access */ 195 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 196 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 197 WREG32(mmBIF_FB_EN, tmp); 198 199 if (adev->mode_info.num_crtc) 200 amdgpu_display_resume_mc_access(adev, save); 201 } 202 203 /** 204 * gmc_v8_0_init_microcode - load ucode images from disk 205 * 206 * @adev: amdgpu_device pointer 207 * 208 * Use the firmware interface to load the ucode images into 209 * the driver (not loaded into hw). 210 * Returns 0 on success, error on failure. 211 */ 212 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) 213 { 214 const char *chip_name; 215 char fw_name[30]; 216 int err; 217 218 DRM_DEBUG("\n"); 219 220 switch (adev->asic_type) { 221 case CHIP_TONGA: 222 chip_name = "tonga"; 223 break; 224 case CHIP_POLARIS11: 225 chip_name = "polaris11"; 226 break; 227 case CHIP_POLARIS10: 228 chip_name = "polaris10"; 229 break; 230 case CHIP_POLARIS12: 231 chip_name = "polaris12"; 232 break; 233 case CHIP_FIJI: 234 case CHIP_CARRIZO: 235 case CHIP_STONEY: 236 return 0; 237 default: BUG(); 238 } 239 240 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name); 241 err = request_firmware(&adev->mc.fw, fw_name, adev->dev); 242 if (err) 243 goto out; 244 err = amdgpu_ucode_validate(adev->mc.fw); 245 246 out: 247 if (err) { 248 pr_err("mc: Failed to load firmware \"%s\"\n", fw_name); 249 release_firmware(adev->mc.fw); 250 adev->mc.fw = NULL; 251 } 252 return err; 253 } 254 255 /** 256 * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw 257 * 258 * @adev: amdgpu_device pointer 259 * 260 * Load the GDDR MC ucode into the hw (CIK). 261 * Returns 0 on success, error on failure. 262 */ 263 static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev) 264 { 265 const struct mc_firmware_header_v1_0 *hdr; 266 const __le32 *fw_data = NULL; 267 const __le32 *io_mc_regs = NULL; 268 u32 running; 269 int i, ucode_size, regs_size; 270 271 /* Skip MC ucode loading on SR-IOV capable boards. 272 * vbios does this for us in asic_init in that case. 273 * Skip MC ucode loading on VF, because hypervisor will do that 274 * for this adaptor. 275 */ 276 if (amdgpu_sriov_bios(adev)) 277 return 0; 278 279 if (!adev->mc.fw) 280 return -EINVAL; 281 282 hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data; 283 amdgpu_ucode_print_mc_hdr(&hdr->header); 284 285 adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version); 286 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 287 io_mc_regs = (const __le32 *) 288 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 289 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 290 fw_data = (const __le32 *) 291 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 292 293 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); 294 295 if (running == 0) { 296 /* reset the engine and set to writable */ 297 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 298 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 299 300 /* load mc io regs */ 301 for (i = 0; i < regs_size; i++) { 302 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 303 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 304 } 305 /* load the MC ucode */ 306 for (i = 0; i < ucode_size; i++) 307 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 308 309 /* put the engine back into the active state */ 310 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 311 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 312 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 313 314 /* wait for training to complete */ 315 for (i = 0; i < adev->usec_timeout; i++) { 316 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 317 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0)) 318 break; 319 udelay(1); 320 } 321 for (i = 0; i < adev->usec_timeout; i++) { 322 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 323 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1)) 324 break; 325 udelay(1); 326 } 327 } 328 329 return 0; 330 } 331 332 static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev) 333 { 334 const struct mc_firmware_header_v1_0 *hdr; 335 const __le32 *fw_data = NULL; 336 const __le32 *io_mc_regs = NULL; 337 u32 data, vbios_version; 338 int i, ucode_size, regs_size; 339 340 /* Skip MC ucode loading on SR-IOV capable boards. 341 * vbios does this for us in asic_init in that case. 342 * Skip MC ucode loading on VF, because hypervisor will do that 343 * for this adaptor. 344 */ 345 if (amdgpu_sriov_bios(adev)) 346 return 0; 347 348 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 0x9F); 349 data = RREG32(mmMC_SEQ_IO_DEBUG_DATA); 350 vbios_version = data & 0xf; 351 352 if (vbios_version == 0) 353 return 0; 354 355 if (!adev->mc.fw) 356 return -EINVAL; 357 358 hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data; 359 amdgpu_ucode_print_mc_hdr(&hdr->header); 360 361 adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version); 362 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 363 io_mc_regs = (const __le32 *) 364 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 365 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 366 fw_data = (const __le32 *) 367 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 368 369 data = RREG32(mmMC_SEQ_MISC0); 370 data &= ~(0x40); 371 WREG32(mmMC_SEQ_MISC0, data); 372 373 /* load mc io regs */ 374 for (i = 0; i < regs_size; i++) { 375 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 376 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 377 } 378 379 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 380 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 381 382 /* load the MC ucode */ 383 for (i = 0; i < ucode_size; i++) 384 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 385 386 /* put the engine back into the active state */ 387 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 388 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 389 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 390 391 /* wait for training to complete */ 392 for (i = 0; i < adev->usec_timeout; i++) { 393 data = RREG32(mmMC_SEQ_MISC0); 394 if (data & 0x80) 395 break; 396 udelay(1); 397 } 398 399 return 0; 400 } 401 402 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev, 403 struct amdgpu_mc *mc) 404 { 405 if (mc->mc_vram_size > 0xFFC0000000ULL) { 406 /* leave room for at least 1024M GTT */ 407 dev_warn(adev->dev, "limiting VRAM\n"); 408 mc->real_vram_size = 0xFFC0000000ULL; 409 mc->mc_vram_size = 0xFFC0000000ULL; 410 } 411 amdgpu_vram_location(adev, &adev->mc, 0); 412 adev->mc.gtt_base_align = 0; 413 amdgpu_gtt_location(adev, mc); 414 } 415 416 /** 417 * gmc_v8_0_mc_program - program the GPU memory controller 418 * 419 * @adev: amdgpu_device pointer 420 * 421 * Set the location of vram, gart, and AGP in the GPU's 422 * physical address space (CIK). 423 */ 424 static void gmc_v8_0_mc_program(struct amdgpu_device *adev) 425 { 426 struct amdgpu_mode_mc_save save; 427 u32 tmp; 428 int i, j; 429 430 /* Initialize HDP */ 431 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 432 WREG32((0xb05 + j), 0x00000000); 433 WREG32((0xb06 + j), 0x00000000); 434 WREG32((0xb07 + j), 0x00000000); 435 WREG32((0xb08 + j), 0x00000000); 436 WREG32((0xb09 + j), 0x00000000); 437 } 438 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 439 440 if (adev->mode_info.num_crtc) 441 amdgpu_display_set_vga_render_state(adev, false); 442 443 gmc_v8_0_mc_stop(adev, &save); 444 if (gmc_v8_0_wait_for_idle((void *)adev)) { 445 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 446 } 447 /* Update configuration */ 448 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 449 adev->mc.vram_start >> 12); 450 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 451 adev->mc.vram_end >> 12); 452 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 453 adev->vram_scratch.gpu_addr >> 12); 454 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16; 455 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF); 456 WREG32(mmMC_VM_FB_LOCATION, tmp); 457 /* XXX double check these! */ 458 WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8)); 459 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); 460 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF); 461 WREG32(mmMC_VM_AGP_BASE, 0); 462 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); 463 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); 464 if (gmc_v8_0_wait_for_idle((void *)adev)) { 465 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 466 } 467 gmc_v8_0_mc_resume(adev, &save); 468 469 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 470 471 tmp = RREG32(mmHDP_MISC_CNTL); 472 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); 473 WREG32(mmHDP_MISC_CNTL, tmp); 474 475 tmp = RREG32(mmHDP_HOST_PATH_CNTL); 476 WREG32(mmHDP_HOST_PATH_CNTL, tmp); 477 } 478 479 /** 480 * gmc_v8_0_mc_init - initialize the memory controller driver params 481 * 482 * @adev: amdgpu_device pointer 483 * 484 * Look up the amount of vram, vram width, and decide how to place 485 * vram and gart within the GPU's physical address space (CIK). 486 * Returns 0 for success. 487 */ 488 static int gmc_v8_0_mc_init(struct amdgpu_device *adev) 489 { 490 u32 tmp; 491 int chansize, numchan; 492 493 /* Get VRAM informations */ 494 tmp = RREG32(mmMC_ARB_RAMCFG); 495 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { 496 chansize = 64; 497 } else { 498 chansize = 32; 499 } 500 tmp = RREG32(mmMC_SHARED_CHMAP); 501 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 502 case 0: 503 default: 504 numchan = 1; 505 break; 506 case 1: 507 numchan = 2; 508 break; 509 case 2: 510 numchan = 4; 511 break; 512 case 3: 513 numchan = 8; 514 break; 515 case 4: 516 numchan = 3; 517 break; 518 case 5: 519 numchan = 6; 520 break; 521 case 6: 522 numchan = 10; 523 break; 524 case 7: 525 numchan = 12; 526 break; 527 case 8: 528 numchan = 16; 529 break; 530 } 531 adev->mc.vram_width = numchan * chansize; 532 /* Could aper size report 0 ? */ 533 adev->mc.aper_base = pci_resource_start(adev->pdev, 0); 534 adev->mc.aper_size = pci_resource_len(adev->pdev, 0); 535 /* size in MB on si */ 536 adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 537 adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 538 539 #ifdef CONFIG_X86_64 540 if (adev->flags & AMD_IS_APU) { 541 adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; 542 adev->mc.aper_size = adev->mc.real_vram_size; 543 } 544 #endif 545 546 /* In case the PCI BAR is larger than the actual amount of vram */ 547 adev->mc.visible_vram_size = adev->mc.aper_size; 548 if (adev->mc.visible_vram_size > adev->mc.real_vram_size) 549 adev->mc.visible_vram_size = adev->mc.real_vram_size; 550 551 /* unless the user had overridden it, set the gart 552 * size equal to the 1024 or vram, whichever is larger. 553 */ 554 if (amdgpu_gart_size == -1) 555 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size); 556 else 557 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20; 558 559 gmc_v8_0_vram_gtt_location(adev, &adev->mc); 560 561 return 0; 562 } 563 564 /* 565 * GART 566 * VMID 0 is the physical GPU addresses as used by the kernel. 567 * VMIDs 1-15 are used for userspace clients and are handled 568 * by the amdgpu vm/hsa code. 569 */ 570 571 /** 572 * gmc_v8_0_gart_flush_gpu_tlb - gart tlb flush callback 573 * 574 * @adev: amdgpu_device pointer 575 * @vmid: vm instance to flush 576 * 577 * Flush the TLB for the requested page table (CIK). 578 */ 579 static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, 580 uint32_t vmid) 581 { 582 /* flush hdp cache */ 583 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0); 584 585 /* bits 0-15 are the VM contexts0-15 */ 586 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 587 } 588 589 /** 590 * gmc_v8_0_gart_set_pte_pde - update the page tables using MMIO 591 * 592 * @adev: amdgpu_device pointer 593 * @cpu_pt_addr: cpu address of the page table 594 * @gpu_page_idx: entry in the page table to update 595 * @addr: dst addr to write into pte/pde 596 * @flags: access flags 597 * 598 * Update the page tables using the CPU. 599 */ 600 static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev, 601 void *cpu_pt_addr, 602 uint32_t gpu_page_idx, 603 uint64_t addr, 604 uint64_t flags) 605 { 606 void __iomem *ptr = (void *)cpu_pt_addr; 607 uint64_t value; 608 609 /* 610 * PTE format on VI: 611 * 63:40 reserved 612 * 39:12 4k physical page base address 613 * 11:7 fragment 614 * 6 write 615 * 5 read 616 * 4 exe 617 * 3 reserved 618 * 2 snooped 619 * 1 system 620 * 0 valid 621 * 622 * PDE format on VI: 623 * 63:59 block fragment size 624 * 58:40 reserved 625 * 39:1 physical base address of PTE 626 * bits 5:1 must be 0. 627 * 0 valid 628 */ 629 value = addr & 0x000000FFFFFFF000ULL; 630 value |= flags; 631 writeq(value, ptr + (gpu_page_idx * 8)); 632 633 return 0; 634 } 635 636 static uint64_t gmc_v8_0_get_vm_pte_flags(struct amdgpu_device *adev, 637 uint32_t flags) 638 { 639 uint64_t pte_flag = 0; 640 641 if (flags & AMDGPU_VM_PAGE_EXECUTABLE) 642 pte_flag |= AMDGPU_PTE_EXECUTABLE; 643 if (flags & AMDGPU_VM_PAGE_READABLE) 644 pte_flag |= AMDGPU_PTE_READABLE; 645 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 646 pte_flag |= AMDGPU_PTE_WRITEABLE; 647 if (flags & AMDGPU_VM_PAGE_PRT) 648 pte_flag |= AMDGPU_PTE_PRT; 649 650 return pte_flag; 651 } 652 653 /** 654 * gmc_v8_0_set_fault_enable_default - update VM fault handling 655 * 656 * @adev: amdgpu_device pointer 657 * @value: true redirects VM faults to the default page 658 */ 659 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev, 660 bool value) 661 { 662 u32 tmp; 663 664 tmp = RREG32(mmVM_CONTEXT1_CNTL); 665 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 666 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 667 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 668 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 669 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 670 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 671 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 672 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 673 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 674 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 675 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 676 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 677 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 678 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 679 WREG32(mmVM_CONTEXT1_CNTL, tmp); 680 } 681 682 /** 683 * gmc_v8_0_set_prt - set PRT VM fault 684 * 685 * @adev: amdgpu_device pointer 686 * @enable: enable/disable VM fault handling for PRT 687 */ 688 static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable) 689 { 690 u32 tmp; 691 692 if (enable && !adev->mc.prt_warning) { 693 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 694 adev->mc.prt_warning = true; 695 } 696 697 tmp = RREG32(mmVM_PRT_CNTL); 698 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 699 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 700 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 701 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 702 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 703 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 704 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 705 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 706 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 707 L2_CACHE_STORE_INVALID_ENTRIES, enable); 708 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 709 L1_TLB_STORE_INVALID_ENTRIES, enable); 710 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 711 MASK_PDE0_FAULT, enable); 712 WREG32(mmVM_PRT_CNTL, tmp); 713 714 if (enable) { 715 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; 716 uint32_t high = adev->vm_manager.max_pfn; 717 718 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); 719 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); 720 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); 721 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); 722 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); 723 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); 724 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); 725 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); 726 } else { 727 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); 728 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); 729 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); 730 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); 731 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); 732 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); 733 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); 734 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); 735 } 736 } 737 738 /** 739 * gmc_v8_0_gart_enable - gart enable 740 * 741 * @adev: amdgpu_device pointer 742 * 743 * This sets up the TLBs, programs the page tables for VMID0, 744 * sets up the hw for VMIDs 1-15 which are allocated on 745 * demand, and sets up the global locations for the LDS, GDS, 746 * and GPUVM for FSA64 clients (CIK). 747 * Returns 0 for success, errors for failure. 748 */ 749 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) 750 { 751 int r, i; 752 u32 tmp; 753 754 if (adev->gart.robj == NULL) { 755 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 756 return -EINVAL; 757 } 758 r = amdgpu_gart_table_vram_pin(adev); 759 if (r) 760 return r; 761 /* Setup TLB control */ 762 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 763 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 764 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); 765 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 766 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); 767 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 768 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 769 /* Setup L2 cache */ 770 tmp = RREG32(mmVM_L2_CNTL); 771 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 772 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 773 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); 774 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); 775 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); 776 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 777 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 778 WREG32(mmVM_L2_CNTL, tmp); 779 tmp = RREG32(mmVM_L2_CNTL2); 780 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 781 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 782 WREG32(mmVM_L2_CNTL2, tmp); 783 tmp = RREG32(mmVM_L2_CNTL3); 784 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); 785 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4); 786 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4); 787 WREG32(mmVM_L2_CNTL3, tmp); 788 /* XXX: set to enable PTE/PDE in system memory */ 789 tmp = RREG32(mmVM_L2_CNTL4); 790 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0); 791 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0); 792 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0); 793 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0); 794 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0); 795 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0); 796 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0); 797 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0); 798 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0); 799 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0); 800 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0); 801 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0); 802 WREG32(mmVM_L2_CNTL4, tmp); 803 /* setup context0 */ 804 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12); 805 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12); 806 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); 807 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 808 (u32)(adev->dummy_page.addr >> 12)); 809 WREG32(mmVM_CONTEXT0_CNTL2, 0); 810 tmp = RREG32(mmVM_CONTEXT0_CNTL); 811 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 812 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 813 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 814 WREG32(mmVM_CONTEXT0_CNTL, tmp); 815 816 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0); 817 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0); 818 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0); 819 820 /* empty context1-15 */ 821 /* FIXME start with 4G, once using 2 level pt switch to full 822 * vm size space 823 */ 824 /* set vm size, must be a multiple of 4 */ 825 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 826 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 827 for (i = 1; i < 16; i++) { 828 if (i < 8) 829 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 830 adev->gart.table_addr >> 12); 831 else 832 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 833 adev->gart.table_addr >> 12); 834 } 835 836 /* enable context1-15 */ 837 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 838 (u32)(adev->dummy_page.addr >> 12)); 839 WREG32(mmVM_CONTEXT1_CNTL2, 4); 840 tmp = RREG32(mmVM_CONTEXT1_CNTL); 841 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 842 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); 843 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 844 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 845 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 846 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 847 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 848 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 849 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 850 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, 851 amdgpu_vm_block_size - 9); 852 WREG32(mmVM_CONTEXT1_CNTL, tmp); 853 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 854 gmc_v8_0_set_fault_enable_default(adev, false); 855 else 856 gmc_v8_0_set_fault_enable_default(adev, true); 857 858 gmc_v8_0_gart_flush_gpu_tlb(adev, 0); 859 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 860 (unsigned)(adev->mc.gtt_size >> 20), 861 (unsigned long long)adev->gart.table_addr); 862 adev->gart.ready = true; 863 return 0; 864 } 865 866 static int gmc_v8_0_gart_init(struct amdgpu_device *adev) 867 { 868 int r; 869 870 if (adev->gart.robj) { 871 WARN(1, "R600 PCIE GART already initialized\n"); 872 return 0; 873 } 874 /* Initialize common gart structure */ 875 r = amdgpu_gart_init(adev); 876 if (r) 877 return r; 878 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 879 adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE; 880 return amdgpu_gart_table_vram_alloc(adev); 881 } 882 883 /** 884 * gmc_v8_0_gart_disable - gart disable 885 * 886 * @adev: amdgpu_device pointer 887 * 888 * This disables all VM page table (CIK). 889 */ 890 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev) 891 { 892 u32 tmp; 893 894 /* Disable all tables */ 895 WREG32(mmVM_CONTEXT0_CNTL, 0); 896 WREG32(mmVM_CONTEXT1_CNTL, 0); 897 /* Setup TLB control */ 898 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 899 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 900 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); 901 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); 902 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 903 /* Setup L2 cache */ 904 tmp = RREG32(mmVM_L2_CNTL); 905 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 906 WREG32(mmVM_L2_CNTL, tmp); 907 WREG32(mmVM_L2_CNTL2, 0); 908 amdgpu_gart_table_vram_unpin(adev); 909 } 910 911 /** 912 * gmc_v8_0_gart_fini - vm fini callback 913 * 914 * @adev: amdgpu_device pointer 915 * 916 * Tears down the driver GART/VM setup (CIK). 917 */ 918 static void gmc_v8_0_gart_fini(struct amdgpu_device *adev) 919 { 920 amdgpu_gart_table_vram_free(adev); 921 amdgpu_gart_fini(adev); 922 } 923 924 /* 925 * vm 926 * VMID 0 is the physical GPU addresses as used by the kernel. 927 * VMIDs 1-15 are used for userspace clients and are handled 928 * by the amdgpu vm/hsa code. 929 */ 930 /** 931 * gmc_v8_0_vm_init - cik vm init callback 932 * 933 * @adev: amdgpu_device pointer 934 * 935 * Inits cik specific vm parameters (number of VMs, base of vram for 936 * VMIDs 1-15) (CIK). 937 * Returns 0 for success. 938 */ 939 static int gmc_v8_0_vm_init(struct amdgpu_device *adev) 940 { 941 /* 942 * number of VMs 943 * VMID 0 is reserved for System 944 * amdgpu graphics/compute will use VMIDs 1-7 945 * amdkfd will use VMIDs 8-15 946 */ 947 adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS; 948 adev->vm_manager.num_level = 1; 949 amdgpu_vm_manager_init(adev); 950 951 /* base offset of vram pages */ 952 if (adev->flags & AMD_IS_APU) { 953 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 954 tmp <<= 22; 955 adev->vm_manager.vram_base_offset = tmp; 956 } else 957 adev->vm_manager.vram_base_offset = 0; 958 959 return 0; 960 } 961 962 /** 963 * gmc_v8_0_vm_fini - cik vm fini callback 964 * 965 * @adev: amdgpu_device pointer 966 * 967 * Tear down any asic specific VM setup (CIK). 968 */ 969 static void gmc_v8_0_vm_fini(struct amdgpu_device *adev) 970 { 971 } 972 973 /** 974 * gmc_v8_0_vm_decode_fault - print human readable fault info 975 * 976 * @adev: amdgpu_device pointer 977 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value 978 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value 979 * 980 * Print human readable fault information (CIK). 981 */ 982 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, 983 u32 status, u32 addr, u32 mc_client) 984 { 985 u32 mc_id; 986 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 987 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 988 PROTECTIONS); 989 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 990 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 991 992 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 993 MEMORY_CLIENT_ID); 994 995 dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 996 protections, vmid, addr, 997 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 998 MEMORY_CLIENT_RW) ? 999 "write" : "read", block, mc_client, mc_id); 1000 } 1001 1002 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type) 1003 { 1004 switch (mc_seq_vram_type) { 1005 case MC_SEQ_MISC0__MT__GDDR1: 1006 return AMDGPU_VRAM_TYPE_GDDR1; 1007 case MC_SEQ_MISC0__MT__DDR2: 1008 return AMDGPU_VRAM_TYPE_DDR2; 1009 case MC_SEQ_MISC0__MT__GDDR3: 1010 return AMDGPU_VRAM_TYPE_GDDR3; 1011 case MC_SEQ_MISC0__MT__GDDR4: 1012 return AMDGPU_VRAM_TYPE_GDDR4; 1013 case MC_SEQ_MISC0__MT__GDDR5: 1014 return AMDGPU_VRAM_TYPE_GDDR5; 1015 case MC_SEQ_MISC0__MT__HBM: 1016 return AMDGPU_VRAM_TYPE_HBM; 1017 case MC_SEQ_MISC0__MT__DDR3: 1018 return AMDGPU_VRAM_TYPE_DDR3; 1019 default: 1020 return AMDGPU_VRAM_TYPE_UNKNOWN; 1021 } 1022 } 1023 1024 static int gmc_v8_0_early_init(void *handle) 1025 { 1026 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1027 1028 gmc_v8_0_set_gart_funcs(adev); 1029 gmc_v8_0_set_irq_funcs(adev); 1030 1031 adev->mc.shared_aperture_start = 0x2000000000000000ULL; 1032 adev->mc.shared_aperture_end = 1033 adev->mc.shared_aperture_start + (4ULL << 30) - 1; 1034 adev->mc.private_aperture_start = 1035 adev->mc.shared_aperture_end + 1; 1036 adev->mc.private_aperture_end = 1037 adev->mc.private_aperture_start + (4ULL << 30) - 1; 1038 1039 return 0; 1040 } 1041 1042 static int gmc_v8_0_late_init(void *handle) 1043 { 1044 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1045 1046 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 1047 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0); 1048 else 1049 return 0; 1050 } 1051 1052 #define mmMC_SEQ_MISC0_FIJI 0xA71 1053 1054 static int gmc_v8_0_sw_init(void *handle) 1055 { 1056 int r; 1057 int dma_bits; 1058 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1059 1060 if (adev->flags & AMD_IS_APU) { 1061 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 1062 } else { 1063 u32 tmp; 1064 1065 if (adev->asic_type == CHIP_FIJI) 1066 tmp = RREG32(mmMC_SEQ_MISC0_FIJI); 1067 else 1068 tmp = RREG32(mmMC_SEQ_MISC0); 1069 tmp &= MC_SEQ_MISC0__MT__MASK; 1070 adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp); 1071 } 1072 1073 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault); 1074 if (r) 1075 return r; 1076 1077 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault); 1078 if (r) 1079 return r; 1080 1081 /* Adjust VM size here. 1082 * Currently set to 4GB ((1 << 20) 4k pages). 1083 * Max GPUVM size for cayman and SI is 40 bits. 1084 */ 1085 adev->vm_manager.max_pfn = amdgpu_vm_size << 18; 1086 1087 /* Set the internal MC address mask 1088 * This is the max address of the GPU's 1089 * internal address space. 1090 */ 1091 adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1092 1093 /* set DMA mask + need_dma32 flags. 1094 * PCIE - can handle 40-bits. 1095 * IGP - can handle 40-bits 1096 * PCI - dma32 for legacy pci gart, 40 bits on newer asics 1097 */ 1098 adev->need_dma32 = false; 1099 dma_bits = adev->need_dma32 ? 32 : 40; 1100 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 1101 if (r) { 1102 adev->need_dma32 = true; 1103 dma_bits = 32; 1104 pr_warn("amdgpu: No suitable DMA available\n"); 1105 } 1106 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 1107 if (r) { 1108 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); 1109 pr_warn("amdgpu: No coherent DMA available\n"); 1110 } 1111 1112 r = gmc_v8_0_init_microcode(adev); 1113 if (r) { 1114 DRM_ERROR("Failed to load mc firmware!\n"); 1115 return r; 1116 } 1117 1118 r = gmc_v8_0_mc_init(adev); 1119 if (r) 1120 return r; 1121 1122 /* Memory manager */ 1123 r = amdgpu_bo_init(adev); 1124 if (r) 1125 return r; 1126 1127 r = gmc_v8_0_gart_init(adev); 1128 if (r) 1129 return r; 1130 1131 if (!adev->vm_manager.enabled) { 1132 r = gmc_v8_0_vm_init(adev); 1133 if (r) { 1134 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r); 1135 return r; 1136 } 1137 adev->vm_manager.enabled = true; 1138 } 1139 1140 return r; 1141 } 1142 1143 static int gmc_v8_0_sw_fini(void *handle) 1144 { 1145 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1146 1147 if (adev->vm_manager.enabled) { 1148 amdgpu_vm_manager_fini(adev); 1149 gmc_v8_0_vm_fini(adev); 1150 adev->vm_manager.enabled = false; 1151 } 1152 gmc_v8_0_gart_fini(adev); 1153 amdgpu_gem_force_release(adev); 1154 amdgpu_bo_fini(adev); 1155 1156 return 0; 1157 } 1158 1159 static int gmc_v8_0_hw_init(void *handle) 1160 { 1161 int r; 1162 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1163 1164 gmc_v8_0_init_golden_registers(adev); 1165 1166 gmc_v8_0_mc_program(adev); 1167 1168 if (adev->asic_type == CHIP_TONGA) { 1169 r = gmc_v8_0_tonga_mc_load_microcode(adev); 1170 if (r) { 1171 DRM_ERROR("Failed to load MC firmware!\n"); 1172 return r; 1173 } 1174 } else if (adev->asic_type == CHIP_POLARIS11 || 1175 adev->asic_type == CHIP_POLARIS10 || 1176 adev->asic_type == CHIP_POLARIS12) { 1177 r = gmc_v8_0_polaris_mc_load_microcode(adev); 1178 if (r) { 1179 DRM_ERROR("Failed to load MC firmware!\n"); 1180 return r; 1181 } 1182 } 1183 1184 r = gmc_v8_0_gart_enable(adev); 1185 if (r) 1186 return r; 1187 1188 return r; 1189 } 1190 1191 static int gmc_v8_0_hw_fini(void *handle) 1192 { 1193 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1194 1195 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0); 1196 gmc_v8_0_gart_disable(adev); 1197 1198 return 0; 1199 } 1200 1201 static int gmc_v8_0_suspend(void *handle) 1202 { 1203 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1204 1205 if (adev->vm_manager.enabled) { 1206 gmc_v8_0_vm_fini(adev); 1207 adev->vm_manager.enabled = false; 1208 } 1209 gmc_v8_0_hw_fini(adev); 1210 1211 return 0; 1212 } 1213 1214 static int gmc_v8_0_resume(void *handle) 1215 { 1216 int r; 1217 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1218 1219 r = gmc_v8_0_hw_init(adev); 1220 if (r) 1221 return r; 1222 1223 if (!adev->vm_manager.enabled) { 1224 r = gmc_v8_0_vm_init(adev); 1225 if (r) { 1226 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r); 1227 return r; 1228 } 1229 adev->vm_manager.enabled = true; 1230 } 1231 1232 return r; 1233 } 1234 1235 static bool gmc_v8_0_is_idle(void *handle) 1236 { 1237 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1238 u32 tmp = RREG32(mmSRBM_STATUS); 1239 1240 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1241 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 1242 return false; 1243 1244 return true; 1245 } 1246 1247 static int gmc_v8_0_wait_for_idle(void *handle) 1248 { 1249 unsigned i; 1250 u32 tmp; 1251 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1252 1253 for (i = 0; i < adev->usec_timeout; i++) { 1254 /* read MC_STATUS */ 1255 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | 1256 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1257 SRBM_STATUS__MCC_BUSY_MASK | 1258 SRBM_STATUS__MCD_BUSY_MASK | 1259 SRBM_STATUS__VMC_BUSY_MASK | 1260 SRBM_STATUS__VMC1_BUSY_MASK); 1261 if (!tmp) 1262 return 0; 1263 udelay(1); 1264 } 1265 return -ETIMEDOUT; 1266 1267 } 1268 1269 static bool gmc_v8_0_check_soft_reset(void *handle) 1270 { 1271 u32 srbm_soft_reset = 0; 1272 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1273 u32 tmp = RREG32(mmSRBM_STATUS); 1274 1275 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1276 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1277 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 1278 1279 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1280 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 1281 if (!(adev->flags & AMD_IS_APU)) 1282 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1283 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1284 } 1285 if (srbm_soft_reset) { 1286 adev->mc.srbm_soft_reset = srbm_soft_reset; 1287 return true; 1288 } else { 1289 adev->mc.srbm_soft_reset = 0; 1290 return false; 1291 } 1292 } 1293 1294 static int gmc_v8_0_pre_soft_reset(void *handle) 1295 { 1296 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1297 1298 if (!adev->mc.srbm_soft_reset) 1299 return 0; 1300 1301 gmc_v8_0_mc_stop(adev, &adev->mc.save); 1302 if (gmc_v8_0_wait_for_idle(adev)) { 1303 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1304 } 1305 1306 return 0; 1307 } 1308 1309 static int gmc_v8_0_soft_reset(void *handle) 1310 { 1311 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1312 u32 srbm_soft_reset; 1313 1314 if (!adev->mc.srbm_soft_reset) 1315 return 0; 1316 srbm_soft_reset = adev->mc.srbm_soft_reset; 1317 1318 if (srbm_soft_reset) { 1319 u32 tmp; 1320 1321 tmp = RREG32(mmSRBM_SOFT_RESET); 1322 tmp |= srbm_soft_reset; 1323 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1324 WREG32(mmSRBM_SOFT_RESET, tmp); 1325 tmp = RREG32(mmSRBM_SOFT_RESET); 1326 1327 udelay(50); 1328 1329 tmp &= ~srbm_soft_reset; 1330 WREG32(mmSRBM_SOFT_RESET, tmp); 1331 tmp = RREG32(mmSRBM_SOFT_RESET); 1332 1333 /* Wait a little for things to settle down */ 1334 udelay(50); 1335 } 1336 1337 return 0; 1338 } 1339 1340 static int gmc_v8_0_post_soft_reset(void *handle) 1341 { 1342 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1343 1344 if (!adev->mc.srbm_soft_reset) 1345 return 0; 1346 1347 gmc_v8_0_mc_resume(adev, &adev->mc.save); 1348 return 0; 1349 } 1350 1351 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1352 struct amdgpu_irq_src *src, 1353 unsigned type, 1354 enum amdgpu_interrupt_state state) 1355 { 1356 u32 tmp; 1357 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1358 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1359 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1360 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1361 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1362 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1363 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1364 1365 switch (state) { 1366 case AMDGPU_IRQ_STATE_DISABLE: 1367 /* system context */ 1368 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1369 tmp &= ~bits; 1370 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1371 /* VMs */ 1372 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1373 tmp &= ~bits; 1374 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1375 break; 1376 case AMDGPU_IRQ_STATE_ENABLE: 1377 /* system context */ 1378 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1379 tmp |= bits; 1380 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1381 /* VMs */ 1382 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1383 tmp |= bits; 1384 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1385 break; 1386 default: 1387 break; 1388 } 1389 1390 return 0; 1391 } 1392 1393 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, 1394 struct amdgpu_irq_src *source, 1395 struct amdgpu_iv_entry *entry) 1396 { 1397 u32 addr, status, mc_client; 1398 1399 if (amdgpu_sriov_vf(adev)) { 1400 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1401 entry->src_id, entry->src_data[0]); 1402 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n"); 1403 return 0; 1404 } 1405 1406 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1407 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1408 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); 1409 /* reset addr and status */ 1410 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1411 1412 if (!addr && !status) 1413 return 0; 1414 1415 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1416 gmc_v8_0_set_fault_enable_default(adev, false); 1417 1418 if (printk_ratelimit()) { 1419 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1420 entry->src_id, entry->src_data[0]); 1421 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1422 addr); 1423 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1424 status); 1425 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client); 1426 } 1427 1428 return 0; 1429 } 1430 1431 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev, 1432 bool enable) 1433 { 1434 uint32_t data; 1435 1436 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 1437 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1438 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1439 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1440 1441 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1442 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1443 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1444 1445 data = RREG32(mmMC_HUB_MISC_VM_CG); 1446 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK; 1447 WREG32(mmMC_HUB_MISC_VM_CG, data); 1448 1449 data = RREG32(mmMC_XPB_CLK_GAT); 1450 data |= MC_XPB_CLK_GAT__ENABLE_MASK; 1451 WREG32(mmMC_XPB_CLK_GAT, data); 1452 1453 data = RREG32(mmATC_MISC_CG); 1454 data |= ATC_MISC_CG__ENABLE_MASK; 1455 WREG32(mmATC_MISC_CG, data); 1456 1457 data = RREG32(mmMC_CITF_MISC_WR_CG); 1458 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK; 1459 WREG32(mmMC_CITF_MISC_WR_CG, data); 1460 1461 data = RREG32(mmMC_CITF_MISC_RD_CG); 1462 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK; 1463 WREG32(mmMC_CITF_MISC_RD_CG, data); 1464 1465 data = RREG32(mmMC_CITF_MISC_VM_CG); 1466 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK; 1467 WREG32(mmMC_CITF_MISC_VM_CG, data); 1468 1469 data = RREG32(mmVM_L2_CG); 1470 data |= VM_L2_CG__ENABLE_MASK; 1471 WREG32(mmVM_L2_CG, data); 1472 } else { 1473 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1474 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1475 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1476 1477 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1478 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1479 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1480 1481 data = RREG32(mmMC_HUB_MISC_VM_CG); 1482 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK; 1483 WREG32(mmMC_HUB_MISC_VM_CG, data); 1484 1485 data = RREG32(mmMC_XPB_CLK_GAT); 1486 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK; 1487 WREG32(mmMC_XPB_CLK_GAT, data); 1488 1489 data = RREG32(mmATC_MISC_CG); 1490 data &= ~ATC_MISC_CG__ENABLE_MASK; 1491 WREG32(mmATC_MISC_CG, data); 1492 1493 data = RREG32(mmMC_CITF_MISC_WR_CG); 1494 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK; 1495 WREG32(mmMC_CITF_MISC_WR_CG, data); 1496 1497 data = RREG32(mmMC_CITF_MISC_RD_CG); 1498 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK; 1499 WREG32(mmMC_CITF_MISC_RD_CG, data); 1500 1501 data = RREG32(mmMC_CITF_MISC_VM_CG); 1502 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK; 1503 WREG32(mmMC_CITF_MISC_VM_CG, data); 1504 1505 data = RREG32(mmVM_L2_CG); 1506 data &= ~VM_L2_CG__ENABLE_MASK; 1507 WREG32(mmVM_L2_CG, data); 1508 } 1509 } 1510 1511 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev, 1512 bool enable) 1513 { 1514 uint32_t data; 1515 1516 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) { 1517 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1518 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1519 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1520 1521 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1522 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1523 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1524 1525 data = RREG32(mmMC_HUB_MISC_VM_CG); 1526 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1527 WREG32(mmMC_HUB_MISC_VM_CG, data); 1528 1529 data = RREG32(mmMC_XPB_CLK_GAT); 1530 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1531 WREG32(mmMC_XPB_CLK_GAT, data); 1532 1533 data = RREG32(mmATC_MISC_CG); 1534 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1535 WREG32(mmATC_MISC_CG, data); 1536 1537 data = RREG32(mmMC_CITF_MISC_WR_CG); 1538 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1539 WREG32(mmMC_CITF_MISC_WR_CG, data); 1540 1541 data = RREG32(mmMC_CITF_MISC_RD_CG); 1542 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1543 WREG32(mmMC_CITF_MISC_RD_CG, data); 1544 1545 data = RREG32(mmMC_CITF_MISC_VM_CG); 1546 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1547 WREG32(mmMC_CITF_MISC_VM_CG, data); 1548 1549 data = RREG32(mmVM_L2_CG); 1550 data |= VM_L2_CG__MEM_LS_ENABLE_MASK; 1551 WREG32(mmVM_L2_CG, data); 1552 } else { 1553 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1554 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1555 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1556 1557 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1558 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1559 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1560 1561 data = RREG32(mmMC_HUB_MISC_VM_CG); 1562 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1563 WREG32(mmMC_HUB_MISC_VM_CG, data); 1564 1565 data = RREG32(mmMC_XPB_CLK_GAT); 1566 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1567 WREG32(mmMC_XPB_CLK_GAT, data); 1568 1569 data = RREG32(mmATC_MISC_CG); 1570 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1571 WREG32(mmATC_MISC_CG, data); 1572 1573 data = RREG32(mmMC_CITF_MISC_WR_CG); 1574 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1575 WREG32(mmMC_CITF_MISC_WR_CG, data); 1576 1577 data = RREG32(mmMC_CITF_MISC_RD_CG); 1578 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1579 WREG32(mmMC_CITF_MISC_RD_CG, data); 1580 1581 data = RREG32(mmMC_CITF_MISC_VM_CG); 1582 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1583 WREG32(mmMC_CITF_MISC_VM_CG, data); 1584 1585 data = RREG32(mmVM_L2_CG); 1586 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK; 1587 WREG32(mmVM_L2_CG, data); 1588 } 1589 } 1590 1591 static int gmc_v8_0_set_clockgating_state(void *handle, 1592 enum amd_clockgating_state state) 1593 { 1594 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1595 1596 if (amdgpu_sriov_vf(adev)) 1597 return 0; 1598 1599 switch (adev->asic_type) { 1600 case CHIP_FIJI: 1601 fiji_update_mc_medium_grain_clock_gating(adev, 1602 state == AMD_CG_STATE_GATE); 1603 fiji_update_mc_light_sleep(adev, 1604 state == AMD_CG_STATE_GATE); 1605 break; 1606 default: 1607 break; 1608 } 1609 return 0; 1610 } 1611 1612 static int gmc_v8_0_set_powergating_state(void *handle, 1613 enum amd_powergating_state state) 1614 { 1615 return 0; 1616 } 1617 1618 static void gmc_v8_0_get_clockgating_state(void *handle, u32 *flags) 1619 { 1620 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1621 int data; 1622 1623 if (amdgpu_sriov_vf(adev)) 1624 *flags = 0; 1625 1626 /* AMD_CG_SUPPORT_MC_MGCG */ 1627 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1628 if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK) 1629 *flags |= AMD_CG_SUPPORT_MC_MGCG; 1630 1631 /* AMD_CG_SUPPORT_MC_LS */ 1632 if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK) 1633 *flags |= AMD_CG_SUPPORT_MC_LS; 1634 } 1635 1636 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = { 1637 .name = "gmc_v8_0", 1638 .early_init = gmc_v8_0_early_init, 1639 .late_init = gmc_v8_0_late_init, 1640 .sw_init = gmc_v8_0_sw_init, 1641 .sw_fini = gmc_v8_0_sw_fini, 1642 .hw_init = gmc_v8_0_hw_init, 1643 .hw_fini = gmc_v8_0_hw_fini, 1644 .suspend = gmc_v8_0_suspend, 1645 .resume = gmc_v8_0_resume, 1646 .is_idle = gmc_v8_0_is_idle, 1647 .wait_for_idle = gmc_v8_0_wait_for_idle, 1648 .check_soft_reset = gmc_v8_0_check_soft_reset, 1649 .pre_soft_reset = gmc_v8_0_pre_soft_reset, 1650 .soft_reset = gmc_v8_0_soft_reset, 1651 .post_soft_reset = gmc_v8_0_post_soft_reset, 1652 .set_clockgating_state = gmc_v8_0_set_clockgating_state, 1653 .set_powergating_state = gmc_v8_0_set_powergating_state, 1654 .get_clockgating_state = gmc_v8_0_get_clockgating_state, 1655 }; 1656 1657 static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = { 1658 .flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb, 1659 .set_pte_pde = gmc_v8_0_gart_set_pte_pde, 1660 .set_prt = gmc_v8_0_set_prt, 1661 .get_vm_pte_flags = gmc_v8_0_get_vm_pte_flags 1662 }; 1663 1664 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = { 1665 .set = gmc_v8_0_vm_fault_interrupt_state, 1666 .process = gmc_v8_0_process_interrupt, 1667 }; 1668 1669 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev) 1670 { 1671 if (adev->gart.gart_funcs == NULL) 1672 adev->gart.gart_funcs = &gmc_v8_0_gart_funcs; 1673 } 1674 1675 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev) 1676 { 1677 adev->mc.vm_fault.num_types = 1; 1678 adev->mc.vm_fault.funcs = &gmc_v8_0_irq_funcs; 1679 } 1680 1681 const struct amdgpu_ip_block_version gmc_v8_0_ip_block = 1682 { 1683 .type = AMD_IP_BLOCK_TYPE_GMC, 1684 .major = 8, 1685 .minor = 0, 1686 .rev = 0, 1687 .funcs = &gmc_v8_0_ip_funcs, 1688 }; 1689 1690 const struct amdgpu_ip_block_version gmc_v8_1_ip_block = 1691 { 1692 .type = AMD_IP_BLOCK_TYPE_GMC, 1693 .major = 8, 1694 .minor = 1, 1695 .rev = 0, 1696 .funcs = &gmc_v8_0_ip_funcs, 1697 }; 1698 1699 const struct amdgpu_ip_block_version gmc_v8_5_ip_block = 1700 { 1701 .type = AMD_IP_BLOCK_TYPE_GMC, 1702 .major = 8, 1703 .minor = 5, 1704 .rev = 0, 1705 .funcs = &gmc_v8_0_ip_funcs, 1706 }; 1707