1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include "drmP.h" 25 #include "amdgpu.h" 26 #include "gmc_v8_0.h" 27 #include "amdgpu_ucode.h" 28 29 #include "gmc/gmc_8_1_d.h" 30 #include "gmc/gmc_8_1_sh_mask.h" 31 32 #include "bif/bif_5_0_d.h" 33 #include "bif/bif_5_0_sh_mask.h" 34 35 #include "oss/oss_3_0_d.h" 36 #include "oss/oss_3_0_sh_mask.h" 37 38 #include "vid.h" 39 #include "vi.h" 40 41 42 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev); 43 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev); 44 static int gmc_v8_0_wait_for_idle(void *handle); 45 46 MODULE_FIRMWARE("amdgpu/tonga_mc.bin"); 47 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin"); 48 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin"); 49 MODULE_FIRMWARE("amdgpu/polaris12_mc.bin"); 50 51 static const u32 golden_settings_tonga_a11[] = 52 { 53 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, 54 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028, 55 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991, 56 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 57 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 58 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 59 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 60 }; 61 62 static const u32 tonga_mgcg_cgcg_init[] = 63 { 64 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 65 }; 66 67 static const u32 golden_settings_fiji_a10[] = 68 { 69 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 70 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 71 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 72 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 73 }; 74 75 static const u32 fiji_mgcg_cgcg_init[] = 76 { 77 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 78 }; 79 80 static const u32 golden_settings_polaris11_a11[] = 81 { 82 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 83 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 84 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 85 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 86 }; 87 88 static const u32 golden_settings_polaris10_a11[] = 89 { 90 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, 91 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 92 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 93 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 94 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 95 }; 96 97 static const u32 cz_mgcg_cgcg_init[] = 98 { 99 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 100 }; 101 102 static const u32 stoney_mgcg_cgcg_init[] = 103 { 104 mmATC_MISC_CG, 0xffffffff, 0x000c0200, 105 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 106 }; 107 108 static const u32 golden_settings_stoney_common[] = 109 { 110 mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004, 111 mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000 112 }; 113 114 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) 115 { 116 switch (adev->asic_type) { 117 case CHIP_FIJI: 118 amdgpu_program_register_sequence(adev, 119 fiji_mgcg_cgcg_init, 120 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); 121 amdgpu_program_register_sequence(adev, 122 golden_settings_fiji_a10, 123 (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); 124 break; 125 case CHIP_TONGA: 126 amdgpu_program_register_sequence(adev, 127 tonga_mgcg_cgcg_init, 128 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); 129 amdgpu_program_register_sequence(adev, 130 golden_settings_tonga_a11, 131 (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); 132 break; 133 case CHIP_POLARIS11: 134 case CHIP_POLARIS12: 135 amdgpu_program_register_sequence(adev, 136 golden_settings_polaris11_a11, 137 (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); 138 break; 139 case CHIP_POLARIS10: 140 amdgpu_program_register_sequence(adev, 141 golden_settings_polaris10_a11, 142 (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); 143 break; 144 case CHIP_CARRIZO: 145 amdgpu_program_register_sequence(adev, 146 cz_mgcg_cgcg_init, 147 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); 148 break; 149 case CHIP_STONEY: 150 amdgpu_program_register_sequence(adev, 151 stoney_mgcg_cgcg_init, 152 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); 153 amdgpu_program_register_sequence(adev, 154 golden_settings_stoney_common, 155 (const u32)ARRAY_SIZE(golden_settings_stoney_common)); 156 break; 157 default: 158 break; 159 } 160 } 161 162 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev, 163 struct amdgpu_mode_mc_save *save) 164 { 165 u32 blackout; 166 167 if (adev->mode_info.num_crtc) 168 amdgpu_display_stop_mc_access(adev, save); 169 170 gmc_v8_0_wait_for_idle(adev); 171 172 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 173 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 174 /* Block CPU access */ 175 WREG32(mmBIF_FB_EN, 0); 176 /* blackout the MC */ 177 blackout = REG_SET_FIELD(blackout, 178 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1); 179 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout); 180 } 181 /* wait for the MC to settle */ 182 udelay(100); 183 } 184 185 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev, 186 struct amdgpu_mode_mc_save *save) 187 { 188 u32 tmp; 189 190 /* unblackout the MC */ 191 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 192 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 193 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 194 /* allow CPU access */ 195 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 196 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 197 WREG32(mmBIF_FB_EN, tmp); 198 199 if (adev->mode_info.num_crtc) 200 amdgpu_display_resume_mc_access(adev, save); 201 } 202 203 /** 204 * gmc_v8_0_init_microcode - load ucode images from disk 205 * 206 * @adev: amdgpu_device pointer 207 * 208 * Use the firmware interface to load the ucode images into 209 * the driver (not loaded into hw). 210 * Returns 0 on success, error on failure. 211 */ 212 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) 213 { 214 const char *chip_name; 215 char fw_name[30]; 216 int err; 217 218 DRM_DEBUG("\n"); 219 220 switch (adev->asic_type) { 221 case CHIP_TONGA: 222 chip_name = "tonga"; 223 break; 224 case CHIP_POLARIS11: 225 chip_name = "polaris11"; 226 break; 227 case CHIP_POLARIS10: 228 chip_name = "polaris10"; 229 break; 230 case CHIP_POLARIS12: 231 chip_name = "polaris12"; 232 break; 233 case CHIP_FIJI: 234 case CHIP_CARRIZO: 235 case CHIP_STONEY: 236 return 0; 237 default: BUG(); 238 } 239 240 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name); 241 err = request_firmware(&adev->mc.fw, fw_name, adev->dev); 242 if (err) 243 goto out; 244 err = amdgpu_ucode_validate(adev->mc.fw); 245 246 out: 247 if (err) { 248 printk(KERN_ERR 249 "mc: Failed to load firmware \"%s\"\n", 250 fw_name); 251 release_firmware(adev->mc.fw); 252 adev->mc.fw = NULL; 253 } 254 return err; 255 } 256 257 /** 258 * gmc_v8_0_mc_load_microcode - load MC ucode into the hw 259 * 260 * @adev: amdgpu_device pointer 261 * 262 * Load the GDDR MC ucode into the hw (CIK). 263 * Returns 0 on success, error on failure. 264 */ 265 static int gmc_v8_0_mc_load_microcode(struct amdgpu_device *adev) 266 { 267 const struct mc_firmware_header_v1_0 *hdr; 268 const __le32 *fw_data = NULL; 269 const __le32 *io_mc_regs = NULL; 270 u32 running; 271 int i, ucode_size, regs_size; 272 273 if (!adev->mc.fw) 274 return -EINVAL; 275 276 /* Skip MC ucode loading on SR-IOV capable boards. 277 * vbios does this for us in asic_init in that case. 278 * Skip MC ucode loading on VF, because hypervisor will do that 279 * for this adaptor. 280 */ 281 if (amdgpu_sriov_bios(adev)) 282 return 0; 283 284 hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data; 285 amdgpu_ucode_print_mc_hdr(&hdr->header); 286 287 adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version); 288 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 289 io_mc_regs = (const __le32 *) 290 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 291 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 292 fw_data = (const __le32 *) 293 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 294 295 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); 296 297 if (running == 0) { 298 /* reset the engine and set to writable */ 299 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 300 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 301 302 /* load mc io regs */ 303 for (i = 0; i < regs_size; i++) { 304 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 305 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 306 } 307 /* load the MC ucode */ 308 for (i = 0; i < ucode_size; i++) 309 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 310 311 /* put the engine back into the active state */ 312 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 313 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 314 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 315 316 /* wait for training to complete */ 317 for (i = 0; i < adev->usec_timeout; i++) { 318 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 319 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0)) 320 break; 321 udelay(1); 322 } 323 for (i = 0; i < adev->usec_timeout; i++) { 324 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 325 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1)) 326 break; 327 udelay(1); 328 } 329 } 330 331 return 0; 332 } 333 334 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev, 335 struct amdgpu_mc *mc) 336 { 337 if (mc->mc_vram_size > 0xFFC0000000ULL) { 338 /* leave room for at least 1024M GTT */ 339 dev_warn(adev->dev, "limiting VRAM\n"); 340 mc->real_vram_size = 0xFFC0000000ULL; 341 mc->mc_vram_size = 0xFFC0000000ULL; 342 } 343 amdgpu_vram_location(adev, &adev->mc, 0); 344 adev->mc.gtt_base_align = 0; 345 amdgpu_gtt_location(adev, mc); 346 } 347 348 /** 349 * gmc_v8_0_mc_program - program the GPU memory controller 350 * 351 * @adev: amdgpu_device pointer 352 * 353 * Set the location of vram, gart, and AGP in the GPU's 354 * physical address space (CIK). 355 */ 356 static void gmc_v8_0_mc_program(struct amdgpu_device *adev) 357 { 358 struct amdgpu_mode_mc_save save; 359 u32 tmp; 360 int i, j; 361 362 /* Initialize HDP */ 363 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 364 WREG32((0xb05 + j), 0x00000000); 365 WREG32((0xb06 + j), 0x00000000); 366 WREG32((0xb07 + j), 0x00000000); 367 WREG32((0xb08 + j), 0x00000000); 368 WREG32((0xb09 + j), 0x00000000); 369 } 370 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 371 372 if (adev->mode_info.num_crtc) 373 amdgpu_display_set_vga_render_state(adev, false); 374 375 gmc_v8_0_mc_stop(adev, &save); 376 if (gmc_v8_0_wait_for_idle((void *)adev)) { 377 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 378 } 379 /* Update configuration */ 380 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 381 adev->mc.vram_start >> 12); 382 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 383 adev->mc.vram_end >> 12); 384 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 385 adev->vram_scratch.gpu_addr >> 12); 386 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16; 387 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF); 388 WREG32(mmMC_VM_FB_LOCATION, tmp); 389 /* XXX double check these! */ 390 WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8)); 391 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); 392 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF); 393 WREG32(mmMC_VM_AGP_BASE, 0); 394 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); 395 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); 396 if (gmc_v8_0_wait_for_idle((void *)adev)) { 397 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 398 } 399 gmc_v8_0_mc_resume(adev, &save); 400 401 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 402 403 tmp = RREG32(mmHDP_MISC_CNTL); 404 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); 405 WREG32(mmHDP_MISC_CNTL, tmp); 406 407 tmp = RREG32(mmHDP_HOST_PATH_CNTL); 408 WREG32(mmHDP_HOST_PATH_CNTL, tmp); 409 } 410 411 /** 412 * gmc_v8_0_mc_init - initialize the memory controller driver params 413 * 414 * @adev: amdgpu_device pointer 415 * 416 * Look up the amount of vram, vram width, and decide how to place 417 * vram and gart within the GPU's physical address space (CIK). 418 * Returns 0 for success. 419 */ 420 static int gmc_v8_0_mc_init(struct amdgpu_device *adev) 421 { 422 u32 tmp; 423 int chansize, numchan; 424 425 /* Get VRAM informations */ 426 tmp = RREG32(mmMC_ARB_RAMCFG); 427 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { 428 chansize = 64; 429 } else { 430 chansize = 32; 431 } 432 tmp = RREG32(mmMC_SHARED_CHMAP); 433 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 434 case 0: 435 default: 436 numchan = 1; 437 break; 438 case 1: 439 numchan = 2; 440 break; 441 case 2: 442 numchan = 4; 443 break; 444 case 3: 445 numchan = 8; 446 break; 447 case 4: 448 numchan = 3; 449 break; 450 case 5: 451 numchan = 6; 452 break; 453 case 6: 454 numchan = 10; 455 break; 456 case 7: 457 numchan = 12; 458 break; 459 case 8: 460 numchan = 16; 461 break; 462 } 463 adev->mc.vram_width = numchan * chansize; 464 /* Could aper size report 0 ? */ 465 adev->mc.aper_base = pci_resource_start(adev->pdev, 0); 466 adev->mc.aper_size = pci_resource_len(adev->pdev, 0); 467 /* size in MB on si */ 468 adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 469 adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 470 471 #ifdef CONFIG_X86_64 472 if (adev->flags & AMD_IS_APU) { 473 adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; 474 adev->mc.aper_size = adev->mc.real_vram_size; 475 } 476 #endif 477 478 /* In case the PCI BAR is larger than the actual amount of vram */ 479 adev->mc.visible_vram_size = adev->mc.aper_size; 480 if (adev->mc.visible_vram_size > adev->mc.real_vram_size) 481 adev->mc.visible_vram_size = adev->mc.real_vram_size; 482 483 /* unless the user had overridden it, set the gart 484 * size equal to the 1024 or vram, whichever is larger. 485 */ 486 if (amdgpu_gart_size == -1) 487 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size); 488 else 489 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20; 490 491 gmc_v8_0_vram_gtt_location(adev, &adev->mc); 492 493 return 0; 494 } 495 496 /* 497 * GART 498 * VMID 0 is the physical GPU addresses as used by the kernel. 499 * VMIDs 1-15 are used for userspace clients and are handled 500 * by the amdgpu vm/hsa code. 501 */ 502 503 /** 504 * gmc_v8_0_gart_flush_gpu_tlb - gart tlb flush callback 505 * 506 * @adev: amdgpu_device pointer 507 * @vmid: vm instance to flush 508 * 509 * Flush the TLB for the requested page table (CIK). 510 */ 511 static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, 512 uint32_t vmid) 513 { 514 /* flush hdp cache */ 515 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0); 516 517 /* bits 0-15 are the VM contexts0-15 */ 518 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 519 } 520 521 /** 522 * gmc_v8_0_gart_set_pte_pde - update the page tables using MMIO 523 * 524 * @adev: amdgpu_device pointer 525 * @cpu_pt_addr: cpu address of the page table 526 * @gpu_page_idx: entry in the page table to update 527 * @addr: dst addr to write into pte/pde 528 * @flags: access flags 529 * 530 * Update the page tables using the CPU. 531 */ 532 static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev, 533 void *cpu_pt_addr, 534 uint32_t gpu_page_idx, 535 uint64_t addr, 536 uint32_t flags) 537 { 538 void __iomem *ptr = (void *)cpu_pt_addr; 539 uint64_t value; 540 541 /* 542 * PTE format on VI: 543 * 63:40 reserved 544 * 39:12 4k physical page base address 545 * 11:7 fragment 546 * 6 write 547 * 5 read 548 * 4 exe 549 * 3 reserved 550 * 2 snooped 551 * 1 system 552 * 0 valid 553 * 554 * PDE format on VI: 555 * 63:59 block fragment size 556 * 58:40 reserved 557 * 39:1 physical base address of PTE 558 * bits 5:1 must be 0. 559 * 0 valid 560 */ 561 value = addr & 0x000000FFFFFFF000ULL; 562 value |= flags; 563 writeq(value, ptr + (gpu_page_idx * 8)); 564 565 return 0; 566 } 567 568 /** 569 * gmc_v8_0_set_fault_enable_default - update VM fault handling 570 * 571 * @adev: amdgpu_device pointer 572 * @value: true redirects VM faults to the default page 573 */ 574 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev, 575 bool value) 576 { 577 u32 tmp; 578 579 tmp = RREG32(mmVM_CONTEXT1_CNTL); 580 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 581 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 582 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 583 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 584 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 585 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 586 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 587 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 588 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 589 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 590 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 591 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 592 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 593 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 594 WREG32(mmVM_CONTEXT1_CNTL, tmp); 595 } 596 597 /** 598 * gmc_v8_0_gart_enable - gart enable 599 * 600 * @adev: amdgpu_device pointer 601 * 602 * This sets up the TLBs, programs the page tables for VMID0, 603 * sets up the hw for VMIDs 1-15 which are allocated on 604 * demand, and sets up the global locations for the LDS, GDS, 605 * and GPUVM for FSA64 clients (CIK). 606 * Returns 0 for success, errors for failure. 607 */ 608 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) 609 { 610 int r, i; 611 u32 tmp; 612 613 if (adev->gart.robj == NULL) { 614 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 615 return -EINVAL; 616 } 617 r = amdgpu_gart_table_vram_pin(adev); 618 if (r) 619 return r; 620 /* Setup TLB control */ 621 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 622 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 623 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); 624 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 625 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); 626 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 627 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 628 /* Setup L2 cache */ 629 tmp = RREG32(mmVM_L2_CNTL); 630 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 631 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 632 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); 633 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); 634 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); 635 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 636 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 637 WREG32(mmVM_L2_CNTL, tmp); 638 tmp = RREG32(mmVM_L2_CNTL2); 639 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 640 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 641 WREG32(mmVM_L2_CNTL2, tmp); 642 tmp = RREG32(mmVM_L2_CNTL3); 643 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); 644 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4); 645 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4); 646 WREG32(mmVM_L2_CNTL3, tmp); 647 /* XXX: set to enable PTE/PDE in system memory */ 648 tmp = RREG32(mmVM_L2_CNTL4); 649 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0); 650 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0); 651 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0); 652 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0); 653 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0); 654 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0); 655 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0); 656 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0); 657 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0); 658 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0); 659 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0); 660 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0); 661 WREG32(mmVM_L2_CNTL4, tmp); 662 /* setup context0 */ 663 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12); 664 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12); 665 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); 666 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 667 (u32)(adev->dummy_page.addr >> 12)); 668 WREG32(mmVM_CONTEXT0_CNTL2, 0); 669 tmp = RREG32(mmVM_CONTEXT0_CNTL); 670 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 671 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 672 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 673 WREG32(mmVM_CONTEXT0_CNTL, tmp); 674 675 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0); 676 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0); 677 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0); 678 679 /* empty context1-15 */ 680 /* FIXME start with 4G, once using 2 level pt switch to full 681 * vm size space 682 */ 683 /* set vm size, must be a multiple of 4 */ 684 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 685 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 686 for (i = 1; i < 16; i++) { 687 if (i < 8) 688 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 689 adev->gart.table_addr >> 12); 690 else 691 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 692 adev->gart.table_addr >> 12); 693 } 694 695 /* enable context1-15 */ 696 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 697 (u32)(adev->dummy_page.addr >> 12)); 698 WREG32(mmVM_CONTEXT1_CNTL2, 4); 699 tmp = RREG32(mmVM_CONTEXT1_CNTL); 700 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 701 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); 702 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 703 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 704 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 705 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 706 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 707 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 708 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 709 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, 710 amdgpu_vm_block_size - 9); 711 WREG32(mmVM_CONTEXT1_CNTL, tmp); 712 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 713 gmc_v8_0_set_fault_enable_default(adev, false); 714 else 715 gmc_v8_0_set_fault_enable_default(adev, true); 716 717 gmc_v8_0_gart_flush_gpu_tlb(adev, 0); 718 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 719 (unsigned)(adev->mc.gtt_size >> 20), 720 (unsigned long long)adev->gart.table_addr); 721 adev->gart.ready = true; 722 return 0; 723 } 724 725 static int gmc_v8_0_gart_init(struct amdgpu_device *adev) 726 { 727 int r; 728 729 if (adev->gart.robj) { 730 WARN(1, "R600 PCIE GART already initialized\n"); 731 return 0; 732 } 733 /* Initialize common gart structure */ 734 r = amdgpu_gart_init(adev); 735 if (r) 736 return r; 737 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 738 return amdgpu_gart_table_vram_alloc(adev); 739 } 740 741 /** 742 * gmc_v8_0_gart_disable - gart disable 743 * 744 * @adev: amdgpu_device pointer 745 * 746 * This disables all VM page table (CIK). 747 */ 748 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev) 749 { 750 u32 tmp; 751 752 /* Disable all tables */ 753 WREG32(mmVM_CONTEXT0_CNTL, 0); 754 WREG32(mmVM_CONTEXT1_CNTL, 0); 755 /* Setup TLB control */ 756 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 757 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 758 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); 759 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); 760 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 761 /* Setup L2 cache */ 762 tmp = RREG32(mmVM_L2_CNTL); 763 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 764 WREG32(mmVM_L2_CNTL, tmp); 765 WREG32(mmVM_L2_CNTL2, 0); 766 amdgpu_gart_table_vram_unpin(adev); 767 } 768 769 /** 770 * gmc_v8_0_gart_fini - vm fini callback 771 * 772 * @adev: amdgpu_device pointer 773 * 774 * Tears down the driver GART/VM setup (CIK). 775 */ 776 static void gmc_v8_0_gart_fini(struct amdgpu_device *adev) 777 { 778 amdgpu_gart_table_vram_free(adev); 779 amdgpu_gart_fini(adev); 780 } 781 782 /* 783 * vm 784 * VMID 0 is the physical GPU addresses as used by the kernel. 785 * VMIDs 1-15 are used for userspace clients and are handled 786 * by the amdgpu vm/hsa code. 787 */ 788 /** 789 * gmc_v8_0_vm_init - cik vm init callback 790 * 791 * @adev: amdgpu_device pointer 792 * 793 * Inits cik specific vm parameters (number of VMs, base of vram for 794 * VMIDs 1-15) (CIK). 795 * Returns 0 for success. 796 */ 797 static int gmc_v8_0_vm_init(struct amdgpu_device *adev) 798 { 799 /* 800 * number of VMs 801 * VMID 0 is reserved for System 802 * amdgpu graphics/compute will use VMIDs 1-7 803 * amdkfd will use VMIDs 8-15 804 */ 805 adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS; 806 amdgpu_vm_manager_init(adev); 807 808 /* base offset of vram pages */ 809 if (adev->flags & AMD_IS_APU) { 810 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 811 tmp <<= 22; 812 adev->vm_manager.vram_base_offset = tmp; 813 } else 814 adev->vm_manager.vram_base_offset = 0; 815 816 return 0; 817 } 818 819 /** 820 * gmc_v8_0_vm_fini - cik vm fini callback 821 * 822 * @adev: amdgpu_device pointer 823 * 824 * Tear down any asic specific VM setup (CIK). 825 */ 826 static void gmc_v8_0_vm_fini(struct amdgpu_device *adev) 827 { 828 } 829 830 /** 831 * gmc_v8_0_vm_decode_fault - print human readable fault info 832 * 833 * @adev: amdgpu_device pointer 834 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value 835 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value 836 * 837 * Print human readable fault information (CIK). 838 */ 839 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, 840 u32 status, u32 addr, u32 mc_client) 841 { 842 u32 mc_id; 843 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 844 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 845 PROTECTIONS); 846 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 847 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 848 849 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 850 MEMORY_CLIENT_ID); 851 852 dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 853 protections, vmid, addr, 854 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 855 MEMORY_CLIENT_RW) ? 856 "write" : "read", block, mc_client, mc_id); 857 } 858 859 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type) 860 { 861 switch (mc_seq_vram_type) { 862 case MC_SEQ_MISC0__MT__GDDR1: 863 return AMDGPU_VRAM_TYPE_GDDR1; 864 case MC_SEQ_MISC0__MT__DDR2: 865 return AMDGPU_VRAM_TYPE_DDR2; 866 case MC_SEQ_MISC0__MT__GDDR3: 867 return AMDGPU_VRAM_TYPE_GDDR3; 868 case MC_SEQ_MISC0__MT__GDDR4: 869 return AMDGPU_VRAM_TYPE_GDDR4; 870 case MC_SEQ_MISC0__MT__GDDR5: 871 return AMDGPU_VRAM_TYPE_GDDR5; 872 case MC_SEQ_MISC0__MT__HBM: 873 return AMDGPU_VRAM_TYPE_HBM; 874 case MC_SEQ_MISC0__MT__DDR3: 875 return AMDGPU_VRAM_TYPE_DDR3; 876 default: 877 return AMDGPU_VRAM_TYPE_UNKNOWN; 878 } 879 } 880 881 static int gmc_v8_0_early_init(void *handle) 882 { 883 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 884 885 gmc_v8_0_set_gart_funcs(adev); 886 gmc_v8_0_set_irq_funcs(adev); 887 888 return 0; 889 } 890 891 static int gmc_v8_0_late_init(void *handle) 892 { 893 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 894 895 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 896 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0); 897 else 898 return 0; 899 } 900 901 #define mmMC_SEQ_MISC0_FIJI 0xA71 902 903 static int gmc_v8_0_sw_init(void *handle) 904 { 905 int r; 906 int dma_bits; 907 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 908 909 if (adev->flags & AMD_IS_APU) { 910 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 911 } else { 912 u32 tmp; 913 914 if (adev->asic_type == CHIP_FIJI) 915 tmp = RREG32(mmMC_SEQ_MISC0_FIJI); 916 else 917 tmp = RREG32(mmMC_SEQ_MISC0); 918 tmp &= MC_SEQ_MISC0__MT__MASK; 919 adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp); 920 } 921 922 r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault); 923 if (r) 924 return r; 925 926 r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault); 927 if (r) 928 return r; 929 930 /* Adjust VM size here. 931 * Currently set to 4GB ((1 << 20) 4k pages). 932 * Max GPUVM size for cayman and SI is 40 bits. 933 */ 934 adev->vm_manager.max_pfn = amdgpu_vm_size << 18; 935 936 /* Set the internal MC address mask 937 * This is the max address of the GPU's 938 * internal address space. 939 */ 940 adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 941 942 /* set DMA mask + need_dma32 flags. 943 * PCIE - can handle 40-bits. 944 * IGP - can handle 40-bits 945 * PCI - dma32 for legacy pci gart, 40 bits on newer asics 946 */ 947 adev->need_dma32 = false; 948 dma_bits = adev->need_dma32 ? 32 : 40; 949 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 950 if (r) { 951 adev->need_dma32 = true; 952 dma_bits = 32; 953 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 954 } 955 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 956 if (r) { 957 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); 958 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n"); 959 } 960 961 r = gmc_v8_0_init_microcode(adev); 962 if (r) { 963 DRM_ERROR("Failed to load mc firmware!\n"); 964 return r; 965 } 966 967 r = gmc_v8_0_mc_init(adev); 968 if (r) 969 return r; 970 971 /* Memory manager */ 972 r = amdgpu_bo_init(adev); 973 if (r) 974 return r; 975 976 r = gmc_v8_0_gart_init(adev); 977 if (r) 978 return r; 979 980 if (!adev->vm_manager.enabled) { 981 r = gmc_v8_0_vm_init(adev); 982 if (r) { 983 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r); 984 return r; 985 } 986 adev->vm_manager.enabled = true; 987 } 988 989 return r; 990 } 991 992 static int gmc_v8_0_sw_fini(void *handle) 993 { 994 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 995 996 if (adev->vm_manager.enabled) { 997 amdgpu_vm_manager_fini(adev); 998 gmc_v8_0_vm_fini(adev); 999 adev->vm_manager.enabled = false; 1000 } 1001 gmc_v8_0_gart_fini(adev); 1002 amdgpu_gem_force_release(adev); 1003 amdgpu_bo_fini(adev); 1004 1005 return 0; 1006 } 1007 1008 static int gmc_v8_0_hw_init(void *handle) 1009 { 1010 int r; 1011 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1012 1013 gmc_v8_0_init_golden_registers(adev); 1014 1015 gmc_v8_0_mc_program(adev); 1016 1017 if (adev->asic_type == CHIP_TONGA) { 1018 r = gmc_v8_0_mc_load_microcode(adev); 1019 if (r) { 1020 DRM_ERROR("Failed to load MC firmware!\n"); 1021 return r; 1022 } 1023 } 1024 1025 r = gmc_v8_0_gart_enable(adev); 1026 if (r) 1027 return r; 1028 1029 return r; 1030 } 1031 1032 static int gmc_v8_0_hw_fini(void *handle) 1033 { 1034 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1035 1036 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0); 1037 gmc_v8_0_gart_disable(adev); 1038 1039 return 0; 1040 } 1041 1042 static int gmc_v8_0_suspend(void *handle) 1043 { 1044 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1045 1046 if (adev->vm_manager.enabled) { 1047 gmc_v8_0_vm_fini(adev); 1048 adev->vm_manager.enabled = false; 1049 } 1050 gmc_v8_0_hw_fini(adev); 1051 1052 return 0; 1053 } 1054 1055 static int gmc_v8_0_resume(void *handle) 1056 { 1057 int r; 1058 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1059 1060 r = gmc_v8_0_hw_init(adev); 1061 if (r) 1062 return r; 1063 1064 if (!adev->vm_manager.enabled) { 1065 r = gmc_v8_0_vm_init(adev); 1066 if (r) { 1067 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r); 1068 return r; 1069 } 1070 adev->vm_manager.enabled = true; 1071 } 1072 1073 return r; 1074 } 1075 1076 static bool gmc_v8_0_is_idle(void *handle) 1077 { 1078 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1079 u32 tmp = RREG32(mmSRBM_STATUS); 1080 1081 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1082 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 1083 return false; 1084 1085 return true; 1086 } 1087 1088 static int gmc_v8_0_wait_for_idle(void *handle) 1089 { 1090 unsigned i; 1091 u32 tmp; 1092 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1093 1094 for (i = 0; i < adev->usec_timeout; i++) { 1095 /* read MC_STATUS */ 1096 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | 1097 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1098 SRBM_STATUS__MCC_BUSY_MASK | 1099 SRBM_STATUS__MCD_BUSY_MASK | 1100 SRBM_STATUS__VMC_BUSY_MASK | 1101 SRBM_STATUS__VMC1_BUSY_MASK); 1102 if (!tmp) 1103 return 0; 1104 udelay(1); 1105 } 1106 return -ETIMEDOUT; 1107 1108 } 1109 1110 static bool gmc_v8_0_check_soft_reset(void *handle) 1111 { 1112 u32 srbm_soft_reset = 0; 1113 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1114 u32 tmp = RREG32(mmSRBM_STATUS); 1115 1116 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1117 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1118 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 1119 1120 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1121 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 1122 if (!(adev->flags & AMD_IS_APU)) 1123 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1124 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1125 } 1126 if (srbm_soft_reset) { 1127 adev->mc.srbm_soft_reset = srbm_soft_reset; 1128 return true; 1129 } else { 1130 adev->mc.srbm_soft_reset = 0; 1131 return false; 1132 } 1133 } 1134 1135 static int gmc_v8_0_pre_soft_reset(void *handle) 1136 { 1137 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1138 1139 if (!adev->mc.srbm_soft_reset) 1140 return 0; 1141 1142 gmc_v8_0_mc_stop(adev, &adev->mc.save); 1143 if (gmc_v8_0_wait_for_idle(adev)) { 1144 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1145 } 1146 1147 return 0; 1148 } 1149 1150 static int gmc_v8_0_soft_reset(void *handle) 1151 { 1152 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1153 u32 srbm_soft_reset; 1154 1155 if (!adev->mc.srbm_soft_reset) 1156 return 0; 1157 srbm_soft_reset = adev->mc.srbm_soft_reset; 1158 1159 if (srbm_soft_reset) { 1160 u32 tmp; 1161 1162 tmp = RREG32(mmSRBM_SOFT_RESET); 1163 tmp |= srbm_soft_reset; 1164 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1165 WREG32(mmSRBM_SOFT_RESET, tmp); 1166 tmp = RREG32(mmSRBM_SOFT_RESET); 1167 1168 udelay(50); 1169 1170 tmp &= ~srbm_soft_reset; 1171 WREG32(mmSRBM_SOFT_RESET, tmp); 1172 tmp = RREG32(mmSRBM_SOFT_RESET); 1173 1174 /* Wait a little for things to settle down */ 1175 udelay(50); 1176 } 1177 1178 return 0; 1179 } 1180 1181 static int gmc_v8_0_post_soft_reset(void *handle) 1182 { 1183 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1184 1185 if (!adev->mc.srbm_soft_reset) 1186 return 0; 1187 1188 gmc_v8_0_mc_resume(adev, &adev->mc.save); 1189 return 0; 1190 } 1191 1192 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1193 struct amdgpu_irq_src *src, 1194 unsigned type, 1195 enum amdgpu_interrupt_state state) 1196 { 1197 u32 tmp; 1198 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1199 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1200 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1201 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1202 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1203 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1204 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1205 1206 switch (state) { 1207 case AMDGPU_IRQ_STATE_DISABLE: 1208 /* system context */ 1209 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1210 tmp &= ~bits; 1211 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1212 /* VMs */ 1213 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1214 tmp &= ~bits; 1215 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1216 break; 1217 case AMDGPU_IRQ_STATE_ENABLE: 1218 /* system context */ 1219 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1220 tmp |= bits; 1221 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1222 /* VMs */ 1223 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1224 tmp |= bits; 1225 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1226 break; 1227 default: 1228 break; 1229 } 1230 1231 return 0; 1232 } 1233 1234 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, 1235 struct amdgpu_irq_src *source, 1236 struct amdgpu_iv_entry *entry) 1237 { 1238 u32 addr, status, mc_client; 1239 1240 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1241 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1242 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); 1243 /* reset addr and status */ 1244 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1245 1246 if (!addr && !status) 1247 return 0; 1248 1249 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1250 gmc_v8_0_set_fault_enable_default(adev, false); 1251 1252 if (printk_ratelimit()) { 1253 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1254 entry->src_id, entry->src_data); 1255 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1256 addr); 1257 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1258 status); 1259 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client); 1260 } 1261 1262 return 0; 1263 } 1264 1265 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev, 1266 bool enable) 1267 { 1268 uint32_t data; 1269 1270 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 1271 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1272 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1273 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1274 1275 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1276 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1277 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1278 1279 data = RREG32(mmMC_HUB_MISC_VM_CG); 1280 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK; 1281 WREG32(mmMC_HUB_MISC_VM_CG, data); 1282 1283 data = RREG32(mmMC_XPB_CLK_GAT); 1284 data |= MC_XPB_CLK_GAT__ENABLE_MASK; 1285 WREG32(mmMC_XPB_CLK_GAT, data); 1286 1287 data = RREG32(mmATC_MISC_CG); 1288 data |= ATC_MISC_CG__ENABLE_MASK; 1289 WREG32(mmATC_MISC_CG, data); 1290 1291 data = RREG32(mmMC_CITF_MISC_WR_CG); 1292 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK; 1293 WREG32(mmMC_CITF_MISC_WR_CG, data); 1294 1295 data = RREG32(mmMC_CITF_MISC_RD_CG); 1296 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK; 1297 WREG32(mmMC_CITF_MISC_RD_CG, data); 1298 1299 data = RREG32(mmMC_CITF_MISC_VM_CG); 1300 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK; 1301 WREG32(mmMC_CITF_MISC_VM_CG, data); 1302 1303 data = RREG32(mmVM_L2_CG); 1304 data |= VM_L2_CG__ENABLE_MASK; 1305 WREG32(mmVM_L2_CG, data); 1306 } else { 1307 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1308 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1309 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1310 1311 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1312 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1313 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1314 1315 data = RREG32(mmMC_HUB_MISC_VM_CG); 1316 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK; 1317 WREG32(mmMC_HUB_MISC_VM_CG, data); 1318 1319 data = RREG32(mmMC_XPB_CLK_GAT); 1320 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK; 1321 WREG32(mmMC_XPB_CLK_GAT, data); 1322 1323 data = RREG32(mmATC_MISC_CG); 1324 data &= ~ATC_MISC_CG__ENABLE_MASK; 1325 WREG32(mmATC_MISC_CG, data); 1326 1327 data = RREG32(mmMC_CITF_MISC_WR_CG); 1328 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK; 1329 WREG32(mmMC_CITF_MISC_WR_CG, data); 1330 1331 data = RREG32(mmMC_CITF_MISC_RD_CG); 1332 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK; 1333 WREG32(mmMC_CITF_MISC_RD_CG, data); 1334 1335 data = RREG32(mmMC_CITF_MISC_VM_CG); 1336 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK; 1337 WREG32(mmMC_CITF_MISC_VM_CG, data); 1338 1339 data = RREG32(mmVM_L2_CG); 1340 data &= ~VM_L2_CG__ENABLE_MASK; 1341 WREG32(mmVM_L2_CG, data); 1342 } 1343 } 1344 1345 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev, 1346 bool enable) 1347 { 1348 uint32_t data; 1349 1350 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) { 1351 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1352 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1353 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1354 1355 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1356 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1357 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1358 1359 data = RREG32(mmMC_HUB_MISC_VM_CG); 1360 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1361 WREG32(mmMC_HUB_MISC_VM_CG, data); 1362 1363 data = RREG32(mmMC_XPB_CLK_GAT); 1364 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1365 WREG32(mmMC_XPB_CLK_GAT, data); 1366 1367 data = RREG32(mmATC_MISC_CG); 1368 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1369 WREG32(mmATC_MISC_CG, data); 1370 1371 data = RREG32(mmMC_CITF_MISC_WR_CG); 1372 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1373 WREG32(mmMC_CITF_MISC_WR_CG, data); 1374 1375 data = RREG32(mmMC_CITF_MISC_RD_CG); 1376 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1377 WREG32(mmMC_CITF_MISC_RD_CG, data); 1378 1379 data = RREG32(mmMC_CITF_MISC_VM_CG); 1380 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1381 WREG32(mmMC_CITF_MISC_VM_CG, data); 1382 1383 data = RREG32(mmVM_L2_CG); 1384 data |= VM_L2_CG__MEM_LS_ENABLE_MASK; 1385 WREG32(mmVM_L2_CG, data); 1386 } else { 1387 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1388 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1389 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1390 1391 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1392 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1393 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1394 1395 data = RREG32(mmMC_HUB_MISC_VM_CG); 1396 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1397 WREG32(mmMC_HUB_MISC_VM_CG, data); 1398 1399 data = RREG32(mmMC_XPB_CLK_GAT); 1400 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1401 WREG32(mmMC_XPB_CLK_GAT, data); 1402 1403 data = RREG32(mmATC_MISC_CG); 1404 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1405 WREG32(mmATC_MISC_CG, data); 1406 1407 data = RREG32(mmMC_CITF_MISC_WR_CG); 1408 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1409 WREG32(mmMC_CITF_MISC_WR_CG, data); 1410 1411 data = RREG32(mmMC_CITF_MISC_RD_CG); 1412 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1413 WREG32(mmMC_CITF_MISC_RD_CG, data); 1414 1415 data = RREG32(mmMC_CITF_MISC_VM_CG); 1416 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1417 WREG32(mmMC_CITF_MISC_VM_CG, data); 1418 1419 data = RREG32(mmVM_L2_CG); 1420 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK; 1421 WREG32(mmVM_L2_CG, data); 1422 } 1423 } 1424 1425 static int gmc_v8_0_set_clockgating_state(void *handle, 1426 enum amd_clockgating_state state) 1427 { 1428 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1429 1430 switch (adev->asic_type) { 1431 case CHIP_FIJI: 1432 fiji_update_mc_medium_grain_clock_gating(adev, 1433 state == AMD_CG_STATE_GATE ? true : false); 1434 fiji_update_mc_light_sleep(adev, 1435 state == AMD_CG_STATE_GATE ? true : false); 1436 break; 1437 default: 1438 break; 1439 } 1440 return 0; 1441 } 1442 1443 static int gmc_v8_0_set_powergating_state(void *handle, 1444 enum amd_powergating_state state) 1445 { 1446 return 0; 1447 } 1448 1449 static void gmc_v8_0_get_clockgating_state(void *handle, u32 *flags) 1450 { 1451 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1452 int data; 1453 1454 /* AMD_CG_SUPPORT_MC_MGCG */ 1455 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1456 if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK) 1457 *flags |= AMD_CG_SUPPORT_MC_MGCG; 1458 1459 /* AMD_CG_SUPPORT_MC_LS */ 1460 if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK) 1461 *flags |= AMD_CG_SUPPORT_MC_LS; 1462 } 1463 1464 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = { 1465 .name = "gmc_v8_0", 1466 .early_init = gmc_v8_0_early_init, 1467 .late_init = gmc_v8_0_late_init, 1468 .sw_init = gmc_v8_0_sw_init, 1469 .sw_fini = gmc_v8_0_sw_fini, 1470 .hw_init = gmc_v8_0_hw_init, 1471 .hw_fini = gmc_v8_0_hw_fini, 1472 .suspend = gmc_v8_0_suspend, 1473 .resume = gmc_v8_0_resume, 1474 .is_idle = gmc_v8_0_is_idle, 1475 .wait_for_idle = gmc_v8_0_wait_for_idle, 1476 .check_soft_reset = gmc_v8_0_check_soft_reset, 1477 .pre_soft_reset = gmc_v8_0_pre_soft_reset, 1478 .soft_reset = gmc_v8_0_soft_reset, 1479 .post_soft_reset = gmc_v8_0_post_soft_reset, 1480 .set_clockgating_state = gmc_v8_0_set_clockgating_state, 1481 .set_powergating_state = gmc_v8_0_set_powergating_state, 1482 .get_clockgating_state = gmc_v8_0_get_clockgating_state, 1483 }; 1484 1485 static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = { 1486 .flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb, 1487 .set_pte_pde = gmc_v8_0_gart_set_pte_pde, 1488 }; 1489 1490 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = { 1491 .set = gmc_v8_0_vm_fault_interrupt_state, 1492 .process = gmc_v8_0_process_interrupt, 1493 }; 1494 1495 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev) 1496 { 1497 if (adev->gart.gart_funcs == NULL) 1498 adev->gart.gart_funcs = &gmc_v8_0_gart_funcs; 1499 } 1500 1501 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev) 1502 { 1503 adev->mc.vm_fault.num_types = 1; 1504 adev->mc.vm_fault.funcs = &gmc_v8_0_irq_funcs; 1505 } 1506 1507 const struct amdgpu_ip_block_version gmc_v8_0_ip_block = 1508 { 1509 .type = AMD_IP_BLOCK_TYPE_GMC, 1510 .major = 8, 1511 .minor = 0, 1512 .rev = 0, 1513 .funcs = &gmc_v8_0_ip_funcs, 1514 }; 1515 1516 const struct amdgpu_ip_block_version gmc_v8_1_ip_block = 1517 { 1518 .type = AMD_IP_BLOCK_TYPE_GMC, 1519 .major = 8, 1520 .minor = 1, 1521 .rev = 0, 1522 .funcs = &gmc_v8_0_ip_funcs, 1523 }; 1524 1525 const struct amdgpu_ip_block_version gmc_v8_5_ip_block = 1526 { 1527 .type = AMD_IP_BLOCK_TYPE_GMC, 1528 .major = 8, 1529 .minor = 5, 1530 .rev = 0, 1531 .funcs = &gmc_v8_0_ip_funcs, 1532 }; 1533