1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/drm_cache.h> 29 #include "amdgpu.h" 30 #include "gmc_v8_0.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_amdkfd.h" 33 #include "amdgpu_gem.h" 34 35 #include "gmc/gmc_8_1_d.h" 36 #include "gmc/gmc_8_1_sh_mask.h" 37 38 #include "bif/bif_5_0_d.h" 39 #include "bif/bif_5_0_sh_mask.h" 40 41 #include "oss/oss_3_0_d.h" 42 #include "oss/oss_3_0_sh_mask.h" 43 44 #include "dce/dce_10_0_d.h" 45 #include "dce/dce_10_0_sh_mask.h" 46 47 #include "vid.h" 48 #include "vi.h" 49 50 #include "amdgpu_atombios.h" 51 52 #include "ivsrcid/ivsrcid_vislands30.h" 53 54 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev); 55 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev); 56 static int gmc_v8_0_wait_for_idle(void *handle); 57 58 MODULE_FIRMWARE("amdgpu/tonga_mc.bin"); 59 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin"); 60 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin"); 61 MODULE_FIRMWARE("amdgpu/polaris12_mc.bin"); 62 MODULE_FIRMWARE("amdgpu/polaris12_32_mc.bin"); 63 MODULE_FIRMWARE("amdgpu/polaris11_k_mc.bin"); 64 MODULE_FIRMWARE("amdgpu/polaris10_k_mc.bin"); 65 MODULE_FIRMWARE("amdgpu/polaris12_k_mc.bin"); 66 67 static const u32 golden_settings_tonga_a11[] = 68 { 69 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, 70 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028, 71 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991, 72 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 73 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 74 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 75 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 76 }; 77 78 static const u32 tonga_mgcg_cgcg_init[] = 79 { 80 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 81 }; 82 83 static const u32 golden_settings_fiji_a10[] = 84 { 85 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 86 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 87 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 88 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 89 }; 90 91 static const u32 fiji_mgcg_cgcg_init[] = 92 { 93 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 94 }; 95 96 static const u32 golden_settings_polaris11_a11[] = 97 { 98 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 99 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 100 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 101 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 102 }; 103 104 static const u32 golden_settings_polaris10_a11[] = 105 { 106 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, 107 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 108 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 109 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 110 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 111 }; 112 113 static const u32 cz_mgcg_cgcg_init[] = 114 { 115 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 116 }; 117 118 static const u32 stoney_mgcg_cgcg_init[] = 119 { 120 mmATC_MISC_CG, 0xffffffff, 0x000c0200, 121 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 122 }; 123 124 static const u32 golden_settings_stoney_common[] = 125 { 126 mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004, 127 mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000 128 }; 129 130 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) 131 { 132 switch (adev->asic_type) { 133 case CHIP_FIJI: 134 amdgpu_device_program_register_sequence(adev, 135 fiji_mgcg_cgcg_init, 136 ARRAY_SIZE(fiji_mgcg_cgcg_init)); 137 amdgpu_device_program_register_sequence(adev, 138 golden_settings_fiji_a10, 139 ARRAY_SIZE(golden_settings_fiji_a10)); 140 break; 141 case CHIP_TONGA: 142 amdgpu_device_program_register_sequence(adev, 143 tonga_mgcg_cgcg_init, 144 ARRAY_SIZE(tonga_mgcg_cgcg_init)); 145 amdgpu_device_program_register_sequence(adev, 146 golden_settings_tonga_a11, 147 ARRAY_SIZE(golden_settings_tonga_a11)); 148 break; 149 case CHIP_POLARIS11: 150 case CHIP_POLARIS12: 151 case CHIP_VEGAM: 152 amdgpu_device_program_register_sequence(adev, 153 golden_settings_polaris11_a11, 154 ARRAY_SIZE(golden_settings_polaris11_a11)); 155 break; 156 case CHIP_POLARIS10: 157 amdgpu_device_program_register_sequence(adev, 158 golden_settings_polaris10_a11, 159 ARRAY_SIZE(golden_settings_polaris10_a11)); 160 break; 161 case CHIP_CARRIZO: 162 amdgpu_device_program_register_sequence(adev, 163 cz_mgcg_cgcg_init, 164 ARRAY_SIZE(cz_mgcg_cgcg_init)); 165 break; 166 case CHIP_STONEY: 167 amdgpu_device_program_register_sequence(adev, 168 stoney_mgcg_cgcg_init, 169 ARRAY_SIZE(stoney_mgcg_cgcg_init)); 170 amdgpu_device_program_register_sequence(adev, 171 golden_settings_stoney_common, 172 ARRAY_SIZE(golden_settings_stoney_common)); 173 break; 174 default: 175 break; 176 } 177 } 178 179 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev) 180 { 181 u32 blackout; 182 183 gmc_v8_0_wait_for_idle(adev); 184 185 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 186 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 187 /* Block CPU access */ 188 WREG32(mmBIF_FB_EN, 0); 189 /* blackout the MC */ 190 blackout = REG_SET_FIELD(blackout, 191 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1); 192 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout); 193 } 194 /* wait for the MC to settle */ 195 udelay(100); 196 } 197 198 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev) 199 { 200 u32 tmp; 201 202 /* unblackout the MC */ 203 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 204 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 205 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 206 /* allow CPU access */ 207 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 208 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 209 WREG32(mmBIF_FB_EN, tmp); 210 } 211 212 /** 213 * gmc_v8_0_init_microcode - load ucode images from disk 214 * 215 * @adev: amdgpu_device pointer 216 * 217 * Use the firmware interface to load the ucode images into 218 * the driver (not loaded into hw). 219 * Returns 0 on success, error on failure. 220 */ 221 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) 222 { 223 const char *chip_name; 224 char fw_name[30]; 225 int err; 226 227 DRM_DEBUG("\n"); 228 229 switch (adev->asic_type) { 230 case CHIP_TONGA: 231 chip_name = "tonga"; 232 break; 233 case CHIP_POLARIS11: 234 if (ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) || 235 ASICID_IS_P31(adev->pdev->device, adev->pdev->revision)) 236 chip_name = "polaris11_k"; 237 else 238 chip_name = "polaris11"; 239 break; 240 case CHIP_POLARIS10: 241 if (ASICID_IS_P30(adev->pdev->device, adev->pdev->revision)) 242 chip_name = "polaris10_k"; 243 else 244 chip_name = "polaris10"; 245 break; 246 case CHIP_POLARIS12: 247 if (ASICID_IS_P23(adev->pdev->device, adev->pdev->revision)) { 248 chip_name = "polaris12_k"; 249 } else { 250 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, ixMC_IO_DEBUG_UP_159); 251 /* Polaris12 32bit ASIC needs a special MC firmware */ 252 if (RREG32(mmMC_SEQ_IO_DEBUG_DATA) == 0x05b4dc40) 253 chip_name = "polaris12_32"; 254 else 255 chip_name = "polaris12"; 256 } 257 break; 258 case CHIP_FIJI: 259 case CHIP_CARRIZO: 260 case CHIP_STONEY: 261 case CHIP_VEGAM: 262 return 0; 263 default: BUG(); 264 } 265 266 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name); 267 err = amdgpu_ucode_request(adev, &adev->gmc.fw, fw_name); 268 if (err) { 269 pr_err("mc: Failed to load firmware \"%s\"\n", fw_name); 270 amdgpu_ucode_release(&adev->gmc.fw); 271 } 272 return err; 273 } 274 275 /** 276 * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw 277 * 278 * @adev: amdgpu_device pointer 279 * 280 * Load the GDDR MC ucode into the hw (VI). 281 * Returns 0 on success, error on failure. 282 */ 283 static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev) 284 { 285 const struct mc_firmware_header_v1_0 *hdr; 286 const __le32 *fw_data = NULL; 287 const __le32 *io_mc_regs = NULL; 288 u32 running; 289 int i, ucode_size, regs_size; 290 291 /* Skip MC ucode loading on SR-IOV capable boards. 292 * vbios does this for us in asic_init in that case. 293 * Skip MC ucode loading on VF, because hypervisor will do that 294 * for this adaptor. 295 */ 296 if (amdgpu_sriov_bios(adev)) 297 return 0; 298 299 if (!adev->gmc.fw) 300 return -EINVAL; 301 302 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 303 amdgpu_ucode_print_mc_hdr(&hdr->header); 304 305 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 306 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 307 io_mc_regs = (const __le32 *) 308 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 309 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 310 fw_data = (const __le32 *) 311 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 312 313 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); 314 315 if (running == 0) { 316 /* reset the engine and set to writable */ 317 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 318 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 319 320 /* load mc io regs */ 321 for (i = 0; i < regs_size; i++) { 322 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 323 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 324 } 325 /* load the MC ucode */ 326 for (i = 0; i < ucode_size; i++) 327 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 328 329 /* put the engine back into the active state */ 330 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 331 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 332 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 333 334 /* wait for training to complete */ 335 for (i = 0; i < adev->usec_timeout; i++) { 336 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 337 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0)) 338 break; 339 udelay(1); 340 } 341 for (i = 0; i < adev->usec_timeout; i++) { 342 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 343 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1)) 344 break; 345 udelay(1); 346 } 347 } 348 349 return 0; 350 } 351 352 static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev) 353 { 354 const struct mc_firmware_header_v1_0 *hdr; 355 const __le32 *fw_data = NULL; 356 const __le32 *io_mc_regs = NULL; 357 u32 data; 358 int i, ucode_size, regs_size; 359 360 /* Skip MC ucode loading on SR-IOV capable boards. 361 * vbios does this for us in asic_init in that case. 362 * Skip MC ucode loading on VF, because hypervisor will do that 363 * for this adaptor. 364 */ 365 if (amdgpu_sriov_bios(adev)) 366 return 0; 367 368 if (!adev->gmc.fw) 369 return -EINVAL; 370 371 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 372 amdgpu_ucode_print_mc_hdr(&hdr->header); 373 374 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 375 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 376 io_mc_regs = (const __le32 *) 377 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 378 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 379 fw_data = (const __le32 *) 380 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 381 382 data = RREG32(mmMC_SEQ_MISC0); 383 data &= ~(0x40); 384 WREG32(mmMC_SEQ_MISC0, data); 385 386 /* load mc io regs */ 387 for (i = 0; i < regs_size; i++) { 388 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 389 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 390 } 391 392 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 393 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 394 395 /* load the MC ucode */ 396 for (i = 0; i < ucode_size; i++) 397 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 398 399 /* put the engine back into the active state */ 400 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 401 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 402 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 403 404 /* wait for training to complete */ 405 for (i = 0; i < adev->usec_timeout; i++) { 406 data = RREG32(mmMC_SEQ_MISC0); 407 if (data & 0x80) 408 break; 409 udelay(1); 410 } 411 412 return 0; 413 } 414 415 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev, 416 struct amdgpu_gmc *mc) 417 { 418 u64 base = 0; 419 420 if (!amdgpu_sriov_vf(adev)) 421 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; 422 base <<= 24; 423 424 amdgpu_gmc_vram_location(adev, mc, base); 425 amdgpu_gmc_gart_location(adev, mc); 426 } 427 428 /** 429 * gmc_v8_0_mc_program - program the GPU memory controller 430 * 431 * @adev: amdgpu_device pointer 432 * 433 * Set the location of vram, gart, and AGP in the GPU's 434 * physical address space (VI). 435 */ 436 static void gmc_v8_0_mc_program(struct amdgpu_device *adev) 437 { 438 u32 tmp; 439 int i, j; 440 441 /* Initialize HDP */ 442 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 443 WREG32((0xb05 + j), 0x00000000); 444 WREG32((0xb06 + j), 0x00000000); 445 WREG32((0xb07 + j), 0x00000000); 446 WREG32((0xb08 + j), 0x00000000); 447 WREG32((0xb09 + j), 0x00000000); 448 } 449 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 450 451 if (gmc_v8_0_wait_for_idle((void *)adev)) { 452 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 453 } 454 if (adev->mode_info.num_crtc) { 455 /* Lockout access through VGA aperture*/ 456 tmp = RREG32(mmVGA_HDP_CONTROL); 457 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 458 WREG32(mmVGA_HDP_CONTROL, tmp); 459 460 /* disable VGA render */ 461 tmp = RREG32(mmVGA_RENDER_CONTROL); 462 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 463 WREG32(mmVGA_RENDER_CONTROL, tmp); 464 } 465 /* Update configuration */ 466 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 467 adev->gmc.vram_start >> 12); 468 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 469 adev->gmc.vram_end >> 12); 470 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 471 adev->mem_scratch.gpu_addr >> 12); 472 473 if (amdgpu_sriov_vf(adev)) { 474 tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16; 475 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF); 476 WREG32(mmMC_VM_FB_LOCATION, tmp); 477 /* XXX double check these! */ 478 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); 479 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); 480 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF); 481 } 482 483 WREG32(mmMC_VM_AGP_BASE, 0); 484 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); 485 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); 486 if (gmc_v8_0_wait_for_idle((void *)adev)) { 487 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 488 } 489 490 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 491 492 tmp = RREG32(mmHDP_MISC_CNTL); 493 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); 494 WREG32(mmHDP_MISC_CNTL, tmp); 495 496 tmp = RREG32(mmHDP_HOST_PATH_CNTL); 497 WREG32(mmHDP_HOST_PATH_CNTL, tmp); 498 } 499 500 /** 501 * gmc_v8_0_mc_init - initialize the memory controller driver params 502 * 503 * @adev: amdgpu_device pointer 504 * 505 * Look up the amount of vram, vram width, and decide how to place 506 * vram and gart within the GPU's physical address space (VI). 507 * Returns 0 for success. 508 */ 509 static int gmc_v8_0_mc_init(struct amdgpu_device *adev) 510 { 511 int r; 512 u32 tmp; 513 514 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev); 515 if (!adev->gmc.vram_width) { 516 int chansize, numchan; 517 518 /* Get VRAM informations */ 519 tmp = RREG32(mmMC_ARB_RAMCFG); 520 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { 521 chansize = 64; 522 } else { 523 chansize = 32; 524 } 525 tmp = RREG32(mmMC_SHARED_CHMAP); 526 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 527 case 0: 528 default: 529 numchan = 1; 530 break; 531 case 1: 532 numchan = 2; 533 break; 534 case 2: 535 numchan = 4; 536 break; 537 case 3: 538 numchan = 8; 539 break; 540 case 4: 541 numchan = 3; 542 break; 543 case 5: 544 numchan = 6; 545 break; 546 case 6: 547 numchan = 10; 548 break; 549 case 7: 550 numchan = 12; 551 break; 552 case 8: 553 numchan = 16; 554 break; 555 } 556 adev->gmc.vram_width = numchan * chansize; 557 } 558 /* size in MB on si */ 559 tmp = RREG32(mmCONFIG_MEMSIZE); 560 /* some boards may have garbage in the upper 16 bits */ 561 if (tmp & 0xffff0000) { 562 DRM_INFO("Probable bad vram size: 0x%08x\n", tmp); 563 if (tmp & 0xffff) 564 tmp &= 0xffff; 565 } 566 adev->gmc.mc_vram_size = tmp * 1024ULL * 1024ULL; 567 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 568 569 if (!(adev->flags & AMD_IS_APU)) { 570 r = amdgpu_device_resize_fb_bar(adev); 571 if (r) 572 return r; 573 } 574 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 575 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 576 577 #ifdef CONFIG_X86_64 578 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { 579 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; 580 adev->gmc.aper_size = adev->gmc.real_vram_size; 581 } 582 #endif 583 584 adev->gmc.visible_vram_size = adev->gmc.aper_size; 585 586 /* set the gart size */ 587 if (amdgpu_gart_size == -1) { 588 switch (adev->asic_type) { 589 case CHIP_POLARIS10: /* all engines support GPUVM */ 590 case CHIP_POLARIS11: /* all engines support GPUVM */ 591 case CHIP_POLARIS12: /* all engines support GPUVM */ 592 case CHIP_VEGAM: /* all engines support GPUVM */ 593 default: 594 adev->gmc.gart_size = 256ULL << 20; 595 break; 596 case CHIP_TONGA: /* UVD, VCE do not support GPUVM */ 597 case CHIP_FIJI: /* UVD, VCE do not support GPUVM */ 598 case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */ 599 case CHIP_STONEY: /* UVD does not support GPUVM, DCE SG support */ 600 adev->gmc.gart_size = 1024ULL << 20; 601 break; 602 } 603 } else { 604 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 605 } 606 607 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; 608 gmc_v8_0_vram_gtt_location(adev, &adev->gmc); 609 610 return 0; 611 } 612 613 /** 614 * gmc_v8_0_flush_gpu_tlb_pasid - tlb flush via pasid 615 * 616 * @adev: amdgpu_device pointer 617 * @pasid: pasid to be flush 618 * @flush_type: type of flush 619 * @all_hub: flush all hubs 620 * @inst: is used to select which instance of KIQ to use for the invalidation 621 * 622 * Flush the TLB for the requested pasid. 623 */ 624 static int gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 625 uint16_t pasid, uint32_t flush_type, 626 bool all_hub, uint32_t inst) 627 { 628 int vmid; 629 unsigned int tmp; 630 631 if (amdgpu_in_reset(adev)) 632 return -EIO; 633 634 for (vmid = 1; vmid < 16; vmid++) { 635 636 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); 637 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) && 638 (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) { 639 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 640 RREG32(mmVM_INVALIDATE_RESPONSE); 641 break; 642 } 643 } 644 645 return 0; 646 647 } 648 649 /* 650 * GART 651 * VMID 0 is the physical GPU addresses as used by the kernel. 652 * VMIDs 1-15 are used for userspace clients and are handled 653 * by the amdgpu vm/hsa code. 654 */ 655 656 /** 657 * gmc_v8_0_flush_gpu_tlb - gart tlb flush callback 658 * 659 * @adev: amdgpu_device pointer 660 * @vmid: vm instance to flush 661 * @vmhub: which hub to flush 662 * @flush_type: type of flush 663 * 664 * Flush the TLB for the requested page table (VI). 665 */ 666 static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 667 uint32_t vmhub, uint32_t flush_type) 668 { 669 /* bits 0-15 are the VM contexts0-15 */ 670 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 671 } 672 673 static uint64_t gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 674 unsigned vmid, uint64_t pd_addr) 675 { 676 uint32_t reg; 677 678 if (vmid < 8) 679 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; 680 else 681 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8; 682 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); 683 684 /* bits 0-15 are the VM contexts0-15 */ 685 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); 686 687 return pd_addr; 688 } 689 690 static void gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 691 unsigned pasid) 692 { 693 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); 694 } 695 696 /* 697 * PTE format on VI: 698 * 63:40 reserved 699 * 39:12 4k physical page base address 700 * 11:7 fragment 701 * 6 write 702 * 5 read 703 * 4 exe 704 * 3 reserved 705 * 2 snooped 706 * 1 system 707 * 0 valid 708 * 709 * PDE format on VI: 710 * 63:59 block fragment size 711 * 58:40 reserved 712 * 39:1 physical base address of PTE 713 * bits 5:1 must be 0. 714 * 0 valid 715 */ 716 717 static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level, 718 uint64_t *addr, uint64_t *flags) 719 { 720 BUG_ON(*addr & 0xFFFFFF0000000FFFULL); 721 } 722 723 static void gmc_v8_0_get_vm_pte(struct amdgpu_device *adev, 724 struct amdgpu_bo_va_mapping *mapping, 725 uint64_t *flags) 726 { 727 *flags &= ~AMDGPU_PTE_EXECUTABLE; 728 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 729 *flags &= ~AMDGPU_PTE_PRT; 730 } 731 732 /** 733 * gmc_v8_0_set_fault_enable_default - update VM fault handling 734 * 735 * @adev: amdgpu_device pointer 736 * @value: true redirects VM faults to the default page 737 */ 738 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev, 739 bool value) 740 { 741 u32 tmp; 742 743 tmp = RREG32(mmVM_CONTEXT1_CNTL); 744 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 745 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 746 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 747 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 748 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 749 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 750 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 751 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 752 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 753 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 754 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 755 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 756 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 757 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 758 WREG32(mmVM_CONTEXT1_CNTL, tmp); 759 } 760 761 /** 762 * gmc_v8_0_set_prt - set PRT VM fault 763 * 764 * @adev: amdgpu_device pointer 765 * @enable: enable/disable VM fault handling for PRT 766 */ 767 static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable) 768 { 769 u32 tmp; 770 771 if (enable && !adev->gmc.prt_warning) { 772 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 773 adev->gmc.prt_warning = true; 774 } 775 776 tmp = RREG32(mmVM_PRT_CNTL); 777 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 778 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 779 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 780 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 781 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 782 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 783 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 784 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 785 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 786 L2_CACHE_STORE_INVALID_ENTRIES, enable); 787 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 788 L1_TLB_STORE_INVALID_ENTRIES, enable); 789 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 790 MASK_PDE0_FAULT, enable); 791 WREG32(mmVM_PRT_CNTL, tmp); 792 793 if (enable) { 794 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; 795 uint32_t high = adev->vm_manager.max_pfn - 796 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT); 797 798 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); 799 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); 800 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); 801 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); 802 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); 803 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); 804 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); 805 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); 806 } else { 807 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); 808 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); 809 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); 810 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); 811 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); 812 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); 813 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); 814 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); 815 } 816 } 817 818 /** 819 * gmc_v8_0_gart_enable - gart enable 820 * 821 * @adev: amdgpu_device pointer 822 * 823 * This sets up the TLBs, programs the page tables for VMID0, 824 * sets up the hw for VMIDs 1-15 which are allocated on 825 * demand, and sets up the global locations for the LDS, GDS, 826 * and GPUVM for FSA64 clients (VI). 827 * Returns 0 for success, errors for failure. 828 */ 829 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) 830 { 831 uint64_t table_addr; 832 u32 tmp, field; 833 int i; 834 835 if (adev->gart.bo == NULL) { 836 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 837 return -EINVAL; 838 } 839 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 840 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 841 842 /* Setup TLB control */ 843 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 844 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 845 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); 846 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 847 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); 848 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 849 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 850 /* Setup L2 cache */ 851 tmp = RREG32(mmVM_L2_CNTL); 852 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 853 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 854 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); 855 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); 856 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); 857 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 858 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 859 WREG32(mmVM_L2_CNTL, tmp); 860 tmp = RREG32(mmVM_L2_CNTL2); 861 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 862 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 863 WREG32(mmVM_L2_CNTL2, tmp); 864 865 field = adev->vm_manager.fragment_size; 866 tmp = RREG32(mmVM_L2_CNTL3); 867 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); 868 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); 869 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); 870 WREG32(mmVM_L2_CNTL3, tmp); 871 /* XXX: set to enable PTE/PDE in system memory */ 872 tmp = RREG32(mmVM_L2_CNTL4); 873 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0); 874 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0); 875 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0); 876 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0); 877 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0); 878 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0); 879 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0); 880 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0); 881 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0); 882 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0); 883 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0); 884 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0); 885 WREG32(mmVM_L2_CNTL4, tmp); 886 /* setup context0 */ 887 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); 888 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); 889 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12); 890 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 891 (u32)(adev->dummy_page_addr >> 12)); 892 WREG32(mmVM_CONTEXT0_CNTL2, 0); 893 tmp = RREG32(mmVM_CONTEXT0_CNTL); 894 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 895 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 896 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 897 WREG32(mmVM_CONTEXT0_CNTL, tmp); 898 899 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0); 900 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0); 901 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0); 902 903 /* empty context1-15 */ 904 /* FIXME start with 4G, once using 2 level pt switch to full 905 * vm size space 906 */ 907 /* set vm size, must be a multiple of 4 */ 908 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 909 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 910 for (i = 1; i < AMDGPU_NUM_VMID; i++) { 911 if (i < 8) 912 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 913 table_addr >> 12); 914 else 915 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 916 table_addr >> 12); 917 } 918 919 /* enable context1-15 */ 920 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 921 (u32)(adev->dummy_page_addr >> 12)); 922 WREG32(mmVM_CONTEXT1_CNTL2, 4); 923 tmp = RREG32(mmVM_CONTEXT1_CNTL); 924 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 925 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); 926 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 927 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 928 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 929 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 930 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 931 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 932 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 933 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, 934 adev->vm_manager.block_size - 9); 935 WREG32(mmVM_CONTEXT1_CNTL, tmp); 936 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 937 gmc_v8_0_set_fault_enable_default(adev, false); 938 else 939 gmc_v8_0_set_fault_enable_default(adev, true); 940 941 gmc_v8_0_flush_gpu_tlb(adev, 0, 0, 0); 942 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 943 (unsigned)(adev->gmc.gart_size >> 20), 944 (unsigned long long)table_addr); 945 return 0; 946 } 947 948 static int gmc_v8_0_gart_init(struct amdgpu_device *adev) 949 { 950 int r; 951 952 if (adev->gart.bo) { 953 WARN(1, "R600 PCIE GART already initialized\n"); 954 return 0; 955 } 956 /* Initialize common gart structure */ 957 r = amdgpu_gart_init(adev); 958 if (r) 959 return r; 960 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 961 adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE; 962 return amdgpu_gart_table_vram_alloc(adev); 963 } 964 965 /** 966 * gmc_v8_0_gart_disable - gart disable 967 * 968 * @adev: amdgpu_device pointer 969 * 970 * This disables all VM page table (VI). 971 */ 972 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev) 973 { 974 u32 tmp; 975 976 /* Disable all tables */ 977 WREG32(mmVM_CONTEXT0_CNTL, 0); 978 WREG32(mmVM_CONTEXT1_CNTL, 0); 979 /* Setup TLB control */ 980 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 981 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 982 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); 983 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); 984 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 985 /* Setup L2 cache */ 986 tmp = RREG32(mmVM_L2_CNTL); 987 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 988 WREG32(mmVM_L2_CNTL, tmp); 989 WREG32(mmVM_L2_CNTL2, 0); 990 } 991 992 /** 993 * gmc_v8_0_vm_decode_fault - print human readable fault info 994 * 995 * @adev: amdgpu_device pointer 996 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value 997 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value 998 * @mc_client: VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT register value 999 * @pasid: debug logging only - no functional use 1000 * 1001 * Print human readable fault information (VI). 1002 */ 1003 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32 status, 1004 u32 addr, u32 mc_client, unsigned pasid) 1005 { 1006 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 1007 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1008 PROTECTIONS); 1009 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 1010 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 1011 u32 mc_id; 1012 1013 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1014 MEMORY_CLIENT_ID); 1015 1016 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 1017 protections, vmid, pasid, addr, 1018 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1019 MEMORY_CLIENT_RW) ? 1020 "write" : "read", block, mc_client, mc_id); 1021 } 1022 1023 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type) 1024 { 1025 switch (mc_seq_vram_type) { 1026 case MC_SEQ_MISC0__MT__GDDR1: 1027 return AMDGPU_VRAM_TYPE_GDDR1; 1028 case MC_SEQ_MISC0__MT__DDR2: 1029 return AMDGPU_VRAM_TYPE_DDR2; 1030 case MC_SEQ_MISC0__MT__GDDR3: 1031 return AMDGPU_VRAM_TYPE_GDDR3; 1032 case MC_SEQ_MISC0__MT__GDDR4: 1033 return AMDGPU_VRAM_TYPE_GDDR4; 1034 case MC_SEQ_MISC0__MT__GDDR5: 1035 return AMDGPU_VRAM_TYPE_GDDR5; 1036 case MC_SEQ_MISC0__MT__HBM: 1037 return AMDGPU_VRAM_TYPE_HBM; 1038 case MC_SEQ_MISC0__MT__DDR3: 1039 return AMDGPU_VRAM_TYPE_DDR3; 1040 default: 1041 return AMDGPU_VRAM_TYPE_UNKNOWN; 1042 } 1043 } 1044 1045 static int gmc_v8_0_early_init(void *handle) 1046 { 1047 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1048 1049 gmc_v8_0_set_gmc_funcs(adev); 1050 gmc_v8_0_set_irq_funcs(adev); 1051 1052 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1053 adev->gmc.shared_aperture_end = 1054 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1055 adev->gmc.private_aperture_start = 1056 adev->gmc.shared_aperture_end + 1; 1057 adev->gmc.private_aperture_end = 1058 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1059 1060 return 0; 1061 } 1062 1063 static int gmc_v8_0_late_init(void *handle) 1064 { 1065 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1066 1067 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 1068 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1069 else 1070 return 0; 1071 } 1072 1073 static unsigned gmc_v8_0_get_vbios_fb_size(struct amdgpu_device *adev) 1074 { 1075 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); 1076 unsigned size; 1077 1078 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1079 size = AMDGPU_VBIOS_VGA_ALLOCATION; 1080 } else { 1081 u32 viewport = RREG32(mmVIEWPORT_SIZE); 1082 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1083 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1084 4); 1085 } 1086 1087 return size; 1088 } 1089 1090 #define mmMC_SEQ_MISC0_FIJI 0xA71 1091 1092 static int gmc_v8_0_sw_init(void *handle) 1093 { 1094 int r; 1095 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1096 1097 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 1098 1099 if (adev->flags & AMD_IS_APU) { 1100 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 1101 } else { 1102 u32 tmp; 1103 1104 if ((adev->asic_type == CHIP_FIJI) || 1105 (adev->asic_type == CHIP_VEGAM)) 1106 tmp = RREG32(mmMC_SEQ_MISC0_FIJI); 1107 else 1108 tmp = RREG32(mmMC_SEQ_MISC0); 1109 tmp &= MC_SEQ_MISC0__MT__MASK; 1110 adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp); 1111 } 1112 1113 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault); 1114 if (r) 1115 return r; 1116 1117 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault); 1118 if (r) 1119 return r; 1120 1121 /* Adjust VM size here. 1122 * Currently set to 4GB ((1 << 20) 4k pages). 1123 * Max GPUVM size for cayman and SI is 40 bits. 1124 */ 1125 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); 1126 1127 /* Set the internal MC address mask 1128 * This is the max address of the GPU's 1129 * internal address space. 1130 */ 1131 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1132 1133 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40)); 1134 if (r) { 1135 pr_warn("No suitable DMA available\n"); 1136 return r; 1137 } 1138 adev->need_swiotlb = drm_need_swiotlb(40); 1139 1140 r = gmc_v8_0_init_microcode(adev); 1141 if (r) { 1142 DRM_ERROR("Failed to load mc firmware!\n"); 1143 return r; 1144 } 1145 1146 r = gmc_v8_0_mc_init(adev); 1147 if (r) 1148 return r; 1149 1150 amdgpu_gmc_get_vbios_allocations(adev); 1151 1152 /* Memory manager */ 1153 r = amdgpu_bo_init(adev); 1154 if (r) 1155 return r; 1156 1157 r = gmc_v8_0_gart_init(adev); 1158 if (r) 1159 return r; 1160 1161 /* 1162 * number of VMs 1163 * VMID 0 is reserved for System 1164 * amdgpu graphics/compute will use VMIDs 1-7 1165 * amdkfd will use VMIDs 8-15 1166 */ 1167 adev->vm_manager.first_kfd_vmid = 8; 1168 amdgpu_vm_manager_init(adev); 1169 1170 /* base offset of vram pages */ 1171 if (adev->flags & AMD_IS_APU) { 1172 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 1173 1174 tmp <<= 22; 1175 adev->vm_manager.vram_base_offset = tmp; 1176 } else { 1177 adev->vm_manager.vram_base_offset = 0; 1178 } 1179 1180 adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info), 1181 GFP_KERNEL); 1182 if (!adev->gmc.vm_fault_info) 1183 return -ENOMEM; 1184 atomic_set(&adev->gmc.vm_fault_info_updated, 0); 1185 1186 return 0; 1187 } 1188 1189 static int gmc_v8_0_sw_fini(void *handle) 1190 { 1191 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1192 1193 amdgpu_gem_force_release(adev); 1194 amdgpu_vm_manager_fini(adev); 1195 kfree(adev->gmc.vm_fault_info); 1196 amdgpu_gart_table_vram_free(adev); 1197 amdgpu_bo_fini(adev); 1198 amdgpu_ucode_release(&adev->gmc.fw); 1199 1200 return 0; 1201 } 1202 1203 static int gmc_v8_0_hw_init(void *handle) 1204 { 1205 int r; 1206 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1207 1208 gmc_v8_0_init_golden_registers(adev); 1209 1210 gmc_v8_0_mc_program(adev); 1211 1212 if (adev->asic_type == CHIP_TONGA) { 1213 r = gmc_v8_0_tonga_mc_load_microcode(adev); 1214 if (r) { 1215 DRM_ERROR("Failed to load MC firmware!\n"); 1216 return r; 1217 } 1218 } else if (adev->asic_type == CHIP_POLARIS11 || 1219 adev->asic_type == CHIP_POLARIS10 || 1220 adev->asic_type == CHIP_POLARIS12) { 1221 r = gmc_v8_0_polaris_mc_load_microcode(adev); 1222 if (r) { 1223 DRM_ERROR("Failed to load MC firmware!\n"); 1224 return r; 1225 } 1226 } 1227 1228 r = gmc_v8_0_gart_enable(adev); 1229 if (r) 1230 return r; 1231 1232 if (amdgpu_emu_mode == 1) 1233 return amdgpu_gmc_vram_checking(adev); 1234 else 1235 return r; 1236 } 1237 1238 static int gmc_v8_0_hw_fini(void *handle) 1239 { 1240 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1241 1242 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1243 gmc_v8_0_gart_disable(adev); 1244 1245 return 0; 1246 } 1247 1248 static int gmc_v8_0_suspend(void *handle) 1249 { 1250 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1251 1252 gmc_v8_0_hw_fini(adev); 1253 1254 return 0; 1255 } 1256 1257 static int gmc_v8_0_resume(void *handle) 1258 { 1259 int r; 1260 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1261 1262 r = gmc_v8_0_hw_init(adev); 1263 if (r) 1264 return r; 1265 1266 amdgpu_vmid_reset_all(adev); 1267 1268 return 0; 1269 } 1270 1271 static bool gmc_v8_0_is_idle(void *handle) 1272 { 1273 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1274 u32 tmp = RREG32(mmSRBM_STATUS); 1275 1276 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1277 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 1278 return false; 1279 1280 return true; 1281 } 1282 1283 static int gmc_v8_0_wait_for_idle(void *handle) 1284 { 1285 unsigned i; 1286 u32 tmp; 1287 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1288 1289 for (i = 0; i < adev->usec_timeout; i++) { 1290 /* read MC_STATUS */ 1291 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | 1292 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1293 SRBM_STATUS__MCC_BUSY_MASK | 1294 SRBM_STATUS__MCD_BUSY_MASK | 1295 SRBM_STATUS__VMC_BUSY_MASK | 1296 SRBM_STATUS__VMC1_BUSY_MASK); 1297 if (!tmp) 1298 return 0; 1299 udelay(1); 1300 } 1301 return -ETIMEDOUT; 1302 1303 } 1304 1305 static bool gmc_v8_0_check_soft_reset(void *handle) 1306 { 1307 u32 srbm_soft_reset = 0; 1308 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1309 u32 tmp = RREG32(mmSRBM_STATUS); 1310 1311 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1312 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1313 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 1314 1315 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1316 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 1317 if (!(adev->flags & AMD_IS_APU)) 1318 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1319 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1320 } 1321 if (srbm_soft_reset) { 1322 adev->gmc.srbm_soft_reset = srbm_soft_reset; 1323 return true; 1324 } else { 1325 adev->gmc.srbm_soft_reset = 0; 1326 return false; 1327 } 1328 } 1329 1330 static int gmc_v8_0_pre_soft_reset(void *handle) 1331 { 1332 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1333 1334 if (!adev->gmc.srbm_soft_reset) 1335 return 0; 1336 1337 gmc_v8_0_mc_stop(adev); 1338 if (gmc_v8_0_wait_for_idle(adev)) { 1339 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1340 } 1341 1342 return 0; 1343 } 1344 1345 static int gmc_v8_0_soft_reset(void *handle) 1346 { 1347 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1348 u32 srbm_soft_reset; 1349 1350 if (!adev->gmc.srbm_soft_reset) 1351 return 0; 1352 srbm_soft_reset = adev->gmc.srbm_soft_reset; 1353 1354 if (srbm_soft_reset) { 1355 u32 tmp; 1356 1357 tmp = RREG32(mmSRBM_SOFT_RESET); 1358 tmp |= srbm_soft_reset; 1359 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1360 WREG32(mmSRBM_SOFT_RESET, tmp); 1361 tmp = RREG32(mmSRBM_SOFT_RESET); 1362 1363 udelay(50); 1364 1365 tmp &= ~srbm_soft_reset; 1366 WREG32(mmSRBM_SOFT_RESET, tmp); 1367 tmp = RREG32(mmSRBM_SOFT_RESET); 1368 1369 /* Wait a little for things to settle down */ 1370 udelay(50); 1371 } 1372 1373 return 0; 1374 } 1375 1376 static int gmc_v8_0_post_soft_reset(void *handle) 1377 { 1378 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1379 1380 if (!adev->gmc.srbm_soft_reset) 1381 return 0; 1382 1383 gmc_v8_0_mc_resume(adev); 1384 return 0; 1385 } 1386 1387 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1388 struct amdgpu_irq_src *src, 1389 unsigned type, 1390 enum amdgpu_interrupt_state state) 1391 { 1392 u32 tmp; 1393 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1394 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1395 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1396 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1397 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1398 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1399 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1400 1401 switch (state) { 1402 case AMDGPU_IRQ_STATE_DISABLE: 1403 /* system context */ 1404 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1405 tmp &= ~bits; 1406 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1407 /* VMs */ 1408 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1409 tmp &= ~bits; 1410 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1411 break; 1412 case AMDGPU_IRQ_STATE_ENABLE: 1413 /* system context */ 1414 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1415 tmp |= bits; 1416 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1417 /* VMs */ 1418 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1419 tmp |= bits; 1420 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1421 break; 1422 default: 1423 break; 1424 } 1425 1426 return 0; 1427 } 1428 1429 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, 1430 struct amdgpu_irq_src *source, 1431 struct amdgpu_iv_entry *entry) 1432 { 1433 u32 addr, status, mc_client, vmid; 1434 1435 if (amdgpu_sriov_vf(adev)) { 1436 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1437 entry->src_id, entry->src_data[0]); 1438 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n"); 1439 return 0; 1440 } 1441 1442 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1443 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1444 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); 1445 /* reset addr and status */ 1446 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1447 1448 if (!addr && !status) 1449 return 0; 1450 1451 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1452 gmc_v8_0_set_fault_enable_default(adev, false); 1453 1454 if (printk_ratelimit()) { 1455 struct amdgpu_task_info task_info; 1456 1457 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 1458 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 1459 1460 dev_err(adev->dev, "GPU fault detected: %d 0x%08x for process %s pid %d thread %s pid %d\n", 1461 entry->src_id, entry->src_data[0], task_info.process_name, 1462 task_info.tgid, task_info.task_name, task_info.pid); 1463 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1464 addr); 1465 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1466 status); 1467 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client, 1468 entry->pasid); 1469 } 1470 1471 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1472 VMID); 1473 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid) 1474 && !atomic_read(&adev->gmc.vm_fault_info_updated)) { 1475 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info; 1476 u32 protections = REG_GET_FIELD(status, 1477 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1478 PROTECTIONS); 1479 1480 info->vmid = vmid; 1481 info->mc_id = REG_GET_FIELD(status, 1482 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1483 MEMORY_CLIENT_ID); 1484 info->status = status; 1485 info->page_addr = addr; 1486 info->prot_valid = protections & 0x7 ? true : false; 1487 info->prot_read = protections & 0x8 ? true : false; 1488 info->prot_write = protections & 0x10 ? true : false; 1489 info->prot_exec = protections & 0x20 ? true : false; 1490 mb(); 1491 atomic_set(&adev->gmc.vm_fault_info_updated, 1); 1492 } 1493 1494 return 0; 1495 } 1496 1497 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev, 1498 bool enable) 1499 { 1500 uint32_t data; 1501 1502 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 1503 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1504 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1505 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1506 1507 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1508 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1509 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1510 1511 data = RREG32(mmMC_HUB_MISC_VM_CG); 1512 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK; 1513 WREG32(mmMC_HUB_MISC_VM_CG, data); 1514 1515 data = RREG32(mmMC_XPB_CLK_GAT); 1516 data |= MC_XPB_CLK_GAT__ENABLE_MASK; 1517 WREG32(mmMC_XPB_CLK_GAT, data); 1518 1519 data = RREG32(mmATC_MISC_CG); 1520 data |= ATC_MISC_CG__ENABLE_MASK; 1521 WREG32(mmATC_MISC_CG, data); 1522 1523 data = RREG32(mmMC_CITF_MISC_WR_CG); 1524 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK; 1525 WREG32(mmMC_CITF_MISC_WR_CG, data); 1526 1527 data = RREG32(mmMC_CITF_MISC_RD_CG); 1528 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK; 1529 WREG32(mmMC_CITF_MISC_RD_CG, data); 1530 1531 data = RREG32(mmMC_CITF_MISC_VM_CG); 1532 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK; 1533 WREG32(mmMC_CITF_MISC_VM_CG, data); 1534 1535 data = RREG32(mmVM_L2_CG); 1536 data |= VM_L2_CG__ENABLE_MASK; 1537 WREG32(mmVM_L2_CG, data); 1538 } else { 1539 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1540 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1541 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1542 1543 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1544 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1545 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1546 1547 data = RREG32(mmMC_HUB_MISC_VM_CG); 1548 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK; 1549 WREG32(mmMC_HUB_MISC_VM_CG, data); 1550 1551 data = RREG32(mmMC_XPB_CLK_GAT); 1552 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK; 1553 WREG32(mmMC_XPB_CLK_GAT, data); 1554 1555 data = RREG32(mmATC_MISC_CG); 1556 data &= ~ATC_MISC_CG__ENABLE_MASK; 1557 WREG32(mmATC_MISC_CG, data); 1558 1559 data = RREG32(mmMC_CITF_MISC_WR_CG); 1560 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK; 1561 WREG32(mmMC_CITF_MISC_WR_CG, data); 1562 1563 data = RREG32(mmMC_CITF_MISC_RD_CG); 1564 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK; 1565 WREG32(mmMC_CITF_MISC_RD_CG, data); 1566 1567 data = RREG32(mmMC_CITF_MISC_VM_CG); 1568 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK; 1569 WREG32(mmMC_CITF_MISC_VM_CG, data); 1570 1571 data = RREG32(mmVM_L2_CG); 1572 data &= ~VM_L2_CG__ENABLE_MASK; 1573 WREG32(mmVM_L2_CG, data); 1574 } 1575 } 1576 1577 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev, 1578 bool enable) 1579 { 1580 uint32_t data; 1581 1582 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) { 1583 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1584 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1585 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1586 1587 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1588 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1589 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1590 1591 data = RREG32(mmMC_HUB_MISC_VM_CG); 1592 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1593 WREG32(mmMC_HUB_MISC_VM_CG, data); 1594 1595 data = RREG32(mmMC_XPB_CLK_GAT); 1596 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1597 WREG32(mmMC_XPB_CLK_GAT, data); 1598 1599 data = RREG32(mmATC_MISC_CG); 1600 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1601 WREG32(mmATC_MISC_CG, data); 1602 1603 data = RREG32(mmMC_CITF_MISC_WR_CG); 1604 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1605 WREG32(mmMC_CITF_MISC_WR_CG, data); 1606 1607 data = RREG32(mmMC_CITF_MISC_RD_CG); 1608 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1609 WREG32(mmMC_CITF_MISC_RD_CG, data); 1610 1611 data = RREG32(mmMC_CITF_MISC_VM_CG); 1612 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1613 WREG32(mmMC_CITF_MISC_VM_CG, data); 1614 1615 data = RREG32(mmVM_L2_CG); 1616 data |= VM_L2_CG__MEM_LS_ENABLE_MASK; 1617 WREG32(mmVM_L2_CG, data); 1618 } else { 1619 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1620 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1621 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1622 1623 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1624 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1625 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1626 1627 data = RREG32(mmMC_HUB_MISC_VM_CG); 1628 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1629 WREG32(mmMC_HUB_MISC_VM_CG, data); 1630 1631 data = RREG32(mmMC_XPB_CLK_GAT); 1632 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1633 WREG32(mmMC_XPB_CLK_GAT, data); 1634 1635 data = RREG32(mmATC_MISC_CG); 1636 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1637 WREG32(mmATC_MISC_CG, data); 1638 1639 data = RREG32(mmMC_CITF_MISC_WR_CG); 1640 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1641 WREG32(mmMC_CITF_MISC_WR_CG, data); 1642 1643 data = RREG32(mmMC_CITF_MISC_RD_CG); 1644 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1645 WREG32(mmMC_CITF_MISC_RD_CG, data); 1646 1647 data = RREG32(mmMC_CITF_MISC_VM_CG); 1648 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1649 WREG32(mmMC_CITF_MISC_VM_CG, data); 1650 1651 data = RREG32(mmVM_L2_CG); 1652 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK; 1653 WREG32(mmVM_L2_CG, data); 1654 } 1655 } 1656 1657 static int gmc_v8_0_set_clockgating_state(void *handle, 1658 enum amd_clockgating_state state) 1659 { 1660 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1661 1662 if (amdgpu_sriov_vf(adev)) 1663 return 0; 1664 1665 switch (adev->asic_type) { 1666 case CHIP_FIJI: 1667 fiji_update_mc_medium_grain_clock_gating(adev, 1668 state == AMD_CG_STATE_GATE); 1669 fiji_update_mc_light_sleep(adev, 1670 state == AMD_CG_STATE_GATE); 1671 break; 1672 default: 1673 break; 1674 } 1675 return 0; 1676 } 1677 1678 static int gmc_v8_0_set_powergating_state(void *handle, 1679 enum amd_powergating_state state) 1680 { 1681 return 0; 1682 } 1683 1684 static void gmc_v8_0_get_clockgating_state(void *handle, u64 *flags) 1685 { 1686 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1687 int data; 1688 1689 if (amdgpu_sriov_vf(adev)) 1690 *flags = 0; 1691 1692 /* AMD_CG_SUPPORT_MC_MGCG */ 1693 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1694 if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK) 1695 *flags |= AMD_CG_SUPPORT_MC_MGCG; 1696 1697 /* AMD_CG_SUPPORT_MC_LS */ 1698 if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK) 1699 *flags |= AMD_CG_SUPPORT_MC_LS; 1700 } 1701 1702 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = { 1703 .name = "gmc_v8_0", 1704 .early_init = gmc_v8_0_early_init, 1705 .late_init = gmc_v8_0_late_init, 1706 .sw_init = gmc_v8_0_sw_init, 1707 .sw_fini = gmc_v8_0_sw_fini, 1708 .hw_init = gmc_v8_0_hw_init, 1709 .hw_fini = gmc_v8_0_hw_fini, 1710 .suspend = gmc_v8_0_suspend, 1711 .resume = gmc_v8_0_resume, 1712 .is_idle = gmc_v8_0_is_idle, 1713 .wait_for_idle = gmc_v8_0_wait_for_idle, 1714 .check_soft_reset = gmc_v8_0_check_soft_reset, 1715 .pre_soft_reset = gmc_v8_0_pre_soft_reset, 1716 .soft_reset = gmc_v8_0_soft_reset, 1717 .post_soft_reset = gmc_v8_0_post_soft_reset, 1718 .set_clockgating_state = gmc_v8_0_set_clockgating_state, 1719 .set_powergating_state = gmc_v8_0_set_powergating_state, 1720 .get_clockgating_state = gmc_v8_0_get_clockgating_state, 1721 }; 1722 1723 static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = { 1724 .flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb, 1725 .flush_gpu_tlb_pasid = gmc_v8_0_flush_gpu_tlb_pasid, 1726 .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb, 1727 .emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping, 1728 .set_prt = gmc_v8_0_set_prt, 1729 .get_vm_pde = gmc_v8_0_get_vm_pde, 1730 .get_vm_pte = gmc_v8_0_get_vm_pte, 1731 .get_vbios_fb_size = gmc_v8_0_get_vbios_fb_size, 1732 }; 1733 1734 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = { 1735 .set = gmc_v8_0_vm_fault_interrupt_state, 1736 .process = gmc_v8_0_process_interrupt, 1737 }; 1738 1739 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev) 1740 { 1741 adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs; 1742 } 1743 1744 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev) 1745 { 1746 adev->gmc.vm_fault.num_types = 1; 1747 adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs; 1748 } 1749 1750 const struct amdgpu_ip_block_version gmc_v8_0_ip_block = 1751 { 1752 .type = AMD_IP_BLOCK_TYPE_GMC, 1753 .major = 8, 1754 .minor = 0, 1755 .rev = 0, 1756 .funcs = &gmc_v8_0_ip_funcs, 1757 }; 1758 1759 const struct amdgpu_ip_block_version gmc_v8_1_ip_block = 1760 { 1761 .type = AMD_IP_BLOCK_TYPE_GMC, 1762 .major = 8, 1763 .minor = 1, 1764 .rev = 0, 1765 .funcs = &gmc_v8_0_ip_funcs, 1766 }; 1767 1768 const struct amdgpu_ip_block_version gmc_v8_5_ip_block = 1769 { 1770 .type = AMD_IP_BLOCK_TYPE_GMC, 1771 .major = 8, 1772 .minor = 5, 1773 .rev = 0, 1774 .funcs = &gmc_v8_0_ip_funcs, 1775 }; 1776