1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <drm/drmP.h> 25 #include <drm/drm_cache.h> 26 #include "amdgpu.h" 27 #include "gmc_v8_0.h" 28 #include "amdgpu_ucode.h" 29 #include "amdgpu_amdkfd.h" 30 #include "amdgpu_gem.h" 31 32 #include "gmc/gmc_8_1_d.h" 33 #include "gmc/gmc_8_1_sh_mask.h" 34 35 #include "bif/bif_5_0_d.h" 36 #include "bif/bif_5_0_sh_mask.h" 37 38 #include "oss/oss_3_0_d.h" 39 #include "oss/oss_3_0_sh_mask.h" 40 41 #include "dce/dce_10_0_d.h" 42 #include "dce/dce_10_0_sh_mask.h" 43 44 #include "vid.h" 45 #include "vi.h" 46 47 #include "amdgpu_atombios.h" 48 49 #include "ivsrcid/ivsrcid_vislands30.h" 50 51 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev); 52 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev); 53 static int gmc_v8_0_wait_for_idle(void *handle); 54 55 MODULE_FIRMWARE("amdgpu/tonga_mc.bin"); 56 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin"); 57 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin"); 58 MODULE_FIRMWARE("amdgpu/polaris12_mc.bin"); 59 MODULE_FIRMWARE("amdgpu/polaris11_k_mc.bin"); 60 MODULE_FIRMWARE("amdgpu/polaris10_k_mc.bin"); 61 MODULE_FIRMWARE("amdgpu/polaris12_k_mc.bin"); 62 63 static const u32 golden_settings_tonga_a11[] = 64 { 65 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, 66 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028, 67 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991, 68 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 69 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 70 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 71 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 72 }; 73 74 static const u32 tonga_mgcg_cgcg_init[] = 75 { 76 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 77 }; 78 79 static const u32 golden_settings_fiji_a10[] = 80 { 81 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 82 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 83 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 84 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 85 }; 86 87 static const u32 fiji_mgcg_cgcg_init[] = 88 { 89 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 90 }; 91 92 static const u32 golden_settings_polaris11_a11[] = 93 { 94 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 95 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 96 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 97 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 98 }; 99 100 static const u32 golden_settings_polaris10_a11[] = 101 { 102 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, 103 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 104 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 105 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 106 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 107 }; 108 109 static const u32 cz_mgcg_cgcg_init[] = 110 { 111 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 112 }; 113 114 static const u32 stoney_mgcg_cgcg_init[] = 115 { 116 mmATC_MISC_CG, 0xffffffff, 0x000c0200, 117 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 118 }; 119 120 static const u32 golden_settings_stoney_common[] = 121 { 122 mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004, 123 mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000 124 }; 125 126 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) 127 { 128 switch (adev->asic_type) { 129 case CHIP_FIJI: 130 amdgpu_device_program_register_sequence(adev, 131 fiji_mgcg_cgcg_init, 132 ARRAY_SIZE(fiji_mgcg_cgcg_init)); 133 amdgpu_device_program_register_sequence(adev, 134 golden_settings_fiji_a10, 135 ARRAY_SIZE(golden_settings_fiji_a10)); 136 break; 137 case CHIP_TONGA: 138 amdgpu_device_program_register_sequence(adev, 139 tonga_mgcg_cgcg_init, 140 ARRAY_SIZE(tonga_mgcg_cgcg_init)); 141 amdgpu_device_program_register_sequence(adev, 142 golden_settings_tonga_a11, 143 ARRAY_SIZE(golden_settings_tonga_a11)); 144 break; 145 case CHIP_POLARIS11: 146 case CHIP_POLARIS12: 147 case CHIP_VEGAM: 148 amdgpu_device_program_register_sequence(adev, 149 golden_settings_polaris11_a11, 150 ARRAY_SIZE(golden_settings_polaris11_a11)); 151 break; 152 case CHIP_POLARIS10: 153 amdgpu_device_program_register_sequence(adev, 154 golden_settings_polaris10_a11, 155 ARRAY_SIZE(golden_settings_polaris10_a11)); 156 break; 157 case CHIP_CARRIZO: 158 amdgpu_device_program_register_sequence(adev, 159 cz_mgcg_cgcg_init, 160 ARRAY_SIZE(cz_mgcg_cgcg_init)); 161 break; 162 case CHIP_STONEY: 163 amdgpu_device_program_register_sequence(adev, 164 stoney_mgcg_cgcg_init, 165 ARRAY_SIZE(stoney_mgcg_cgcg_init)); 166 amdgpu_device_program_register_sequence(adev, 167 golden_settings_stoney_common, 168 ARRAY_SIZE(golden_settings_stoney_common)); 169 break; 170 default: 171 break; 172 } 173 } 174 175 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev) 176 { 177 u32 blackout; 178 179 gmc_v8_0_wait_for_idle(adev); 180 181 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 182 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 183 /* Block CPU access */ 184 WREG32(mmBIF_FB_EN, 0); 185 /* blackout the MC */ 186 blackout = REG_SET_FIELD(blackout, 187 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1); 188 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout); 189 } 190 /* wait for the MC to settle */ 191 udelay(100); 192 } 193 194 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev) 195 { 196 u32 tmp; 197 198 /* unblackout the MC */ 199 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 200 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 201 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 202 /* allow CPU access */ 203 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 204 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 205 WREG32(mmBIF_FB_EN, tmp); 206 } 207 208 /** 209 * gmc_v8_0_init_microcode - load ucode images from disk 210 * 211 * @adev: amdgpu_device pointer 212 * 213 * Use the firmware interface to load the ucode images into 214 * the driver (not loaded into hw). 215 * Returns 0 on success, error on failure. 216 */ 217 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) 218 { 219 const char *chip_name; 220 char fw_name[30]; 221 int err; 222 223 DRM_DEBUG("\n"); 224 225 switch (adev->asic_type) { 226 case CHIP_TONGA: 227 chip_name = "tonga"; 228 break; 229 case CHIP_POLARIS11: 230 if (((adev->pdev->device == 0x67ef) && 231 ((adev->pdev->revision == 0xe0) || 232 (adev->pdev->revision == 0xe5))) || 233 ((adev->pdev->device == 0x67ff) && 234 ((adev->pdev->revision == 0xcf) || 235 (adev->pdev->revision == 0xef) || 236 (adev->pdev->revision == 0xff)))) 237 chip_name = "polaris11_k"; 238 else if ((adev->pdev->device == 0x67ef) && 239 (adev->pdev->revision == 0xe2)) 240 chip_name = "polaris11_k"; 241 else 242 chip_name = "polaris11"; 243 break; 244 case CHIP_POLARIS10: 245 if ((adev->pdev->device == 0x67df) && 246 ((adev->pdev->revision == 0xe1) || 247 (adev->pdev->revision == 0xf7))) 248 chip_name = "polaris10_k"; 249 else 250 chip_name = "polaris10"; 251 break; 252 case CHIP_POLARIS12: 253 if (((adev->pdev->device == 0x6987) && 254 ((adev->pdev->revision == 0xc0) || 255 (adev->pdev->revision == 0xc3))) || 256 ((adev->pdev->device == 0x6981) && 257 ((adev->pdev->revision == 0x00) || 258 (adev->pdev->revision == 0x01) || 259 (adev->pdev->revision == 0x10)))) 260 chip_name = "polaris12_k"; 261 else 262 chip_name = "polaris12"; 263 break; 264 case CHIP_FIJI: 265 case CHIP_CARRIZO: 266 case CHIP_STONEY: 267 case CHIP_VEGAM: 268 return 0; 269 default: BUG(); 270 } 271 272 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name); 273 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); 274 if (err) 275 goto out; 276 err = amdgpu_ucode_validate(adev->gmc.fw); 277 278 out: 279 if (err) { 280 pr_err("mc: Failed to load firmware \"%s\"\n", fw_name); 281 release_firmware(adev->gmc.fw); 282 adev->gmc.fw = NULL; 283 } 284 return err; 285 } 286 287 /** 288 * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw 289 * 290 * @adev: amdgpu_device pointer 291 * 292 * Load the GDDR MC ucode into the hw (CIK). 293 * Returns 0 on success, error on failure. 294 */ 295 static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev) 296 { 297 const struct mc_firmware_header_v1_0 *hdr; 298 const __le32 *fw_data = NULL; 299 const __le32 *io_mc_regs = NULL; 300 u32 running; 301 int i, ucode_size, regs_size; 302 303 /* Skip MC ucode loading on SR-IOV capable boards. 304 * vbios does this for us in asic_init in that case. 305 * Skip MC ucode loading on VF, because hypervisor will do that 306 * for this adaptor. 307 */ 308 if (amdgpu_sriov_bios(adev)) 309 return 0; 310 311 if (!adev->gmc.fw) 312 return -EINVAL; 313 314 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 315 amdgpu_ucode_print_mc_hdr(&hdr->header); 316 317 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 318 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 319 io_mc_regs = (const __le32 *) 320 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 321 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 322 fw_data = (const __le32 *) 323 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 324 325 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); 326 327 if (running == 0) { 328 /* reset the engine and set to writable */ 329 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 330 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 331 332 /* load mc io regs */ 333 for (i = 0; i < regs_size; i++) { 334 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 335 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 336 } 337 /* load the MC ucode */ 338 for (i = 0; i < ucode_size; i++) 339 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 340 341 /* put the engine back into the active state */ 342 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 343 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 344 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 345 346 /* wait for training to complete */ 347 for (i = 0; i < adev->usec_timeout; i++) { 348 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 349 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0)) 350 break; 351 udelay(1); 352 } 353 for (i = 0; i < adev->usec_timeout; i++) { 354 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 355 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1)) 356 break; 357 udelay(1); 358 } 359 } 360 361 return 0; 362 } 363 364 static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev) 365 { 366 const struct mc_firmware_header_v1_0 *hdr; 367 const __le32 *fw_data = NULL; 368 const __le32 *io_mc_regs = NULL; 369 u32 data; 370 int i, ucode_size, regs_size; 371 372 /* Skip MC ucode loading on SR-IOV capable boards. 373 * vbios does this for us in asic_init in that case. 374 * Skip MC ucode loading on VF, because hypervisor will do that 375 * for this adaptor. 376 */ 377 if (amdgpu_sriov_bios(adev)) 378 return 0; 379 380 if (!adev->gmc.fw) 381 return -EINVAL; 382 383 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 384 amdgpu_ucode_print_mc_hdr(&hdr->header); 385 386 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 387 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 388 io_mc_regs = (const __le32 *) 389 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 390 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 391 fw_data = (const __le32 *) 392 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 393 394 data = RREG32(mmMC_SEQ_MISC0); 395 data &= ~(0x40); 396 WREG32(mmMC_SEQ_MISC0, data); 397 398 /* load mc io regs */ 399 for (i = 0; i < regs_size; i++) { 400 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 401 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 402 } 403 404 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 405 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 406 407 /* load the MC ucode */ 408 for (i = 0; i < ucode_size; i++) 409 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 410 411 /* put the engine back into the active state */ 412 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 413 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 414 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 415 416 /* wait for training to complete */ 417 for (i = 0; i < adev->usec_timeout; i++) { 418 data = RREG32(mmMC_SEQ_MISC0); 419 if (data & 0x80) 420 break; 421 udelay(1); 422 } 423 424 return 0; 425 } 426 427 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev, 428 struct amdgpu_gmc *mc) 429 { 430 u64 base = 0; 431 432 if (!amdgpu_sriov_vf(adev)) 433 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; 434 base <<= 24; 435 436 amdgpu_gmc_vram_location(adev, mc, base); 437 amdgpu_gmc_gart_location(adev, mc); 438 } 439 440 /** 441 * gmc_v8_0_mc_program - program the GPU memory controller 442 * 443 * @adev: amdgpu_device pointer 444 * 445 * Set the location of vram, gart, and AGP in the GPU's 446 * physical address space (CIK). 447 */ 448 static void gmc_v8_0_mc_program(struct amdgpu_device *adev) 449 { 450 u32 tmp; 451 int i, j; 452 453 /* Initialize HDP */ 454 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 455 WREG32((0xb05 + j), 0x00000000); 456 WREG32((0xb06 + j), 0x00000000); 457 WREG32((0xb07 + j), 0x00000000); 458 WREG32((0xb08 + j), 0x00000000); 459 WREG32((0xb09 + j), 0x00000000); 460 } 461 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 462 463 if (gmc_v8_0_wait_for_idle((void *)adev)) { 464 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 465 } 466 if (adev->mode_info.num_crtc) { 467 /* Lockout access through VGA aperture*/ 468 tmp = RREG32(mmVGA_HDP_CONTROL); 469 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 470 WREG32(mmVGA_HDP_CONTROL, tmp); 471 472 /* disable VGA render */ 473 tmp = RREG32(mmVGA_RENDER_CONTROL); 474 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 475 WREG32(mmVGA_RENDER_CONTROL, tmp); 476 } 477 /* Update configuration */ 478 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 479 adev->gmc.vram_start >> 12); 480 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 481 adev->gmc.vram_end >> 12); 482 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 483 adev->vram_scratch.gpu_addr >> 12); 484 485 if (amdgpu_sriov_vf(adev)) { 486 tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16; 487 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF); 488 WREG32(mmMC_VM_FB_LOCATION, tmp); 489 /* XXX double check these! */ 490 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); 491 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); 492 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF); 493 } 494 495 WREG32(mmMC_VM_AGP_BASE, 0); 496 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); 497 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); 498 if (gmc_v8_0_wait_for_idle((void *)adev)) { 499 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 500 } 501 502 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 503 504 tmp = RREG32(mmHDP_MISC_CNTL); 505 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); 506 WREG32(mmHDP_MISC_CNTL, tmp); 507 508 tmp = RREG32(mmHDP_HOST_PATH_CNTL); 509 WREG32(mmHDP_HOST_PATH_CNTL, tmp); 510 } 511 512 /** 513 * gmc_v8_0_mc_init - initialize the memory controller driver params 514 * 515 * @adev: amdgpu_device pointer 516 * 517 * Look up the amount of vram, vram width, and decide how to place 518 * vram and gart within the GPU's physical address space (CIK). 519 * Returns 0 for success. 520 */ 521 static int gmc_v8_0_mc_init(struct amdgpu_device *adev) 522 { 523 int r; 524 525 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev); 526 if (!adev->gmc.vram_width) { 527 u32 tmp; 528 int chansize, numchan; 529 530 /* Get VRAM informations */ 531 tmp = RREG32(mmMC_ARB_RAMCFG); 532 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { 533 chansize = 64; 534 } else { 535 chansize = 32; 536 } 537 tmp = RREG32(mmMC_SHARED_CHMAP); 538 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 539 case 0: 540 default: 541 numchan = 1; 542 break; 543 case 1: 544 numchan = 2; 545 break; 546 case 2: 547 numchan = 4; 548 break; 549 case 3: 550 numchan = 8; 551 break; 552 case 4: 553 numchan = 3; 554 break; 555 case 5: 556 numchan = 6; 557 break; 558 case 6: 559 numchan = 10; 560 break; 561 case 7: 562 numchan = 12; 563 break; 564 case 8: 565 numchan = 16; 566 break; 567 } 568 adev->gmc.vram_width = numchan * chansize; 569 } 570 /* size in MB on si */ 571 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 572 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 573 574 if (!(adev->flags & AMD_IS_APU)) { 575 r = amdgpu_device_resize_fb_bar(adev); 576 if (r) 577 return r; 578 } 579 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 580 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 581 582 #ifdef CONFIG_X86_64 583 if (adev->flags & AMD_IS_APU) { 584 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; 585 adev->gmc.aper_size = adev->gmc.real_vram_size; 586 } 587 #endif 588 589 /* In case the PCI BAR is larger than the actual amount of vram */ 590 adev->gmc.visible_vram_size = adev->gmc.aper_size; 591 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 592 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 593 594 /* set the gart size */ 595 if (amdgpu_gart_size == -1) { 596 switch (adev->asic_type) { 597 case CHIP_POLARIS10: /* all engines support GPUVM */ 598 case CHIP_POLARIS11: /* all engines support GPUVM */ 599 case CHIP_POLARIS12: /* all engines support GPUVM */ 600 case CHIP_VEGAM: /* all engines support GPUVM */ 601 default: 602 adev->gmc.gart_size = 256ULL << 20; 603 break; 604 case CHIP_TONGA: /* UVD, VCE do not support GPUVM */ 605 case CHIP_FIJI: /* UVD, VCE do not support GPUVM */ 606 case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */ 607 case CHIP_STONEY: /* UVD does not support GPUVM, DCE SG support */ 608 adev->gmc.gart_size = 1024ULL << 20; 609 break; 610 } 611 } else { 612 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 613 } 614 615 gmc_v8_0_vram_gtt_location(adev, &adev->gmc); 616 617 return 0; 618 } 619 620 /* 621 * GART 622 * VMID 0 is the physical GPU addresses as used by the kernel. 623 * VMIDs 1-15 are used for userspace clients and are handled 624 * by the amdgpu vm/hsa code. 625 */ 626 627 /** 628 * gmc_v8_0_flush_gpu_tlb - gart tlb flush callback 629 * 630 * @adev: amdgpu_device pointer 631 * @vmid: vm instance to flush 632 * 633 * Flush the TLB for the requested page table (CIK). 634 */ 635 static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev, 636 uint32_t vmid, uint32_t flush_type) 637 { 638 /* bits 0-15 are the VM contexts0-15 */ 639 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 640 } 641 642 static uint64_t gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 643 unsigned vmid, uint64_t pd_addr) 644 { 645 uint32_t reg; 646 647 if (vmid < 8) 648 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; 649 else 650 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8; 651 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); 652 653 /* bits 0-15 are the VM contexts0-15 */ 654 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); 655 656 return pd_addr; 657 } 658 659 static void gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 660 unsigned pasid) 661 { 662 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); 663 } 664 665 /* 666 * PTE format on VI: 667 * 63:40 reserved 668 * 39:12 4k physical page base address 669 * 11:7 fragment 670 * 6 write 671 * 5 read 672 * 4 exe 673 * 3 reserved 674 * 2 snooped 675 * 1 system 676 * 0 valid 677 * 678 * PDE format on VI: 679 * 63:59 block fragment size 680 * 58:40 reserved 681 * 39:1 physical base address of PTE 682 * bits 5:1 must be 0. 683 * 0 valid 684 */ 685 686 static uint64_t gmc_v8_0_get_vm_pte_flags(struct amdgpu_device *adev, 687 uint32_t flags) 688 { 689 uint64_t pte_flag = 0; 690 691 if (flags & AMDGPU_VM_PAGE_EXECUTABLE) 692 pte_flag |= AMDGPU_PTE_EXECUTABLE; 693 if (flags & AMDGPU_VM_PAGE_READABLE) 694 pte_flag |= AMDGPU_PTE_READABLE; 695 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 696 pte_flag |= AMDGPU_PTE_WRITEABLE; 697 if (flags & AMDGPU_VM_PAGE_PRT) 698 pte_flag |= AMDGPU_PTE_PRT; 699 700 return pte_flag; 701 } 702 703 static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level, 704 uint64_t *addr, uint64_t *flags) 705 { 706 BUG_ON(*addr & 0xFFFFFF0000000FFFULL); 707 } 708 709 /** 710 * gmc_v8_0_set_fault_enable_default - update VM fault handling 711 * 712 * @adev: amdgpu_device pointer 713 * @value: true redirects VM faults to the default page 714 */ 715 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev, 716 bool value) 717 { 718 u32 tmp; 719 720 tmp = RREG32(mmVM_CONTEXT1_CNTL); 721 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 722 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 723 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 724 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 725 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 726 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 727 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 728 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 729 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 730 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 731 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 732 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 733 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 734 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 735 WREG32(mmVM_CONTEXT1_CNTL, tmp); 736 } 737 738 /** 739 * gmc_v8_0_set_prt - set PRT VM fault 740 * 741 * @adev: amdgpu_device pointer 742 * @enable: enable/disable VM fault handling for PRT 743 */ 744 static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable) 745 { 746 u32 tmp; 747 748 if (enable && !adev->gmc.prt_warning) { 749 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 750 adev->gmc.prt_warning = true; 751 } 752 753 tmp = RREG32(mmVM_PRT_CNTL); 754 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 755 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 756 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 757 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 758 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 759 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 760 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 761 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 762 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 763 L2_CACHE_STORE_INVALID_ENTRIES, enable); 764 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 765 L1_TLB_STORE_INVALID_ENTRIES, enable); 766 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 767 MASK_PDE0_FAULT, enable); 768 WREG32(mmVM_PRT_CNTL, tmp); 769 770 if (enable) { 771 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; 772 uint32_t high = adev->vm_manager.max_pfn - 773 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT); 774 775 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); 776 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); 777 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); 778 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); 779 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); 780 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); 781 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); 782 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); 783 } else { 784 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); 785 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); 786 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); 787 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); 788 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); 789 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); 790 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); 791 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); 792 } 793 } 794 795 /** 796 * gmc_v8_0_gart_enable - gart enable 797 * 798 * @adev: amdgpu_device pointer 799 * 800 * This sets up the TLBs, programs the page tables for VMID0, 801 * sets up the hw for VMIDs 1-15 which are allocated on 802 * demand, and sets up the global locations for the LDS, GDS, 803 * and GPUVM for FSA64 clients (CIK). 804 * Returns 0 for success, errors for failure. 805 */ 806 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) 807 { 808 uint64_t table_addr; 809 int r, i; 810 u32 tmp, field; 811 812 if (adev->gart.bo == NULL) { 813 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 814 return -EINVAL; 815 } 816 r = amdgpu_gart_table_vram_pin(adev); 817 if (r) 818 return r; 819 820 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 821 822 /* Setup TLB control */ 823 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 824 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 825 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); 826 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 827 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); 828 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 829 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 830 /* Setup L2 cache */ 831 tmp = RREG32(mmVM_L2_CNTL); 832 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 833 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 834 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); 835 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); 836 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); 837 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 838 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 839 WREG32(mmVM_L2_CNTL, tmp); 840 tmp = RREG32(mmVM_L2_CNTL2); 841 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 842 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 843 WREG32(mmVM_L2_CNTL2, tmp); 844 845 field = adev->vm_manager.fragment_size; 846 tmp = RREG32(mmVM_L2_CNTL3); 847 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); 848 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); 849 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); 850 WREG32(mmVM_L2_CNTL3, tmp); 851 /* XXX: set to enable PTE/PDE in system memory */ 852 tmp = RREG32(mmVM_L2_CNTL4); 853 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0); 854 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0); 855 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0); 856 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0); 857 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0); 858 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0); 859 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0); 860 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0); 861 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0); 862 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0); 863 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0); 864 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0); 865 WREG32(mmVM_L2_CNTL4, tmp); 866 /* setup context0 */ 867 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); 868 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); 869 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12); 870 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 871 (u32)(adev->dummy_page_addr >> 12)); 872 WREG32(mmVM_CONTEXT0_CNTL2, 0); 873 tmp = RREG32(mmVM_CONTEXT0_CNTL); 874 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 875 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 876 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 877 WREG32(mmVM_CONTEXT0_CNTL, tmp); 878 879 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0); 880 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0); 881 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0); 882 883 /* empty context1-15 */ 884 /* FIXME start with 4G, once using 2 level pt switch to full 885 * vm size space 886 */ 887 /* set vm size, must be a multiple of 4 */ 888 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 889 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 890 for (i = 1; i < 16; i++) { 891 if (i < 8) 892 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 893 table_addr >> 12); 894 else 895 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 896 table_addr >> 12); 897 } 898 899 /* enable context1-15 */ 900 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 901 (u32)(adev->dummy_page_addr >> 12)); 902 WREG32(mmVM_CONTEXT1_CNTL2, 4); 903 tmp = RREG32(mmVM_CONTEXT1_CNTL); 904 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 905 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); 906 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 907 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 908 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 909 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 910 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 911 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 912 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 913 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, 914 adev->vm_manager.block_size - 9); 915 WREG32(mmVM_CONTEXT1_CNTL, tmp); 916 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 917 gmc_v8_0_set_fault_enable_default(adev, false); 918 else 919 gmc_v8_0_set_fault_enable_default(adev, true); 920 921 gmc_v8_0_flush_gpu_tlb(adev, 0, 0); 922 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 923 (unsigned)(adev->gmc.gart_size >> 20), 924 (unsigned long long)table_addr); 925 adev->gart.ready = true; 926 return 0; 927 } 928 929 static int gmc_v8_0_gart_init(struct amdgpu_device *adev) 930 { 931 int r; 932 933 if (adev->gart.bo) { 934 WARN(1, "R600 PCIE GART already initialized\n"); 935 return 0; 936 } 937 /* Initialize common gart structure */ 938 r = amdgpu_gart_init(adev); 939 if (r) 940 return r; 941 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 942 adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE; 943 return amdgpu_gart_table_vram_alloc(adev); 944 } 945 946 /** 947 * gmc_v8_0_gart_disable - gart disable 948 * 949 * @adev: amdgpu_device pointer 950 * 951 * This disables all VM page table (CIK). 952 */ 953 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev) 954 { 955 u32 tmp; 956 957 /* Disable all tables */ 958 WREG32(mmVM_CONTEXT0_CNTL, 0); 959 WREG32(mmVM_CONTEXT1_CNTL, 0); 960 /* Setup TLB control */ 961 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 962 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 963 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); 964 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); 965 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 966 /* Setup L2 cache */ 967 tmp = RREG32(mmVM_L2_CNTL); 968 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 969 WREG32(mmVM_L2_CNTL, tmp); 970 WREG32(mmVM_L2_CNTL2, 0); 971 amdgpu_gart_table_vram_unpin(adev); 972 } 973 974 /** 975 * gmc_v8_0_vm_decode_fault - print human readable fault info 976 * 977 * @adev: amdgpu_device pointer 978 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value 979 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value 980 * 981 * Print human readable fault information (CIK). 982 */ 983 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32 status, 984 u32 addr, u32 mc_client, unsigned pasid) 985 { 986 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 987 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 988 PROTECTIONS); 989 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 990 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 991 u32 mc_id; 992 993 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 994 MEMORY_CLIENT_ID); 995 996 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 997 protections, vmid, pasid, addr, 998 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 999 MEMORY_CLIENT_RW) ? 1000 "write" : "read", block, mc_client, mc_id); 1001 } 1002 1003 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type) 1004 { 1005 switch (mc_seq_vram_type) { 1006 case MC_SEQ_MISC0__MT__GDDR1: 1007 return AMDGPU_VRAM_TYPE_GDDR1; 1008 case MC_SEQ_MISC0__MT__DDR2: 1009 return AMDGPU_VRAM_TYPE_DDR2; 1010 case MC_SEQ_MISC0__MT__GDDR3: 1011 return AMDGPU_VRAM_TYPE_GDDR3; 1012 case MC_SEQ_MISC0__MT__GDDR4: 1013 return AMDGPU_VRAM_TYPE_GDDR4; 1014 case MC_SEQ_MISC0__MT__GDDR5: 1015 return AMDGPU_VRAM_TYPE_GDDR5; 1016 case MC_SEQ_MISC0__MT__HBM: 1017 return AMDGPU_VRAM_TYPE_HBM; 1018 case MC_SEQ_MISC0__MT__DDR3: 1019 return AMDGPU_VRAM_TYPE_DDR3; 1020 default: 1021 return AMDGPU_VRAM_TYPE_UNKNOWN; 1022 } 1023 } 1024 1025 static int gmc_v8_0_early_init(void *handle) 1026 { 1027 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1028 1029 gmc_v8_0_set_gmc_funcs(adev); 1030 gmc_v8_0_set_irq_funcs(adev); 1031 1032 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1033 adev->gmc.shared_aperture_end = 1034 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1035 adev->gmc.private_aperture_start = 1036 adev->gmc.shared_aperture_end + 1; 1037 adev->gmc.private_aperture_end = 1038 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1039 1040 return 0; 1041 } 1042 1043 static int gmc_v8_0_late_init(void *handle) 1044 { 1045 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1046 1047 amdgpu_bo_late_init(adev); 1048 1049 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 1050 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1051 else 1052 return 0; 1053 } 1054 1055 static unsigned gmc_v8_0_get_vbios_fb_size(struct amdgpu_device *adev) 1056 { 1057 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); 1058 unsigned size; 1059 1060 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1061 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */ 1062 } else { 1063 u32 viewport = RREG32(mmVIEWPORT_SIZE); 1064 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1065 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1066 4); 1067 } 1068 /* return 0 if the pre-OS buffer uses up most of vram */ 1069 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 1070 return 0; 1071 return size; 1072 } 1073 1074 #define mmMC_SEQ_MISC0_FIJI 0xA71 1075 1076 static int gmc_v8_0_sw_init(void *handle) 1077 { 1078 int r; 1079 int dma_bits; 1080 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1081 1082 if (adev->flags & AMD_IS_APU) { 1083 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 1084 } else { 1085 u32 tmp; 1086 1087 if ((adev->asic_type == CHIP_FIJI) || 1088 (adev->asic_type == CHIP_VEGAM)) 1089 tmp = RREG32(mmMC_SEQ_MISC0_FIJI); 1090 else 1091 tmp = RREG32(mmMC_SEQ_MISC0); 1092 tmp &= MC_SEQ_MISC0__MT__MASK; 1093 adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp); 1094 } 1095 1096 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault); 1097 if (r) 1098 return r; 1099 1100 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault); 1101 if (r) 1102 return r; 1103 1104 /* Adjust VM size here. 1105 * Currently set to 4GB ((1 << 20) 4k pages). 1106 * Max GPUVM size for cayman and SI is 40 bits. 1107 */ 1108 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); 1109 1110 /* Set the internal MC address mask 1111 * This is the max address of the GPU's 1112 * internal address space. 1113 */ 1114 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1115 1116 /* set DMA mask + need_dma32 flags. 1117 * PCIE - can handle 40-bits. 1118 * IGP - can handle 40-bits 1119 * PCI - dma32 for legacy pci gart, 40 bits on newer asics 1120 */ 1121 adev->need_dma32 = false; 1122 dma_bits = adev->need_dma32 ? 32 : 40; 1123 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 1124 if (r) { 1125 adev->need_dma32 = true; 1126 dma_bits = 32; 1127 pr_warn("amdgpu: No suitable DMA available\n"); 1128 } 1129 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 1130 if (r) { 1131 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); 1132 pr_warn("amdgpu: No coherent DMA available\n"); 1133 } 1134 adev->need_swiotlb = drm_need_swiotlb(dma_bits); 1135 1136 r = gmc_v8_0_init_microcode(adev); 1137 if (r) { 1138 DRM_ERROR("Failed to load mc firmware!\n"); 1139 return r; 1140 } 1141 1142 r = gmc_v8_0_mc_init(adev); 1143 if (r) 1144 return r; 1145 1146 adev->gmc.stolen_size = gmc_v8_0_get_vbios_fb_size(adev); 1147 1148 /* Memory manager */ 1149 r = amdgpu_bo_init(adev); 1150 if (r) 1151 return r; 1152 1153 r = gmc_v8_0_gart_init(adev); 1154 if (r) 1155 return r; 1156 1157 /* 1158 * number of VMs 1159 * VMID 0 is reserved for System 1160 * amdgpu graphics/compute will use VMIDs 1-7 1161 * amdkfd will use VMIDs 8-15 1162 */ 1163 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; 1164 amdgpu_vm_manager_init(adev); 1165 1166 /* base offset of vram pages */ 1167 if (adev->flags & AMD_IS_APU) { 1168 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 1169 1170 tmp <<= 22; 1171 adev->vm_manager.vram_base_offset = tmp; 1172 } else { 1173 adev->vm_manager.vram_base_offset = 0; 1174 } 1175 1176 adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info), 1177 GFP_KERNEL); 1178 if (!adev->gmc.vm_fault_info) 1179 return -ENOMEM; 1180 atomic_set(&adev->gmc.vm_fault_info_updated, 0); 1181 1182 return 0; 1183 } 1184 1185 static int gmc_v8_0_sw_fini(void *handle) 1186 { 1187 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1188 1189 amdgpu_gem_force_release(adev); 1190 amdgpu_vm_manager_fini(adev); 1191 kfree(adev->gmc.vm_fault_info); 1192 amdgpu_gart_table_vram_free(adev); 1193 amdgpu_bo_fini(adev); 1194 amdgpu_gart_fini(adev); 1195 release_firmware(adev->gmc.fw); 1196 adev->gmc.fw = NULL; 1197 1198 return 0; 1199 } 1200 1201 static int gmc_v8_0_hw_init(void *handle) 1202 { 1203 int r; 1204 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1205 1206 gmc_v8_0_init_golden_registers(adev); 1207 1208 gmc_v8_0_mc_program(adev); 1209 1210 if (adev->asic_type == CHIP_TONGA) { 1211 r = gmc_v8_0_tonga_mc_load_microcode(adev); 1212 if (r) { 1213 DRM_ERROR("Failed to load MC firmware!\n"); 1214 return r; 1215 } 1216 } else if (adev->asic_type == CHIP_POLARIS11 || 1217 adev->asic_type == CHIP_POLARIS10 || 1218 adev->asic_type == CHIP_POLARIS12) { 1219 r = gmc_v8_0_polaris_mc_load_microcode(adev); 1220 if (r) { 1221 DRM_ERROR("Failed to load MC firmware!\n"); 1222 return r; 1223 } 1224 } 1225 1226 r = gmc_v8_0_gart_enable(adev); 1227 if (r) 1228 return r; 1229 1230 return r; 1231 } 1232 1233 static int gmc_v8_0_hw_fini(void *handle) 1234 { 1235 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1236 1237 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1238 gmc_v8_0_gart_disable(adev); 1239 1240 return 0; 1241 } 1242 1243 static int gmc_v8_0_suspend(void *handle) 1244 { 1245 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1246 1247 gmc_v8_0_hw_fini(adev); 1248 1249 return 0; 1250 } 1251 1252 static int gmc_v8_0_resume(void *handle) 1253 { 1254 int r; 1255 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1256 1257 r = gmc_v8_0_hw_init(adev); 1258 if (r) 1259 return r; 1260 1261 amdgpu_vmid_reset_all(adev); 1262 1263 return 0; 1264 } 1265 1266 static bool gmc_v8_0_is_idle(void *handle) 1267 { 1268 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1269 u32 tmp = RREG32(mmSRBM_STATUS); 1270 1271 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1272 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 1273 return false; 1274 1275 return true; 1276 } 1277 1278 static int gmc_v8_0_wait_for_idle(void *handle) 1279 { 1280 unsigned i; 1281 u32 tmp; 1282 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1283 1284 for (i = 0; i < adev->usec_timeout; i++) { 1285 /* read MC_STATUS */ 1286 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | 1287 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1288 SRBM_STATUS__MCC_BUSY_MASK | 1289 SRBM_STATUS__MCD_BUSY_MASK | 1290 SRBM_STATUS__VMC_BUSY_MASK | 1291 SRBM_STATUS__VMC1_BUSY_MASK); 1292 if (!tmp) 1293 return 0; 1294 udelay(1); 1295 } 1296 return -ETIMEDOUT; 1297 1298 } 1299 1300 static bool gmc_v8_0_check_soft_reset(void *handle) 1301 { 1302 u32 srbm_soft_reset = 0; 1303 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1304 u32 tmp = RREG32(mmSRBM_STATUS); 1305 1306 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1307 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1308 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 1309 1310 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1311 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 1312 if (!(adev->flags & AMD_IS_APU)) 1313 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1314 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1315 } 1316 if (srbm_soft_reset) { 1317 adev->gmc.srbm_soft_reset = srbm_soft_reset; 1318 return true; 1319 } else { 1320 adev->gmc.srbm_soft_reset = 0; 1321 return false; 1322 } 1323 } 1324 1325 static int gmc_v8_0_pre_soft_reset(void *handle) 1326 { 1327 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1328 1329 if (!adev->gmc.srbm_soft_reset) 1330 return 0; 1331 1332 gmc_v8_0_mc_stop(adev); 1333 if (gmc_v8_0_wait_for_idle(adev)) { 1334 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1335 } 1336 1337 return 0; 1338 } 1339 1340 static int gmc_v8_0_soft_reset(void *handle) 1341 { 1342 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1343 u32 srbm_soft_reset; 1344 1345 if (!adev->gmc.srbm_soft_reset) 1346 return 0; 1347 srbm_soft_reset = adev->gmc.srbm_soft_reset; 1348 1349 if (srbm_soft_reset) { 1350 u32 tmp; 1351 1352 tmp = RREG32(mmSRBM_SOFT_RESET); 1353 tmp |= srbm_soft_reset; 1354 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1355 WREG32(mmSRBM_SOFT_RESET, tmp); 1356 tmp = RREG32(mmSRBM_SOFT_RESET); 1357 1358 udelay(50); 1359 1360 tmp &= ~srbm_soft_reset; 1361 WREG32(mmSRBM_SOFT_RESET, tmp); 1362 tmp = RREG32(mmSRBM_SOFT_RESET); 1363 1364 /* Wait a little for things to settle down */ 1365 udelay(50); 1366 } 1367 1368 return 0; 1369 } 1370 1371 static int gmc_v8_0_post_soft_reset(void *handle) 1372 { 1373 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1374 1375 if (!adev->gmc.srbm_soft_reset) 1376 return 0; 1377 1378 gmc_v8_0_mc_resume(adev); 1379 return 0; 1380 } 1381 1382 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1383 struct amdgpu_irq_src *src, 1384 unsigned type, 1385 enum amdgpu_interrupt_state state) 1386 { 1387 u32 tmp; 1388 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1389 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1390 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1391 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1392 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1393 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1394 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1395 1396 switch (state) { 1397 case AMDGPU_IRQ_STATE_DISABLE: 1398 /* system context */ 1399 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1400 tmp &= ~bits; 1401 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1402 /* VMs */ 1403 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1404 tmp &= ~bits; 1405 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1406 break; 1407 case AMDGPU_IRQ_STATE_ENABLE: 1408 /* system context */ 1409 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1410 tmp |= bits; 1411 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1412 /* VMs */ 1413 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1414 tmp |= bits; 1415 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1416 break; 1417 default: 1418 break; 1419 } 1420 1421 return 0; 1422 } 1423 1424 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, 1425 struct amdgpu_irq_src *source, 1426 struct amdgpu_iv_entry *entry) 1427 { 1428 u32 addr, status, mc_client, vmid; 1429 1430 if (amdgpu_sriov_vf(adev)) { 1431 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1432 entry->src_id, entry->src_data[0]); 1433 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n"); 1434 return 0; 1435 } 1436 1437 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1438 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1439 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); 1440 /* reset addr and status */ 1441 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1442 1443 if (!addr && !status) 1444 return 0; 1445 1446 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1447 gmc_v8_0_set_fault_enable_default(adev, false); 1448 1449 if (printk_ratelimit()) { 1450 struct amdgpu_task_info task_info; 1451 1452 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 1453 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 1454 1455 dev_err(adev->dev, "GPU fault detected: %d 0x%08x for process %s pid %d thread %s pid %d\n", 1456 entry->src_id, entry->src_data[0], task_info.process_name, 1457 task_info.tgid, task_info.task_name, task_info.pid); 1458 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1459 addr); 1460 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1461 status); 1462 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client, 1463 entry->pasid); 1464 } 1465 1466 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1467 VMID); 1468 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid) 1469 && !atomic_read(&adev->gmc.vm_fault_info_updated)) { 1470 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info; 1471 u32 protections = REG_GET_FIELD(status, 1472 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1473 PROTECTIONS); 1474 1475 info->vmid = vmid; 1476 info->mc_id = REG_GET_FIELD(status, 1477 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1478 MEMORY_CLIENT_ID); 1479 info->status = status; 1480 info->page_addr = addr; 1481 info->prot_valid = protections & 0x7 ? true : false; 1482 info->prot_read = protections & 0x8 ? true : false; 1483 info->prot_write = protections & 0x10 ? true : false; 1484 info->prot_exec = protections & 0x20 ? true : false; 1485 mb(); 1486 atomic_set(&adev->gmc.vm_fault_info_updated, 1); 1487 } 1488 1489 return 0; 1490 } 1491 1492 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev, 1493 bool enable) 1494 { 1495 uint32_t data; 1496 1497 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 1498 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1499 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1500 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1501 1502 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1503 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1504 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1505 1506 data = RREG32(mmMC_HUB_MISC_VM_CG); 1507 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK; 1508 WREG32(mmMC_HUB_MISC_VM_CG, data); 1509 1510 data = RREG32(mmMC_XPB_CLK_GAT); 1511 data |= MC_XPB_CLK_GAT__ENABLE_MASK; 1512 WREG32(mmMC_XPB_CLK_GAT, data); 1513 1514 data = RREG32(mmATC_MISC_CG); 1515 data |= ATC_MISC_CG__ENABLE_MASK; 1516 WREG32(mmATC_MISC_CG, data); 1517 1518 data = RREG32(mmMC_CITF_MISC_WR_CG); 1519 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK; 1520 WREG32(mmMC_CITF_MISC_WR_CG, data); 1521 1522 data = RREG32(mmMC_CITF_MISC_RD_CG); 1523 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK; 1524 WREG32(mmMC_CITF_MISC_RD_CG, data); 1525 1526 data = RREG32(mmMC_CITF_MISC_VM_CG); 1527 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK; 1528 WREG32(mmMC_CITF_MISC_VM_CG, data); 1529 1530 data = RREG32(mmVM_L2_CG); 1531 data |= VM_L2_CG__ENABLE_MASK; 1532 WREG32(mmVM_L2_CG, data); 1533 } else { 1534 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1535 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1536 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1537 1538 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1539 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1540 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1541 1542 data = RREG32(mmMC_HUB_MISC_VM_CG); 1543 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK; 1544 WREG32(mmMC_HUB_MISC_VM_CG, data); 1545 1546 data = RREG32(mmMC_XPB_CLK_GAT); 1547 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK; 1548 WREG32(mmMC_XPB_CLK_GAT, data); 1549 1550 data = RREG32(mmATC_MISC_CG); 1551 data &= ~ATC_MISC_CG__ENABLE_MASK; 1552 WREG32(mmATC_MISC_CG, data); 1553 1554 data = RREG32(mmMC_CITF_MISC_WR_CG); 1555 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK; 1556 WREG32(mmMC_CITF_MISC_WR_CG, data); 1557 1558 data = RREG32(mmMC_CITF_MISC_RD_CG); 1559 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK; 1560 WREG32(mmMC_CITF_MISC_RD_CG, data); 1561 1562 data = RREG32(mmMC_CITF_MISC_VM_CG); 1563 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK; 1564 WREG32(mmMC_CITF_MISC_VM_CG, data); 1565 1566 data = RREG32(mmVM_L2_CG); 1567 data &= ~VM_L2_CG__ENABLE_MASK; 1568 WREG32(mmVM_L2_CG, data); 1569 } 1570 } 1571 1572 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev, 1573 bool enable) 1574 { 1575 uint32_t data; 1576 1577 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) { 1578 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1579 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1580 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1581 1582 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1583 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1584 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1585 1586 data = RREG32(mmMC_HUB_MISC_VM_CG); 1587 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1588 WREG32(mmMC_HUB_MISC_VM_CG, data); 1589 1590 data = RREG32(mmMC_XPB_CLK_GAT); 1591 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1592 WREG32(mmMC_XPB_CLK_GAT, data); 1593 1594 data = RREG32(mmATC_MISC_CG); 1595 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1596 WREG32(mmATC_MISC_CG, data); 1597 1598 data = RREG32(mmMC_CITF_MISC_WR_CG); 1599 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1600 WREG32(mmMC_CITF_MISC_WR_CG, data); 1601 1602 data = RREG32(mmMC_CITF_MISC_RD_CG); 1603 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1604 WREG32(mmMC_CITF_MISC_RD_CG, data); 1605 1606 data = RREG32(mmMC_CITF_MISC_VM_CG); 1607 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1608 WREG32(mmMC_CITF_MISC_VM_CG, data); 1609 1610 data = RREG32(mmVM_L2_CG); 1611 data |= VM_L2_CG__MEM_LS_ENABLE_MASK; 1612 WREG32(mmVM_L2_CG, data); 1613 } else { 1614 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1615 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1616 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1617 1618 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1619 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1620 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1621 1622 data = RREG32(mmMC_HUB_MISC_VM_CG); 1623 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1624 WREG32(mmMC_HUB_MISC_VM_CG, data); 1625 1626 data = RREG32(mmMC_XPB_CLK_GAT); 1627 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1628 WREG32(mmMC_XPB_CLK_GAT, data); 1629 1630 data = RREG32(mmATC_MISC_CG); 1631 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1632 WREG32(mmATC_MISC_CG, data); 1633 1634 data = RREG32(mmMC_CITF_MISC_WR_CG); 1635 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1636 WREG32(mmMC_CITF_MISC_WR_CG, data); 1637 1638 data = RREG32(mmMC_CITF_MISC_RD_CG); 1639 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1640 WREG32(mmMC_CITF_MISC_RD_CG, data); 1641 1642 data = RREG32(mmMC_CITF_MISC_VM_CG); 1643 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1644 WREG32(mmMC_CITF_MISC_VM_CG, data); 1645 1646 data = RREG32(mmVM_L2_CG); 1647 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK; 1648 WREG32(mmVM_L2_CG, data); 1649 } 1650 } 1651 1652 static int gmc_v8_0_set_clockgating_state(void *handle, 1653 enum amd_clockgating_state state) 1654 { 1655 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1656 1657 if (amdgpu_sriov_vf(adev)) 1658 return 0; 1659 1660 switch (adev->asic_type) { 1661 case CHIP_FIJI: 1662 fiji_update_mc_medium_grain_clock_gating(adev, 1663 state == AMD_CG_STATE_GATE); 1664 fiji_update_mc_light_sleep(adev, 1665 state == AMD_CG_STATE_GATE); 1666 break; 1667 default: 1668 break; 1669 } 1670 return 0; 1671 } 1672 1673 static int gmc_v8_0_set_powergating_state(void *handle, 1674 enum amd_powergating_state state) 1675 { 1676 return 0; 1677 } 1678 1679 static void gmc_v8_0_get_clockgating_state(void *handle, u32 *flags) 1680 { 1681 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1682 int data; 1683 1684 if (amdgpu_sriov_vf(adev)) 1685 *flags = 0; 1686 1687 /* AMD_CG_SUPPORT_MC_MGCG */ 1688 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1689 if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK) 1690 *flags |= AMD_CG_SUPPORT_MC_MGCG; 1691 1692 /* AMD_CG_SUPPORT_MC_LS */ 1693 if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK) 1694 *flags |= AMD_CG_SUPPORT_MC_LS; 1695 } 1696 1697 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = { 1698 .name = "gmc_v8_0", 1699 .early_init = gmc_v8_0_early_init, 1700 .late_init = gmc_v8_0_late_init, 1701 .sw_init = gmc_v8_0_sw_init, 1702 .sw_fini = gmc_v8_0_sw_fini, 1703 .hw_init = gmc_v8_0_hw_init, 1704 .hw_fini = gmc_v8_0_hw_fini, 1705 .suspend = gmc_v8_0_suspend, 1706 .resume = gmc_v8_0_resume, 1707 .is_idle = gmc_v8_0_is_idle, 1708 .wait_for_idle = gmc_v8_0_wait_for_idle, 1709 .check_soft_reset = gmc_v8_0_check_soft_reset, 1710 .pre_soft_reset = gmc_v8_0_pre_soft_reset, 1711 .soft_reset = gmc_v8_0_soft_reset, 1712 .post_soft_reset = gmc_v8_0_post_soft_reset, 1713 .set_clockgating_state = gmc_v8_0_set_clockgating_state, 1714 .set_powergating_state = gmc_v8_0_set_powergating_state, 1715 .get_clockgating_state = gmc_v8_0_get_clockgating_state, 1716 }; 1717 1718 static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = { 1719 .flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb, 1720 .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb, 1721 .emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping, 1722 .set_prt = gmc_v8_0_set_prt, 1723 .get_vm_pte_flags = gmc_v8_0_get_vm_pte_flags, 1724 .get_vm_pde = gmc_v8_0_get_vm_pde 1725 }; 1726 1727 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = { 1728 .set = gmc_v8_0_vm_fault_interrupt_state, 1729 .process = gmc_v8_0_process_interrupt, 1730 }; 1731 1732 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev) 1733 { 1734 adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs; 1735 } 1736 1737 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev) 1738 { 1739 adev->gmc.vm_fault.num_types = 1; 1740 adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs; 1741 } 1742 1743 const struct amdgpu_ip_block_version gmc_v8_0_ip_block = 1744 { 1745 .type = AMD_IP_BLOCK_TYPE_GMC, 1746 .major = 8, 1747 .minor = 0, 1748 .rev = 0, 1749 .funcs = &gmc_v8_0_ip_funcs, 1750 }; 1751 1752 const struct amdgpu_ip_block_version gmc_v8_1_ip_block = 1753 { 1754 .type = AMD_IP_BLOCK_TYPE_GMC, 1755 .major = 8, 1756 .minor = 1, 1757 .rev = 0, 1758 .funcs = &gmc_v8_0_ip_funcs, 1759 }; 1760 1761 const struct amdgpu_ip_block_version gmc_v8_5_ip_block = 1762 { 1763 .type = AMD_IP_BLOCK_TYPE_GMC, 1764 .major = 8, 1765 .minor = 5, 1766 .rev = 0, 1767 .funcs = &gmc_v8_0_ip_funcs, 1768 }; 1769