1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <drm/drmP.h> 25 #include <drm/drm_cache.h> 26 #include "amdgpu.h" 27 #include "gmc_v8_0.h" 28 #include "amdgpu_ucode.h" 29 30 #include "gmc/gmc_8_1_d.h" 31 #include "gmc/gmc_8_1_sh_mask.h" 32 33 #include "bif/bif_5_0_d.h" 34 #include "bif/bif_5_0_sh_mask.h" 35 36 #include "oss/oss_3_0_d.h" 37 #include "oss/oss_3_0_sh_mask.h" 38 39 #include "dce/dce_10_0_d.h" 40 #include "dce/dce_10_0_sh_mask.h" 41 42 #include "vid.h" 43 #include "vi.h" 44 45 #include "amdgpu_atombios.h" 46 47 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev); 48 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev); 49 static int gmc_v8_0_wait_for_idle(void *handle); 50 51 MODULE_FIRMWARE("amdgpu/tonga_mc.bin"); 52 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin"); 53 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin"); 54 MODULE_FIRMWARE("amdgpu/polaris12_mc.bin"); 55 56 static const u32 golden_settings_tonga_a11[] = 57 { 58 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, 59 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028, 60 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991, 61 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 62 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 63 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 64 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 65 }; 66 67 static const u32 tonga_mgcg_cgcg_init[] = 68 { 69 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 70 }; 71 72 static const u32 golden_settings_fiji_a10[] = 73 { 74 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 75 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 76 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 77 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 78 }; 79 80 static const u32 fiji_mgcg_cgcg_init[] = 81 { 82 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 83 }; 84 85 static const u32 golden_settings_polaris11_a11[] = 86 { 87 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 88 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 89 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 90 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 91 }; 92 93 static const u32 golden_settings_polaris10_a11[] = 94 { 95 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, 96 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 97 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 98 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 99 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 100 }; 101 102 static const u32 cz_mgcg_cgcg_init[] = 103 { 104 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 105 }; 106 107 static const u32 stoney_mgcg_cgcg_init[] = 108 { 109 mmATC_MISC_CG, 0xffffffff, 0x000c0200, 110 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 111 }; 112 113 static const u32 golden_settings_stoney_common[] = 114 { 115 mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004, 116 mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000 117 }; 118 119 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) 120 { 121 switch (adev->asic_type) { 122 case CHIP_FIJI: 123 amdgpu_device_program_register_sequence(adev, 124 fiji_mgcg_cgcg_init, 125 ARRAY_SIZE(fiji_mgcg_cgcg_init)); 126 amdgpu_device_program_register_sequence(adev, 127 golden_settings_fiji_a10, 128 ARRAY_SIZE(golden_settings_fiji_a10)); 129 break; 130 case CHIP_TONGA: 131 amdgpu_device_program_register_sequence(adev, 132 tonga_mgcg_cgcg_init, 133 ARRAY_SIZE(tonga_mgcg_cgcg_init)); 134 amdgpu_device_program_register_sequence(adev, 135 golden_settings_tonga_a11, 136 ARRAY_SIZE(golden_settings_tonga_a11)); 137 break; 138 case CHIP_POLARIS11: 139 case CHIP_POLARIS12: 140 case CHIP_VEGAM: 141 amdgpu_device_program_register_sequence(adev, 142 golden_settings_polaris11_a11, 143 ARRAY_SIZE(golden_settings_polaris11_a11)); 144 break; 145 case CHIP_POLARIS10: 146 amdgpu_device_program_register_sequence(adev, 147 golden_settings_polaris10_a11, 148 ARRAY_SIZE(golden_settings_polaris10_a11)); 149 break; 150 case CHIP_CARRIZO: 151 amdgpu_device_program_register_sequence(adev, 152 cz_mgcg_cgcg_init, 153 ARRAY_SIZE(cz_mgcg_cgcg_init)); 154 break; 155 case CHIP_STONEY: 156 amdgpu_device_program_register_sequence(adev, 157 stoney_mgcg_cgcg_init, 158 ARRAY_SIZE(stoney_mgcg_cgcg_init)); 159 amdgpu_device_program_register_sequence(adev, 160 golden_settings_stoney_common, 161 ARRAY_SIZE(golden_settings_stoney_common)); 162 break; 163 default: 164 break; 165 } 166 } 167 168 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev) 169 { 170 u32 blackout; 171 172 gmc_v8_0_wait_for_idle(adev); 173 174 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 175 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 176 /* Block CPU access */ 177 WREG32(mmBIF_FB_EN, 0); 178 /* blackout the MC */ 179 blackout = REG_SET_FIELD(blackout, 180 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1); 181 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout); 182 } 183 /* wait for the MC to settle */ 184 udelay(100); 185 } 186 187 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev) 188 { 189 u32 tmp; 190 191 /* unblackout the MC */ 192 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 193 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 194 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 195 /* allow CPU access */ 196 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 197 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 198 WREG32(mmBIF_FB_EN, tmp); 199 } 200 201 /** 202 * gmc_v8_0_init_microcode - load ucode images from disk 203 * 204 * @adev: amdgpu_device pointer 205 * 206 * Use the firmware interface to load the ucode images into 207 * the driver (not loaded into hw). 208 * Returns 0 on success, error on failure. 209 */ 210 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) 211 { 212 const char *chip_name; 213 char fw_name[30]; 214 int err; 215 216 DRM_DEBUG("\n"); 217 218 switch (adev->asic_type) { 219 case CHIP_TONGA: 220 chip_name = "tonga"; 221 break; 222 case CHIP_POLARIS11: 223 chip_name = "polaris11"; 224 break; 225 case CHIP_POLARIS10: 226 chip_name = "polaris10"; 227 break; 228 case CHIP_POLARIS12: 229 chip_name = "polaris12"; 230 break; 231 case CHIP_FIJI: 232 case CHIP_CARRIZO: 233 case CHIP_STONEY: 234 case CHIP_VEGAM: 235 return 0; 236 default: BUG(); 237 } 238 239 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name); 240 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); 241 if (err) 242 goto out; 243 err = amdgpu_ucode_validate(adev->gmc.fw); 244 245 out: 246 if (err) { 247 pr_err("mc: Failed to load firmware \"%s\"\n", fw_name); 248 release_firmware(adev->gmc.fw); 249 adev->gmc.fw = NULL; 250 } 251 return err; 252 } 253 254 /** 255 * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw 256 * 257 * @adev: amdgpu_device pointer 258 * 259 * Load the GDDR MC ucode into the hw (CIK). 260 * Returns 0 on success, error on failure. 261 */ 262 static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev) 263 { 264 const struct mc_firmware_header_v1_0 *hdr; 265 const __le32 *fw_data = NULL; 266 const __le32 *io_mc_regs = NULL; 267 u32 running; 268 int i, ucode_size, regs_size; 269 270 /* Skip MC ucode loading on SR-IOV capable boards. 271 * vbios does this for us in asic_init in that case. 272 * Skip MC ucode loading on VF, because hypervisor will do that 273 * for this adaptor. 274 */ 275 if (amdgpu_sriov_bios(adev)) 276 return 0; 277 278 if (!adev->gmc.fw) 279 return -EINVAL; 280 281 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 282 amdgpu_ucode_print_mc_hdr(&hdr->header); 283 284 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 285 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 286 io_mc_regs = (const __le32 *) 287 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 288 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 289 fw_data = (const __le32 *) 290 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 291 292 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); 293 294 if (running == 0) { 295 /* reset the engine and set to writable */ 296 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 297 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 298 299 /* load mc io regs */ 300 for (i = 0; i < regs_size; i++) { 301 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 302 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 303 } 304 /* load the MC ucode */ 305 for (i = 0; i < ucode_size; i++) 306 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 307 308 /* put the engine back into the active state */ 309 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 310 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 311 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 312 313 /* wait for training to complete */ 314 for (i = 0; i < adev->usec_timeout; i++) { 315 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 316 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0)) 317 break; 318 udelay(1); 319 } 320 for (i = 0; i < adev->usec_timeout; i++) { 321 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 322 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1)) 323 break; 324 udelay(1); 325 } 326 } 327 328 return 0; 329 } 330 331 static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev) 332 { 333 const struct mc_firmware_header_v1_0 *hdr; 334 const __le32 *fw_data = NULL; 335 const __le32 *io_mc_regs = NULL; 336 u32 data, vbios_version; 337 int i, ucode_size, regs_size; 338 339 /* Skip MC ucode loading on SR-IOV capable boards. 340 * vbios does this for us in asic_init in that case. 341 * Skip MC ucode loading on VF, because hypervisor will do that 342 * for this adaptor. 343 */ 344 if (amdgpu_sriov_bios(adev)) 345 return 0; 346 347 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 0x9F); 348 data = RREG32(mmMC_SEQ_IO_DEBUG_DATA); 349 vbios_version = data & 0xf; 350 351 if (vbios_version == 0) 352 return 0; 353 354 if (!adev->gmc.fw) 355 return -EINVAL; 356 357 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 358 amdgpu_ucode_print_mc_hdr(&hdr->header); 359 360 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 361 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 362 io_mc_regs = (const __le32 *) 363 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 364 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 365 fw_data = (const __le32 *) 366 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 367 368 data = RREG32(mmMC_SEQ_MISC0); 369 data &= ~(0x40); 370 WREG32(mmMC_SEQ_MISC0, data); 371 372 /* load mc io regs */ 373 for (i = 0; i < regs_size; i++) { 374 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 375 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 376 } 377 378 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 379 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 380 381 /* load the MC ucode */ 382 for (i = 0; i < ucode_size; i++) 383 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 384 385 /* put the engine back into the active state */ 386 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 387 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 388 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 389 390 /* wait for training to complete */ 391 for (i = 0; i < adev->usec_timeout; i++) { 392 data = RREG32(mmMC_SEQ_MISC0); 393 if (data & 0x80) 394 break; 395 udelay(1); 396 } 397 398 return 0; 399 } 400 401 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev, 402 struct amdgpu_gmc *mc) 403 { 404 u64 base = 0; 405 406 if (!amdgpu_sriov_vf(adev)) 407 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; 408 base <<= 24; 409 410 amdgpu_device_vram_location(adev, &adev->gmc, base); 411 amdgpu_device_gart_location(adev, mc); 412 } 413 414 /** 415 * gmc_v8_0_mc_program - program the GPU memory controller 416 * 417 * @adev: amdgpu_device pointer 418 * 419 * Set the location of vram, gart, and AGP in the GPU's 420 * physical address space (CIK). 421 */ 422 static void gmc_v8_0_mc_program(struct amdgpu_device *adev) 423 { 424 u32 tmp; 425 int i, j; 426 427 /* Initialize HDP */ 428 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 429 WREG32((0xb05 + j), 0x00000000); 430 WREG32((0xb06 + j), 0x00000000); 431 WREG32((0xb07 + j), 0x00000000); 432 WREG32((0xb08 + j), 0x00000000); 433 WREG32((0xb09 + j), 0x00000000); 434 } 435 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 436 437 if (gmc_v8_0_wait_for_idle((void *)adev)) { 438 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 439 } 440 if (adev->mode_info.num_crtc) { 441 /* Lockout access through VGA aperture*/ 442 tmp = RREG32(mmVGA_HDP_CONTROL); 443 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 444 WREG32(mmVGA_HDP_CONTROL, tmp); 445 446 /* disable VGA render */ 447 tmp = RREG32(mmVGA_RENDER_CONTROL); 448 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 449 WREG32(mmVGA_RENDER_CONTROL, tmp); 450 } 451 /* Update configuration */ 452 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 453 adev->gmc.vram_start >> 12); 454 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 455 adev->gmc.vram_end >> 12); 456 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 457 adev->vram_scratch.gpu_addr >> 12); 458 459 if (amdgpu_sriov_vf(adev)) { 460 tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16; 461 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF); 462 WREG32(mmMC_VM_FB_LOCATION, tmp); 463 /* XXX double check these! */ 464 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); 465 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); 466 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF); 467 } 468 469 WREG32(mmMC_VM_AGP_BASE, 0); 470 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); 471 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); 472 if (gmc_v8_0_wait_for_idle((void *)adev)) { 473 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 474 } 475 476 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 477 478 tmp = RREG32(mmHDP_MISC_CNTL); 479 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); 480 WREG32(mmHDP_MISC_CNTL, tmp); 481 482 tmp = RREG32(mmHDP_HOST_PATH_CNTL); 483 WREG32(mmHDP_HOST_PATH_CNTL, tmp); 484 } 485 486 /** 487 * gmc_v8_0_mc_init - initialize the memory controller driver params 488 * 489 * @adev: amdgpu_device pointer 490 * 491 * Look up the amount of vram, vram width, and decide how to place 492 * vram and gart within the GPU's physical address space (CIK). 493 * Returns 0 for success. 494 */ 495 static int gmc_v8_0_mc_init(struct amdgpu_device *adev) 496 { 497 int r; 498 499 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev); 500 if (!adev->gmc.vram_width) { 501 u32 tmp; 502 int chansize, numchan; 503 504 /* Get VRAM informations */ 505 tmp = RREG32(mmMC_ARB_RAMCFG); 506 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { 507 chansize = 64; 508 } else { 509 chansize = 32; 510 } 511 tmp = RREG32(mmMC_SHARED_CHMAP); 512 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 513 case 0: 514 default: 515 numchan = 1; 516 break; 517 case 1: 518 numchan = 2; 519 break; 520 case 2: 521 numchan = 4; 522 break; 523 case 3: 524 numchan = 8; 525 break; 526 case 4: 527 numchan = 3; 528 break; 529 case 5: 530 numchan = 6; 531 break; 532 case 6: 533 numchan = 10; 534 break; 535 case 7: 536 numchan = 12; 537 break; 538 case 8: 539 numchan = 16; 540 break; 541 } 542 adev->gmc.vram_width = numchan * chansize; 543 } 544 /* size in MB on si */ 545 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 546 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 547 548 if (!(adev->flags & AMD_IS_APU)) { 549 r = amdgpu_device_resize_fb_bar(adev); 550 if (r) 551 return r; 552 } 553 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 554 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 555 556 #ifdef CONFIG_X86_64 557 if (adev->flags & AMD_IS_APU) { 558 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; 559 adev->gmc.aper_size = adev->gmc.real_vram_size; 560 } 561 #endif 562 563 /* In case the PCI BAR is larger than the actual amount of vram */ 564 adev->gmc.visible_vram_size = adev->gmc.aper_size; 565 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 566 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 567 568 /* set the gart size */ 569 if (amdgpu_gart_size == -1) { 570 switch (adev->asic_type) { 571 case CHIP_POLARIS10: /* all engines support GPUVM */ 572 case CHIP_POLARIS11: /* all engines support GPUVM */ 573 case CHIP_POLARIS12: /* all engines support GPUVM */ 574 case CHIP_VEGAM: /* all engines support GPUVM */ 575 default: 576 adev->gmc.gart_size = 256ULL << 20; 577 break; 578 case CHIP_TONGA: /* UVD, VCE do not support GPUVM */ 579 case CHIP_FIJI: /* UVD, VCE do not support GPUVM */ 580 case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */ 581 case CHIP_STONEY: /* UVD does not support GPUVM, DCE SG support */ 582 adev->gmc.gart_size = 1024ULL << 20; 583 break; 584 } 585 } else { 586 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 587 } 588 589 gmc_v8_0_vram_gtt_location(adev, &adev->gmc); 590 591 return 0; 592 } 593 594 /* 595 * GART 596 * VMID 0 is the physical GPU addresses as used by the kernel. 597 * VMIDs 1-15 are used for userspace clients and are handled 598 * by the amdgpu vm/hsa code. 599 */ 600 601 /** 602 * gmc_v8_0_flush_gpu_tlb - gart tlb flush callback 603 * 604 * @adev: amdgpu_device pointer 605 * @vmid: vm instance to flush 606 * 607 * Flush the TLB for the requested page table (CIK). 608 */ 609 static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev, 610 uint32_t vmid) 611 { 612 /* bits 0-15 are the VM contexts0-15 */ 613 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 614 } 615 616 static uint64_t gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 617 unsigned vmid, uint64_t pd_addr) 618 { 619 uint32_t reg; 620 621 if (vmid < 8) 622 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; 623 else 624 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8; 625 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); 626 627 /* bits 0-15 are the VM contexts0-15 */ 628 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); 629 630 return pd_addr; 631 } 632 633 static void gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 634 unsigned pasid) 635 { 636 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); 637 } 638 639 /** 640 * gmc_v8_0_set_pte_pde - update the page tables using MMIO 641 * 642 * @adev: amdgpu_device pointer 643 * @cpu_pt_addr: cpu address of the page table 644 * @gpu_page_idx: entry in the page table to update 645 * @addr: dst addr to write into pte/pde 646 * @flags: access flags 647 * 648 * Update the page tables using the CPU. 649 */ 650 static int gmc_v8_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 651 uint32_t gpu_page_idx, uint64_t addr, 652 uint64_t flags) 653 { 654 void __iomem *ptr = (void *)cpu_pt_addr; 655 uint64_t value; 656 657 /* 658 * PTE format on VI: 659 * 63:40 reserved 660 * 39:12 4k physical page base address 661 * 11:7 fragment 662 * 6 write 663 * 5 read 664 * 4 exe 665 * 3 reserved 666 * 2 snooped 667 * 1 system 668 * 0 valid 669 * 670 * PDE format on VI: 671 * 63:59 block fragment size 672 * 58:40 reserved 673 * 39:1 physical base address of PTE 674 * bits 5:1 must be 0. 675 * 0 valid 676 */ 677 value = addr & 0x000000FFFFFFF000ULL; 678 value |= flags; 679 writeq(value, ptr + (gpu_page_idx * 8)); 680 681 return 0; 682 } 683 684 static uint64_t gmc_v8_0_get_vm_pte_flags(struct amdgpu_device *adev, 685 uint32_t flags) 686 { 687 uint64_t pte_flag = 0; 688 689 if (flags & AMDGPU_VM_PAGE_EXECUTABLE) 690 pte_flag |= AMDGPU_PTE_EXECUTABLE; 691 if (flags & AMDGPU_VM_PAGE_READABLE) 692 pte_flag |= AMDGPU_PTE_READABLE; 693 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 694 pte_flag |= AMDGPU_PTE_WRITEABLE; 695 if (flags & AMDGPU_VM_PAGE_PRT) 696 pte_flag |= AMDGPU_PTE_PRT; 697 698 return pte_flag; 699 } 700 701 static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level, 702 uint64_t *addr, uint64_t *flags) 703 { 704 BUG_ON(*addr & 0xFFFFFF0000000FFFULL); 705 } 706 707 /** 708 * gmc_v8_0_set_fault_enable_default - update VM fault handling 709 * 710 * @adev: amdgpu_device pointer 711 * @value: true redirects VM faults to the default page 712 */ 713 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev, 714 bool value) 715 { 716 u32 tmp; 717 718 tmp = RREG32(mmVM_CONTEXT1_CNTL); 719 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 720 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 721 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 722 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 723 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 724 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 725 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 726 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 727 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 728 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 729 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 730 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 731 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 732 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 733 WREG32(mmVM_CONTEXT1_CNTL, tmp); 734 } 735 736 /** 737 * gmc_v8_0_set_prt - set PRT VM fault 738 * 739 * @adev: amdgpu_device pointer 740 * @enable: enable/disable VM fault handling for PRT 741 */ 742 static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable) 743 { 744 u32 tmp; 745 746 if (enable && !adev->gmc.prt_warning) { 747 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 748 adev->gmc.prt_warning = true; 749 } 750 751 tmp = RREG32(mmVM_PRT_CNTL); 752 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 753 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 754 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 755 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 756 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 757 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 758 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 759 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 760 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 761 L2_CACHE_STORE_INVALID_ENTRIES, enable); 762 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 763 L1_TLB_STORE_INVALID_ENTRIES, enable); 764 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 765 MASK_PDE0_FAULT, enable); 766 WREG32(mmVM_PRT_CNTL, tmp); 767 768 if (enable) { 769 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; 770 uint32_t high = adev->vm_manager.max_pfn - 771 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT); 772 773 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); 774 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); 775 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); 776 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); 777 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); 778 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); 779 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); 780 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); 781 } else { 782 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); 783 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); 784 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); 785 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); 786 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); 787 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); 788 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); 789 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); 790 } 791 } 792 793 /** 794 * gmc_v8_0_gart_enable - gart enable 795 * 796 * @adev: amdgpu_device pointer 797 * 798 * This sets up the TLBs, programs the page tables for VMID0, 799 * sets up the hw for VMIDs 1-15 which are allocated on 800 * demand, and sets up the global locations for the LDS, GDS, 801 * and GPUVM for FSA64 clients (CIK). 802 * Returns 0 for success, errors for failure. 803 */ 804 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) 805 { 806 int r, i; 807 u32 tmp, field; 808 809 if (adev->gart.robj == NULL) { 810 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 811 return -EINVAL; 812 } 813 r = amdgpu_gart_table_vram_pin(adev); 814 if (r) 815 return r; 816 /* Setup TLB control */ 817 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 818 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 819 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); 820 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 821 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); 822 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 823 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 824 /* Setup L2 cache */ 825 tmp = RREG32(mmVM_L2_CNTL); 826 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 827 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 828 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); 829 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); 830 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); 831 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 832 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 833 WREG32(mmVM_L2_CNTL, tmp); 834 tmp = RREG32(mmVM_L2_CNTL2); 835 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 836 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 837 WREG32(mmVM_L2_CNTL2, tmp); 838 839 field = adev->vm_manager.fragment_size; 840 tmp = RREG32(mmVM_L2_CNTL3); 841 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); 842 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); 843 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); 844 WREG32(mmVM_L2_CNTL3, tmp); 845 /* XXX: set to enable PTE/PDE in system memory */ 846 tmp = RREG32(mmVM_L2_CNTL4); 847 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0); 848 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0); 849 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0); 850 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0); 851 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0); 852 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0); 853 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0); 854 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0); 855 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0); 856 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0); 857 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0); 858 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0); 859 WREG32(mmVM_L2_CNTL4, tmp); 860 /* setup context0 */ 861 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); 862 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); 863 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); 864 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 865 (u32)(adev->dummy_page_addr >> 12)); 866 WREG32(mmVM_CONTEXT0_CNTL2, 0); 867 tmp = RREG32(mmVM_CONTEXT0_CNTL); 868 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 869 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 870 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 871 WREG32(mmVM_CONTEXT0_CNTL, tmp); 872 873 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0); 874 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0); 875 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0); 876 877 /* empty context1-15 */ 878 /* FIXME start with 4G, once using 2 level pt switch to full 879 * vm size space 880 */ 881 /* set vm size, must be a multiple of 4 */ 882 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 883 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 884 for (i = 1; i < 16; i++) { 885 if (i < 8) 886 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 887 adev->gart.table_addr >> 12); 888 else 889 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 890 adev->gart.table_addr >> 12); 891 } 892 893 /* enable context1-15 */ 894 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 895 (u32)(adev->dummy_page_addr >> 12)); 896 WREG32(mmVM_CONTEXT1_CNTL2, 4); 897 tmp = RREG32(mmVM_CONTEXT1_CNTL); 898 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 899 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); 900 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 901 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 902 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 903 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 904 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 905 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 906 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 907 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, 908 adev->vm_manager.block_size - 9); 909 WREG32(mmVM_CONTEXT1_CNTL, tmp); 910 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 911 gmc_v8_0_set_fault_enable_default(adev, false); 912 else 913 gmc_v8_0_set_fault_enable_default(adev, true); 914 915 gmc_v8_0_flush_gpu_tlb(adev, 0); 916 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 917 (unsigned)(adev->gmc.gart_size >> 20), 918 (unsigned long long)adev->gart.table_addr); 919 adev->gart.ready = true; 920 return 0; 921 } 922 923 static int gmc_v8_0_gart_init(struct amdgpu_device *adev) 924 { 925 int r; 926 927 if (adev->gart.robj) { 928 WARN(1, "R600 PCIE GART already initialized\n"); 929 return 0; 930 } 931 /* Initialize common gart structure */ 932 r = amdgpu_gart_init(adev); 933 if (r) 934 return r; 935 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 936 adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE; 937 return amdgpu_gart_table_vram_alloc(adev); 938 } 939 940 /** 941 * gmc_v8_0_gart_disable - gart disable 942 * 943 * @adev: amdgpu_device pointer 944 * 945 * This disables all VM page table (CIK). 946 */ 947 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev) 948 { 949 u32 tmp; 950 951 /* Disable all tables */ 952 WREG32(mmVM_CONTEXT0_CNTL, 0); 953 WREG32(mmVM_CONTEXT1_CNTL, 0); 954 /* Setup TLB control */ 955 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 956 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 957 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); 958 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); 959 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 960 /* Setup L2 cache */ 961 tmp = RREG32(mmVM_L2_CNTL); 962 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 963 WREG32(mmVM_L2_CNTL, tmp); 964 WREG32(mmVM_L2_CNTL2, 0); 965 amdgpu_gart_table_vram_unpin(adev); 966 } 967 968 /** 969 * gmc_v8_0_gart_fini - vm fini callback 970 * 971 * @adev: amdgpu_device pointer 972 * 973 * Tears down the driver GART/VM setup (CIK). 974 */ 975 static void gmc_v8_0_gart_fini(struct amdgpu_device *adev) 976 { 977 amdgpu_gart_table_vram_free(adev); 978 amdgpu_gart_fini(adev); 979 } 980 981 /** 982 * gmc_v8_0_vm_decode_fault - print human readable fault info 983 * 984 * @adev: amdgpu_device pointer 985 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value 986 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value 987 * 988 * Print human readable fault information (CIK). 989 */ 990 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32 status, 991 u32 addr, u32 mc_client, unsigned pasid) 992 { 993 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 994 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 995 PROTECTIONS); 996 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 997 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 998 u32 mc_id; 999 1000 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1001 MEMORY_CLIENT_ID); 1002 1003 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 1004 protections, vmid, pasid, addr, 1005 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1006 MEMORY_CLIENT_RW) ? 1007 "write" : "read", block, mc_client, mc_id); 1008 } 1009 1010 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type) 1011 { 1012 switch (mc_seq_vram_type) { 1013 case MC_SEQ_MISC0__MT__GDDR1: 1014 return AMDGPU_VRAM_TYPE_GDDR1; 1015 case MC_SEQ_MISC0__MT__DDR2: 1016 return AMDGPU_VRAM_TYPE_DDR2; 1017 case MC_SEQ_MISC0__MT__GDDR3: 1018 return AMDGPU_VRAM_TYPE_GDDR3; 1019 case MC_SEQ_MISC0__MT__GDDR4: 1020 return AMDGPU_VRAM_TYPE_GDDR4; 1021 case MC_SEQ_MISC0__MT__GDDR5: 1022 return AMDGPU_VRAM_TYPE_GDDR5; 1023 case MC_SEQ_MISC0__MT__HBM: 1024 return AMDGPU_VRAM_TYPE_HBM; 1025 case MC_SEQ_MISC0__MT__DDR3: 1026 return AMDGPU_VRAM_TYPE_DDR3; 1027 default: 1028 return AMDGPU_VRAM_TYPE_UNKNOWN; 1029 } 1030 } 1031 1032 static int gmc_v8_0_early_init(void *handle) 1033 { 1034 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1035 1036 gmc_v8_0_set_gmc_funcs(adev); 1037 gmc_v8_0_set_irq_funcs(adev); 1038 1039 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1040 adev->gmc.shared_aperture_end = 1041 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1042 adev->gmc.private_aperture_start = 1043 adev->gmc.shared_aperture_end + 1; 1044 adev->gmc.private_aperture_end = 1045 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1046 1047 return 0; 1048 } 1049 1050 static int gmc_v8_0_late_init(void *handle) 1051 { 1052 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1053 1054 amdgpu_bo_late_init(adev); 1055 1056 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 1057 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1058 else 1059 return 0; 1060 } 1061 1062 static unsigned gmc_v8_0_get_vbios_fb_size(struct amdgpu_device *adev) 1063 { 1064 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); 1065 unsigned size; 1066 1067 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1068 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */ 1069 } else { 1070 u32 viewport = RREG32(mmVIEWPORT_SIZE); 1071 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1072 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1073 4); 1074 } 1075 /* return 0 if the pre-OS buffer uses up most of vram */ 1076 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 1077 return 0; 1078 return size; 1079 } 1080 1081 #define mmMC_SEQ_MISC0_FIJI 0xA71 1082 1083 static int gmc_v8_0_sw_init(void *handle) 1084 { 1085 int r; 1086 int dma_bits; 1087 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1088 1089 if (adev->flags & AMD_IS_APU) { 1090 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 1091 } else { 1092 u32 tmp; 1093 1094 if ((adev->asic_type == CHIP_FIJI) || 1095 (adev->asic_type == CHIP_VEGAM)) 1096 tmp = RREG32(mmMC_SEQ_MISC0_FIJI); 1097 else 1098 tmp = RREG32(mmMC_SEQ_MISC0); 1099 tmp &= MC_SEQ_MISC0__MT__MASK; 1100 adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp); 1101 } 1102 1103 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault); 1104 if (r) 1105 return r; 1106 1107 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault); 1108 if (r) 1109 return r; 1110 1111 /* Adjust VM size here. 1112 * Currently set to 4GB ((1 << 20) 4k pages). 1113 * Max GPUVM size for cayman and SI is 40 bits. 1114 */ 1115 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); 1116 1117 /* Set the internal MC address mask 1118 * This is the max address of the GPU's 1119 * internal address space. 1120 */ 1121 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1122 1123 /* set DMA mask + need_dma32 flags. 1124 * PCIE - can handle 40-bits. 1125 * IGP - can handle 40-bits 1126 * PCI - dma32 for legacy pci gart, 40 bits on newer asics 1127 */ 1128 adev->need_dma32 = false; 1129 dma_bits = adev->need_dma32 ? 32 : 40; 1130 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 1131 if (r) { 1132 adev->need_dma32 = true; 1133 dma_bits = 32; 1134 pr_warn("amdgpu: No suitable DMA available\n"); 1135 } 1136 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 1137 if (r) { 1138 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); 1139 pr_warn("amdgpu: No coherent DMA available\n"); 1140 } 1141 adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits); 1142 1143 r = gmc_v8_0_init_microcode(adev); 1144 if (r) { 1145 DRM_ERROR("Failed to load mc firmware!\n"); 1146 return r; 1147 } 1148 1149 r = gmc_v8_0_mc_init(adev); 1150 if (r) 1151 return r; 1152 1153 adev->gmc.stolen_size = gmc_v8_0_get_vbios_fb_size(adev); 1154 1155 /* Memory manager */ 1156 r = amdgpu_bo_init(adev); 1157 if (r) 1158 return r; 1159 1160 r = gmc_v8_0_gart_init(adev); 1161 if (r) 1162 return r; 1163 1164 /* 1165 * number of VMs 1166 * VMID 0 is reserved for System 1167 * amdgpu graphics/compute will use VMIDs 1-7 1168 * amdkfd will use VMIDs 8-15 1169 */ 1170 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; 1171 amdgpu_vm_manager_init(adev); 1172 1173 /* base offset of vram pages */ 1174 if (adev->flags & AMD_IS_APU) { 1175 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 1176 1177 tmp <<= 22; 1178 adev->vm_manager.vram_base_offset = tmp; 1179 } else { 1180 adev->vm_manager.vram_base_offset = 0; 1181 } 1182 1183 return 0; 1184 } 1185 1186 static int gmc_v8_0_sw_fini(void *handle) 1187 { 1188 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1189 1190 amdgpu_gem_force_release(adev); 1191 amdgpu_vm_manager_fini(adev); 1192 gmc_v8_0_gart_fini(adev); 1193 amdgpu_bo_fini(adev); 1194 release_firmware(adev->gmc.fw); 1195 adev->gmc.fw = NULL; 1196 1197 return 0; 1198 } 1199 1200 static int gmc_v8_0_hw_init(void *handle) 1201 { 1202 int r; 1203 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1204 1205 gmc_v8_0_init_golden_registers(adev); 1206 1207 gmc_v8_0_mc_program(adev); 1208 1209 if (adev->asic_type == CHIP_TONGA) { 1210 r = gmc_v8_0_tonga_mc_load_microcode(adev); 1211 if (r) { 1212 DRM_ERROR("Failed to load MC firmware!\n"); 1213 return r; 1214 } 1215 } else if (adev->asic_type == CHIP_POLARIS11 || 1216 adev->asic_type == CHIP_POLARIS10 || 1217 adev->asic_type == CHIP_POLARIS12) { 1218 r = gmc_v8_0_polaris_mc_load_microcode(adev); 1219 if (r) { 1220 DRM_ERROR("Failed to load MC firmware!\n"); 1221 return r; 1222 } 1223 } 1224 1225 r = gmc_v8_0_gart_enable(adev); 1226 if (r) 1227 return r; 1228 1229 return r; 1230 } 1231 1232 static int gmc_v8_0_hw_fini(void *handle) 1233 { 1234 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1235 1236 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1237 gmc_v8_0_gart_disable(adev); 1238 1239 return 0; 1240 } 1241 1242 static int gmc_v8_0_suspend(void *handle) 1243 { 1244 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1245 1246 gmc_v8_0_hw_fini(adev); 1247 1248 return 0; 1249 } 1250 1251 static int gmc_v8_0_resume(void *handle) 1252 { 1253 int r; 1254 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1255 1256 r = gmc_v8_0_hw_init(adev); 1257 if (r) 1258 return r; 1259 1260 amdgpu_vmid_reset_all(adev); 1261 1262 return 0; 1263 } 1264 1265 static bool gmc_v8_0_is_idle(void *handle) 1266 { 1267 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1268 u32 tmp = RREG32(mmSRBM_STATUS); 1269 1270 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1271 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 1272 return false; 1273 1274 return true; 1275 } 1276 1277 static int gmc_v8_0_wait_for_idle(void *handle) 1278 { 1279 unsigned i; 1280 u32 tmp; 1281 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1282 1283 for (i = 0; i < adev->usec_timeout; i++) { 1284 /* read MC_STATUS */ 1285 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | 1286 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1287 SRBM_STATUS__MCC_BUSY_MASK | 1288 SRBM_STATUS__MCD_BUSY_MASK | 1289 SRBM_STATUS__VMC_BUSY_MASK | 1290 SRBM_STATUS__VMC1_BUSY_MASK); 1291 if (!tmp) 1292 return 0; 1293 udelay(1); 1294 } 1295 return -ETIMEDOUT; 1296 1297 } 1298 1299 static bool gmc_v8_0_check_soft_reset(void *handle) 1300 { 1301 u32 srbm_soft_reset = 0; 1302 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1303 u32 tmp = RREG32(mmSRBM_STATUS); 1304 1305 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1306 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1307 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 1308 1309 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1310 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 1311 if (!(adev->flags & AMD_IS_APU)) 1312 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1313 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1314 } 1315 if (srbm_soft_reset) { 1316 adev->gmc.srbm_soft_reset = srbm_soft_reset; 1317 return true; 1318 } else { 1319 adev->gmc.srbm_soft_reset = 0; 1320 return false; 1321 } 1322 } 1323 1324 static int gmc_v8_0_pre_soft_reset(void *handle) 1325 { 1326 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1327 1328 if (!adev->gmc.srbm_soft_reset) 1329 return 0; 1330 1331 gmc_v8_0_mc_stop(adev); 1332 if (gmc_v8_0_wait_for_idle(adev)) { 1333 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1334 } 1335 1336 return 0; 1337 } 1338 1339 static int gmc_v8_0_soft_reset(void *handle) 1340 { 1341 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1342 u32 srbm_soft_reset; 1343 1344 if (!adev->gmc.srbm_soft_reset) 1345 return 0; 1346 srbm_soft_reset = adev->gmc.srbm_soft_reset; 1347 1348 if (srbm_soft_reset) { 1349 u32 tmp; 1350 1351 tmp = RREG32(mmSRBM_SOFT_RESET); 1352 tmp |= srbm_soft_reset; 1353 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1354 WREG32(mmSRBM_SOFT_RESET, tmp); 1355 tmp = RREG32(mmSRBM_SOFT_RESET); 1356 1357 udelay(50); 1358 1359 tmp &= ~srbm_soft_reset; 1360 WREG32(mmSRBM_SOFT_RESET, tmp); 1361 tmp = RREG32(mmSRBM_SOFT_RESET); 1362 1363 /* Wait a little for things to settle down */ 1364 udelay(50); 1365 } 1366 1367 return 0; 1368 } 1369 1370 static int gmc_v8_0_post_soft_reset(void *handle) 1371 { 1372 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1373 1374 if (!adev->gmc.srbm_soft_reset) 1375 return 0; 1376 1377 gmc_v8_0_mc_resume(adev); 1378 return 0; 1379 } 1380 1381 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1382 struct amdgpu_irq_src *src, 1383 unsigned type, 1384 enum amdgpu_interrupt_state state) 1385 { 1386 u32 tmp; 1387 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1388 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1389 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1390 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1391 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1392 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1393 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1394 1395 switch (state) { 1396 case AMDGPU_IRQ_STATE_DISABLE: 1397 /* system context */ 1398 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1399 tmp &= ~bits; 1400 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1401 /* VMs */ 1402 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1403 tmp &= ~bits; 1404 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1405 break; 1406 case AMDGPU_IRQ_STATE_ENABLE: 1407 /* system context */ 1408 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1409 tmp |= bits; 1410 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1411 /* VMs */ 1412 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1413 tmp |= bits; 1414 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1415 break; 1416 default: 1417 break; 1418 } 1419 1420 return 0; 1421 } 1422 1423 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, 1424 struct amdgpu_irq_src *source, 1425 struct amdgpu_iv_entry *entry) 1426 { 1427 u32 addr, status, mc_client; 1428 1429 if (amdgpu_sriov_vf(adev)) { 1430 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1431 entry->src_id, entry->src_data[0]); 1432 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n"); 1433 return 0; 1434 } 1435 1436 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1437 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1438 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); 1439 /* reset addr and status */ 1440 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1441 1442 if (!addr && !status) 1443 return 0; 1444 1445 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1446 gmc_v8_0_set_fault_enable_default(adev, false); 1447 1448 if (printk_ratelimit()) { 1449 struct amdgpu_task_info task_info = { 0 }; 1450 1451 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 1452 1453 dev_err(adev->dev, "GPU fault detected: %d 0x%08x for process %s pid %d thread %s pid %d\n", 1454 entry->src_id, entry->src_data[0], task_info.process_name, 1455 task_info.tgid, task_info.task_name, task_info.pid); 1456 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1457 addr); 1458 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1459 status); 1460 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client, 1461 entry->pasid); 1462 } 1463 1464 return 0; 1465 } 1466 1467 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev, 1468 bool enable) 1469 { 1470 uint32_t data; 1471 1472 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 1473 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1474 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1475 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1476 1477 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1478 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1479 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1480 1481 data = RREG32(mmMC_HUB_MISC_VM_CG); 1482 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK; 1483 WREG32(mmMC_HUB_MISC_VM_CG, data); 1484 1485 data = RREG32(mmMC_XPB_CLK_GAT); 1486 data |= MC_XPB_CLK_GAT__ENABLE_MASK; 1487 WREG32(mmMC_XPB_CLK_GAT, data); 1488 1489 data = RREG32(mmATC_MISC_CG); 1490 data |= ATC_MISC_CG__ENABLE_MASK; 1491 WREG32(mmATC_MISC_CG, data); 1492 1493 data = RREG32(mmMC_CITF_MISC_WR_CG); 1494 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK; 1495 WREG32(mmMC_CITF_MISC_WR_CG, data); 1496 1497 data = RREG32(mmMC_CITF_MISC_RD_CG); 1498 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK; 1499 WREG32(mmMC_CITF_MISC_RD_CG, data); 1500 1501 data = RREG32(mmMC_CITF_MISC_VM_CG); 1502 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK; 1503 WREG32(mmMC_CITF_MISC_VM_CG, data); 1504 1505 data = RREG32(mmVM_L2_CG); 1506 data |= VM_L2_CG__ENABLE_MASK; 1507 WREG32(mmVM_L2_CG, data); 1508 } else { 1509 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1510 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1511 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1512 1513 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1514 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1515 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1516 1517 data = RREG32(mmMC_HUB_MISC_VM_CG); 1518 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK; 1519 WREG32(mmMC_HUB_MISC_VM_CG, data); 1520 1521 data = RREG32(mmMC_XPB_CLK_GAT); 1522 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK; 1523 WREG32(mmMC_XPB_CLK_GAT, data); 1524 1525 data = RREG32(mmATC_MISC_CG); 1526 data &= ~ATC_MISC_CG__ENABLE_MASK; 1527 WREG32(mmATC_MISC_CG, data); 1528 1529 data = RREG32(mmMC_CITF_MISC_WR_CG); 1530 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK; 1531 WREG32(mmMC_CITF_MISC_WR_CG, data); 1532 1533 data = RREG32(mmMC_CITF_MISC_RD_CG); 1534 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK; 1535 WREG32(mmMC_CITF_MISC_RD_CG, data); 1536 1537 data = RREG32(mmMC_CITF_MISC_VM_CG); 1538 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK; 1539 WREG32(mmMC_CITF_MISC_VM_CG, data); 1540 1541 data = RREG32(mmVM_L2_CG); 1542 data &= ~VM_L2_CG__ENABLE_MASK; 1543 WREG32(mmVM_L2_CG, data); 1544 } 1545 } 1546 1547 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev, 1548 bool enable) 1549 { 1550 uint32_t data; 1551 1552 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) { 1553 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1554 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1555 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1556 1557 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1558 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1559 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1560 1561 data = RREG32(mmMC_HUB_MISC_VM_CG); 1562 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1563 WREG32(mmMC_HUB_MISC_VM_CG, data); 1564 1565 data = RREG32(mmMC_XPB_CLK_GAT); 1566 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1567 WREG32(mmMC_XPB_CLK_GAT, data); 1568 1569 data = RREG32(mmATC_MISC_CG); 1570 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1571 WREG32(mmATC_MISC_CG, data); 1572 1573 data = RREG32(mmMC_CITF_MISC_WR_CG); 1574 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1575 WREG32(mmMC_CITF_MISC_WR_CG, data); 1576 1577 data = RREG32(mmMC_CITF_MISC_RD_CG); 1578 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1579 WREG32(mmMC_CITF_MISC_RD_CG, data); 1580 1581 data = RREG32(mmMC_CITF_MISC_VM_CG); 1582 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1583 WREG32(mmMC_CITF_MISC_VM_CG, data); 1584 1585 data = RREG32(mmVM_L2_CG); 1586 data |= VM_L2_CG__MEM_LS_ENABLE_MASK; 1587 WREG32(mmVM_L2_CG, data); 1588 } else { 1589 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1590 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1591 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1592 1593 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1594 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1595 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1596 1597 data = RREG32(mmMC_HUB_MISC_VM_CG); 1598 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1599 WREG32(mmMC_HUB_MISC_VM_CG, data); 1600 1601 data = RREG32(mmMC_XPB_CLK_GAT); 1602 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1603 WREG32(mmMC_XPB_CLK_GAT, data); 1604 1605 data = RREG32(mmATC_MISC_CG); 1606 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1607 WREG32(mmATC_MISC_CG, data); 1608 1609 data = RREG32(mmMC_CITF_MISC_WR_CG); 1610 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1611 WREG32(mmMC_CITF_MISC_WR_CG, data); 1612 1613 data = RREG32(mmMC_CITF_MISC_RD_CG); 1614 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1615 WREG32(mmMC_CITF_MISC_RD_CG, data); 1616 1617 data = RREG32(mmMC_CITF_MISC_VM_CG); 1618 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1619 WREG32(mmMC_CITF_MISC_VM_CG, data); 1620 1621 data = RREG32(mmVM_L2_CG); 1622 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK; 1623 WREG32(mmVM_L2_CG, data); 1624 } 1625 } 1626 1627 static int gmc_v8_0_set_clockgating_state(void *handle, 1628 enum amd_clockgating_state state) 1629 { 1630 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1631 1632 if (amdgpu_sriov_vf(adev)) 1633 return 0; 1634 1635 switch (adev->asic_type) { 1636 case CHIP_FIJI: 1637 fiji_update_mc_medium_grain_clock_gating(adev, 1638 state == AMD_CG_STATE_GATE); 1639 fiji_update_mc_light_sleep(adev, 1640 state == AMD_CG_STATE_GATE); 1641 break; 1642 default: 1643 break; 1644 } 1645 return 0; 1646 } 1647 1648 static int gmc_v8_0_set_powergating_state(void *handle, 1649 enum amd_powergating_state state) 1650 { 1651 return 0; 1652 } 1653 1654 static void gmc_v8_0_get_clockgating_state(void *handle, u32 *flags) 1655 { 1656 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1657 int data; 1658 1659 if (amdgpu_sriov_vf(adev)) 1660 *flags = 0; 1661 1662 /* AMD_CG_SUPPORT_MC_MGCG */ 1663 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1664 if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK) 1665 *flags |= AMD_CG_SUPPORT_MC_MGCG; 1666 1667 /* AMD_CG_SUPPORT_MC_LS */ 1668 if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK) 1669 *flags |= AMD_CG_SUPPORT_MC_LS; 1670 } 1671 1672 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = { 1673 .name = "gmc_v8_0", 1674 .early_init = gmc_v8_0_early_init, 1675 .late_init = gmc_v8_0_late_init, 1676 .sw_init = gmc_v8_0_sw_init, 1677 .sw_fini = gmc_v8_0_sw_fini, 1678 .hw_init = gmc_v8_0_hw_init, 1679 .hw_fini = gmc_v8_0_hw_fini, 1680 .suspend = gmc_v8_0_suspend, 1681 .resume = gmc_v8_0_resume, 1682 .is_idle = gmc_v8_0_is_idle, 1683 .wait_for_idle = gmc_v8_0_wait_for_idle, 1684 .check_soft_reset = gmc_v8_0_check_soft_reset, 1685 .pre_soft_reset = gmc_v8_0_pre_soft_reset, 1686 .soft_reset = gmc_v8_0_soft_reset, 1687 .post_soft_reset = gmc_v8_0_post_soft_reset, 1688 .set_clockgating_state = gmc_v8_0_set_clockgating_state, 1689 .set_powergating_state = gmc_v8_0_set_powergating_state, 1690 .get_clockgating_state = gmc_v8_0_get_clockgating_state, 1691 }; 1692 1693 static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = { 1694 .flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb, 1695 .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb, 1696 .emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping, 1697 .set_pte_pde = gmc_v8_0_set_pte_pde, 1698 .set_prt = gmc_v8_0_set_prt, 1699 .get_vm_pte_flags = gmc_v8_0_get_vm_pte_flags, 1700 .get_vm_pde = gmc_v8_0_get_vm_pde 1701 }; 1702 1703 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = { 1704 .set = gmc_v8_0_vm_fault_interrupt_state, 1705 .process = gmc_v8_0_process_interrupt, 1706 }; 1707 1708 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev) 1709 { 1710 if (adev->gmc.gmc_funcs == NULL) 1711 adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs; 1712 } 1713 1714 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev) 1715 { 1716 adev->gmc.vm_fault.num_types = 1; 1717 adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs; 1718 } 1719 1720 const struct amdgpu_ip_block_version gmc_v8_0_ip_block = 1721 { 1722 .type = AMD_IP_BLOCK_TYPE_GMC, 1723 .major = 8, 1724 .minor = 0, 1725 .rev = 0, 1726 .funcs = &gmc_v8_0_ip_funcs, 1727 }; 1728 1729 const struct amdgpu_ip_block_version gmc_v8_1_ip_block = 1730 { 1731 .type = AMD_IP_BLOCK_TYPE_GMC, 1732 .major = 8, 1733 .minor = 1, 1734 .rev = 0, 1735 .funcs = &gmc_v8_0_ip_funcs, 1736 }; 1737 1738 const struct amdgpu_ip_block_version gmc_v8_5_ip_block = 1739 { 1740 .type = AMD_IP_BLOCK_TYPE_GMC, 1741 .major = 8, 1742 .minor = 5, 1743 .rev = 0, 1744 .funcs = &gmc_v8_0_ip_funcs, 1745 }; 1746