1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <drm/drmP.h> 25 #include "amdgpu.h" 26 #include "gmc_v8_0.h" 27 #include "amdgpu_ucode.h" 28 29 #include "gmc/gmc_8_1_d.h" 30 #include "gmc/gmc_8_1_sh_mask.h" 31 32 #include "bif/bif_5_0_d.h" 33 #include "bif/bif_5_0_sh_mask.h" 34 35 #include "oss/oss_3_0_d.h" 36 #include "oss/oss_3_0_sh_mask.h" 37 38 #include "vid.h" 39 #include "vi.h" 40 41 #include "amdgpu_atombios.h" 42 43 44 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev); 45 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev); 46 static int gmc_v8_0_wait_for_idle(void *handle); 47 48 MODULE_FIRMWARE("amdgpu/tonga_mc.bin"); 49 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin"); 50 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin"); 51 MODULE_FIRMWARE("amdgpu/polaris12_mc.bin"); 52 53 static const u32 golden_settings_tonga_a11[] = 54 { 55 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, 56 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028, 57 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991, 58 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 59 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 60 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 61 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 62 }; 63 64 static const u32 tonga_mgcg_cgcg_init[] = 65 { 66 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 67 }; 68 69 static const u32 golden_settings_fiji_a10[] = 70 { 71 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 72 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 73 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 74 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 75 }; 76 77 static const u32 fiji_mgcg_cgcg_init[] = 78 { 79 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 80 }; 81 82 static const u32 golden_settings_polaris11_a11[] = 83 { 84 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 85 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 86 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 87 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 88 }; 89 90 static const u32 golden_settings_polaris10_a11[] = 91 { 92 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, 93 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 94 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 95 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 96 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 97 }; 98 99 static const u32 cz_mgcg_cgcg_init[] = 100 { 101 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 102 }; 103 104 static const u32 stoney_mgcg_cgcg_init[] = 105 { 106 mmATC_MISC_CG, 0xffffffff, 0x000c0200, 107 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 108 }; 109 110 static const u32 golden_settings_stoney_common[] = 111 { 112 mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004, 113 mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000 114 }; 115 116 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) 117 { 118 switch (adev->asic_type) { 119 case CHIP_FIJI: 120 amdgpu_program_register_sequence(adev, 121 fiji_mgcg_cgcg_init, 122 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); 123 amdgpu_program_register_sequence(adev, 124 golden_settings_fiji_a10, 125 (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); 126 break; 127 case CHIP_TONGA: 128 amdgpu_program_register_sequence(adev, 129 tonga_mgcg_cgcg_init, 130 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); 131 amdgpu_program_register_sequence(adev, 132 golden_settings_tonga_a11, 133 (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); 134 break; 135 case CHIP_POLARIS11: 136 case CHIP_POLARIS12: 137 amdgpu_program_register_sequence(adev, 138 golden_settings_polaris11_a11, 139 (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); 140 break; 141 case CHIP_POLARIS10: 142 amdgpu_program_register_sequence(adev, 143 golden_settings_polaris10_a11, 144 (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); 145 break; 146 case CHIP_CARRIZO: 147 amdgpu_program_register_sequence(adev, 148 cz_mgcg_cgcg_init, 149 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); 150 break; 151 case CHIP_STONEY: 152 amdgpu_program_register_sequence(adev, 153 stoney_mgcg_cgcg_init, 154 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); 155 amdgpu_program_register_sequence(adev, 156 golden_settings_stoney_common, 157 (const u32)ARRAY_SIZE(golden_settings_stoney_common)); 158 break; 159 default: 160 break; 161 } 162 } 163 164 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev, 165 struct amdgpu_mode_mc_save *save) 166 { 167 u32 blackout; 168 169 if (adev->mode_info.num_crtc) 170 amdgpu_display_stop_mc_access(adev, save); 171 172 gmc_v8_0_wait_for_idle(adev); 173 174 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 175 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 176 /* Block CPU access */ 177 WREG32(mmBIF_FB_EN, 0); 178 /* blackout the MC */ 179 blackout = REG_SET_FIELD(blackout, 180 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1); 181 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout); 182 } 183 /* wait for the MC to settle */ 184 udelay(100); 185 } 186 187 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev, 188 struct amdgpu_mode_mc_save *save) 189 { 190 u32 tmp; 191 192 /* unblackout the MC */ 193 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 194 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 195 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 196 /* allow CPU access */ 197 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 198 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 199 WREG32(mmBIF_FB_EN, tmp); 200 201 if (adev->mode_info.num_crtc) 202 amdgpu_display_resume_mc_access(adev, save); 203 } 204 205 /** 206 * gmc_v8_0_init_microcode - load ucode images from disk 207 * 208 * @adev: amdgpu_device pointer 209 * 210 * Use the firmware interface to load the ucode images into 211 * the driver (not loaded into hw). 212 * Returns 0 on success, error on failure. 213 */ 214 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) 215 { 216 const char *chip_name; 217 char fw_name[30]; 218 int err; 219 220 DRM_DEBUG("\n"); 221 222 switch (adev->asic_type) { 223 case CHIP_TONGA: 224 chip_name = "tonga"; 225 break; 226 case CHIP_POLARIS11: 227 chip_name = "polaris11"; 228 break; 229 case CHIP_POLARIS10: 230 chip_name = "polaris10"; 231 break; 232 case CHIP_POLARIS12: 233 chip_name = "polaris12"; 234 break; 235 case CHIP_FIJI: 236 case CHIP_CARRIZO: 237 case CHIP_STONEY: 238 return 0; 239 default: BUG(); 240 } 241 242 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name); 243 err = request_firmware(&adev->mc.fw, fw_name, adev->dev); 244 if (err) 245 goto out; 246 err = amdgpu_ucode_validate(adev->mc.fw); 247 248 out: 249 if (err) { 250 pr_err("mc: Failed to load firmware \"%s\"\n", fw_name); 251 release_firmware(adev->mc.fw); 252 adev->mc.fw = NULL; 253 } 254 return err; 255 } 256 257 /** 258 * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw 259 * 260 * @adev: amdgpu_device pointer 261 * 262 * Load the GDDR MC ucode into the hw (CIK). 263 * Returns 0 on success, error on failure. 264 */ 265 static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev) 266 { 267 const struct mc_firmware_header_v1_0 *hdr; 268 const __le32 *fw_data = NULL; 269 const __le32 *io_mc_regs = NULL; 270 u32 running; 271 int i, ucode_size, regs_size; 272 273 /* Skip MC ucode loading on SR-IOV capable boards. 274 * vbios does this for us in asic_init in that case. 275 * Skip MC ucode loading on VF, because hypervisor will do that 276 * for this adaptor. 277 */ 278 if (amdgpu_sriov_bios(adev)) 279 return 0; 280 281 if (!adev->mc.fw) 282 return -EINVAL; 283 284 hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data; 285 amdgpu_ucode_print_mc_hdr(&hdr->header); 286 287 adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version); 288 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 289 io_mc_regs = (const __le32 *) 290 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 291 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 292 fw_data = (const __le32 *) 293 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 294 295 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); 296 297 if (running == 0) { 298 /* reset the engine and set to writable */ 299 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 300 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 301 302 /* load mc io regs */ 303 for (i = 0; i < regs_size; i++) { 304 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 305 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 306 } 307 /* load the MC ucode */ 308 for (i = 0; i < ucode_size; i++) 309 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 310 311 /* put the engine back into the active state */ 312 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 313 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 314 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 315 316 /* wait for training to complete */ 317 for (i = 0; i < adev->usec_timeout; i++) { 318 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 319 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0)) 320 break; 321 udelay(1); 322 } 323 for (i = 0; i < adev->usec_timeout; i++) { 324 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 325 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1)) 326 break; 327 udelay(1); 328 } 329 } 330 331 return 0; 332 } 333 334 static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev) 335 { 336 const struct mc_firmware_header_v1_0 *hdr; 337 const __le32 *fw_data = NULL; 338 const __le32 *io_mc_regs = NULL; 339 u32 data, vbios_version; 340 int i, ucode_size, regs_size; 341 342 /* Skip MC ucode loading on SR-IOV capable boards. 343 * vbios does this for us in asic_init in that case. 344 * Skip MC ucode loading on VF, because hypervisor will do that 345 * for this adaptor. 346 */ 347 if (amdgpu_sriov_bios(adev)) 348 return 0; 349 350 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 0x9F); 351 data = RREG32(mmMC_SEQ_IO_DEBUG_DATA); 352 vbios_version = data & 0xf; 353 354 if (vbios_version == 0) 355 return 0; 356 357 if (!adev->mc.fw) 358 return -EINVAL; 359 360 hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data; 361 amdgpu_ucode_print_mc_hdr(&hdr->header); 362 363 adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version); 364 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 365 io_mc_regs = (const __le32 *) 366 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 367 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 368 fw_data = (const __le32 *) 369 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 370 371 data = RREG32(mmMC_SEQ_MISC0); 372 data &= ~(0x40); 373 WREG32(mmMC_SEQ_MISC0, data); 374 375 /* load mc io regs */ 376 for (i = 0; i < regs_size; i++) { 377 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 378 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 379 } 380 381 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 382 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 383 384 /* load the MC ucode */ 385 for (i = 0; i < ucode_size; i++) 386 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 387 388 /* put the engine back into the active state */ 389 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 390 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 391 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 392 393 /* wait for training to complete */ 394 for (i = 0; i < adev->usec_timeout; i++) { 395 data = RREG32(mmMC_SEQ_MISC0); 396 if (data & 0x80) 397 break; 398 udelay(1); 399 } 400 401 return 0; 402 } 403 404 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev, 405 struct amdgpu_mc *mc) 406 { 407 if (mc->mc_vram_size > 0xFFC0000000ULL) { 408 /* leave room for at least 1024M GTT */ 409 dev_warn(adev->dev, "limiting VRAM\n"); 410 mc->real_vram_size = 0xFFC0000000ULL; 411 mc->mc_vram_size = 0xFFC0000000ULL; 412 } 413 amdgpu_vram_location(adev, &adev->mc, 0); 414 adev->mc.gtt_base_align = 0; 415 amdgpu_gtt_location(adev, mc); 416 } 417 418 /** 419 * gmc_v8_0_mc_program - program the GPU memory controller 420 * 421 * @adev: amdgpu_device pointer 422 * 423 * Set the location of vram, gart, and AGP in the GPU's 424 * physical address space (CIK). 425 */ 426 static void gmc_v8_0_mc_program(struct amdgpu_device *adev) 427 { 428 struct amdgpu_mode_mc_save save; 429 u32 tmp; 430 int i, j; 431 432 /* Initialize HDP */ 433 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 434 WREG32((0xb05 + j), 0x00000000); 435 WREG32((0xb06 + j), 0x00000000); 436 WREG32((0xb07 + j), 0x00000000); 437 WREG32((0xb08 + j), 0x00000000); 438 WREG32((0xb09 + j), 0x00000000); 439 } 440 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 441 442 if (adev->mode_info.num_crtc) 443 amdgpu_display_set_vga_render_state(adev, false); 444 445 gmc_v8_0_mc_stop(adev, &save); 446 if (gmc_v8_0_wait_for_idle((void *)adev)) { 447 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 448 } 449 /* Update configuration */ 450 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 451 adev->mc.vram_start >> 12); 452 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 453 adev->mc.vram_end >> 12); 454 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 455 adev->vram_scratch.gpu_addr >> 12); 456 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16; 457 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF); 458 WREG32(mmMC_VM_FB_LOCATION, tmp); 459 /* XXX double check these! */ 460 WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8)); 461 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); 462 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF); 463 WREG32(mmMC_VM_AGP_BASE, 0); 464 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); 465 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); 466 if (gmc_v8_0_wait_for_idle((void *)adev)) { 467 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 468 } 469 gmc_v8_0_mc_resume(adev, &save); 470 471 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 472 473 tmp = RREG32(mmHDP_MISC_CNTL); 474 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); 475 WREG32(mmHDP_MISC_CNTL, tmp); 476 477 tmp = RREG32(mmHDP_HOST_PATH_CNTL); 478 WREG32(mmHDP_HOST_PATH_CNTL, tmp); 479 } 480 481 /** 482 * gmc_v8_0_mc_init - initialize the memory controller driver params 483 * 484 * @adev: amdgpu_device pointer 485 * 486 * Look up the amount of vram, vram width, and decide how to place 487 * vram and gart within the GPU's physical address space (CIK). 488 * Returns 0 for success. 489 */ 490 static int gmc_v8_0_mc_init(struct amdgpu_device *adev) 491 { 492 adev->mc.vram_width = amdgpu_atombios_get_vram_width(adev); 493 if (!adev->mc.vram_width) { 494 u32 tmp; 495 int chansize, numchan; 496 497 /* Get VRAM informations */ 498 tmp = RREG32(mmMC_ARB_RAMCFG); 499 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { 500 chansize = 64; 501 } else { 502 chansize = 32; 503 } 504 tmp = RREG32(mmMC_SHARED_CHMAP); 505 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 506 case 0: 507 default: 508 numchan = 1; 509 break; 510 case 1: 511 numchan = 2; 512 break; 513 case 2: 514 numchan = 4; 515 break; 516 case 3: 517 numchan = 8; 518 break; 519 case 4: 520 numchan = 3; 521 break; 522 case 5: 523 numchan = 6; 524 break; 525 case 6: 526 numchan = 10; 527 break; 528 case 7: 529 numchan = 12; 530 break; 531 case 8: 532 numchan = 16; 533 break; 534 } 535 adev->mc.vram_width = numchan * chansize; 536 } 537 /* Could aper size report 0 ? */ 538 adev->mc.aper_base = pci_resource_start(adev->pdev, 0); 539 adev->mc.aper_size = pci_resource_len(adev->pdev, 0); 540 /* size in MB on si */ 541 adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 542 adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 543 544 #ifdef CONFIG_X86_64 545 if (adev->flags & AMD_IS_APU) { 546 adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; 547 adev->mc.aper_size = adev->mc.real_vram_size; 548 } 549 #endif 550 551 /* In case the PCI BAR is larger than the actual amount of vram */ 552 adev->mc.visible_vram_size = adev->mc.aper_size; 553 if (adev->mc.visible_vram_size > adev->mc.real_vram_size) 554 adev->mc.visible_vram_size = adev->mc.real_vram_size; 555 556 /* unless the user had overridden it, set the gart 557 * size equal to the 1024 or vram, whichever is larger. 558 */ 559 if (amdgpu_gart_size == -1) 560 adev->mc.gtt_size = max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20), 561 adev->mc.mc_vram_size); 562 else 563 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20; 564 565 gmc_v8_0_vram_gtt_location(adev, &adev->mc); 566 567 return 0; 568 } 569 570 /* 571 * GART 572 * VMID 0 is the physical GPU addresses as used by the kernel. 573 * VMIDs 1-15 are used for userspace clients and are handled 574 * by the amdgpu vm/hsa code. 575 */ 576 577 /** 578 * gmc_v8_0_gart_flush_gpu_tlb - gart tlb flush callback 579 * 580 * @adev: amdgpu_device pointer 581 * @vmid: vm instance to flush 582 * 583 * Flush the TLB for the requested page table (CIK). 584 */ 585 static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, 586 uint32_t vmid) 587 { 588 /* flush hdp cache */ 589 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0); 590 591 /* bits 0-15 are the VM contexts0-15 */ 592 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 593 } 594 595 /** 596 * gmc_v8_0_gart_set_pte_pde - update the page tables using MMIO 597 * 598 * @adev: amdgpu_device pointer 599 * @cpu_pt_addr: cpu address of the page table 600 * @gpu_page_idx: entry in the page table to update 601 * @addr: dst addr to write into pte/pde 602 * @flags: access flags 603 * 604 * Update the page tables using the CPU. 605 */ 606 static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev, 607 void *cpu_pt_addr, 608 uint32_t gpu_page_idx, 609 uint64_t addr, 610 uint64_t flags) 611 { 612 void __iomem *ptr = (void *)cpu_pt_addr; 613 uint64_t value; 614 615 /* 616 * PTE format on VI: 617 * 63:40 reserved 618 * 39:12 4k physical page base address 619 * 11:7 fragment 620 * 6 write 621 * 5 read 622 * 4 exe 623 * 3 reserved 624 * 2 snooped 625 * 1 system 626 * 0 valid 627 * 628 * PDE format on VI: 629 * 63:59 block fragment size 630 * 58:40 reserved 631 * 39:1 physical base address of PTE 632 * bits 5:1 must be 0. 633 * 0 valid 634 */ 635 value = addr & 0x000000FFFFFFF000ULL; 636 value |= flags; 637 writeq(value, ptr + (gpu_page_idx * 8)); 638 639 return 0; 640 } 641 642 static uint64_t gmc_v8_0_get_vm_pte_flags(struct amdgpu_device *adev, 643 uint32_t flags) 644 { 645 uint64_t pte_flag = 0; 646 647 if (flags & AMDGPU_VM_PAGE_EXECUTABLE) 648 pte_flag |= AMDGPU_PTE_EXECUTABLE; 649 if (flags & AMDGPU_VM_PAGE_READABLE) 650 pte_flag |= AMDGPU_PTE_READABLE; 651 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 652 pte_flag |= AMDGPU_PTE_WRITEABLE; 653 if (flags & AMDGPU_VM_PAGE_PRT) 654 pte_flag |= AMDGPU_PTE_PRT; 655 656 return pte_flag; 657 } 658 659 static uint64_t gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, uint64_t addr) 660 { 661 BUG_ON(addr & 0xFFFFFF0000000FFFULL); 662 return addr; 663 } 664 665 /** 666 * gmc_v8_0_set_fault_enable_default - update VM fault handling 667 * 668 * @adev: amdgpu_device pointer 669 * @value: true redirects VM faults to the default page 670 */ 671 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev, 672 bool value) 673 { 674 u32 tmp; 675 676 tmp = RREG32(mmVM_CONTEXT1_CNTL); 677 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 678 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 679 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 680 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 681 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 682 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 683 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 684 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 685 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 686 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 687 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 688 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 689 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 690 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 691 WREG32(mmVM_CONTEXT1_CNTL, tmp); 692 } 693 694 /** 695 * gmc_v8_0_set_prt - set PRT VM fault 696 * 697 * @adev: amdgpu_device pointer 698 * @enable: enable/disable VM fault handling for PRT 699 */ 700 static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable) 701 { 702 u32 tmp; 703 704 if (enable && !adev->mc.prt_warning) { 705 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 706 adev->mc.prt_warning = true; 707 } 708 709 tmp = RREG32(mmVM_PRT_CNTL); 710 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 711 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 712 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 713 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 714 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 715 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 716 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 717 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 718 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 719 L2_CACHE_STORE_INVALID_ENTRIES, enable); 720 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 721 L1_TLB_STORE_INVALID_ENTRIES, enable); 722 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 723 MASK_PDE0_FAULT, enable); 724 WREG32(mmVM_PRT_CNTL, tmp); 725 726 if (enable) { 727 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; 728 uint32_t high = adev->vm_manager.max_pfn; 729 730 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); 731 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); 732 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); 733 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); 734 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); 735 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); 736 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); 737 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); 738 } else { 739 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); 740 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); 741 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); 742 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); 743 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); 744 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); 745 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); 746 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); 747 } 748 } 749 750 /** 751 * gmc_v8_0_gart_enable - gart enable 752 * 753 * @adev: amdgpu_device pointer 754 * 755 * This sets up the TLBs, programs the page tables for VMID0, 756 * sets up the hw for VMIDs 1-15 which are allocated on 757 * demand, and sets up the global locations for the LDS, GDS, 758 * and GPUVM for FSA64 clients (CIK). 759 * Returns 0 for success, errors for failure. 760 */ 761 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) 762 { 763 int r, i; 764 u32 tmp; 765 766 if (adev->gart.robj == NULL) { 767 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 768 return -EINVAL; 769 } 770 r = amdgpu_gart_table_vram_pin(adev); 771 if (r) 772 return r; 773 /* Setup TLB control */ 774 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 775 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 776 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); 777 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 778 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); 779 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 780 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 781 /* Setup L2 cache */ 782 tmp = RREG32(mmVM_L2_CNTL); 783 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 784 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 785 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); 786 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); 787 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); 788 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 789 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 790 WREG32(mmVM_L2_CNTL, tmp); 791 tmp = RREG32(mmVM_L2_CNTL2); 792 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 793 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 794 WREG32(mmVM_L2_CNTL2, tmp); 795 tmp = RREG32(mmVM_L2_CNTL3); 796 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); 797 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4); 798 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4); 799 WREG32(mmVM_L2_CNTL3, tmp); 800 /* XXX: set to enable PTE/PDE in system memory */ 801 tmp = RREG32(mmVM_L2_CNTL4); 802 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0); 803 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0); 804 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0); 805 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0); 806 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0); 807 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0); 808 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0); 809 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0); 810 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0); 811 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0); 812 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0); 813 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0); 814 WREG32(mmVM_L2_CNTL4, tmp); 815 /* setup context0 */ 816 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12); 817 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12); 818 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); 819 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 820 (u32)(adev->dummy_page.addr >> 12)); 821 WREG32(mmVM_CONTEXT0_CNTL2, 0); 822 tmp = RREG32(mmVM_CONTEXT0_CNTL); 823 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 824 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 825 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 826 WREG32(mmVM_CONTEXT0_CNTL, tmp); 827 828 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0); 829 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0); 830 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0); 831 832 /* empty context1-15 */ 833 /* FIXME start with 4G, once using 2 level pt switch to full 834 * vm size space 835 */ 836 /* set vm size, must be a multiple of 4 */ 837 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 838 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 839 for (i = 1; i < 16; i++) { 840 if (i < 8) 841 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 842 adev->gart.table_addr >> 12); 843 else 844 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 845 adev->gart.table_addr >> 12); 846 } 847 848 /* enable context1-15 */ 849 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 850 (u32)(adev->dummy_page.addr >> 12)); 851 WREG32(mmVM_CONTEXT1_CNTL2, 4); 852 tmp = RREG32(mmVM_CONTEXT1_CNTL); 853 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 854 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); 855 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 856 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 857 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 858 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 859 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 860 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 861 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 862 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, 863 adev->vm_manager.block_size - 9); 864 WREG32(mmVM_CONTEXT1_CNTL, tmp); 865 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 866 gmc_v8_0_set_fault_enable_default(adev, false); 867 else 868 gmc_v8_0_set_fault_enable_default(adev, true); 869 870 gmc_v8_0_gart_flush_gpu_tlb(adev, 0); 871 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 872 (unsigned)(adev->mc.gtt_size >> 20), 873 (unsigned long long)adev->gart.table_addr); 874 adev->gart.ready = true; 875 return 0; 876 } 877 878 static int gmc_v8_0_gart_init(struct amdgpu_device *adev) 879 { 880 int r; 881 882 if (adev->gart.robj) { 883 WARN(1, "R600 PCIE GART already initialized\n"); 884 return 0; 885 } 886 /* Initialize common gart structure */ 887 r = amdgpu_gart_init(adev); 888 if (r) 889 return r; 890 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 891 adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE; 892 return amdgpu_gart_table_vram_alloc(adev); 893 } 894 895 /** 896 * gmc_v8_0_gart_disable - gart disable 897 * 898 * @adev: amdgpu_device pointer 899 * 900 * This disables all VM page table (CIK). 901 */ 902 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev) 903 { 904 u32 tmp; 905 906 /* Disable all tables */ 907 WREG32(mmVM_CONTEXT0_CNTL, 0); 908 WREG32(mmVM_CONTEXT1_CNTL, 0); 909 /* Setup TLB control */ 910 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 911 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 912 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); 913 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); 914 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 915 /* Setup L2 cache */ 916 tmp = RREG32(mmVM_L2_CNTL); 917 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 918 WREG32(mmVM_L2_CNTL, tmp); 919 WREG32(mmVM_L2_CNTL2, 0); 920 amdgpu_gart_table_vram_unpin(adev); 921 } 922 923 /** 924 * gmc_v8_0_gart_fini - vm fini callback 925 * 926 * @adev: amdgpu_device pointer 927 * 928 * Tears down the driver GART/VM setup (CIK). 929 */ 930 static void gmc_v8_0_gart_fini(struct amdgpu_device *adev) 931 { 932 amdgpu_gart_table_vram_free(adev); 933 amdgpu_gart_fini(adev); 934 } 935 936 /** 937 * gmc_v8_0_vm_decode_fault - print human readable fault info 938 * 939 * @adev: amdgpu_device pointer 940 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value 941 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value 942 * 943 * Print human readable fault information (CIK). 944 */ 945 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, 946 u32 status, u32 addr, u32 mc_client) 947 { 948 u32 mc_id; 949 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 950 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 951 PROTECTIONS); 952 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 953 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 954 955 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 956 MEMORY_CLIENT_ID); 957 958 dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 959 protections, vmid, addr, 960 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 961 MEMORY_CLIENT_RW) ? 962 "write" : "read", block, mc_client, mc_id); 963 } 964 965 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type) 966 { 967 switch (mc_seq_vram_type) { 968 case MC_SEQ_MISC0__MT__GDDR1: 969 return AMDGPU_VRAM_TYPE_GDDR1; 970 case MC_SEQ_MISC0__MT__DDR2: 971 return AMDGPU_VRAM_TYPE_DDR2; 972 case MC_SEQ_MISC0__MT__GDDR3: 973 return AMDGPU_VRAM_TYPE_GDDR3; 974 case MC_SEQ_MISC0__MT__GDDR4: 975 return AMDGPU_VRAM_TYPE_GDDR4; 976 case MC_SEQ_MISC0__MT__GDDR5: 977 return AMDGPU_VRAM_TYPE_GDDR5; 978 case MC_SEQ_MISC0__MT__HBM: 979 return AMDGPU_VRAM_TYPE_HBM; 980 case MC_SEQ_MISC0__MT__DDR3: 981 return AMDGPU_VRAM_TYPE_DDR3; 982 default: 983 return AMDGPU_VRAM_TYPE_UNKNOWN; 984 } 985 } 986 987 static int gmc_v8_0_early_init(void *handle) 988 { 989 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 990 991 gmc_v8_0_set_gart_funcs(adev); 992 gmc_v8_0_set_irq_funcs(adev); 993 994 adev->mc.shared_aperture_start = 0x2000000000000000ULL; 995 adev->mc.shared_aperture_end = 996 adev->mc.shared_aperture_start + (4ULL << 30) - 1; 997 adev->mc.private_aperture_start = 998 adev->mc.shared_aperture_end + 1; 999 adev->mc.private_aperture_end = 1000 adev->mc.private_aperture_start + (4ULL << 30) - 1; 1001 1002 return 0; 1003 } 1004 1005 static int gmc_v8_0_late_init(void *handle) 1006 { 1007 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1008 1009 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 1010 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0); 1011 else 1012 return 0; 1013 } 1014 1015 #define mmMC_SEQ_MISC0_FIJI 0xA71 1016 1017 static int gmc_v8_0_sw_init(void *handle) 1018 { 1019 int r; 1020 int dma_bits; 1021 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1022 1023 if (adev->flags & AMD_IS_APU) { 1024 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 1025 } else { 1026 u32 tmp; 1027 1028 if (adev->asic_type == CHIP_FIJI) 1029 tmp = RREG32(mmMC_SEQ_MISC0_FIJI); 1030 else 1031 tmp = RREG32(mmMC_SEQ_MISC0); 1032 tmp &= MC_SEQ_MISC0__MT__MASK; 1033 adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp); 1034 } 1035 1036 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault); 1037 if (r) 1038 return r; 1039 1040 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault); 1041 if (r) 1042 return r; 1043 1044 /* Adjust VM size here. 1045 * Currently set to 4GB ((1 << 20) 4k pages). 1046 * Max GPUVM size for cayman and SI is 40 bits. 1047 */ 1048 amdgpu_vm_adjust_size(adev, 64); 1049 adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; 1050 1051 /* Set the internal MC address mask 1052 * This is the max address of the GPU's 1053 * internal address space. 1054 */ 1055 adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1056 1057 adev->mc.stolen_size = 256 * 1024; 1058 1059 /* set DMA mask + need_dma32 flags. 1060 * PCIE - can handle 40-bits. 1061 * IGP - can handle 40-bits 1062 * PCI - dma32 for legacy pci gart, 40 bits on newer asics 1063 */ 1064 adev->need_dma32 = false; 1065 dma_bits = adev->need_dma32 ? 32 : 40; 1066 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 1067 if (r) { 1068 adev->need_dma32 = true; 1069 dma_bits = 32; 1070 pr_warn("amdgpu: No suitable DMA available\n"); 1071 } 1072 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 1073 if (r) { 1074 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); 1075 pr_warn("amdgpu: No coherent DMA available\n"); 1076 } 1077 1078 r = gmc_v8_0_init_microcode(adev); 1079 if (r) { 1080 DRM_ERROR("Failed to load mc firmware!\n"); 1081 return r; 1082 } 1083 1084 r = gmc_v8_0_mc_init(adev); 1085 if (r) 1086 return r; 1087 1088 /* Memory manager */ 1089 r = amdgpu_bo_init(adev); 1090 if (r) 1091 return r; 1092 1093 r = gmc_v8_0_gart_init(adev); 1094 if (r) 1095 return r; 1096 1097 /* 1098 * number of VMs 1099 * VMID 0 is reserved for System 1100 * amdgpu graphics/compute will use VMIDs 1-7 1101 * amdkfd will use VMIDs 8-15 1102 */ 1103 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; 1104 adev->vm_manager.num_level = 1; 1105 amdgpu_vm_manager_init(adev); 1106 1107 /* base offset of vram pages */ 1108 if (adev->flags & AMD_IS_APU) { 1109 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 1110 1111 tmp <<= 22; 1112 adev->vm_manager.vram_base_offset = tmp; 1113 } else { 1114 adev->vm_manager.vram_base_offset = 0; 1115 } 1116 1117 return 0; 1118 } 1119 1120 static int gmc_v8_0_sw_fini(void *handle) 1121 { 1122 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1123 1124 amdgpu_vm_manager_fini(adev); 1125 gmc_v8_0_gart_fini(adev); 1126 amdgpu_gem_force_release(adev); 1127 amdgpu_bo_fini(adev); 1128 1129 return 0; 1130 } 1131 1132 static int gmc_v8_0_hw_init(void *handle) 1133 { 1134 int r; 1135 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1136 1137 gmc_v8_0_init_golden_registers(adev); 1138 1139 gmc_v8_0_mc_program(adev); 1140 1141 if (adev->asic_type == CHIP_TONGA) { 1142 r = gmc_v8_0_tonga_mc_load_microcode(adev); 1143 if (r) { 1144 DRM_ERROR("Failed to load MC firmware!\n"); 1145 return r; 1146 } 1147 } else if (adev->asic_type == CHIP_POLARIS11 || 1148 adev->asic_type == CHIP_POLARIS10 || 1149 adev->asic_type == CHIP_POLARIS12) { 1150 r = gmc_v8_0_polaris_mc_load_microcode(adev); 1151 if (r) { 1152 DRM_ERROR("Failed to load MC firmware!\n"); 1153 return r; 1154 } 1155 } 1156 1157 r = gmc_v8_0_gart_enable(adev); 1158 if (r) 1159 return r; 1160 1161 return r; 1162 } 1163 1164 static int gmc_v8_0_hw_fini(void *handle) 1165 { 1166 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1167 1168 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0); 1169 gmc_v8_0_gart_disable(adev); 1170 1171 return 0; 1172 } 1173 1174 static int gmc_v8_0_suspend(void *handle) 1175 { 1176 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1177 1178 gmc_v8_0_hw_fini(adev); 1179 1180 return 0; 1181 } 1182 1183 static int gmc_v8_0_resume(void *handle) 1184 { 1185 int r; 1186 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1187 1188 r = gmc_v8_0_hw_init(adev); 1189 if (r) 1190 return r; 1191 1192 amdgpu_vm_reset_all_ids(adev); 1193 1194 return 0; 1195 } 1196 1197 static bool gmc_v8_0_is_idle(void *handle) 1198 { 1199 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1200 u32 tmp = RREG32(mmSRBM_STATUS); 1201 1202 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1203 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 1204 return false; 1205 1206 return true; 1207 } 1208 1209 static int gmc_v8_0_wait_for_idle(void *handle) 1210 { 1211 unsigned i; 1212 u32 tmp; 1213 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1214 1215 for (i = 0; i < adev->usec_timeout; i++) { 1216 /* read MC_STATUS */ 1217 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | 1218 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1219 SRBM_STATUS__MCC_BUSY_MASK | 1220 SRBM_STATUS__MCD_BUSY_MASK | 1221 SRBM_STATUS__VMC_BUSY_MASK | 1222 SRBM_STATUS__VMC1_BUSY_MASK); 1223 if (!tmp) 1224 return 0; 1225 udelay(1); 1226 } 1227 return -ETIMEDOUT; 1228 1229 } 1230 1231 static bool gmc_v8_0_check_soft_reset(void *handle) 1232 { 1233 u32 srbm_soft_reset = 0; 1234 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1235 u32 tmp = RREG32(mmSRBM_STATUS); 1236 1237 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1238 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1239 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 1240 1241 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1242 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 1243 if (!(adev->flags & AMD_IS_APU)) 1244 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1245 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1246 } 1247 if (srbm_soft_reset) { 1248 adev->mc.srbm_soft_reset = srbm_soft_reset; 1249 return true; 1250 } else { 1251 adev->mc.srbm_soft_reset = 0; 1252 return false; 1253 } 1254 } 1255 1256 static int gmc_v8_0_pre_soft_reset(void *handle) 1257 { 1258 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1259 1260 if (!adev->mc.srbm_soft_reset) 1261 return 0; 1262 1263 gmc_v8_0_mc_stop(adev, &adev->mc.save); 1264 if (gmc_v8_0_wait_for_idle(adev)) { 1265 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1266 } 1267 1268 return 0; 1269 } 1270 1271 static int gmc_v8_0_soft_reset(void *handle) 1272 { 1273 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1274 u32 srbm_soft_reset; 1275 1276 if (!adev->mc.srbm_soft_reset) 1277 return 0; 1278 srbm_soft_reset = adev->mc.srbm_soft_reset; 1279 1280 if (srbm_soft_reset) { 1281 u32 tmp; 1282 1283 tmp = RREG32(mmSRBM_SOFT_RESET); 1284 tmp |= srbm_soft_reset; 1285 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1286 WREG32(mmSRBM_SOFT_RESET, tmp); 1287 tmp = RREG32(mmSRBM_SOFT_RESET); 1288 1289 udelay(50); 1290 1291 tmp &= ~srbm_soft_reset; 1292 WREG32(mmSRBM_SOFT_RESET, tmp); 1293 tmp = RREG32(mmSRBM_SOFT_RESET); 1294 1295 /* Wait a little for things to settle down */ 1296 udelay(50); 1297 } 1298 1299 return 0; 1300 } 1301 1302 static int gmc_v8_0_post_soft_reset(void *handle) 1303 { 1304 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1305 1306 if (!adev->mc.srbm_soft_reset) 1307 return 0; 1308 1309 gmc_v8_0_mc_resume(adev, &adev->mc.save); 1310 return 0; 1311 } 1312 1313 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1314 struct amdgpu_irq_src *src, 1315 unsigned type, 1316 enum amdgpu_interrupt_state state) 1317 { 1318 u32 tmp; 1319 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1320 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1321 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1322 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1323 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1324 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1325 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1326 1327 switch (state) { 1328 case AMDGPU_IRQ_STATE_DISABLE: 1329 /* system context */ 1330 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1331 tmp &= ~bits; 1332 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1333 /* VMs */ 1334 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1335 tmp &= ~bits; 1336 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1337 break; 1338 case AMDGPU_IRQ_STATE_ENABLE: 1339 /* system context */ 1340 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1341 tmp |= bits; 1342 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1343 /* VMs */ 1344 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1345 tmp |= bits; 1346 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1347 break; 1348 default: 1349 break; 1350 } 1351 1352 return 0; 1353 } 1354 1355 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, 1356 struct amdgpu_irq_src *source, 1357 struct amdgpu_iv_entry *entry) 1358 { 1359 u32 addr, status, mc_client; 1360 1361 if (amdgpu_sriov_vf(adev)) { 1362 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1363 entry->src_id, entry->src_data[0]); 1364 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n"); 1365 return 0; 1366 } 1367 1368 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1369 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1370 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); 1371 /* reset addr and status */ 1372 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1373 1374 if (!addr && !status) 1375 return 0; 1376 1377 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1378 gmc_v8_0_set_fault_enable_default(adev, false); 1379 1380 if (printk_ratelimit()) { 1381 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1382 entry->src_id, entry->src_data[0]); 1383 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1384 addr); 1385 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1386 status); 1387 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client); 1388 } 1389 1390 return 0; 1391 } 1392 1393 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev, 1394 bool enable) 1395 { 1396 uint32_t data; 1397 1398 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 1399 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1400 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1401 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1402 1403 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1404 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1405 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1406 1407 data = RREG32(mmMC_HUB_MISC_VM_CG); 1408 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK; 1409 WREG32(mmMC_HUB_MISC_VM_CG, data); 1410 1411 data = RREG32(mmMC_XPB_CLK_GAT); 1412 data |= MC_XPB_CLK_GAT__ENABLE_MASK; 1413 WREG32(mmMC_XPB_CLK_GAT, data); 1414 1415 data = RREG32(mmATC_MISC_CG); 1416 data |= ATC_MISC_CG__ENABLE_MASK; 1417 WREG32(mmATC_MISC_CG, data); 1418 1419 data = RREG32(mmMC_CITF_MISC_WR_CG); 1420 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK; 1421 WREG32(mmMC_CITF_MISC_WR_CG, data); 1422 1423 data = RREG32(mmMC_CITF_MISC_RD_CG); 1424 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK; 1425 WREG32(mmMC_CITF_MISC_RD_CG, data); 1426 1427 data = RREG32(mmMC_CITF_MISC_VM_CG); 1428 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK; 1429 WREG32(mmMC_CITF_MISC_VM_CG, data); 1430 1431 data = RREG32(mmVM_L2_CG); 1432 data |= VM_L2_CG__ENABLE_MASK; 1433 WREG32(mmVM_L2_CG, data); 1434 } else { 1435 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1436 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1437 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1438 1439 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1440 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1441 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1442 1443 data = RREG32(mmMC_HUB_MISC_VM_CG); 1444 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK; 1445 WREG32(mmMC_HUB_MISC_VM_CG, data); 1446 1447 data = RREG32(mmMC_XPB_CLK_GAT); 1448 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK; 1449 WREG32(mmMC_XPB_CLK_GAT, data); 1450 1451 data = RREG32(mmATC_MISC_CG); 1452 data &= ~ATC_MISC_CG__ENABLE_MASK; 1453 WREG32(mmATC_MISC_CG, data); 1454 1455 data = RREG32(mmMC_CITF_MISC_WR_CG); 1456 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK; 1457 WREG32(mmMC_CITF_MISC_WR_CG, data); 1458 1459 data = RREG32(mmMC_CITF_MISC_RD_CG); 1460 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK; 1461 WREG32(mmMC_CITF_MISC_RD_CG, data); 1462 1463 data = RREG32(mmMC_CITF_MISC_VM_CG); 1464 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK; 1465 WREG32(mmMC_CITF_MISC_VM_CG, data); 1466 1467 data = RREG32(mmVM_L2_CG); 1468 data &= ~VM_L2_CG__ENABLE_MASK; 1469 WREG32(mmVM_L2_CG, data); 1470 } 1471 } 1472 1473 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev, 1474 bool enable) 1475 { 1476 uint32_t data; 1477 1478 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) { 1479 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1480 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1481 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1482 1483 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1484 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1485 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1486 1487 data = RREG32(mmMC_HUB_MISC_VM_CG); 1488 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1489 WREG32(mmMC_HUB_MISC_VM_CG, data); 1490 1491 data = RREG32(mmMC_XPB_CLK_GAT); 1492 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1493 WREG32(mmMC_XPB_CLK_GAT, data); 1494 1495 data = RREG32(mmATC_MISC_CG); 1496 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1497 WREG32(mmATC_MISC_CG, data); 1498 1499 data = RREG32(mmMC_CITF_MISC_WR_CG); 1500 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1501 WREG32(mmMC_CITF_MISC_WR_CG, data); 1502 1503 data = RREG32(mmMC_CITF_MISC_RD_CG); 1504 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1505 WREG32(mmMC_CITF_MISC_RD_CG, data); 1506 1507 data = RREG32(mmMC_CITF_MISC_VM_CG); 1508 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1509 WREG32(mmMC_CITF_MISC_VM_CG, data); 1510 1511 data = RREG32(mmVM_L2_CG); 1512 data |= VM_L2_CG__MEM_LS_ENABLE_MASK; 1513 WREG32(mmVM_L2_CG, data); 1514 } else { 1515 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1516 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1517 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1518 1519 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1520 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1521 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1522 1523 data = RREG32(mmMC_HUB_MISC_VM_CG); 1524 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1525 WREG32(mmMC_HUB_MISC_VM_CG, data); 1526 1527 data = RREG32(mmMC_XPB_CLK_GAT); 1528 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1529 WREG32(mmMC_XPB_CLK_GAT, data); 1530 1531 data = RREG32(mmATC_MISC_CG); 1532 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1533 WREG32(mmATC_MISC_CG, data); 1534 1535 data = RREG32(mmMC_CITF_MISC_WR_CG); 1536 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1537 WREG32(mmMC_CITF_MISC_WR_CG, data); 1538 1539 data = RREG32(mmMC_CITF_MISC_RD_CG); 1540 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1541 WREG32(mmMC_CITF_MISC_RD_CG, data); 1542 1543 data = RREG32(mmMC_CITF_MISC_VM_CG); 1544 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1545 WREG32(mmMC_CITF_MISC_VM_CG, data); 1546 1547 data = RREG32(mmVM_L2_CG); 1548 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK; 1549 WREG32(mmVM_L2_CG, data); 1550 } 1551 } 1552 1553 static int gmc_v8_0_set_clockgating_state(void *handle, 1554 enum amd_clockgating_state state) 1555 { 1556 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1557 1558 if (amdgpu_sriov_vf(adev)) 1559 return 0; 1560 1561 switch (adev->asic_type) { 1562 case CHIP_FIJI: 1563 fiji_update_mc_medium_grain_clock_gating(adev, 1564 state == AMD_CG_STATE_GATE); 1565 fiji_update_mc_light_sleep(adev, 1566 state == AMD_CG_STATE_GATE); 1567 break; 1568 default: 1569 break; 1570 } 1571 return 0; 1572 } 1573 1574 static int gmc_v8_0_set_powergating_state(void *handle, 1575 enum amd_powergating_state state) 1576 { 1577 return 0; 1578 } 1579 1580 static void gmc_v8_0_get_clockgating_state(void *handle, u32 *flags) 1581 { 1582 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1583 int data; 1584 1585 if (amdgpu_sriov_vf(adev)) 1586 *flags = 0; 1587 1588 /* AMD_CG_SUPPORT_MC_MGCG */ 1589 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1590 if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK) 1591 *flags |= AMD_CG_SUPPORT_MC_MGCG; 1592 1593 /* AMD_CG_SUPPORT_MC_LS */ 1594 if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK) 1595 *flags |= AMD_CG_SUPPORT_MC_LS; 1596 } 1597 1598 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = { 1599 .name = "gmc_v8_0", 1600 .early_init = gmc_v8_0_early_init, 1601 .late_init = gmc_v8_0_late_init, 1602 .sw_init = gmc_v8_0_sw_init, 1603 .sw_fini = gmc_v8_0_sw_fini, 1604 .hw_init = gmc_v8_0_hw_init, 1605 .hw_fini = gmc_v8_0_hw_fini, 1606 .suspend = gmc_v8_0_suspend, 1607 .resume = gmc_v8_0_resume, 1608 .is_idle = gmc_v8_0_is_idle, 1609 .wait_for_idle = gmc_v8_0_wait_for_idle, 1610 .check_soft_reset = gmc_v8_0_check_soft_reset, 1611 .pre_soft_reset = gmc_v8_0_pre_soft_reset, 1612 .soft_reset = gmc_v8_0_soft_reset, 1613 .post_soft_reset = gmc_v8_0_post_soft_reset, 1614 .set_clockgating_state = gmc_v8_0_set_clockgating_state, 1615 .set_powergating_state = gmc_v8_0_set_powergating_state, 1616 .get_clockgating_state = gmc_v8_0_get_clockgating_state, 1617 }; 1618 1619 static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = { 1620 .flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb, 1621 .set_pte_pde = gmc_v8_0_gart_set_pte_pde, 1622 .set_prt = gmc_v8_0_set_prt, 1623 .get_vm_pte_flags = gmc_v8_0_get_vm_pte_flags, 1624 .get_vm_pde = gmc_v8_0_get_vm_pde 1625 }; 1626 1627 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = { 1628 .set = gmc_v8_0_vm_fault_interrupt_state, 1629 .process = gmc_v8_0_process_interrupt, 1630 }; 1631 1632 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev) 1633 { 1634 if (adev->gart.gart_funcs == NULL) 1635 adev->gart.gart_funcs = &gmc_v8_0_gart_funcs; 1636 } 1637 1638 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev) 1639 { 1640 adev->mc.vm_fault.num_types = 1; 1641 adev->mc.vm_fault.funcs = &gmc_v8_0_irq_funcs; 1642 } 1643 1644 const struct amdgpu_ip_block_version gmc_v8_0_ip_block = 1645 { 1646 .type = AMD_IP_BLOCK_TYPE_GMC, 1647 .major = 8, 1648 .minor = 0, 1649 .rev = 0, 1650 .funcs = &gmc_v8_0_ip_funcs, 1651 }; 1652 1653 const struct amdgpu_ip_block_version gmc_v8_1_ip_block = 1654 { 1655 .type = AMD_IP_BLOCK_TYPE_GMC, 1656 .major = 8, 1657 .minor = 1, 1658 .rev = 0, 1659 .funcs = &gmc_v8_0_ip_funcs, 1660 }; 1661 1662 const struct amdgpu_ip_block_version gmc_v8_5_ip_block = 1663 { 1664 .type = AMD_IP_BLOCK_TYPE_GMC, 1665 .major = 8, 1666 .minor = 5, 1667 .rev = 0, 1668 .funcs = &gmc_v8_0_ip_funcs, 1669 }; 1670