1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/drm_cache.h> 29 #include "amdgpu.h" 30 #include "gmc_v8_0.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_amdkfd.h" 33 #include "amdgpu_gem.h" 34 35 #include "gmc/gmc_8_1_d.h" 36 #include "gmc/gmc_8_1_sh_mask.h" 37 38 #include "bif/bif_5_0_d.h" 39 #include "bif/bif_5_0_sh_mask.h" 40 41 #include "oss/oss_3_0_d.h" 42 #include "oss/oss_3_0_sh_mask.h" 43 44 #include "dce/dce_10_0_d.h" 45 #include "dce/dce_10_0_sh_mask.h" 46 47 #include "vid.h" 48 #include "vi.h" 49 50 #include "amdgpu_atombios.h" 51 52 #include "ivsrcid/ivsrcid_vislands30.h" 53 54 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev); 55 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev); 56 static int gmc_v8_0_wait_for_idle(void *handle); 57 58 MODULE_FIRMWARE("amdgpu/tonga_mc.bin"); 59 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin"); 60 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin"); 61 MODULE_FIRMWARE("amdgpu/polaris12_mc.bin"); 62 MODULE_FIRMWARE("amdgpu/polaris11_k_mc.bin"); 63 MODULE_FIRMWARE("amdgpu/polaris10_k_mc.bin"); 64 MODULE_FIRMWARE("amdgpu/polaris12_k_mc.bin"); 65 66 static const u32 golden_settings_tonga_a11[] = 67 { 68 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, 69 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028, 70 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991, 71 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 72 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 73 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 74 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 75 }; 76 77 static const u32 tonga_mgcg_cgcg_init[] = 78 { 79 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 80 }; 81 82 static const u32 golden_settings_fiji_a10[] = 83 { 84 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 85 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 86 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 87 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 88 }; 89 90 static const u32 fiji_mgcg_cgcg_init[] = 91 { 92 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 93 }; 94 95 static const u32 golden_settings_polaris11_a11[] = 96 { 97 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 98 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 99 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 100 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 101 }; 102 103 static const u32 golden_settings_polaris10_a11[] = 104 { 105 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, 106 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 107 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 108 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 109 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 110 }; 111 112 static const u32 cz_mgcg_cgcg_init[] = 113 { 114 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 115 }; 116 117 static const u32 stoney_mgcg_cgcg_init[] = 118 { 119 mmATC_MISC_CG, 0xffffffff, 0x000c0200, 120 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 121 }; 122 123 static const u32 golden_settings_stoney_common[] = 124 { 125 mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004, 126 mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000 127 }; 128 129 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) 130 { 131 switch (adev->asic_type) { 132 case CHIP_FIJI: 133 amdgpu_device_program_register_sequence(adev, 134 fiji_mgcg_cgcg_init, 135 ARRAY_SIZE(fiji_mgcg_cgcg_init)); 136 amdgpu_device_program_register_sequence(adev, 137 golden_settings_fiji_a10, 138 ARRAY_SIZE(golden_settings_fiji_a10)); 139 break; 140 case CHIP_TONGA: 141 amdgpu_device_program_register_sequence(adev, 142 tonga_mgcg_cgcg_init, 143 ARRAY_SIZE(tonga_mgcg_cgcg_init)); 144 amdgpu_device_program_register_sequence(adev, 145 golden_settings_tonga_a11, 146 ARRAY_SIZE(golden_settings_tonga_a11)); 147 break; 148 case CHIP_POLARIS11: 149 case CHIP_POLARIS12: 150 case CHIP_VEGAM: 151 amdgpu_device_program_register_sequence(adev, 152 golden_settings_polaris11_a11, 153 ARRAY_SIZE(golden_settings_polaris11_a11)); 154 break; 155 case CHIP_POLARIS10: 156 amdgpu_device_program_register_sequence(adev, 157 golden_settings_polaris10_a11, 158 ARRAY_SIZE(golden_settings_polaris10_a11)); 159 break; 160 case CHIP_CARRIZO: 161 amdgpu_device_program_register_sequence(adev, 162 cz_mgcg_cgcg_init, 163 ARRAY_SIZE(cz_mgcg_cgcg_init)); 164 break; 165 case CHIP_STONEY: 166 amdgpu_device_program_register_sequence(adev, 167 stoney_mgcg_cgcg_init, 168 ARRAY_SIZE(stoney_mgcg_cgcg_init)); 169 amdgpu_device_program_register_sequence(adev, 170 golden_settings_stoney_common, 171 ARRAY_SIZE(golden_settings_stoney_common)); 172 break; 173 default: 174 break; 175 } 176 } 177 178 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev) 179 { 180 u32 blackout; 181 182 gmc_v8_0_wait_for_idle(adev); 183 184 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 185 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 186 /* Block CPU access */ 187 WREG32(mmBIF_FB_EN, 0); 188 /* blackout the MC */ 189 blackout = REG_SET_FIELD(blackout, 190 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1); 191 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout); 192 } 193 /* wait for the MC to settle */ 194 udelay(100); 195 } 196 197 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev) 198 { 199 u32 tmp; 200 201 /* unblackout the MC */ 202 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 203 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 204 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 205 /* allow CPU access */ 206 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 207 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 208 WREG32(mmBIF_FB_EN, tmp); 209 } 210 211 /** 212 * gmc_v8_0_init_microcode - load ucode images from disk 213 * 214 * @adev: amdgpu_device pointer 215 * 216 * Use the firmware interface to load the ucode images into 217 * the driver (not loaded into hw). 218 * Returns 0 on success, error on failure. 219 */ 220 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) 221 { 222 const char *chip_name; 223 char fw_name[30]; 224 int err; 225 226 DRM_DEBUG("\n"); 227 228 switch (adev->asic_type) { 229 case CHIP_TONGA: 230 chip_name = "tonga"; 231 break; 232 case CHIP_POLARIS11: 233 if (ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) || 234 ASICID_IS_P31(adev->pdev->device, adev->pdev->revision)) 235 chip_name = "polaris11_k"; 236 else 237 chip_name = "polaris11"; 238 break; 239 case CHIP_POLARIS10: 240 if (ASICID_IS_P30(adev->pdev->device, adev->pdev->revision)) 241 chip_name = "polaris10_k"; 242 else 243 chip_name = "polaris10"; 244 break; 245 case CHIP_POLARIS12: 246 if (ASICID_IS_P23(adev->pdev->device, adev->pdev->revision)) 247 chip_name = "polaris12_k"; 248 else 249 chip_name = "polaris12"; 250 break; 251 case CHIP_FIJI: 252 case CHIP_CARRIZO: 253 case CHIP_STONEY: 254 case CHIP_VEGAM: 255 return 0; 256 default: BUG(); 257 } 258 259 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name); 260 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); 261 if (err) 262 goto out; 263 err = amdgpu_ucode_validate(adev->gmc.fw); 264 265 out: 266 if (err) { 267 pr_err("mc: Failed to load firmware \"%s\"\n", fw_name); 268 release_firmware(adev->gmc.fw); 269 adev->gmc.fw = NULL; 270 } 271 return err; 272 } 273 274 /** 275 * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw 276 * 277 * @adev: amdgpu_device pointer 278 * 279 * Load the GDDR MC ucode into the hw (VI). 280 * Returns 0 on success, error on failure. 281 */ 282 static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev) 283 { 284 const struct mc_firmware_header_v1_0 *hdr; 285 const __le32 *fw_data = NULL; 286 const __le32 *io_mc_regs = NULL; 287 u32 running; 288 int i, ucode_size, regs_size; 289 290 /* Skip MC ucode loading on SR-IOV capable boards. 291 * vbios does this for us in asic_init in that case. 292 * Skip MC ucode loading on VF, because hypervisor will do that 293 * for this adaptor. 294 */ 295 if (amdgpu_sriov_bios(adev)) 296 return 0; 297 298 if (!adev->gmc.fw) 299 return -EINVAL; 300 301 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 302 amdgpu_ucode_print_mc_hdr(&hdr->header); 303 304 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 305 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 306 io_mc_regs = (const __le32 *) 307 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 308 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 309 fw_data = (const __le32 *) 310 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 311 312 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); 313 314 if (running == 0) { 315 /* reset the engine and set to writable */ 316 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 317 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 318 319 /* load mc io regs */ 320 for (i = 0; i < regs_size; i++) { 321 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 322 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 323 } 324 /* load the MC ucode */ 325 for (i = 0; i < ucode_size; i++) 326 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 327 328 /* put the engine back into the active state */ 329 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 330 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 331 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 332 333 /* wait for training to complete */ 334 for (i = 0; i < adev->usec_timeout; i++) { 335 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 336 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0)) 337 break; 338 udelay(1); 339 } 340 for (i = 0; i < adev->usec_timeout; i++) { 341 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 342 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1)) 343 break; 344 udelay(1); 345 } 346 } 347 348 return 0; 349 } 350 351 static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev) 352 { 353 const struct mc_firmware_header_v1_0 *hdr; 354 const __le32 *fw_data = NULL; 355 const __le32 *io_mc_regs = NULL; 356 u32 data; 357 int i, ucode_size, regs_size; 358 359 /* Skip MC ucode loading on SR-IOV capable boards. 360 * vbios does this for us in asic_init in that case. 361 * Skip MC ucode loading on VF, because hypervisor will do that 362 * for this adaptor. 363 */ 364 if (amdgpu_sriov_bios(adev)) 365 return 0; 366 367 if (!adev->gmc.fw) 368 return -EINVAL; 369 370 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 371 amdgpu_ucode_print_mc_hdr(&hdr->header); 372 373 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 374 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 375 io_mc_regs = (const __le32 *) 376 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 377 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 378 fw_data = (const __le32 *) 379 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 380 381 data = RREG32(mmMC_SEQ_MISC0); 382 data &= ~(0x40); 383 WREG32(mmMC_SEQ_MISC0, data); 384 385 /* load mc io regs */ 386 for (i = 0; i < regs_size; i++) { 387 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 388 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 389 } 390 391 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 392 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 393 394 /* load the MC ucode */ 395 for (i = 0; i < ucode_size; i++) 396 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 397 398 /* put the engine back into the active state */ 399 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 400 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 401 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 402 403 /* wait for training to complete */ 404 for (i = 0; i < adev->usec_timeout; i++) { 405 data = RREG32(mmMC_SEQ_MISC0); 406 if (data & 0x80) 407 break; 408 udelay(1); 409 } 410 411 return 0; 412 } 413 414 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev, 415 struct amdgpu_gmc *mc) 416 { 417 u64 base = 0; 418 419 if (!amdgpu_sriov_vf(adev)) 420 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; 421 base <<= 24; 422 423 amdgpu_gmc_vram_location(adev, mc, base); 424 amdgpu_gmc_gart_location(adev, mc); 425 } 426 427 /** 428 * gmc_v8_0_mc_program - program the GPU memory controller 429 * 430 * @adev: amdgpu_device pointer 431 * 432 * Set the location of vram, gart, and AGP in the GPU's 433 * physical address space (VI). 434 */ 435 static void gmc_v8_0_mc_program(struct amdgpu_device *adev) 436 { 437 u32 tmp; 438 int i, j; 439 440 /* Initialize HDP */ 441 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 442 WREG32((0xb05 + j), 0x00000000); 443 WREG32((0xb06 + j), 0x00000000); 444 WREG32((0xb07 + j), 0x00000000); 445 WREG32((0xb08 + j), 0x00000000); 446 WREG32((0xb09 + j), 0x00000000); 447 } 448 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 449 450 if (gmc_v8_0_wait_for_idle((void *)adev)) { 451 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 452 } 453 if (adev->mode_info.num_crtc) { 454 /* Lockout access through VGA aperture*/ 455 tmp = RREG32(mmVGA_HDP_CONTROL); 456 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 457 WREG32(mmVGA_HDP_CONTROL, tmp); 458 459 /* disable VGA render */ 460 tmp = RREG32(mmVGA_RENDER_CONTROL); 461 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 462 WREG32(mmVGA_RENDER_CONTROL, tmp); 463 } 464 /* Update configuration */ 465 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 466 adev->gmc.vram_start >> 12); 467 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 468 adev->gmc.vram_end >> 12); 469 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 470 adev->vram_scratch.gpu_addr >> 12); 471 472 if (amdgpu_sriov_vf(adev)) { 473 tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16; 474 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF); 475 WREG32(mmMC_VM_FB_LOCATION, tmp); 476 /* XXX double check these! */ 477 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); 478 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); 479 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF); 480 } 481 482 WREG32(mmMC_VM_AGP_BASE, 0); 483 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); 484 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); 485 if (gmc_v8_0_wait_for_idle((void *)adev)) { 486 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 487 } 488 489 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 490 491 tmp = RREG32(mmHDP_MISC_CNTL); 492 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); 493 WREG32(mmHDP_MISC_CNTL, tmp); 494 495 tmp = RREG32(mmHDP_HOST_PATH_CNTL); 496 WREG32(mmHDP_HOST_PATH_CNTL, tmp); 497 } 498 499 /** 500 * gmc_v8_0_mc_init - initialize the memory controller driver params 501 * 502 * @adev: amdgpu_device pointer 503 * 504 * Look up the amount of vram, vram width, and decide how to place 505 * vram and gart within the GPU's physical address space (VI). 506 * Returns 0 for success. 507 */ 508 static int gmc_v8_0_mc_init(struct amdgpu_device *adev) 509 { 510 int r; 511 512 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev); 513 if (!adev->gmc.vram_width) { 514 u32 tmp; 515 int chansize, numchan; 516 517 /* Get VRAM informations */ 518 tmp = RREG32(mmMC_ARB_RAMCFG); 519 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { 520 chansize = 64; 521 } else { 522 chansize = 32; 523 } 524 tmp = RREG32(mmMC_SHARED_CHMAP); 525 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 526 case 0: 527 default: 528 numchan = 1; 529 break; 530 case 1: 531 numchan = 2; 532 break; 533 case 2: 534 numchan = 4; 535 break; 536 case 3: 537 numchan = 8; 538 break; 539 case 4: 540 numchan = 3; 541 break; 542 case 5: 543 numchan = 6; 544 break; 545 case 6: 546 numchan = 10; 547 break; 548 case 7: 549 numchan = 12; 550 break; 551 case 8: 552 numchan = 16; 553 break; 554 } 555 adev->gmc.vram_width = numchan * chansize; 556 } 557 /* size in MB on si */ 558 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 559 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 560 561 if (!(adev->flags & AMD_IS_APU)) { 562 r = amdgpu_device_resize_fb_bar(adev); 563 if (r) 564 return r; 565 } 566 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 567 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 568 569 #ifdef CONFIG_X86_64 570 if (adev->flags & AMD_IS_APU) { 571 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; 572 adev->gmc.aper_size = adev->gmc.real_vram_size; 573 } 574 #endif 575 576 /* In case the PCI BAR is larger than the actual amount of vram */ 577 adev->gmc.visible_vram_size = adev->gmc.aper_size; 578 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 579 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 580 581 /* set the gart size */ 582 if (amdgpu_gart_size == -1) { 583 switch (adev->asic_type) { 584 case CHIP_POLARIS10: /* all engines support GPUVM */ 585 case CHIP_POLARIS11: /* all engines support GPUVM */ 586 case CHIP_POLARIS12: /* all engines support GPUVM */ 587 case CHIP_VEGAM: /* all engines support GPUVM */ 588 default: 589 adev->gmc.gart_size = 256ULL << 20; 590 break; 591 case CHIP_TONGA: /* UVD, VCE do not support GPUVM */ 592 case CHIP_FIJI: /* UVD, VCE do not support GPUVM */ 593 case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */ 594 case CHIP_STONEY: /* UVD does not support GPUVM, DCE SG support */ 595 adev->gmc.gart_size = 1024ULL << 20; 596 break; 597 } 598 } else { 599 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 600 } 601 602 gmc_v8_0_vram_gtt_location(adev, &adev->gmc); 603 604 return 0; 605 } 606 607 /** 608 * gmc_v8_0_flush_gpu_tlb_pasid - tlb flush via pasid 609 * 610 * @adev: amdgpu_device pointer 611 * @pasid: pasid to be flush 612 * @flush_type: type of flush 613 * @all_hub: flush all hubs 614 * 615 * Flush the TLB for the requested pasid. 616 */ 617 static int gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 618 uint16_t pasid, uint32_t flush_type, 619 bool all_hub) 620 { 621 int vmid; 622 unsigned int tmp; 623 624 if (amdgpu_in_reset(adev)) 625 return -EIO; 626 627 for (vmid = 1; vmid < 16; vmid++) { 628 629 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); 630 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) && 631 (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) { 632 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 633 RREG32(mmVM_INVALIDATE_RESPONSE); 634 break; 635 } 636 } 637 638 return 0; 639 640 } 641 642 /* 643 * GART 644 * VMID 0 is the physical GPU addresses as used by the kernel. 645 * VMIDs 1-15 are used for userspace clients and are handled 646 * by the amdgpu vm/hsa code. 647 */ 648 649 /** 650 * gmc_v8_0_flush_gpu_tlb - gart tlb flush callback 651 * 652 * @adev: amdgpu_device pointer 653 * @vmid: vm instance to flush 654 * @vmhub: which hub to flush 655 * @flush_type: type of flush 656 * 657 * Flush the TLB for the requested page table (VI). 658 */ 659 static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 660 uint32_t vmhub, uint32_t flush_type) 661 { 662 /* bits 0-15 are the VM contexts0-15 */ 663 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 664 } 665 666 static uint64_t gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 667 unsigned vmid, uint64_t pd_addr) 668 { 669 uint32_t reg; 670 671 if (vmid < 8) 672 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; 673 else 674 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8; 675 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); 676 677 /* bits 0-15 are the VM contexts0-15 */ 678 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); 679 680 return pd_addr; 681 } 682 683 static void gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 684 unsigned pasid) 685 { 686 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); 687 } 688 689 /* 690 * PTE format on VI: 691 * 63:40 reserved 692 * 39:12 4k physical page base address 693 * 11:7 fragment 694 * 6 write 695 * 5 read 696 * 4 exe 697 * 3 reserved 698 * 2 snooped 699 * 1 system 700 * 0 valid 701 * 702 * PDE format on VI: 703 * 63:59 block fragment size 704 * 58:40 reserved 705 * 39:1 physical base address of PTE 706 * bits 5:1 must be 0. 707 * 0 valid 708 */ 709 710 static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level, 711 uint64_t *addr, uint64_t *flags) 712 { 713 BUG_ON(*addr & 0xFFFFFF0000000FFFULL); 714 } 715 716 static void gmc_v8_0_get_vm_pte(struct amdgpu_device *adev, 717 struct amdgpu_bo_va_mapping *mapping, 718 uint64_t *flags) 719 { 720 *flags &= ~AMDGPU_PTE_EXECUTABLE; 721 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 722 *flags &= ~AMDGPU_PTE_PRT; 723 } 724 725 /** 726 * gmc_v8_0_set_fault_enable_default - update VM fault handling 727 * 728 * @adev: amdgpu_device pointer 729 * @value: true redirects VM faults to the default page 730 */ 731 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev, 732 bool value) 733 { 734 u32 tmp; 735 736 tmp = RREG32(mmVM_CONTEXT1_CNTL); 737 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 738 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 739 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 740 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 741 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 742 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 743 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 744 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 745 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 746 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 747 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 748 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 749 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 750 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 751 WREG32(mmVM_CONTEXT1_CNTL, tmp); 752 } 753 754 /** 755 * gmc_v8_0_set_prt - set PRT VM fault 756 * 757 * @adev: amdgpu_device pointer 758 * @enable: enable/disable VM fault handling for PRT 759 */ 760 static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable) 761 { 762 u32 tmp; 763 764 if (enable && !adev->gmc.prt_warning) { 765 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 766 adev->gmc.prt_warning = true; 767 } 768 769 tmp = RREG32(mmVM_PRT_CNTL); 770 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 771 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 772 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 773 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 774 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 775 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 776 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 777 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 778 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 779 L2_CACHE_STORE_INVALID_ENTRIES, enable); 780 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 781 L1_TLB_STORE_INVALID_ENTRIES, enable); 782 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 783 MASK_PDE0_FAULT, enable); 784 WREG32(mmVM_PRT_CNTL, tmp); 785 786 if (enable) { 787 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; 788 uint32_t high = adev->vm_manager.max_pfn - 789 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT); 790 791 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); 792 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); 793 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); 794 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); 795 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); 796 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); 797 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); 798 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); 799 } else { 800 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); 801 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); 802 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); 803 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); 804 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); 805 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); 806 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); 807 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); 808 } 809 } 810 811 /** 812 * gmc_v8_0_gart_enable - gart enable 813 * 814 * @adev: amdgpu_device pointer 815 * 816 * This sets up the TLBs, programs the page tables for VMID0, 817 * sets up the hw for VMIDs 1-15 which are allocated on 818 * demand, and sets up the global locations for the LDS, GDS, 819 * and GPUVM for FSA64 clients (VI). 820 * Returns 0 for success, errors for failure. 821 */ 822 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) 823 { 824 uint64_t table_addr; 825 int r, i; 826 u32 tmp, field; 827 828 if (adev->gart.bo == NULL) { 829 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 830 return -EINVAL; 831 } 832 r = amdgpu_gart_table_vram_pin(adev); 833 if (r) 834 return r; 835 836 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 837 838 /* Setup TLB control */ 839 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 840 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 841 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); 842 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 843 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); 844 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 845 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 846 /* Setup L2 cache */ 847 tmp = RREG32(mmVM_L2_CNTL); 848 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 849 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 850 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); 851 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); 852 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); 853 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 854 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 855 WREG32(mmVM_L2_CNTL, tmp); 856 tmp = RREG32(mmVM_L2_CNTL2); 857 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 858 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 859 WREG32(mmVM_L2_CNTL2, tmp); 860 861 field = adev->vm_manager.fragment_size; 862 tmp = RREG32(mmVM_L2_CNTL3); 863 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); 864 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); 865 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); 866 WREG32(mmVM_L2_CNTL3, tmp); 867 /* XXX: set to enable PTE/PDE in system memory */ 868 tmp = RREG32(mmVM_L2_CNTL4); 869 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0); 870 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0); 871 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0); 872 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0); 873 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0); 874 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0); 875 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0); 876 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0); 877 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0); 878 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0); 879 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0); 880 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0); 881 WREG32(mmVM_L2_CNTL4, tmp); 882 /* setup context0 */ 883 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); 884 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); 885 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12); 886 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 887 (u32)(adev->dummy_page_addr >> 12)); 888 WREG32(mmVM_CONTEXT0_CNTL2, 0); 889 tmp = RREG32(mmVM_CONTEXT0_CNTL); 890 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 891 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 892 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 893 WREG32(mmVM_CONTEXT0_CNTL, tmp); 894 895 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0); 896 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0); 897 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0); 898 899 /* empty context1-15 */ 900 /* FIXME start with 4G, once using 2 level pt switch to full 901 * vm size space 902 */ 903 /* set vm size, must be a multiple of 4 */ 904 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 905 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 906 for (i = 1; i < AMDGPU_NUM_VMID; i++) { 907 if (i < 8) 908 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 909 table_addr >> 12); 910 else 911 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 912 table_addr >> 12); 913 } 914 915 /* enable context1-15 */ 916 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 917 (u32)(adev->dummy_page_addr >> 12)); 918 WREG32(mmVM_CONTEXT1_CNTL2, 4); 919 tmp = RREG32(mmVM_CONTEXT1_CNTL); 920 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 921 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); 922 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 923 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 924 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 925 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 926 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 927 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 928 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 929 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, 930 adev->vm_manager.block_size - 9); 931 WREG32(mmVM_CONTEXT1_CNTL, tmp); 932 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 933 gmc_v8_0_set_fault_enable_default(adev, false); 934 else 935 gmc_v8_0_set_fault_enable_default(adev, true); 936 937 gmc_v8_0_flush_gpu_tlb(adev, 0, 0, 0); 938 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 939 (unsigned)(adev->gmc.gart_size >> 20), 940 (unsigned long long)table_addr); 941 adev->gart.ready = true; 942 return 0; 943 } 944 945 static int gmc_v8_0_gart_init(struct amdgpu_device *adev) 946 { 947 int r; 948 949 if (adev->gart.bo) { 950 WARN(1, "R600 PCIE GART already initialized\n"); 951 return 0; 952 } 953 /* Initialize common gart structure */ 954 r = amdgpu_gart_init(adev); 955 if (r) 956 return r; 957 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 958 adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE; 959 return amdgpu_gart_table_vram_alloc(adev); 960 } 961 962 /** 963 * gmc_v8_0_gart_disable - gart disable 964 * 965 * @adev: amdgpu_device pointer 966 * 967 * This disables all VM page table (VI). 968 */ 969 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev) 970 { 971 u32 tmp; 972 973 /* Disable all tables */ 974 WREG32(mmVM_CONTEXT0_CNTL, 0); 975 WREG32(mmVM_CONTEXT1_CNTL, 0); 976 /* Setup TLB control */ 977 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 978 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 979 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); 980 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); 981 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 982 /* Setup L2 cache */ 983 tmp = RREG32(mmVM_L2_CNTL); 984 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 985 WREG32(mmVM_L2_CNTL, tmp); 986 WREG32(mmVM_L2_CNTL2, 0); 987 amdgpu_gart_table_vram_unpin(adev); 988 } 989 990 /** 991 * gmc_v8_0_vm_decode_fault - print human readable fault info 992 * 993 * @adev: amdgpu_device pointer 994 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value 995 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value 996 * @mc_client: VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT register value 997 * @pasid: debug logging only - no functional use 998 * 999 * Print human readable fault information (VI). 1000 */ 1001 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32 status, 1002 u32 addr, u32 mc_client, unsigned pasid) 1003 { 1004 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 1005 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1006 PROTECTIONS); 1007 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 1008 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 1009 u32 mc_id; 1010 1011 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1012 MEMORY_CLIENT_ID); 1013 1014 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 1015 protections, vmid, pasid, addr, 1016 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1017 MEMORY_CLIENT_RW) ? 1018 "write" : "read", block, mc_client, mc_id); 1019 } 1020 1021 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type) 1022 { 1023 switch (mc_seq_vram_type) { 1024 case MC_SEQ_MISC0__MT__GDDR1: 1025 return AMDGPU_VRAM_TYPE_GDDR1; 1026 case MC_SEQ_MISC0__MT__DDR2: 1027 return AMDGPU_VRAM_TYPE_DDR2; 1028 case MC_SEQ_MISC0__MT__GDDR3: 1029 return AMDGPU_VRAM_TYPE_GDDR3; 1030 case MC_SEQ_MISC0__MT__GDDR4: 1031 return AMDGPU_VRAM_TYPE_GDDR4; 1032 case MC_SEQ_MISC0__MT__GDDR5: 1033 return AMDGPU_VRAM_TYPE_GDDR5; 1034 case MC_SEQ_MISC0__MT__HBM: 1035 return AMDGPU_VRAM_TYPE_HBM; 1036 case MC_SEQ_MISC0__MT__DDR3: 1037 return AMDGPU_VRAM_TYPE_DDR3; 1038 default: 1039 return AMDGPU_VRAM_TYPE_UNKNOWN; 1040 } 1041 } 1042 1043 static int gmc_v8_0_early_init(void *handle) 1044 { 1045 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1046 1047 gmc_v8_0_set_gmc_funcs(adev); 1048 gmc_v8_0_set_irq_funcs(adev); 1049 1050 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1051 adev->gmc.shared_aperture_end = 1052 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1053 adev->gmc.private_aperture_start = 1054 adev->gmc.shared_aperture_end + 1; 1055 adev->gmc.private_aperture_end = 1056 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1057 1058 return 0; 1059 } 1060 1061 static int gmc_v8_0_late_init(void *handle) 1062 { 1063 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1064 1065 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 1066 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1067 else 1068 return 0; 1069 } 1070 1071 static unsigned gmc_v8_0_get_vbios_fb_size(struct amdgpu_device *adev) 1072 { 1073 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); 1074 unsigned size; 1075 1076 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1077 size = AMDGPU_VBIOS_VGA_ALLOCATION; 1078 } else { 1079 u32 viewport = RREG32(mmVIEWPORT_SIZE); 1080 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1081 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1082 4); 1083 } 1084 1085 return size; 1086 } 1087 1088 #define mmMC_SEQ_MISC0_FIJI 0xA71 1089 1090 static int gmc_v8_0_sw_init(void *handle) 1091 { 1092 int r; 1093 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1094 1095 adev->num_vmhubs = 1; 1096 1097 if (adev->flags & AMD_IS_APU) { 1098 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 1099 } else { 1100 u32 tmp; 1101 1102 if ((adev->asic_type == CHIP_FIJI) || 1103 (adev->asic_type == CHIP_VEGAM)) 1104 tmp = RREG32(mmMC_SEQ_MISC0_FIJI); 1105 else 1106 tmp = RREG32(mmMC_SEQ_MISC0); 1107 tmp &= MC_SEQ_MISC0__MT__MASK; 1108 adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp); 1109 } 1110 1111 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault); 1112 if (r) 1113 return r; 1114 1115 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault); 1116 if (r) 1117 return r; 1118 1119 /* Adjust VM size here. 1120 * Currently set to 4GB ((1 << 20) 4k pages). 1121 * Max GPUVM size for cayman and SI is 40 bits. 1122 */ 1123 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); 1124 1125 /* Set the internal MC address mask 1126 * This is the max address of the GPU's 1127 * internal address space. 1128 */ 1129 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1130 1131 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40)); 1132 if (r) { 1133 pr_warn("No suitable DMA available\n"); 1134 return r; 1135 } 1136 adev->need_swiotlb = drm_need_swiotlb(40); 1137 1138 r = gmc_v8_0_init_microcode(adev); 1139 if (r) { 1140 DRM_ERROR("Failed to load mc firmware!\n"); 1141 return r; 1142 } 1143 1144 r = gmc_v8_0_mc_init(adev); 1145 if (r) 1146 return r; 1147 1148 amdgpu_gmc_get_vbios_allocations(adev); 1149 1150 /* Memory manager */ 1151 r = amdgpu_bo_init(adev); 1152 if (r) 1153 return r; 1154 1155 r = gmc_v8_0_gart_init(adev); 1156 if (r) 1157 return r; 1158 1159 /* 1160 * number of VMs 1161 * VMID 0 is reserved for System 1162 * amdgpu graphics/compute will use VMIDs 1-7 1163 * amdkfd will use VMIDs 8-15 1164 */ 1165 adev->vm_manager.first_kfd_vmid = 8; 1166 amdgpu_vm_manager_init(adev); 1167 1168 /* base offset of vram pages */ 1169 if (adev->flags & AMD_IS_APU) { 1170 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 1171 1172 tmp <<= 22; 1173 adev->vm_manager.vram_base_offset = tmp; 1174 } else { 1175 adev->vm_manager.vram_base_offset = 0; 1176 } 1177 1178 adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info), 1179 GFP_KERNEL); 1180 if (!adev->gmc.vm_fault_info) 1181 return -ENOMEM; 1182 atomic_set(&adev->gmc.vm_fault_info_updated, 0); 1183 1184 return 0; 1185 } 1186 1187 static int gmc_v8_0_sw_fini(void *handle) 1188 { 1189 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1190 1191 amdgpu_gem_force_release(adev); 1192 amdgpu_vm_manager_fini(adev); 1193 kfree(adev->gmc.vm_fault_info); 1194 amdgpu_gart_table_vram_free(adev); 1195 amdgpu_bo_fini(adev); 1196 amdgpu_gart_fini(adev); 1197 release_firmware(adev->gmc.fw); 1198 adev->gmc.fw = NULL; 1199 1200 return 0; 1201 } 1202 1203 static int gmc_v8_0_hw_init(void *handle) 1204 { 1205 int r; 1206 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1207 1208 gmc_v8_0_init_golden_registers(adev); 1209 1210 gmc_v8_0_mc_program(adev); 1211 1212 if (adev->asic_type == CHIP_TONGA) { 1213 r = gmc_v8_0_tonga_mc_load_microcode(adev); 1214 if (r) { 1215 DRM_ERROR("Failed to load MC firmware!\n"); 1216 return r; 1217 } 1218 } else if (adev->asic_type == CHIP_POLARIS11 || 1219 adev->asic_type == CHIP_POLARIS10 || 1220 adev->asic_type == CHIP_POLARIS12) { 1221 r = gmc_v8_0_polaris_mc_load_microcode(adev); 1222 if (r) { 1223 DRM_ERROR("Failed to load MC firmware!\n"); 1224 return r; 1225 } 1226 } 1227 1228 r = gmc_v8_0_gart_enable(adev); 1229 if (r) 1230 return r; 1231 1232 return r; 1233 } 1234 1235 static int gmc_v8_0_hw_fini(void *handle) 1236 { 1237 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1238 1239 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1240 gmc_v8_0_gart_disable(adev); 1241 1242 return 0; 1243 } 1244 1245 static int gmc_v8_0_suspend(void *handle) 1246 { 1247 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1248 1249 gmc_v8_0_hw_fini(adev); 1250 1251 return 0; 1252 } 1253 1254 static int gmc_v8_0_resume(void *handle) 1255 { 1256 int r; 1257 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1258 1259 r = gmc_v8_0_hw_init(adev); 1260 if (r) 1261 return r; 1262 1263 amdgpu_vmid_reset_all(adev); 1264 1265 return 0; 1266 } 1267 1268 static bool gmc_v8_0_is_idle(void *handle) 1269 { 1270 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1271 u32 tmp = RREG32(mmSRBM_STATUS); 1272 1273 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1274 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 1275 return false; 1276 1277 return true; 1278 } 1279 1280 static int gmc_v8_0_wait_for_idle(void *handle) 1281 { 1282 unsigned i; 1283 u32 tmp; 1284 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1285 1286 for (i = 0; i < adev->usec_timeout; i++) { 1287 /* read MC_STATUS */ 1288 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | 1289 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1290 SRBM_STATUS__MCC_BUSY_MASK | 1291 SRBM_STATUS__MCD_BUSY_MASK | 1292 SRBM_STATUS__VMC_BUSY_MASK | 1293 SRBM_STATUS__VMC1_BUSY_MASK); 1294 if (!tmp) 1295 return 0; 1296 udelay(1); 1297 } 1298 return -ETIMEDOUT; 1299 1300 } 1301 1302 static bool gmc_v8_0_check_soft_reset(void *handle) 1303 { 1304 u32 srbm_soft_reset = 0; 1305 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1306 u32 tmp = RREG32(mmSRBM_STATUS); 1307 1308 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1309 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1310 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 1311 1312 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1313 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 1314 if (!(adev->flags & AMD_IS_APU)) 1315 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1316 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1317 } 1318 if (srbm_soft_reset) { 1319 adev->gmc.srbm_soft_reset = srbm_soft_reset; 1320 return true; 1321 } else { 1322 adev->gmc.srbm_soft_reset = 0; 1323 return false; 1324 } 1325 } 1326 1327 static int gmc_v8_0_pre_soft_reset(void *handle) 1328 { 1329 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1330 1331 if (!adev->gmc.srbm_soft_reset) 1332 return 0; 1333 1334 gmc_v8_0_mc_stop(adev); 1335 if (gmc_v8_0_wait_for_idle(adev)) { 1336 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1337 } 1338 1339 return 0; 1340 } 1341 1342 static int gmc_v8_0_soft_reset(void *handle) 1343 { 1344 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1345 u32 srbm_soft_reset; 1346 1347 if (!adev->gmc.srbm_soft_reset) 1348 return 0; 1349 srbm_soft_reset = adev->gmc.srbm_soft_reset; 1350 1351 if (srbm_soft_reset) { 1352 u32 tmp; 1353 1354 tmp = RREG32(mmSRBM_SOFT_RESET); 1355 tmp |= srbm_soft_reset; 1356 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1357 WREG32(mmSRBM_SOFT_RESET, tmp); 1358 tmp = RREG32(mmSRBM_SOFT_RESET); 1359 1360 udelay(50); 1361 1362 tmp &= ~srbm_soft_reset; 1363 WREG32(mmSRBM_SOFT_RESET, tmp); 1364 tmp = RREG32(mmSRBM_SOFT_RESET); 1365 1366 /* Wait a little for things to settle down */ 1367 udelay(50); 1368 } 1369 1370 return 0; 1371 } 1372 1373 static int gmc_v8_0_post_soft_reset(void *handle) 1374 { 1375 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1376 1377 if (!adev->gmc.srbm_soft_reset) 1378 return 0; 1379 1380 gmc_v8_0_mc_resume(adev); 1381 return 0; 1382 } 1383 1384 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1385 struct amdgpu_irq_src *src, 1386 unsigned type, 1387 enum amdgpu_interrupt_state state) 1388 { 1389 u32 tmp; 1390 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1391 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1392 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1393 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1394 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1395 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1396 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1397 1398 switch (state) { 1399 case AMDGPU_IRQ_STATE_DISABLE: 1400 /* system context */ 1401 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1402 tmp &= ~bits; 1403 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1404 /* VMs */ 1405 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1406 tmp &= ~bits; 1407 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1408 break; 1409 case AMDGPU_IRQ_STATE_ENABLE: 1410 /* system context */ 1411 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1412 tmp |= bits; 1413 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1414 /* VMs */ 1415 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1416 tmp |= bits; 1417 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1418 break; 1419 default: 1420 break; 1421 } 1422 1423 return 0; 1424 } 1425 1426 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, 1427 struct amdgpu_irq_src *source, 1428 struct amdgpu_iv_entry *entry) 1429 { 1430 u32 addr, status, mc_client, vmid; 1431 1432 if (amdgpu_sriov_vf(adev)) { 1433 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1434 entry->src_id, entry->src_data[0]); 1435 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n"); 1436 return 0; 1437 } 1438 1439 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1440 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1441 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); 1442 /* reset addr and status */ 1443 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1444 1445 if (!addr && !status) 1446 return 0; 1447 1448 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1449 gmc_v8_0_set_fault_enable_default(adev, false); 1450 1451 if (printk_ratelimit()) { 1452 struct amdgpu_task_info task_info; 1453 1454 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 1455 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 1456 1457 dev_err(adev->dev, "GPU fault detected: %d 0x%08x for process %s pid %d thread %s pid %d\n", 1458 entry->src_id, entry->src_data[0], task_info.process_name, 1459 task_info.tgid, task_info.task_name, task_info.pid); 1460 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1461 addr); 1462 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1463 status); 1464 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client, 1465 entry->pasid); 1466 } 1467 1468 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1469 VMID); 1470 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid) 1471 && !atomic_read(&adev->gmc.vm_fault_info_updated)) { 1472 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info; 1473 u32 protections = REG_GET_FIELD(status, 1474 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1475 PROTECTIONS); 1476 1477 info->vmid = vmid; 1478 info->mc_id = REG_GET_FIELD(status, 1479 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1480 MEMORY_CLIENT_ID); 1481 info->status = status; 1482 info->page_addr = addr; 1483 info->prot_valid = protections & 0x7 ? true : false; 1484 info->prot_read = protections & 0x8 ? true : false; 1485 info->prot_write = protections & 0x10 ? true : false; 1486 info->prot_exec = protections & 0x20 ? true : false; 1487 mb(); 1488 atomic_set(&adev->gmc.vm_fault_info_updated, 1); 1489 } 1490 1491 return 0; 1492 } 1493 1494 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev, 1495 bool enable) 1496 { 1497 uint32_t data; 1498 1499 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 1500 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1501 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1502 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1503 1504 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1505 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1506 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1507 1508 data = RREG32(mmMC_HUB_MISC_VM_CG); 1509 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK; 1510 WREG32(mmMC_HUB_MISC_VM_CG, data); 1511 1512 data = RREG32(mmMC_XPB_CLK_GAT); 1513 data |= MC_XPB_CLK_GAT__ENABLE_MASK; 1514 WREG32(mmMC_XPB_CLK_GAT, data); 1515 1516 data = RREG32(mmATC_MISC_CG); 1517 data |= ATC_MISC_CG__ENABLE_MASK; 1518 WREG32(mmATC_MISC_CG, data); 1519 1520 data = RREG32(mmMC_CITF_MISC_WR_CG); 1521 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK; 1522 WREG32(mmMC_CITF_MISC_WR_CG, data); 1523 1524 data = RREG32(mmMC_CITF_MISC_RD_CG); 1525 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK; 1526 WREG32(mmMC_CITF_MISC_RD_CG, data); 1527 1528 data = RREG32(mmMC_CITF_MISC_VM_CG); 1529 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK; 1530 WREG32(mmMC_CITF_MISC_VM_CG, data); 1531 1532 data = RREG32(mmVM_L2_CG); 1533 data |= VM_L2_CG__ENABLE_MASK; 1534 WREG32(mmVM_L2_CG, data); 1535 } else { 1536 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1537 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1538 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1539 1540 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1541 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1542 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1543 1544 data = RREG32(mmMC_HUB_MISC_VM_CG); 1545 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK; 1546 WREG32(mmMC_HUB_MISC_VM_CG, data); 1547 1548 data = RREG32(mmMC_XPB_CLK_GAT); 1549 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK; 1550 WREG32(mmMC_XPB_CLK_GAT, data); 1551 1552 data = RREG32(mmATC_MISC_CG); 1553 data &= ~ATC_MISC_CG__ENABLE_MASK; 1554 WREG32(mmATC_MISC_CG, data); 1555 1556 data = RREG32(mmMC_CITF_MISC_WR_CG); 1557 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK; 1558 WREG32(mmMC_CITF_MISC_WR_CG, data); 1559 1560 data = RREG32(mmMC_CITF_MISC_RD_CG); 1561 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK; 1562 WREG32(mmMC_CITF_MISC_RD_CG, data); 1563 1564 data = RREG32(mmMC_CITF_MISC_VM_CG); 1565 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK; 1566 WREG32(mmMC_CITF_MISC_VM_CG, data); 1567 1568 data = RREG32(mmVM_L2_CG); 1569 data &= ~VM_L2_CG__ENABLE_MASK; 1570 WREG32(mmVM_L2_CG, data); 1571 } 1572 } 1573 1574 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev, 1575 bool enable) 1576 { 1577 uint32_t data; 1578 1579 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) { 1580 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1581 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1582 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1583 1584 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1585 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1586 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1587 1588 data = RREG32(mmMC_HUB_MISC_VM_CG); 1589 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1590 WREG32(mmMC_HUB_MISC_VM_CG, data); 1591 1592 data = RREG32(mmMC_XPB_CLK_GAT); 1593 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1594 WREG32(mmMC_XPB_CLK_GAT, data); 1595 1596 data = RREG32(mmATC_MISC_CG); 1597 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1598 WREG32(mmATC_MISC_CG, data); 1599 1600 data = RREG32(mmMC_CITF_MISC_WR_CG); 1601 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1602 WREG32(mmMC_CITF_MISC_WR_CG, data); 1603 1604 data = RREG32(mmMC_CITF_MISC_RD_CG); 1605 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1606 WREG32(mmMC_CITF_MISC_RD_CG, data); 1607 1608 data = RREG32(mmMC_CITF_MISC_VM_CG); 1609 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1610 WREG32(mmMC_CITF_MISC_VM_CG, data); 1611 1612 data = RREG32(mmVM_L2_CG); 1613 data |= VM_L2_CG__MEM_LS_ENABLE_MASK; 1614 WREG32(mmVM_L2_CG, data); 1615 } else { 1616 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1617 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1618 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1619 1620 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1621 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1622 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1623 1624 data = RREG32(mmMC_HUB_MISC_VM_CG); 1625 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1626 WREG32(mmMC_HUB_MISC_VM_CG, data); 1627 1628 data = RREG32(mmMC_XPB_CLK_GAT); 1629 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1630 WREG32(mmMC_XPB_CLK_GAT, data); 1631 1632 data = RREG32(mmATC_MISC_CG); 1633 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1634 WREG32(mmATC_MISC_CG, data); 1635 1636 data = RREG32(mmMC_CITF_MISC_WR_CG); 1637 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1638 WREG32(mmMC_CITF_MISC_WR_CG, data); 1639 1640 data = RREG32(mmMC_CITF_MISC_RD_CG); 1641 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1642 WREG32(mmMC_CITF_MISC_RD_CG, data); 1643 1644 data = RREG32(mmMC_CITF_MISC_VM_CG); 1645 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1646 WREG32(mmMC_CITF_MISC_VM_CG, data); 1647 1648 data = RREG32(mmVM_L2_CG); 1649 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK; 1650 WREG32(mmVM_L2_CG, data); 1651 } 1652 } 1653 1654 static int gmc_v8_0_set_clockgating_state(void *handle, 1655 enum amd_clockgating_state state) 1656 { 1657 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1658 1659 if (amdgpu_sriov_vf(adev)) 1660 return 0; 1661 1662 switch (adev->asic_type) { 1663 case CHIP_FIJI: 1664 fiji_update_mc_medium_grain_clock_gating(adev, 1665 state == AMD_CG_STATE_GATE); 1666 fiji_update_mc_light_sleep(adev, 1667 state == AMD_CG_STATE_GATE); 1668 break; 1669 default: 1670 break; 1671 } 1672 return 0; 1673 } 1674 1675 static int gmc_v8_0_set_powergating_state(void *handle, 1676 enum amd_powergating_state state) 1677 { 1678 return 0; 1679 } 1680 1681 static void gmc_v8_0_get_clockgating_state(void *handle, u32 *flags) 1682 { 1683 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1684 int data; 1685 1686 if (amdgpu_sriov_vf(adev)) 1687 *flags = 0; 1688 1689 /* AMD_CG_SUPPORT_MC_MGCG */ 1690 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1691 if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK) 1692 *flags |= AMD_CG_SUPPORT_MC_MGCG; 1693 1694 /* AMD_CG_SUPPORT_MC_LS */ 1695 if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK) 1696 *flags |= AMD_CG_SUPPORT_MC_LS; 1697 } 1698 1699 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = { 1700 .name = "gmc_v8_0", 1701 .early_init = gmc_v8_0_early_init, 1702 .late_init = gmc_v8_0_late_init, 1703 .sw_init = gmc_v8_0_sw_init, 1704 .sw_fini = gmc_v8_0_sw_fini, 1705 .hw_init = gmc_v8_0_hw_init, 1706 .hw_fini = gmc_v8_0_hw_fini, 1707 .suspend = gmc_v8_0_suspend, 1708 .resume = gmc_v8_0_resume, 1709 .is_idle = gmc_v8_0_is_idle, 1710 .wait_for_idle = gmc_v8_0_wait_for_idle, 1711 .check_soft_reset = gmc_v8_0_check_soft_reset, 1712 .pre_soft_reset = gmc_v8_0_pre_soft_reset, 1713 .soft_reset = gmc_v8_0_soft_reset, 1714 .post_soft_reset = gmc_v8_0_post_soft_reset, 1715 .set_clockgating_state = gmc_v8_0_set_clockgating_state, 1716 .set_powergating_state = gmc_v8_0_set_powergating_state, 1717 .get_clockgating_state = gmc_v8_0_get_clockgating_state, 1718 }; 1719 1720 static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = { 1721 .flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb, 1722 .flush_gpu_tlb_pasid = gmc_v8_0_flush_gpu_tlb_pasid, 1723 .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb, 1724 .emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping, 1725 .set_prt = gmc_v8_0_set_prt, 1726 .get_vm_pde = gmc_v8_0_get_vm_pde, 1727 .get_vm_pte = gmc_v8_0_get_vm_pte, 1728 .get_vbios_fb_size = gmc_v8_0_get_vbios_fb_size, 1729 }; 1730 1731 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = { 1732 .set = gmc_v8_0_vm_fault_interrupt_state, 1733 .process = gmc_v8_0_process_interrupt, 1734 }; 1735 1736 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev) 1737 { 1738 adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs; 1739 } 1740 1741 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev) 1742 { 1743 adev->gmc.vm_fault.num_types = 1; 1744 adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs; 1745 } 1746 1747 const struct amdgpu_ip_block_version gmc_v8_0_ip_block = 1748 { 1749 .type = AMD_IP_BLOCK_TYPE_GMC, 1750 .major = 8, 1751 .minor = 0, 1752 .rev = 0, 1753 .funcs = &gmc_v8_0_ip_funcs, 1754 }; 1755 1756 const struct amdgpu_ip_block_version gmc_v8_1_ip_block = 1757 { 1758 .type = AMD_IP_BLOCK_TYPE_GMC, 1759 .major = 8, 1760 .minor = 1, 1761 .rev = 0, 1762 .funcs = &gmc_v8_0_ip_funcs, 1763 }; 1764 1765 const struct amdgpu_ip_block_version gmc_v8_5_ip_block = 1766 { 1767 .type = AMD_IP_BLOCK_TYPE_GMC, 1768 .major = 8, 1769 .minor = 5, 1770 .rev = 0, 1771 .funcs = &gmc_v8_0_ip_funcs, 1772 }; 1773