1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include "drmP.h" 25 #include "amdgpu.h" 26 #include "cikd.h" 27 #include "cik.h" 28 #include "gmc_v7_0.h" 29 #include "amdgpu_ucode.h" 30 31 #include "bif/bif_4_1_d.h" 32 #include "bif/bif_4_1_sh_mask.h" 33 34 #include "gmc/gmc_7_1_d.h" 35 #include "gmc/gmc_7_1_sh_mask.h" 36 37 #include "oss/oss_2_0_d.h" 38 #include "oss/oss_2_0_sh_mask.h" 39 40 static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev); 41 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev); 42 static int gmc_v7_0_wait_for_idle(void *handle); 43 44 MODULE_FIRMWARE("radeon/bonaire_mc.bin"); 45 MODULE_FIRMWARE("radeon/hawaii_mc.bin"); 46 MODULE_FIRMWARE("amdgpu/topaz_mc.bin"); 47 48 static const u32 golden_settings_iceland_a11[] = 49 { 50 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 51 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 52 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 53 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 54 }; 55 56 static const u32 iceland_mgcg_cgcg_init[] = 57 { 58 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 59 }; 60 61 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev) 62 { 63 switch (adev->asic_type) { 64 case CHIP_TOPAZ: 65 amdgpu_program_register_sequence(adev, 66 iceland_mgcg_cgcg_init, 67 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init)); 68 amdgpu_program_register_sequence(adev, 69 golden_settings_iceland_a11, 70 (const u32)ARRAY_SIZE(golden_settings_iceland_a11)); 71 break; 72 default: 73 break; 74 } 75 } 76 77 static void gmc_v7_0_mc_stop(struct amdgpu_device *adev, 78 struct amdgpu_mode_mc_save *save) 79 { 80 u32 blackout; 81 82 if (adev->mode_info.num_crtc) 83 amdgpu_display_stop_mc_access(adev, save); 84 85 gmc_v7_0_wait_for_idle((void *)adev); 86 87 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 88 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 89 /* Block CPU access */ 90 WREG32(mmBIF_FB_EN, 0); 91 /* blackout the MC */ 92 blackout = REG_SET_FIELD(blackout, 93 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 94 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); 95 } 96 /* wait for the MC to settle */ 97 udelay(100); 98 } 99 100 static void gmc_v7_0_mc_resume(struct amdgpu_device *adev, 101 struct amdgpu_mode_mc_save *save) 102 { 103 u32 tmp; 104 105 /* unblackout the MC */ 106 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 107 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 108 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 109 /* allow CPU access */ 110 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 111 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 112 WREG32(mmBIF_FB_EN, tmp); 113 114 if (adev->mode_info.num_crtc) 115 amdgpu_display_resume_mc_access(adev, save); 116 } 117 118 /** 119 * gmc_v7_0_init_microcode - load ucode images from disk 120 * 121 * @adev: amdgpu_device pointer 122 * 123 * Use the firmware interface to load the ucode images into 124 * the driver (not loaded into hw). 125 * Returns 0 on success, error on failure. 126 */ 127 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev) 128 { 129 const char *chip_name; 130 char fw_name[30]; 131 int err; 132 133 DRM_DEBUG("\n"); 134 135 switch (adev->asic_type) { 136 case CHIP_BONAIRE: 137 chip_name = "bonaire"; 138 break; 139 case CHIP_HAWAII: 140 chip_name = "hawaii"; 141 break; 142 case CHIP_TOPAZ: 143 chip_name = "topaz"; 144 break; 145 case CHIP_KAVERI: 146 case CHIP_KABINI: 147 case CHIP_MULLINS: 148 return 0; 149 default: BUG(); 150 } 151 152 if (adev->asic_type == CHIP_TOPAZ) 153 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name); 154 else 155 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); 156 157 err = request_firmware(&adev->mc.fw, fw_name, adev->dev); 158 if (err) 159 goto out; 160 err = amdgpu_ucode_validate(adev->mc.fw); 161 162 out: 163 if (err) { 164 pr_err("cik_mc: Failed to load firmware \"%s\"\n", fw_name); 165 release_firmware(adev->mc.fw); 166 adev->mc.fw = NULL; 167 } 168 return err; 169 } 170 171 /** 172 * gmc_v7_0_mc_load_microcode - load MC ucode into the hw 173 * 174 * @adev: amdgpu_device pointer 175 * 176 * Load the GDDR MC ucode into the hw (CIK). 177 * Returns 0 on success, error on failure. 178 */ 179 static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev) 180 { 181 const struct mc_firmware_header_v1_0 *hdr; 182 const __le32 *fw_data = NULL; 183 const __le32 *io_mc_regs = NULL; 184 u32 running; 185 int i, ucode_size, regs_size; 186 187 if (!adev->mc.fw) 188 return -EINVAL; 189 190 hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data; 191 amdgpu_ucode_print_mc_hdr(&hdr->header); 192 193 adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version); 194 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 195 io_mc_regs = (const __le32 *) 196 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 197 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 198 fw_data = (const __le32 *) 199 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 200 201 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); 202 203 if (running == 0) { 204 /* reset the engine and set to writable */ 205 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 206 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 207 208 /* load mc io regs */ 209 for (i = 0; i < regs_size; i++) { 210 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 211 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 212 } 213 /* load the MC ucode */ 214 for (i = 0; i < ucode_size; i++) 215 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 216 217 /* put the engine back into the active state */ 218 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 219 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 220 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 221 222 /* wait for training to complete */ 223 for (i = 0; i < adev->usec_timeout; i++) { 224 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 225 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0)) 226 break; 227 udelay(1); 228 } 229 for (i = 0; i < adev->usec_timeout; i++) { 230 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 231 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1)) 232 break; 233 udelay(1); 234 } 235 } 236 237 return 0; 238 } 239 240 static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev, 241 struct amdgpu_mc *mc) 242 { 243 if (mc->mc_vram_size > 0xFFC0000000ULL) { 244 /* leave room for at least 1024M GTT */ 245 dev_warn(adev->dev, "limiting VRAM\n"); 246 mc->real_vram_size = 0xFFC0000000ULL; 247 mc->mc_vram_size = 0xFFC0000000ULL; 248 } 249 amdgpu_vram_location(adev, &adev->mc, 0); 250 adev->mc.gtt_base_align = 0; 251 amdgpu_gtt_location(adev, mc); 252 } 253 254 /** 255 * gmc_v7_0_mc_program - program the GPU memory controller 256 * 257 * @adev: amdgpu_device pointer 258 * 259 * Set the location of vram, gart, and AGP in the GPU's 260 * physical address space (CIK). 261 */ 262 static void gmc_v7_0_mc_program(struct amdgpu_device *adev) 263 { 264 struct amdgpu_mode_mc_save save; 265 u32 tmp; 266 int i, j; 267 268 /* Initialize HDP */ 269 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 270 WREG32((0xb05 + j), 0x00000000); 271 WREG32((0xb06 + j), 0x00000000); 272 WREG32((0xb07 + j), 0x00000000); 273 WREG32((0xb08 + j), 0x00000000); 274 WREG32((0xb09 + j), 0x00000000); 275 } 276 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 277 278 if (adev->mode_info.num_crtc) 279 amdgpu_display_set_vga_render_state(adev, false); 280 281 gmc_v7_0_mc_stop(adev, &save); 282 if (gmc_v7_0_wait_for_idle((void *)adev)) { 283 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 284 } 285 /* Update configuration */ 286 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 287 adev->mc.vram_start >> 12); 288 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 289 adev->mc.vram_end >> 12); 290 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 291 adev->vram_scratch.gpu_addr >> 12); 292 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16; 293 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF); 294 WREG32(mmMC_VM_FB_LOCATION, tmp); 295 /* XXX double check these! */ 296 WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8)); 297 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); 298 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF); 299 WREG32(mmMC_VM_AGP_BASE, 0); 300 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); 301 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); 302 if (gmc_v7_0_wait_for_idle((void *)adev)) { 303 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 304 } 305 gmc_v7_0_mc_resume(adev, &save); 306 307 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 308 309 tmp = RREG32(mmHDP_MISC_CNTL); 310 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); 311 WREG32(mmHDP_MISC_CNTL, tmp); 312 313 tmp = RREG32(mmHDP_HOST_PATH_CNTL); 314 WREG32(mmHDP_HOST_PATH_CNTL, tmp); 315 } 316 317 /** 318 * gmc_v7_0_mc_init - initialize the memory controller driver params 319 * 320 * @adev: amdgpu_device pointer 321 * 322 * Look up the amount of vram, vram width, and decide how to place 323 * vram and gart within the GPU's physical address space (CIK). 324 * Returns 0 for success. 325 */ 326 static int gmc_v7_0_mc_init(struct amdgpu_device *adev) 327 { 328 u32 tmp; 329 int chansize, numchan; 330 331 /* Get VRAM informations */ 332 tmp = RREG32(mmMC_ARB_RAMCFG); 333 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { 334 chansize = 64; 335 } else { 336 chansize = 32; 337 } 338 tmp = RREG32(mmMC_SHARED_CHMAP); 339 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 340 case 0: 341 default: 342 numchan = 1; 343 break; 344 case 1: 345 numchan = 2; 346 break; 347 case 2: 348 numchan = 4; 349 break; 350 case 3: 351 numchan = 8; 352 break; 353 case 4: 354 numchan = 3; 355 break; 356 case 5: 357 numchan = 6; 358 break; 359 case 6: 360 numchan = 10; 361 break; 362 case 7: 363 numchan = 12; 364 break; 365 case 8: 366 numchan = 16; 367 break; 368 } 369 adev->mc.vram_width = numchan * chansize; 370 /* Could aper size report 0 ? */ 371 adev->mc.aper_base = pci_resource_start(adev->pdev, 0); 372 adev->mc.aper_size = pci_resource_len(adev->pdev, 0); 373 /* size in MB on si */ 374 adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 375 adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 376 377 #ifdef CONFIG_X86_64 378 if (adev->flags & AMD_IS_APU) { 379 adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; 380 adev->mc.aper_size = adev->mc.real_vram_size; 381 } 382 #endif 383 384 /* In case the PCI BAR is larger than the actual amount of vram */ 385 adev->mc.visible_vram_size = adev->mc.aper_size; 386 if (adev->mc.visible_vram_size > adev->mc.real_vram_size) 387 adev->mc.visible_vram_size = adev->mc.real_vram_size; 388 389 /* unless the user had overridden it, set the gart 390 * size equal to the 1024 or vram, whichever is larger. 391 */ 392 if (amdgpu_gart_size == -1) 393 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size); 394 else 395 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20; 396 397 gmc_v7_0_vram_gtt_location(adev, &adev->mc); 398 399 return 0; 400 } 401 402 /* 403 * GART 404 * VMID 0 is the physical GPU addresses as used by the kernel. 405 * VMIDs 1-15 are used for userspace clients and are handled 406 * by the amdgpu vm/hsa code. 407 */ 408 409 /** 410 * gmc_v7_0_gart_flush_gpu_tlb - gart tlb flush callback 411 * 412 * @adev: amdgpu_device pointer 413 * @vmid: vm instance to flush 414 * 415 * Flush the TLB for the requested page table (CIK). 416 */ 417 static void gmc_v7_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, 418 uint32_t vmid) 419 { 420 /* flush hdp cache */ 421 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0); 422 423 /* bits 0-15 are the VM contexts0-15 */ 424 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 425 } 426 427 /** 428 * gmc_v7_0_gart_set_pte_pde - update the page tables using MMIO 429 * 430 * @adev: amdgpu_device pointer 431 * @cpu_pt_addr: cpu address of the page table 432 * @gpu_page_idx: entry in the page table to update 433 * @addr: dst addr to write into pte/pde 434 * @flags: access flags 435 * 436 * Update the page tables using the CPU. 437 */ 438 static int gmc_v7_0_gart_set_pte_pde(struct amdgpu_device *adev, 439 void *cpu_pt_addr, 440 uint32_t gpu_page_idx, 441 uint64_t addr, 442 uint64_t flags) 443 { 444 void __iomem *ptr = (void *)cpu_pt_addr; 445 uint64_t value; 446 447 value = addr & 0xFFFFFFFFFFFFF000ULL; 448 value |= flags; 449 writeq(value, ptr + (gpu_page_idx * 8)); 450 451 return 0; 452 } 453 454 static uint64_t gmc_v7_0_get_vm_pte_flags(struct amdgpu_device *adev, 455 uint32_t flags) 456 { 457 uint64_t pte_flag = 0; 458 459 if (flags & AMDGPU_VM_PAGE_READABLE) 460 pte_flag |= AMDGPU_PTE_READABLE; 461 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 462 pte_flag |= AMDGPU_PTE_WRITEABLE; 463 if (flags & AMDGPU_VM_PAGE_PRT) 464 pte_flag |= AMDGPU_PTE_PRT; 465 466 return pte_flag; 467 } 468 469 /** 470 * gmc_v8_0_set_fault_enable_default - update VM fault handling 471 * 472 * @adev: amdgpu_device pointer 473 * @value: true redirects VM faults to the default page 474 */ 475 static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev, 476 bool value) 477 { 478 u32 tmp; 479 480 tmp = RREG32(mmVM_CONTEXT1_CNTL); 481 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 482 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 483 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 484 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 485 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 486 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 487 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 488 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 489 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 490 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 491 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 492 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 493 WREG32(mmVM_CONTEXT1_CNTL, tmp); 494 } 495 496 /** 497 * gmc_v7_0_set_prt - set PRT VM fault 498 * 499 * @adev: amdgpu_device pointer 500 * @enable: enable/disable VM fault handling for PRT 501 */ 502 static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable) 503 { 504 uint32_t tmp; 505 506 if (enable && !adev->mc.prt_warning) { 507 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 508 adev->mc.prt_warning = true; 509 } 510 511 tmp = RREG32(mmVM_PRT_CNTL); 512 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 513 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 514 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 515 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 516 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 517 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 518 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 519 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 520 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 521 L2_CACHE_STORE_INVALID_ENTRIES, enable); 522 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 523 L1_TLB_STORE_INVALID_ENTRIES, enable); 524 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 525 MASK_PDE0_FAULT, enable); 526 WREG32(mmVM_PRT_CNTL, tmp); 527 528 if (enable) { 529 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; 530 uint32_t high = adev->vm_manager.max_pfn; 531 532 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); 533 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); 534 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); 535 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); 536 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); 537 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); 538 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); 539 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); 540 } else { 541 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); 542 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); 543 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); 544 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); 545 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); 546 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); 547 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); 548 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); 549 } 550 } 551 552 /** 553 * gmc_v7_0_gart_enable - gart enable 554 * 555 * @adev: amdgpu_device pointer 556 * 557 * This sets up the TLBs, programs the page tables for VMID0, 558 * sets up the hw for VMIDs 1-15 which are allocated on 559 * demand, and sets up the global locations for the LDS, GDS, 560 * and GPUVM for FSA64 clients (CIK). 561 * Returns 0 for success, errors for failure. 562 */ 563 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev) 564 { 565 int r, i; 566 u32 tmp; 567 568 if (adev->gart.robj == NULL) { 569 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 570 return -EINVAL; 571 } 572 r = amdgpu_gart_table_vram_pin(adev); 573 if (r) 574 return r; 575 /* Setup TLB control */ 576 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 577 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 578 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); 579 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 580 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); 581 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 582 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 583 /* Setup L2 cache */ 584 tmp = RREG32(mmVM_L2_CNTL); 585 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 586 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 587 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); 588 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); 589 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); 590 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 591 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 592 WREG32(mmVM_L2_CNTL, tmp); 593 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 594 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 595 WREG32(mmVM_L2_CNTL2, tmp); 596 tmp = RREG32(mmVM_L2_CNTL3); 597 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); 598 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4); 599 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4); 600 WREG32(mmVM_L2_CNTL3, tmp); 601 /* setup context0 */ 602 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12); 603 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12); 604 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); 605 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 606 (u32)(adev->dummy_page.addr >> 12)); 607 WREG32(mmVM_CONTEXT0_CNTL2, 0); 608 tmp = RREG32(mmVM_CONTEXT0_CNTL); 609 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 610 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 611 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 612 WREG32(mmVM_CONTEXT0_CNTL, tmp); 613 614 WREG32(0x575, 0); 615 WREG32(0x576, 0); 616 WREG32(0x577, 0); 617 618 /* empty context1-15 */ 619 /* FIXME start with 4G, once using 2 level pt switch to full 620 * vm size space 621 */ 622 /* set vm size, must be a multiple of 4 */ 623 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 624 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 625 for (i = 1; i < 16; i++) { 626 if (i < 8) 627 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 628 adev->gart.table_addr >> 12); 629 else 630 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 631 adev->gart.table_addr >> 12); 632 } 633 634 /* enable context1-15 */ 635 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 636 (u32)(adev->dummy_page.addr >> 12)); 637 WREG32(mmVM_CONTEXT1_CNTL2, 4); 638 tmp = RREG32(mmVM_CONTEXT1_CNTL); 639 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 640 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); 641 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, 642 amdgpu_vm_block_size - 9); 643 WREG32(mmVM_CONTEXT1_CNTL, tmp); 644 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 645 gmc_v7_0_set_fault_enable_default(adev, false); 646 else 647 gmc_v7_0_set_fault_enable_default(adev, true); 648 649 if (adev->asic_type == CHIP_KAVERI) { 650 tmp = RREG32(mmCHUB_CONTROL); 651 tmp &= ~BYPASS_VM; 652 WREG32(mmCHUB_CONTROL, tmp); 653 } 654 655 gmc_v7_0_gart_flush_gpu_tlb(adev, 0); 656 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 657 (unsigned)(adev->mc.gtt_size >> 20), 658 (unsigned long long)adev->gart.table_addr); 659 adev->gart.ready = true; 660 return 0; 661 } 662 663 static int gmc_v7_0_gart_init(struct amdgpu_device *adev) 664 { 665 int r; 666 667 if (adev->gart.robj) { 668 WARN(1, "R600 PCIE GART already initialized\n"); 669 return 0; 670 } 671 /* Initialize common gart structure */ 672 r = amdgpu_gart_init(adev); 673 if (r) 674 return r; 675 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 676 adev->gart.gart_pte_flags = 0; 677 return amdgpu_gart_table_vram_alloc(adev); 678 } 679 680 /** 681 * gmc_v7_0_gart_disable - gart disable 682 * 683 * @adev: amdgpu_device pointer 684 * 685 * This disables all VM page table (CIK). 686 */ 687 static void gmc_v7_0_gart_disable(struct amdgpu_device *adev) 688 { 689 u32 tmp; 690 691 /* Disable all tables */ 692 WREG32(mmVM_CONTEXT0_CNTL, 0); 693 WREG32(mmVM_CONTEXT1_CNTL, 0); 694 /* Setup TLB control */ 695 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 696 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 697 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); 698 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); 699 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 700 /* Setup L2 cache */ 701 tmp = RREG32(mmVM_L2_CNTL); 702 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 703 WREG32(mmVM_L2_CNTL, tmp); 704 WREG32(mmVM_L2_CNTL2, 0); 705 amdgpu_gart_table_vram_unpin(adev); 706 } 707 708 /** 709 * gmc_v7_0_gart_fini - vm fini callback 710 * 711 * @adev: amdgpu_device pointer 712 * 713 * Tears down the driver GART/VM setup (CIK). 714 */ 715 static void gmc_v7_0_gart_fini(struct amdgpu_device *adev) 716 { 717 amdgpu_gart_table_vram_free(adev); 718 amdgpu_gart_fini(adev); 719 } 720 721 /* 722 * vm 723 * VMID 0 is the physical GPU addresses as used by the kernel. 724 * VMIDs 1-15 are used for userspace clients and are handled 725 * by the amdgpu vm/hsa code. 726 */ 727 /** 728 * gmc_v7_0_vm_init - cik vm init callback 729 * 730 * @adev: amdgpu_device pointer 731 * 732 * Inits cik specific vm parameters (number of VMs, base of vram for 733 * VMIDs 1-15) (CIK). 734 * Returns 0 for success. 735 */ 736 static int gmc_v7_0_vm_init(struct amdgpu_device *adev) 737 { 738 /* 739 * number of VMs 740 * VMID 0 is reserved for System 741 * amdgpu graphics/compute will use VMIDs 1-7 742 * amdkfd will use VMIDs 8-15 743 */ 744 adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS; 745 adev->vm_manager.num_level = 1; 746 amdgpu_vm_manager_init(adev); 747 748 /* base offset of vram pages */ 749 if (adev->flags & AMD_IS_APU) { 750 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 751 tmp <<= 22; 752 adev->vm_manager.vram_base_offset = tmp; 753 } else 754 adev->vm_manager.vram_base_offset = 0; 755 756 return 0; 757 } 758 759 /** 760 * gmc_v7_0_vm_fini - cik vm fini callback 761 * 762 * @adev: amdgpu_device pointer 763 * 764 * Tear down any asic specific VM setup (CIK). 765 */ 766 static void gmc_v7_0_vm_fini(struct amdgpu_device *adev) 767 { 768 } 769 770 /** 771 * gmc_v7_0_vm_decode_fault - print human readable fault info 772 * 773 * @adev: amdgpu_device pointer 774 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value 775 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value 776 * 777 * Print human readable fault information (CIK). 778 */ 779 static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev, 780 u32 status, u32 addr, u32 mc_client) 781 { 782 u32 mc_id; 783 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 784 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 785 PROTECTIONS); 786 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 787 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 788 789 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 790 MEMORY_CLIENT_ID); 791 792 dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 793 protections, vmid, addr, 794 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 795 MEMORY_CLIENT_RW) ? 796 "write" : "read", block, mc_client, mc_id); 797 } 798 799 800 static const u32 mc_cg_registers[] = { 801 mmMC_HUB_MISC_HUB_CG, 802 mmMC_HUB_MISC_SIP_CG, 803 mmMC_HUB_MISC_VM_CG, 804 mmMC_XPB_CLK_GAT, 805 mmATC_MISC_CG, 806 mmMC_CITF_MISC_WR_CG, 807 mmMC_CITF_MISC_RD_CG, 808 mmMC_CITF_MISC_VM_CG, 809 mmVM_L2_CG, 810 }; 811 812 static const u32 mc_cg_ls_en[] = { 813 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK, 814 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK, 815 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK, 816 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK, 817 ATC_MISC_CG__MEM_LS_ENABLE_MASK, 818 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK, 819 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK, 820 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK, 821 VM_L2_CG__MEM_LS_ENABLE_MASK, 822 }; 823 824 static const u32 mc_cg_en[] = { 825 MC_HUB_MISC_HUB_CG__ENABLE_MASK, 826 MC_HUB_MISC_SIP_CG__ENABLE_MASK, 827 MC_HUB_MISC_VM_CG__ENABLE_MASK, 828 MC_XPB_CLK_GAT__ENABLE_MASK, 829 ATC_MISC_CG__ENABLE_MASK, 830 MC_CITF_MISC_WR_CG__ENABLE_MASK, 831 MC_CITF_MISC_RD_CG__ENABLE_MASK, 832 MC_CITF_MISC_VM_CG__ENABLE_MASK, 833 VM_L2_CG__ENABLE_MASK, 834 }; 835 836 static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev, 837 bool enable) 838 { 839 int i; 840 u32 orig, data; 841 842 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 843 orig = data = RREG32(mc_cg_registers[i]); 844 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) 845 data |= mc_cg_ls_en[i]; 846 else 847 data &= ~mc_cg_ls_en[i]; 848 if (data != orig) 849 WREG32(mc_cg_registers[i], data); 850 } 851 } 852 853 static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev, 854 bool enable) 855 { 856 int i; 857 u32 orig, data; 858 859 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 860 orig = data = RREG32(mc_cg_registers[i]); 861 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) 862 data |= mc_cg_en[i]; 863 else 864 data &= ~mc_cg_en[i]; 865 if (data != orig) 866 WREG32(mc_cg_registers[i], data); 867 } 868 } 869 870 static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev, 871 bool enable) 872 { 873 u32 orig, data; 874 875 orig = data = RREG32_PCIE(ixPCIE_CNTL2); 876 877 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 878 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1); 879 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1); 880 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1); 881 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1); 882 } else { 883 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0); 884 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0); 885 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0); 886 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0); 887 } 888 889 if (orig != data) 890 WREG32_PCIE(ixPCIE_CNTL2, data); 891 } 892 893 static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev, 894 bool enable) 895 { 896 u32 orig, data; 897 898 orig = data = RREG32(mmHDP_HOST_PATH_CNTL); 899 900 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 901 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0); 902 else 903 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1); 904 905 if (orig != data) 906 WREG32(mmHDP_HOST_PATH_CNTL, data); 907 } 908 909 static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev, 910 bool enable) 911 { 912 u32 orig, data; 913 914 orig = data = RREG32(mmHDP_MEM_POWER_LS); 915 916 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 917 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1); 918 else 919 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0); 920 921 if (orig != data) 922 WREG32(mmHDP_MEM_POWER_LS, data); 923 } 924 925 static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type) 926 { 927 switch (mc_seq_vram_type) { 928 case MC_SEQ_MISC0__MT__GDDR1: 929 return AMDGPU_VRAM_TYPE_GDDR1; 930 case MC_SEQ_MISC0__MT__DDR2: 931 return AMDGPU_VRAM_TYPE_DDR2; 932 case MC_SEQ_MISC0__MT__GDDR3: 933 return AMDGPU_VRAM_TYPE_GDDR3; 934 case MC_SEQ_MISC0__MT__GDDR4: 935 return AMDGPU_VRAM_TYPE_GDDR4; 936 case MC_SEQ_MISC0__MT__GDDR5: 937 return AMDGPU_VRAM_TYPE_GDDR5; 938 case MC_SEQ_MISC0__MT__HBM: 939 return AMDGPU_VRAM_TYPE_HBM; 940 case MC_SEQ_MISC0__MT__DDR3: 941 return AMDGPU_VRAM_TYPE_DDR3; 942 default: 943 return AMDGPU_VRAM_TYPE_UNKNOWN; 944 } 945 } 946 947 static int gmc_v7_0_early_init(void *handle) 948 { 949 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 950 951 gmc_v7_0_set_gart_funcs(adev); 952 gmc_v7_0_set_irq_funcs(adev); 953 954 adev->mc.shared_aperture_start = 0x2000000000000000ULL; 955 adev->mc.shared_aperture_end = 956 adev->mc.shared_aperture_start + (4ULL << 30) - 1; 957 adev->mc.private_aperture_start = 958 adev->mc.shared_aperture_end + 1; 959 adev->mc.private_aperture_end = 960 adev->mc.private_aperture_start + (4ULL << 30) - 1; 961 962 return 0; 963 } 964 965 static int gmc_v7_0_late_init(void *handle) 966 { 967 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 968 969 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 970 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0); 971 else 972 return 0; 973 } 974 975 static int gmc_v7_0_sw_init(void *handle) 976 { 977 int r; 978 int dma_bits; 979 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 980 981 if (adev->flags & AMD_IS_APU) { 982 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 983 } else { 984 u32 tmp = RREG32(mmMC_SEQ_MISC0); 985 tmp &= MC_SEQ_MISC0__MT__MASK; 986 adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp); 987 } 988 989 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault); 990 if (r) 991 return r; 992 993 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault); 994 if (r) 995 return r; 996 997 /* Adjust VM size here. 998 * Currently set to 4GB ((1 << 20) 4k pages). 999 * Max GPUVM size for cayman and SI is 40 bits. 1000 */ 1001 adev->vm_manager.max_pfn = amdgpu_vm_size << 18; 1002 1003 /* Set the internal MC address mask 1004 * This is the max address of the GPU's 1005 * internal address space. 1006 */ 1007 adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1008 1009 /* set DMA mask + need_dma32 flags. 1010 * PCIE - can handle 40-bits. 1011 * IGP - can handle 40-bits 1012 * PCI - dma32 for legacy pci gart, 40 bits on newer asics 1013 */ 1014 adev->need_dma32 = false; 1015 dma_bits = adev->need_dma32 ? 32 : 40; 1016 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 1017 if (r) { 1018 adev->need_dma32 = true; 1019 dma_bits = 32; 1020 pr_warn("amdgpu: No suitable DMA available\n"); 1021 } 1022 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 1023 if (r) { 1024 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); 1025 pr_warn("amdgpu: No coherent DMA available\n"); 1026 } 1027 1028 r = gmc_v7_0_init_microcode(adev); 1029 if (r) { 1030 DRM_ERROR("Failed to load mc firmware!\n"); 1031 return r; 1032 } 1033 1034 r = gmc_v7_0_mc_init(adev); 1035 if (r) 1036 return r; 1037 1038 /* Memory manager */ 1039 r = amdgpu_bo_init(adev); 1040 if (r) 1041 return r; 1042 1043 r = gmc_v7_0_gart_init(adev); 1044 if (r) 1045 return r; 1046 1047 if (!adev->vm_manager.enabled) { 1048 r = gmc_v7_0_vm_init(adev); 1049 if (r) { 1050 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r); 1051 return r; 1052 } 1053 adev->vm_manager.enabled = true; 1054 } 1055 1056 return r; 1057 } 1058 1059 static int gmc_v7_0_sw_fini(void *handle) 1060 { 1061 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1062 1063 if (adev->vm_manager.enabled) { 1064 amdgpu_vm_manager_fini(adev); 1065 gmc_v7_0_vm_fini(adev); 1066 adev->vm_manager.enabled = false; 1067 } 1068 gmc_v7_0_gart_fini(adev); 1069 amdgpu_gem_force_release(adev); 1070 amdgpu_bo_fini(adev); 1071 1072 return 0; 1073 } 1074 1075 static int gmc_v7_0_hw_init(void *handle) 1076 { 1077 int r; 1078 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1079 1080 gmc_v7_0_init_golden_registers(adev); 1081 1082 gmc_v7_0_mc_program(adev); 1083 1084 if (!(adev->flags & AMD_IS_APU)) { 1085 r = gmc_v7_0_mc_load_microcode(adev); 1086 if (r) { 1087 DRM_ERROR("Failed to load MC firmware!\n"); 1088 return r; 1089 } 1090 } 1091 1092 r = gmc_v7_0_gart_enable(adev); 1093 if (r) 1094 return r; 1095 1096 return r; 1097 } 1098 1099 static int gmc_v7_0_hw_fini(void *handle) 1100 { 1101 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1102 1103 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0); 1104 gmc_v7_0_gart_disable(adev); 1105 1106 return 0; 1107 } 1108 1109 static int gmc_v7_0_suspend(void *handle) 1110 { 1111 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1112 1113 if (adev->vm_manager.enabled) { 1114 gmc_v7_0_vm_fini(adev); 1115 adev->vm_manager.enabled = false; 1116 } 1117 gmc_v7_0_hw_fini(adev); 1118 1119 return 0; 1120 } 1121 1122 static int gmc_v7_0_resume(void *handle) 1123 { 1124 int r; 1125 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1126 1127 r = gmc_v7_0_hw_init(adev); 1128 if (r) 1129 return r; 1130 1131 if (!adev->vm_manager.enabled) { 1132 r = gmc_v7_0_vm_init(adev); 1133 if (r) { 1134 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r); 1135 return r; 1136 } 1137 adev->vm_manager.enabled = true; 1138 } 1139 1140 return r; 1141 } 1142 1143 static bool gmc_v7_0_is_idle(void *handle) 1144 { 1145 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1146 u32 tmp = RREG32(mmSRBM_STATUS); 1147 1148 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1149 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 1150 return false; 1151 1152 return true; 1153 } 1154 1155 static int gmc_v7_0_wait_for_idle(void *handle) 1156 { 1157 unsigned i; 1158 u32 tmp; 1159 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1160 1161 for (i = 0; i < adev->usec_timeout; i++) { 1162 /* read MC_STATUS */ 1163 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | 1164 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1165 SRBM_STATUS__MCC_BUSY_MASK | 1166 SRBM_STATUS__MCD_BUSY_MASK | 1167 SRBM_STATUS__VMC_BUSY_MASK); 1168 if (!tmp) 1169 return 0; 1170 udelay(1); 1171 } 1172 return -ETIMEDOUT; 1173 1174 } 1175 1176 static int gmc_v7_0_soft_reset(void *handle) 1177 { 1178 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1179 struct amdgpu_mode_mc_save save; 1180 u32 srbm_soft_reset = 0; 1181 u32 tmp = RREG32(mmSRBM_STATUS); 1182 1183 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1184 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1185 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 1186 1187 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1188 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 1189 if (!(adev->flags & AMD_IS_APU)) 1190 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1191 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1192 } 1193 1194 if (srbm_soft_reset) { 1195 gmc_v7_0_mc_stop(adev, &save); 1196 if (gmc_v7_0_wait_for_idle((void *)adev)) { 1197 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1198 } 1199 1200 1201 tmp = RREG32(mmSRBM_SOFT_RESET); 1202 tmp |= srbm_soft_reset; 1203 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1204 WREG32(mmSRBM_SOFT_RESET, tmp); 1205 tmp = RREG32(mmSRBM_SOFT_RESET); 1206 1207 udelay(50); 1208 1209 tmp &= ~srbm_soft_reset; 1210 WREG32(mmSRBM_SOFT_RESET, tmp); 1211 tmp = RREG32(mmSRBM_SOFT_RESET); 1212 1213 /* Wait a little for things to settle down */ 1214 udelay(50); 1215 1216 gmc_v7_0_mc_resume(adev, &save); 1217 udelay(50); 1218 } 1219 1220 return 0; 1221 } 1222 1223 static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1224 struct amdgpu_irq_src *src, 1225 unsigned type, 1226 enum amdgpu_interrupt_state state) 1227 { 1228 u32 tmp; 1229 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1230 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1231 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1232 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1233 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1234 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1235 1236 switch (state) { 1237 case AMDGPU_IRQ_STATE_DISABLE: 1238 /* system context */ 1239 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1240 tmp &= ~bits; 1241 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1242 /* VMs */ 1243 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1244 tmp &= ~bits; 1245 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1246 break; 1247 case AMDGPU_IRQ_STATE_ENABLE: 1248 /* system context */ 1249 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1250 tmp |= bits; 1251 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1252 /* VMs */ 1253 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1254 tmp |= bits; 1255 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1256 break; 1257 default: 1258 break; 1259 } 1260 1261 return 0; 1262 } 1263 1264 static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev, 1265 struct amdgpu_irq_src *source, 1266 struct amdgpu_iv_entry *entry) 1267 { 1268 u32 addr, status, mc_client; 1269 1270 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1271 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1272 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); 1273 /* reset addr and status */ 1274 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1275 1276 if (!addr && !status) 1277 return 0; 1278 1279 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1280 gmc_v7_0_set_fault_enable_default(adev, false); 1281 1282 if (printk_ratelimit()) { 1283 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1284 entry->src_id, entry->src_data[0]); 1285 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1286 addr); 1287 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1288 status); 1289 gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client); 1290 } 1291 1292 return 0; 1293 } 1294 1295 static int gmc_v7_0_set_clockgating_state(void *handle, 1296 enum amd_clockgating_state state) 1297 { 1298 bool gate = false; 1299 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1300 1301 if (state == AMD_CG_STATE_GATE) 1302 gate = true; 1303 1304 if (!(adev->flags & AMD_IS_APU)) { 1305 gmc_v7_0_enable_mc_mgcg(adev, gate); 1306 gmc_v7_0_enable_mc_ls(adev, gate); 1307 } 1308 gmc_v7_0_enable_bif_mgls(adev, gate); 1309 gmc_v7_0_enable_hdp_mgcg(adev, gate); 1310 gmc_v7_0_enable_hdp_ls(adev, gate); 1311 1312 return 0; 1313 } 1314 1315 static int gmc_v7_0_set_powergating_state(void *handle, 1316 enum amd_powergating_state state) 1317 { 1318 return 0; 1319 } 1320 1321 static const struct amd_ip_funcs gmc_v7_0_ip_funcs = { 1322 .name = "gmc_v7_0", 1323 .early_init = gmc_v7_0_early_init, 1324 .late_init = gmc_v7_0_late_init, 1325 .sw_init = gmc_v7_0_sw_init, 1326 .sw_fini = gmc_v7_0_sw_fini, 1327 .hw_init = gmc_v7_0_hw_init, 1328 .hw_fini = gmc_v7_0_hw_fini, 1329 .suspend = gmc_v7_0_suspend, 1330 .resume = gmc_v7_0_resume, 1331 .is_idle = gmc_v7_0_is_idle, 1332 .wait_for_idle = gmc_v7_0_wait_for_idle, 1333 .soft_reset = gmc_v7_0_soft_reset, 1334 .set_clockgating_state = gmc_v7_0_set_clockgating_state, 1335 .set_powergating_state = gmc_v7_0_set_powergating_state, 1336 }; 1337 1338 static const struct amdgpu_gart_funcs gmc_v7_0_gart_funcs = { 1339 .flush_gpu_tlb = gmc_v7_0_gart_flush_gpu_tlb, 1340 .set_pte_pde = gmc_v7_0_gart_set_pte_pde, 1341 .set_prt = gmc_v7_0_set_prt, 1342 .get_vm_pte_flags = gmc_v7_0_get_vm_pte_flags 1343 }; 1344 1345 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = { 1346 .set = gmc_v7_0_vm_fault_interrupt_state, 1347 .process = gmc_v7_0_process_interrupt, 1348 }; 1349 1350 static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev) 1351 { 1352 if (adev->gart.gart_funcs == NULL) 1353 adev->gart.gart_funcs = &gmc_v7_0_gart_funcs; 1354 } 1355 1356 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev) 1357 { 1358 adev->mc.vm_fault.num_types = 1; 1359 adev->mc.vm_fault.funcs = &gmc_v7_0_irq_funcs; 1360 } 1361 1362 const struct amdgpu_ip_block_version gmc_v7_0_ip_block = 1363 { 1364 .type = AMD_IP_BLOCK_TYPE_GMC, 1365 .major = 7, 1366 .minor = 0, 1367 .rev = 0, 1368 .funcs = &gmc_v7_0_ip_funcs, 1369 }; 1370 1371 const struct amdgpu_ip_block_version gmc_v7_4_ip_block = 1372 { 1373 .type = AMD_IP_BLOCK_TYPE_GMC, 1374 .major = 7, 1375 .minor = 4, 1376 .rev = 0, 1377 .funcs = &gmc_v7_0_ip_funcs, 1378 }; 1379