1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <drm/drmP.h> 25 #include <drm/drm_cache.h> 26 #include "amdgpu.h" 27 #include "cikd.h" 28 #include "cik.h" 29 #include "gmc_v7_0.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_amdkfd.h" 32 #include "amdgpu_gem.h" 33 34 #include "bif/bif_4_1_d.h" 35 #include "bif/bif_4_1_sh_mask.h" 36 37 #include "gmc/gmc_7_1_d.h" 38 #include "gmc/gmc_7_1_sh_mask.h" 39 40 #include "oss/oss_2_0_d.h" 41 #include "oss/oss_2_0_sh_mask.h" 42 43 #include "dce/dce_8_0_d.h" 44 #include "dce/dce_8_0_sh_mask.h" 45 46 #include "amdgpu_atombios.h" 47 48 #include "ivsrcid/ivsrcid_vislands30.h" 49 50 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev); 51 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev); 52 static int gmc_v7_0_wait_for_idle(void *handle); 53 54 MODULE_FIRMWARE("amdgpu/bonaire_mc.bin"); 55 MODULE_FIRMWARE("amdgpu/hawaii_mc.bin"); 56 MODULE_FIRMWARE("amdgpu/topaz_mc.bin"); 57 58 static const u32 golden_settings_iceland_a11[] = 59 { 60 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 61 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 62 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 63 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 64 }; 65 66 static const u32 iceland_mgcg_cgcg_init[] = 67 { 68 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 69 }; 70 71 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev) 72 { 73 switch (adev->asic_type) { 74 case CHIP_TOPAZ: 75 amdgpu_device_program_register_sequence(adev, 76 iceland_mgcg_cgcg_init, 77 ARRAY_SIZE(iceland_mgcg_cgcg_init)); 78 amdgpu_device_program_register_sequence(adev, 79 golden_settings_iceland_a11, 80 ARRAY_SIZE(golden_settings_iceland_a11)); 81 break; 82 default: 83 break; 84 } 85 } 86 87 static void gmc_v7_0_mc_stop(struct amdgpu_device *adev) 88 { 89 u32 blackout; 90 91 gmc_v7_0_wait_for_idle((void *)adev); 92 93 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 94 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 95 /* Block CPU access */ 96 WREG32(mmBIF_FB_EN, 0); 97 /* blackout the MC */ 98 blackout = REG_SET_FIELD(blackout, 99 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 100 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); 101 } 102 /* wait for the MC to settle */ 103 udelay(100); 104 } 105 106 static void gmc_v7_0_mc_resume(struct amdgpu_device *adev) 107 { 108 u32 tmp; 109 110 /* unblackout the MC */ 111 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 112 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 113 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 114 /* allow CPU access */ 115 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 116 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 117 WREG32(mmBIF_FB_EN, tmp); 118 } 119 120 /** 121 * gmc_v7_0_init_microcode - load ucode images from disk 122 * 123 * @adev: amdgpu_device pointer 124 * 125 * Use the firmware interface to load the ucode images into 126 * the driver (not loaded into hw). 127 * Returns 0 on success, error on failure. 128 */ 129 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev) 130 { 131 const char *chip_name; 132 char fw_name[30]; 133 int err; 134 135 DRM_DEBUG("\n"); 136 137 switch (adev->asic_type) { 138 case CHIP_BONAIRE: 139 chip_name = "bonaire"; 140 break; 141 case CHIP_HAWAII: 142 chip_name = "hawaii"; 143 break; 144 case CHIP_TOPAZ: 145 chip_name = "topaz"; 146 break; 147 case CHIP_KAVERI: 148 case CHIP_KABINI: 149 case CHIP_MULLINS: 150 return 0; 151 default: BUG(); 152 } 153 154 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name); 155 156 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); 157 if (err) 158 goto out; 159 err = amdgpu_ucode_validate(adev->gmc.fw); 160 161 out: 162 if (err) { 163 pr_err("cik_mc: Failed to load firmware \"%s\"\n", fw_name); 164 release_firmware(adev->gmc.fw); 165 adev->gmc.fw = NULL; 166 } 167 return err; 168 } 169 170 /** 171 * gmc_v7_0_mc_load_microcode - load MC ucode into the hw 172 * 173 * @adev: amdgpu_device pointer 174 * 175 * Load the GDDR MC ucode into the hw (CIK). 176 * Returns 0 on success, error on failure. 177 */ 178 static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev) 179 { 180 const struct mc_firmware_header_v1_0 *hdr; 181 const __le32 *fw_data = NULL; 182 const __le32 *io_mc_regs = NULL; 183 u32 running; 184 int i, ucode_size, regs_size; 185 186 if (!adev->gmc.fw) 187 return -EINVAL; 188 189 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 190 amdgpu_ucode_print_mc_hdr(&hdr->header); 191 192 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 193 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 194 io_mc_regs = (const __le32 *) 195 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 196 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 197 fw_data = (const __le32 *) 198 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 199 200 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); 201 202 if (running == 0) { 203 /* reset the engine and set to writable */ 204 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 205 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 206 207 /* load mc io regs */ 208 for (i = 0; i < regs_size; i++) { 209 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 210 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 211 } 212 /* load the MC ucode */ 213 for (i = 0; i < ucode_size; i++) 214 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 215 216 /* put the engine back into the active state */ 217 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 218 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 219 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 220 221 /* wait for training to complete */ 222 for (i = 0; i < adev->usec_timeout; i++) { 223 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 224 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0)) 225 break; 226 udelay(1); 227 } 228 for (i = 0; i < adev->usec_timeout; i++) { 229 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 230 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1)) 231 break; 232 udelay(1); 233 } 234 } 235 236 return 0; 237 } 238 239 static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev, 240 struct amdgpu_gmc *mc) 241 { 242 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; 243 base <<= 24; 244 245 amdgpu_gmc_vram_location(adev, mc, base); 246 amdgpu_gmc_gart_location(adev, mc); 247 } 248 249 /** 250 * gmc_v7_0_mc_program - program the GPU memory controller 251 * 252 * @adev: amdgpu_device pointer 253 * 254 * Set the location of vram, gart, and AGP in the GPU's 255 * physical address space (CIK). 256 */ 257 static void gmc_v7_0_mc_program(struct amdgpu_device *adev) 258 { 259 u32 tmp; 260 int i, j; 261 262 /* Initialize HDP */ 263 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 264 WREG32((0xb05 + j), 0x00000000); 265 WREG32((0xb06 + j), 0x00000000); 266 WREG32((0xb07 + j), 0x00000000); 267 WREG32((0xb08 + j), 0x00000000); 268 WREG32((0xb09 + j), 0x00000000); 269 } 270 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 271 272 if (gmc_v7_0_wait_for_idle((void *)adev)) { 273 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 274 } 275 if (adev->mode_info.num_crtc) { 276 /* Lockout access through VGA aperture*/ 277 tmp = RREG32(mmVGA_HDP_CONTROL); 278 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 279 WREG32(mmVGA_HDP_CONTROL, tmp); 280 281 /* disable VGA render */ 282 tmp = RREG32(mmVGA_RENDER_CONTROL); 283 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 284 WREG32(mmVGA_RENDER_CONTROL, tmp); 285 } 286 /* Update configuration */ 287 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 288 adev->gmc.vram_start >> 12); 289 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 290 adev->gmc.vram_end >> 12); 291 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 292 adev->vram_scratch.gpu_addr >> 12); 293 WREG32(mmMC_VM_AGP_BASE, 0); 294 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); 295 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); 296 if (gmc_v7_0_wait_for_idle((void *)adev)) { 297 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 298 } 299 300 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 301 302 tmp = RREG32(mmHDP_MISC_CNTL); 303 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); 304 WREG32(mmHDP_MISC_CNTL, tmp); 305 306 tmp = RREG32(mmHDP_HOST_PATH_CNTL); 307 WREG32(mmHDP_HOST_PATH_CNTL, tmp); 308 } 309 310 /** 311 * gmc_v7_0_mc_init - initialize the memory controller driver params 312 * 313 * @adev: amdgpu_device pointer 314 * 315 * Look up the amount of vram, vram width, and decide how to place 316 * vram and gart within the GPU's physical address space (CIK). 317 * Returns 0 for success. 318 */ 319 static int gmc_v7_0_mc_init(struct amdgpu_device *adev) 320 { 321 int r; 322 323 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev); 324 if (!adev->gmc.vram_width) { 325 u32 tmp; 326 int chansize, numchan; 327 328 /* Get VRAM informations */ 329 tmp = RREG32(mmMC_ARB_RAMCFG); 330 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { 331 chansize = 64; 332 } else { 333 chansize = 32; 334 } 335 tmp = RREG32(mmMC_SHARED_CHMAP); 336 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 337 case 0: 338 default: 339 numchan = 1; 340 break; 341 case 1: 342 numchan = 2; 343 break; 344 case 2: 345 numchan = 4; 346 break; 347 case 3: 348 numchan = 8; 349 break; 350 case 4: 351 numchan = 3; 352 break; 353 case 5: 354 numchan = 6; 355 break; 356 case 6: 357 numchan = 10; 358 break; 359 case 7: 360 numchan = 12; 361 break; 362 case 8: 363 numchan = 16; 364 break; 365 } 366 adev->gmc.vram_width = numchan * chansize; 367 } 368 /* size in MB on si */ 369 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 370 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 371 372 if (!(adev->flags & AMD_IS_APU)) { 373 r = amdgpu_device_resize_fb_bar(adev); 374 if (r) 375 return r; 376 } 377 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 378 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 379 380 #ifdef CONFIG_X86_64 381 if (adev->flags & AMD_IS_APU) { 382 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; 383 adev->gmc.aper_size = adev->gmc.real_vram_size; 384 } 385 #endif 386 387 /* In case the PCI BAR is larger than the actual amount of vram */ 388 adev->gmc.visible_vram_size = adev->gmc.aper_size; 389 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 390 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 391 392 /* set the gart size */ 393 if (amdgpu_gart_size == -1) { 394 switch (adev->asic_type) { 395 case CHIP_TOPAZ: /* no MM engines */ 396 default: 397 adev->gmc.gart_size = 256ULL << 20; 398 break; 399 #ifdef CONFIG_DRM_AMDGPU_CIK 400 case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */ 401 case CHIP_HAWAII: /* UVD, VCE do not support GPUVM */ 402 case CHIP_KAVERI: /* UVD, VCE do not support GPUVM */ 403 case CHIP_KABINI: /* UVD, VCE do not support GPUVM */ 404 case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */ 405 adev->gmc.gart_size = 1024ULL << 20; 406 break; 407 #endif 408 } 409 } else { 410 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 411 } 412 413 gmc_v7_0_vram_gtt_location(adev, &adev->gmc); 414 415 return 0; 416 } 417 418 /* 419 * GART 420 * VMID 0 is the physical GPU addresses as used by the kernel. 421 * VMIDs 1-15 are used for userspace clients and are handled 422 * by the amdgpu vm/hsa code. 423 */ 424 425 /** 426 * gmc_v7_0_flush_gpu_tlb - gart tlb flush callback 427 * 428 * @adev: amdgpu_device pointer 429 * @vmid: vm instance to flush 430 * 431 * Flush the TLB for the requested page table (CIK). 432 */ 433 static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, 434 uint32_t vmid, uint32_t flush_type) 435 { 436 /* bits 0-15 are the VM contexts0-15 */ 437 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 438 } 439 440 static uint64_t gmc_v7_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 441 unsigned vmid, uint64_t pd_addr) 442 { 443 uint32_t reg; 444 445 if (vmid < 8) 446 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; 447 else 448 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8; 449 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); 450 451 /* bits 0-15 are the VM contexts0-15 */ 452 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); 453 454 return pd_addr; 455 } 456 457 static void gmc_v7_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 458 unsigned pasid) 459 { 460 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); 461 } 462 463 static uint64_t gmc_v7_0_get_vm_pte_flags(struct amdgpu_device *adev, 464 uint32_t flags) 465 { 466 uint64_t pte_flag = 0; 467 468 if (flags & AMDGPU_VM_PAGE_READABLE) 469 pte_flag |= AMDGPU_PTE_READABLE; 470 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 471 pte_flag |= AMDGPU_PTE_WRITEABLE; 472 if (flags & AMDGPU_VM_PAGE_PRT) 473 pte_flag |= AMDGPU_PTE_PRT; 474 475 return pte_flag; 476 } 477 478 static void gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, int level, 479 uint64_t *addr, uint64_t *flags) 480 { 481 BUG_ON(*addr & 0xFFFFFF0000000FFFULL); 482 } 483 484 /** 485 * gmc_v8_0_set_fault_enable_default - update VM fault handling 486 * 487 * @adev: amdgpu_device pointer 488 * @value: true redirects VM faults to the default page 489 */ 490 static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev, 491 bool value) 492 { 493 u32 tmp; 494 495 tmp = RREG32(mmVM_CONTEXT1_CNTL); 496 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 497 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 498 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 499 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 500 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 501 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 502 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 503 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 504 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 505 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 506 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 507 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 508 WREG32(mmVM_CONTEXT1_CNTL, tmp); 509 } 510 511 /** 512 * gmc_v7_0_set_prt - set PRT VM fault 513 * 514 * @adev: amdgpu_device pointer 515 * @enable: enable/disable VM fault handling for PRT 516 */ 517 static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable) 518 { 519 uint32_t tmp; 520 521 if (enable && !adev->gmc.prt_warning) { 522 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 523 adev->gmc.prt_warning = true; 524 } 525 526 tmp = RREG32(mmVM_PRT_CNTL); 527 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 528 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 529 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 530 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 531 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 532 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 533 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 534 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 535 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 536 L2_CACHE_STORE_INVALID_ENTRIES, enable); 537 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 538 L1_TLB_STORE_INVALID_ENTRIES, enable); 539 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 540 MASK_PDE0_FAULT, enable); 541 WREG32(mmVM_PRT_CNTL, tmp); 542 543 if (enable) { 544 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; 545 uint32_t high = adev->vm_manager.max_pfn - 546 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT); 547 548 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); 549 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); 550 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); 551 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); 552 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); 553 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); 554 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); 555 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); 556 } else { 557 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); 558 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); 559 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); 560 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); 561 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); 562 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); 563 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); 564 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); 565 } 566 } 567 568 /** 569 * gmc_v7_0_gart_enable - gart enable 570 * 571 * @adev: amdgpu_device pointer 572 * 573 * This sets up the TLBs, programs the page tables for VMID0, 574 * sets up the hw for VMIDs 1-15 which are allocated on 575 * demand, and sets up the global locations for the LDS, GDS, 576 * and GPUVM for FSA64 clients (CIK). 577 * Returns 0 for success, errors for failure. 578 */ 579 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev) 580 { 581 uint64_t table_addr; 582 int r, i; 583 u32 tmp, field; 584 585 if (adev->gart.bo == NULL) { 586 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 587 return -EINVAL; 588 } 589 r = amdgpu_gart_table_vram_pin(adev); 590 if (r) 591 return r; 592 593 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 594 595 /* Setup TLB control */ 596 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 597 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 598 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); 599 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 600 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); 601 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 602 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 603 /* Setup L2 cache */ 604 tmp = RREG32(mmVM_L2_CNTL); 605 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 606 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 607 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); 608 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); 609 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); 610 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 611 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 612 WREG32(mmVM_L2_CNTL, tmp); 613 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 614 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 615 WREG32(mmVM_L2_CNTL2, tmp); 616 617 field = adev->vm_manager.fragment_size; 618 tmp = RREG32(mmVM_L2_CNTL3); 619 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); 620 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); 621 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); 622 WREG32(mmVM_L2_CNTL3, tmp); 623 /* setup context0 */ 624 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); 625 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); 626 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12); 627 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 628 (u32)(adev->dummy_page_addr >> 12)); 629 WREG32(mmVM_CONTEXT0_CNTL2, 0); 630 tmp = RREG32(mmVM_CONTEXT0_CNTL); 631 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 632 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 633 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 634 WREG32(mmVM_CONTEXT0_CNTL, tmp); 635 636 WREG32(0x575, 0); 637 WREG32(0x576, 0); 638 WREG32(0x577, 0); 639 640 /* empty context1-15 */ 641 /* FIXME start with 4G, once using 2 level pt switch to full 642 * vm size space 643 */ 644 /* set vm size, must be a multiple of 4 */ 645 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 646 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 647 for (i = 1; i < 16; i++) { 648 if (i < 8) 649 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 650 table_addr >> 12); 651 else 652 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 653 table_addr >> 12); 654 } 655 656 /* enable context1-15 */ 657 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 658 (u32)(adev->dummy_page_addr >> 12)); 659 WREG32(mmVM_CONTEXT1_CNTL2, 4); 660 tmp = RREG32(mmVM_CONTEXT1_CNTL); 661 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 662 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); 663 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, 664 adev->vm_manager.block_size - 9); 665 WREG32(mmVM_CONTEXT1_CNTL, tmp); 666 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 667 gmc_v7_0_set_fault_enable_default(adev, false); 668 else 669 gmc_v7_0_set_fault_enable_default(adev, true); 670 671 if (adev->asic_type == CHIP_KAVERI) { 672 tmp = RREG32(mmCHUB_CONTROL); 673 tmp &= ~BYPASS_VM; 674 WREG32(mmCHUB_CONTROL, tmp); 675 } 676 677 gmc_v7_0_flush_gpu_tlb(adev, 0, 0); 678 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 679 (unsigned)(adev->gmc.gart_size >> 20), 680 (unsigned long long)table_addr); 681 adev->gart.ready = true; 682 return 0; 683 } 684 685 static int gmc_v7_0_gart_init(struct amdgpu_device *adev) 686 { 687 int r; 688 689 if (adev->gart.bo) { 690 WARN(1, "R600 PCIE GART already initialized\n"); 691 return 0; 692 } 693 /* Initialize common gart structure */ 694 r = amdgpu_gart_init(adev); 695 if (r) 696 return r; 697 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 698 adev->gart.gart_pte_flags = 0; 699 return amdgpu_gart_table_vram_alloc(adev); 700 } 701 702 /** 703 * gmc_v7_0_gart_disable - gart disable 704 * 705 * @adev: amdgpu_device pointer 706 * 707 * This disables all VM page table (CIK). 708 */ 709 static void gmc_v7_0_gart_disable(struct amdgpu_device *adev) 710 { 711 u32 tmp; 712 713 /* Disable all tables */ 714 WREG32(mmVM_CONTEXT0_CNTL, 0); 715 WREG32(mmVM_CONTEXT1_CNTL, 0); 716 /* Setup TLB control */ 717 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 718 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 719 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); 720 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); 721 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 722 /* Setup L2 cache */ 723 tmp = RREG32(mmVM_L2_CNTL); 724 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 725 WREG32(mmVM_L2_CNTL, tmp); 726 WREG32(mmVM_L2_CNTL2, 0); 727 amdgpu_gart_table_vram_unpin(adev); 728 } 729 730 /** 731 * gmc_v7_0_vm_decode_fault - print human readable fault info 732 * 733 * @adev: amdgpu_device pointer 734 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value 735 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value 736 * 737 * Print human readable fault information (CIK). 738 */ 739 static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev, u32 status, 740 u32 addr, u32 mc_client, unsigned pasid) 741 { 742 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 743 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 744 PROTECTIONS); 745 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 746 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 747 u32 mc_id; 748 749 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 750 MEMORY_CLIENT_ID); 751 752 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 753 protections, vmid, pasid, addr, 754 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 755 MEMORY_CLIENT_RW) ? 756 "write" : "read", block, mc_client, mc_id); 757 } 758 759 760 static const u32 mc_cg_registers[] = { 761 mmMC_HUB_MISC_HUB_CG, 762 mmMC_HUB_MISC_SIP_CG, 763 mmMC_HUB_MISC_VM_CG, 764 mmMC_XPB_CLK_GAT, 765 mmATC_MISC_CG, 766 mmMC_CITF_MISC_WR_CG, 767 mmMC_CITF_MISC_RD_CG, 768 mmMC_CITF_MISC_VM_CG, 769 mmVM_L2_CG, 770 }; 771 772 static const u32 mc_cg_ls_en[] = { 773 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK, 774 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK, 775 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK, 776 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK, 777 ATC_MISC_CG__MEM_LS_ENABLE_MASK, 778 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK, 779 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK, 780 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK, 781 VM_L2_CG__MEM_LS_ENABLE_MASK, 782 }; 783 784 static const u32 mc_cg_en[] = { 785 MC_HUB_MISC_HUB_CG__ENABLE_MASK, 786 MC_HUB_MISC_SIP_CG__ENABLE_MASK, 787 MC_HUB_MISC_VM_CG__ENABLE_MASK, 788 MC_XPB_CLK_GAT__ENABLE_MASK, 789 ATC_MISC_CG__ENABLE_MASK, 790 MC_CITF_MISC_WR_CG__ENABLE_MASK, 791 MC_CITF_MISC_RD_CG__ENABLE_MASK, 792 MC_CITF_MISC_VM_CG__ENABLE_MASK, 793 VM_L2_CG__ENABLE_MASK, 794 }; 795 796 static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev, 797 bool enable) 798 { 799 int i; 800 u32 orig, data; 801 802 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 803 orig = data = RREG32(mc_cg_registers[i]); 804 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) 805 data |= mc_cg_ls_en[i]; 806 else 807 data &= ~mc_cg_ls_en[i]; 808 if (data != orig) 809 WREG32(mc_cg_registers[i], data); 810 } 811 } 812 813 static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev, 814 bool enable) 815 { 816 int i; 817 u32 orig, data; 818 819 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 820 orig = data = RREG32(mc_cg_registers[i]); 821 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) 822 data |= mc_cg_en[i]; 823 else 824 data &= ~mc_cg_en[i]; 825 if (data != orig) 826 WREG32(mc_cg_registers[i], data); 827 } 828 } 829 830 static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev, 831 bool enable) 832 { 833 u32 orig, data; 834 835 orig = data = RREG32_PCIE(ixPCIE_CNTL2); 836 837 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 838 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1); 839 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1); 840 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1); 841 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1); 842 } else { 843 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0); 844 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0); 845 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0); 846 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0); 847 } 848 849 if (orig != data) 850 WREG32_PCIE(ixPCIE_CNTL2, data); 851 } 852 853 static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev, 854 bool enable) 855 { 856 u32 orig, data; 857 858 orig = data = RREG32(mmHDP_HOST_PATH_CNTL); 859 860 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 861 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0); 862 else 863 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1); 864 865 if (orig != data) 866 WREG32(mmHDP_HOST_PATH_CNTL, data); 867 } 868 869 static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev, 870 bool enable) 871 { 872 u32 orig, data; 873 874 orig = data = RREG32(mmHDP_MEM_POWER_LS); 875 876 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 877 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1); 878 else 879 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0); 880 881 if (orig != data) 882 WREG32(mmHDP_MEM_POWER_LS, data); 883 } 884 885 static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type) 886 { 887 switch (mc_seq_vram_type) { 888 case MC_SEQ_MISC0__MT__GDDR1: 889 return AMDGPU_VRAM_TYPE_GDDR1; 890 case MC_SEQ_MISC0__MT__DDR2: 891 return AMDGPU_VRAM_TYPE_DDR2; 892 case MC_SEQ_MISC0__MT__GDDR3: 893 return AMDGPU_VRAM_TYPE_GDDR3; 894 case MC_SEQ_MISC0__MT__GDDR4: 895 return AMDGPU_VRAM_TYPE_GDDR4; 896 case MC_SEQ_MISC0__MT__GDDR5: 897 return AMDGPU_VRAM_TYPE_GDDR5; 898 case MC_SEQ_MISC0__MT__HBM: 899 return AMDGPU_VRAM_TYPE_HBM; 900 case MC_SEQ_MISC0__MT__DDR3: 901 return AMDGPU_VRAM_TYPE_DDR3; 902 default: 903 return AMDGPU_VRAM_TYPE_UNKNOWN; 904 } 905 } 906 907 static int gmc_v7_0_early_init(void *handle) 908 { 909 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 910 911 gmc_v7_0_set_gmc_funcs(adev); 912 gmc_v7_0_set_irq_funcs(adev); 913 914 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 915 adev->gmc.shared_aperture_end = 916 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 917 adev->gmc.private_aperture_start = 918 adev->gmc.shared_aperture_end + 1; 919 adev->gmc.private_aperture_end = 920 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 921 922 return 0; 923 } 924 925 static int gmc_v7_0_late_init(void *handle) 926 { 927 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 928 929 amdgpu_bo_late_init(adev); 930 931 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 932 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 933 else 934 return 0; 935 } 936 937 static unsigned gmc_v7_0_get_vbios_fb_size(struct amdgpu_device *adev) 938 { 939 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); 940 unsigned size; 941 942 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 943 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */ 944 } else { 945 u32 viewport = RREG32(mmVIEWPORT_SIZE); 946 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 947 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * 948 4); 949 } 950 /* return 0 if the pre-OS buffer uses up most of vram */ 951 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 952 return 0; 953 return size; 954 } 955 956 static int gmc_v7_0_sw_init(void *handle) 957 { 958 int r; 959 int dma_bits; 960 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 961 962 if (adev->flags & AMD_IS_APU) { 963 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 964 } else { 965 u32 tmp = RREG32(mmMC_SEQ_MISC0); 966 tmp &= MC_SEQ_MISC0__MT__MASK; 967 adev->gmc.vram_type = gmc_v7_0_convert_vram_type(tmp); 968 } 969 970 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault); 971 if (r) 972 return r; 973 974 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault); 975 if (r) 976 return r; 977 978 /* Adjust VM size here. 979 * Currently set to 4GB ((1 << 20) 4k pages). 980 * Max GPUVM size for cayman and SI is 40 bits. 981 */ 982 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); 983 984 /* Set the internal MC address mask 985 * This is the max address of the GPU's 986 * internal address space. 987 */ 988 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 989 990 /* set DMA mask + need_dma32 flags. 991 * PCIE - can handle 40-bits. 992 * IGP - can handle 40-bits 993 * PCI - dma32 for legacy pci gart, 40 bits on newer asics 994 */ 995 adev->need_dma32 = false; 996 dma_bits = adev->need_dma32 ? 32 : 40; 997 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 998 if (r) { 999 adev->need_dma32 = true; 1000 dma_bits = 32; 1001 pr_warn("amdgpu: No suitable DMA available\n"); 1002 } 1003 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 1004 if (r) { 1005 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); 1006 pr_warn("amdgpu: No coherent DMA available\n"); 1007 } 1008 adev->need_swiotlb = drm_need_swiotlb(dma_bits); 1009 1010 r = gmc_v7_0_init_microcode(adev); 1011 if (r) { 1012 DRM_ERROR("Failed to load mc firmware!\n"); 1013 return r; 1014 } 1015 1016 r = gmc_v7_0_mc_init(adev); 1017 if (r) 1018 return r; 1019 1020 adev->gmc.stolen_size = gmc_v7_0_get_vbios_fb_size(adev); 1021 1022 /* Memory manager */ 1023 r = amdgpu_bo_init(adev); 1024 if (r) 1025 return r; 1026 1027 r = gmc_v7_0_gart_init(adev); 1028 if (r) 1029 return r; 1030 1031 /* 1032 * number of VMs 1033 * VMID 0 is reserved for System 1034 * amdgpu graphics/compute will use VMIDs 1-7 1035 * amdkfd will use VMIDs 8-15 1036 */ 1037 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; 1038 amdgpu_vm_manager_init(adev); 1039 1040 /* base offset of vram pages */ 1041 if (adev->flags & AMD_IS_APU) { 1042 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 1043 1044 tmp <<= 22; 1045 adev->vm_manager.vram_base_offset = tmp; 1046 } else { 1047 adev->vm_manager.vram_base_offset = 0; 1048 } 1049 1050 adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info), 1051 GFP_KERNEL); 1052 if (!adev->gmc.vm_fault_info) 1053 return -ENOMEM; 1054 atomic_set(&adev->gmc.vm_fault_info_updated, 0); 1055 1056 return 0; 1057 } 1058 1059 static int gmc_v7_0_sw_fini(void *handle) 1060 { 1061 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1062 1063 amdgpu_gem_force_release(adev); 1064 amdgpu_vm_manager_fini(adev); 1065 kfree(adev->gmc.vm_fault_info); 1066 amdgpu_gart_table_vram_free(adev); 1067 amdgpu_bo_fini(adev); 1068 amdgpu_gart_fini(adev); 1069 release_firmware(adev->gmc.fw); 1070 adev->gmc.fw = NULL; 1071 1072 return 0; 1073 } 1074 1075 static int gmc_v7_0_hw_init(void *handle) 1076 { 1077 int r; 1078 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1079 1080 gmc_v7_0_init_golden_registers(adev); 1081 1082 gmc_v7_0_mc_program(adev); 1083 1084 if (!(adev->flags & AMD_IS_APU)) { 1085 r = gmc_v7_0_mc_load_microcode(adev); 1086 if (r) { 1087 DRM_ERROR("Failed to load MC firmware!\n"); 1088 return r; 1089 } 1090 } 1091 1092 r = gmc_v7_0_gart_enable(adev); 1093 if (r) 1094 return r; 1095 1096 return r; 1097 } 1098 1099 static int gmc_v7_0_hw_fini(void *handle) 1100 { 1101 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1102 1103 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1104 gmc_v7_0_gart_disable(adev); 1105 1106 return 0; 1107 } 1108 1109 static int gmc_v7_0_suspend(void *handle) 1110 { 1111 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1112 1113 gmc_v7_0_hw_fini(adev); 1114 1115 return 0; 1116 } 1117 1118 static int gmc_v7_0_resume(void *handle) 1119 { 1120 int r; 1121 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1122 1123 r = gmc_v7_0_hw_init(adev); 1124 if (r) 1125 return r; 1126 1127 amdgpu_vmid_reset_all(adev); 1128 1129 return 0; 1130 } 1131 1132 static bool gmc_v7_0_is_idle(void *handle) 1133 { 1134 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1135 u32 tmp = RREG32(mmSRBM_STATUS); 1136 1137 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1138 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 1139 return false; 1140 1141 return true; 1142 } 1143 1144 static int gmc_v7_0_wait_for_idle(void *handle) 1145 { 1146 unsigned i; 1147 u32 tmp; 1148 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1149 1150 for (i = 0; i < adev->usec_timeout; i++) { 1151 /* read MC_STATUS */ 1152 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | 1153 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1154 SRBM_STATUS__MCC_BUSY_MASK | 1155 SRBM_STATUS__MCD_BUSY_MASK | 1156 SRBM_STATUS__VMC_BUSY_MASK); 1157 if (!tmp) 1158 return 0; 1159 udelay(1); 1160 } 1161 return -ETIMEDOUT; 1162 1163 } 1164 1165 static int gmc_v7_0_soft_reset(void *handle) 1166 { 1167 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1168 u32 srbm_soft_reset = 0; 1169 u32 tmp = RREG32(mmSRBM_STATUS); 1170 1171 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1172 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1173 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 1174 1175 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1176 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 1177 if (!(adev->flags & AMD_IS_APU)) 1178 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1179 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1180 } 1181 1182 if (srbm_soft_reset) { 1183 gmc_v7_0_mc_stop(adev); 1184 if (gmc_v7_0_wait_for_idle((void *)adev)) { 1185 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1186 } 1187 1188 1189 tmp = RREG32(mmSRBM_SOFT_RESET); 1190 tmp |= srbm_soft_reset; 1191 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1192 WREG32(mmSRBM_SOFT_RESET, tmp); 1193 tmp = RREG32(mmSRBM_SOFT_RESET); 1194 1195 udelay(50); 1196 1197 tmp &= ~srbm_soft_reset; 1198 WREG32(mmSRBM_SOFT_RESET, tmp); 1199 tmp = RREG32(mmSRBM_SOFT_RESET); 1200 1201 /* Wait a little for things to settle down */ 1202 udelay(50); 1203 1204 gmc_v7_0_mc_resume(adev); 1205 udelay(50); 1206 } 1207 1208 return 0; 1209 } 1210 1211 static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1212 struct amdgpu_irq_src *src, 1213 unsigned type, 1214 enum amdgpu_interrupt_state state) 1215 { 1216 u32 tmp; 1217 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1218 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1219 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1220 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1221 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1222 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1223 1224 switch (state) { 1225 case AMDGPU_IRQ_STATE_DISABLE: 1226 /* system context */ 1227 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1228 tmp &= ~bits; 1229 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1230 /* VMs */ 1231 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1232 tmp &= ~bits; 1233 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1234 break; 1235 case AMDGPU_IRQ_STATE_ENABLE: 1236 /* system context */ 1237 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1238 tmp |= bits; 1239 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1240 /* VMs */ 1241 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1242 tmp |= bits; 1243 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1244 break; 1245 default: 1246 break; 1247 } 1248 1249 return 0; 1250 } 1251 1252 static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev, 1253 struct amdgpu_irq_src *source, 1254 struct amdgpu_iv_entry *entry) 1255 { 1256 u32 addr, status, mc_client, vmid; 1257 1258 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1259 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1260 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); 1261 /* reset addr and status */ 1262 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1263 1264 if (!addr && !status) 1265 return 0; 1266 1267 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1268 gmc_v7_0_set_fault_enable_default(adev, false); 1269 1270 if (printk_ratelimit()) { 1271 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1272 entry->src_id, entry->src_data[0]); 1273 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1274 addr); 1275 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1276 status); 1277 gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client, 1278 entry->pasid); 1279 } 1280 1281 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1282 VMID); 1283 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid) 1284 && !atomic_read(&adev->gmc.vm_fault_info_updated)) { 1285 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info; 1286 u32 protections = REG_GET_FIELD(status, 1287 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1288 PROTECTIONS); 1289 1290 info->vmid = vmid; 1291 info->mc_id = REG_GET_FIELD(status, 1292 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1293 MEMORY_CLIENT_ID); 1294 info->status = status; 1295 info->page_addr = addr; 1296 info->prot_valid = protections & 0x7 ? true : false; 1297 info->prot_read = protections & 0x8 ? true : false; 1298 info->prot_write = protections & 0x10 ? true : false; 1299 info->prot_exec = protections & 0x20 ? true : false; 1300 mb(); 1301 atomic_set(&adev->gmc.vm_fault_info_updated, 1); 1302 } 1303 1304 return 0; 1305 } 1306 1307 static int gmc_v7_0_set_clockgating_state(void *handle, 1308 enum amd_clockgating_state state) 1309 { 1310 bool gate = false; 1311 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1312 1313 if (state == AMD_CG_STATE_GATE) 1314 gate = true; 1315 1316 if (!(adev->flags & AMD_IS_APU)) { 1317 gmc_v7_0_enable_mc_mgcg(adev, gate); 1318 gmc_v7_0_enable_mc_ls(adev, gate); 1319 } 1320 gmc_v7_0_enable_bif_mgls(adev, gate); 1321 gmc_v7_0_enable_hdp_mgcg(adev, gate); 1322 gmc_v7_0_enable_hdp_ls(adev, gate); 1323 1324 return 0; 1325 } 1326 1327 static int gmc_v7_0_set_powergating_state(void *handle, 1328 enum amd_powergating_state state) 1329 { 1330 return 0; 1331 } 1332 1333 static const struct amd_ip_funcs gmc_v7_0_ip_funcs = { 1334 .name = "gmc_v7_0", 1335 .early_init = gmc_v7_0_early_init, 1336 .late_init = gmc_v7_0_late_init, 1337 .sw_init = gmc_v7_0_sw_init, 1338 .sw_fini = gmc_v7_0_sw_fini, 1339 .hw_init = gmc_v7_0_hw_init, 1340 .hw_fini = gmc_v7_0_hw_fini, 1341 .suspend = gmc_v7_0_suspend, 1342 .resume = gmc_v7_0_resume, 1343 .is_idle = gmc_v7_0_is_idle, 1344 .wait_for_idle = gmc_v7_0_wait_for_idle, 1345 .soft_reset = gmc_v7_0_soft_reset, 1346 .set_clockgating_state = gmc_v7_0_set_clockgating_state, 1347 .set_powergating_state = gmc_v7_0_set_powergating_state, 1348 }; 1349 1350 static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = { 1351 .flush_gpu_tlb = gmc_v7_0_flush_gpu_tlb, 1352 .emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb, 1353 .emit_pasid_mapping = gmc_v7_0_emit_pasid_mapping, 1354 .set_prt = gmc_v7_0_set_prt, 1355 .get_vm_pte_flags = gmc_v7_0_get_vm_pte_flags, 1356 .get_vm_pde = gmc_v7_0_get_vm_pde 1357 }; 1358 1359 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = { 1360 .set = gmc_v7_0_vm_fault_interrupt_state, 1361 .process = gmc_v7_0_process_interrupt, 1362 }; 1363 1364 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev) 1365 { 1366 adev->gmc.gmc_funcs = &gmc_v7_0_gmc_funcs; 1367 } 1368 1369 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev) 1370 { 1371 adev->gmc.vm_fault.num_types = 1; 1372 adev->gmc.vm_fault.funcs = &gmc_v7_0_irq_funcs; 1373 } 1374 1375 const struct amdgpu_ip_block_version gmc_v7_0_ip_block = 1376 { 1377 .type = AMD_IP_BLOCK_TYPE_GMC, 1378 .major = 7, 1379 .minor = 0, 1380 .rev = 0, 1381 .funcs = &gmc_v7_0_ip_funcs, 1382 }; 1383 1384 const struct amdgpu_ip_block_version gmc_v7_4_ip_block = 1385 { 1386 .type = AMD_IP_BLOCK_TYPE_GMC, 1387 .major = 7, 1388 .minor = 4, 1389 .rev = 0, 1390 .funcs = &gmc_v7_0_ip_funcs, 1391 }; 1392