1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/drm_cache.h> 29 #include "amdgpu.h" 30 #include "cikd.h" 31 #include "cik.h" 32 #include "gmc_v7_0.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_amdkfd.h" 35 #include "amdgpu_gem.h" 36 37 #include "bif/bif_4_1_d.h" 38 #include "bif/bif_4_1_sh_mask.h" 39 40 #include "gmc/gmc_7_1_d.h" 41 #include "gmc/gmc_7_1_sh_mask.h" 42 43 #include "oss/oss_2_0_d.h" 44 #include "oss/oss_2_0_sh_mask.h" 45 46 #include "dce/dce_8_0_d.h" 47 #include "dce/dce_8_0_sh_mask.h" 48 49 #include "amdgpu_atombios.h" 50 51 #include "ivsrcid/ivsrcid_vislands30.h" 52 53 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev); 54 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev); 55 static int gmc_v7_0_wait_for_idle(void *handle); 56 57 MODULE_FIRMWARE("amdgpu/bonaire_mc.bin"); 58 MODULE_FIRMWARE("amdgpu/hawaii_mc.bin"); 59 MODULE_FIRMWARE("amdgpu/topaz_mc.bin"); 60 61 static const u32 golden_settings_iceland_a11[] = 62 { 63 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 64 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 65 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 66 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 67 }; 68 69 static const u32 iceland_mgcg_cgcg_init[] = 70 { 71 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 72 }; 73 74 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev) 75 { 76 switch (adev->asic_type) { 77 case CHIP_TOPAZ: 78 amdgpu_device_program_register_sequence(adev, 79 iceland_mgcg_cgcg_init, 80 ARRAY_SIZE(iceland_mgcg_cgcg_init)); 81 amdgpu_device_program_register_sequence(adev, 82 golden_settings_iceland_a11, 83 ARRAY_SIZE(golden_settings_iceland_a11)); 84 break; 85 default: 86 break; 87 } 88 } 89 90 static void gmc_v7_0_mc_stop(struct amdgpu_device *adev) 91 { 92 u32 blackout; 93 94 gmc_v7_0_wait_for_idle((void *)adev); 95 96 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 97 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 98 /* Block CPU access */ 99 WREG32(mmBIF_FB_EN, 0); 100 /* blackout the MC */ 101 blackout = REG_SET_FIELD(blackout, 102 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 103 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); 104 } 105 /* wait for the MC to settle */ 106 udelay(100); 107 } 108 109 static void gmc_v7_0_mc_resume(struct amdgpu_device *adev) 110 { 111 u32 tmp; 112 113 /* unblackout the MC */ 114 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 115 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 116 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 117 /* allow CPU access */ 118 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 119 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 120 WREG32(mmBIF_FB_EN, tmp); 121 } 122 123 /** 124 * gmc_v7_0_init_microcode - load ucode images from disk 125 * 126 * @adev: amdgpu_device pointer 127 * 128 * Use the firmware interface to load the ucode images into 129 * the driver (not loaded into hw). 130 * Returns 0 on success, error on failure. 131 */ 132 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev) 133 { 134 const char *chip_name; 135 char fw_name[30]; 136 int err; 137 138 DRM_DEBUG("\n"); 139 140 switch (adev->asic_type) { 141 case CHIP_BONAIRE: 142 chip_name = "bonaire"; 143 break; 144 case CHIP_HAWAII: 145 chip_name = "hawaii"; 146 break; 147 case CHIP_TOPAZ: 148 chip_name = "topaz"; 149 break; 150 case CHIP_KAVERI: 151 case CHIP_KABINI: 152 case CHIP_MULLINS: 153 return 0; 154 default: BUG(); 155 } 156 157 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name); 158 159 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); 160 if (err) 161 goto out; 162 err = amdgpu_ucode_validate(adev->gmc.fw); 163 164 out: 165 if (err) { 166 pr_err("cik_mc: Failed to load firmware \"%s\"\n", fw_name); 167 release_firmware(adev->gmc.fw); 168 adev->gmc.fw = NULL; 169 } 170 return err; 171 } 172 173 /** 174 * gmc_v7_0_mc_load_microcode - load MC ucode into the hw 175 * 176 * @adev: amdgpu_device pointer 177 * 178 * Load the GDDR MC ucode into the hw (CIK). 179 * Returns 0 on success, error on failure. 180 */ 181 static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev) 182 { 183 const struct mc_firmware_header_v1_0 *hdr; 184 const __le32 *fw_data = NULL; 185 const __le32 *io_mc_regs = NULL; 186 u32 running; 187 int i, ucode_size, regs_size; 188 189 if (!adev->gmc.fw) 190 return -EINVAL; 191 192 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 193 amdgpu_ucode_print_mc_hdr(&hdr->header); 194 195 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 196 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 197 io_mc_regs = (const __le32 *) 198 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 199 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 200 fw_data = (const __le32 *) 201 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 202 203 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); 204 205 if (running == 0) { 206 /* reset the engine and set to writable */ 207 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 208 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 209 210 /* load mc io regs */ 211 for (i = 0; i < regs_size; i++) { 212 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 213 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 214 } 215 /* load the MC ucode */ 216 for (i = 0; i < ucode_size; i++) 217 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 218 219 /* put the engine back into the active state */ 220 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 221 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 222 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 223 224 /* wait for training to complete */ 225 for (i = 0; i < adev->usec_timeout; i++) { 226 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 227 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0)) 228 break; 229 udelay(1); 230 } 231 for (i = 0; i < adev->usec_timeout; i++) { 232 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 233 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1)) 234 break; 235 udelay(1); 236 } 237 } 238 239 return 0; 240 } 241 242 static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev, 243 struct amdgpu_gmc *mc) 244 { 245 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; 246 base <<= 24; 247 248 amdgpu_gmc_vram_location(adev, mc, base); 249 amdgpu_gmc_gart_location(adev, mc); 250 } 251 252 /** 253 * gmc_v7_0_mc_program - program the GPU memory controller 254 * 255 * @adev: amdgpu_device pointer 256 * 257 * Set the location of vram, gart, and AGP in the GPU's 258 * physical address space (CIK). 259 */ 260 static void gmc_v7_0_mc_program(struct amdgpu_device *adev) 261 { 262 u32 tmp; 263 int i, j; 264 265 /* Initialize HDP */ 266 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 267 WREG32((0xb05 + j), 0x00000000); 268 WREG32((0xb06 + j), 0x00000000); 269 WREG32((0xb07 + j), 0x00000000); 270 WREG32((0xb08 + j), 0x00000000); 271 WREG32((0xb09 + j), 0x00000000); 272 } 273 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 274 275 if (gmc_v7_0_wait_for_idle((void *)adev)) { 276 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 277 } 278 if (adev->mode_info.num_crtc) { 279 /* Lockout access through VGA aperture*/ 280 tmp = RREG32(mmVGA_HDP_CONTROL); 281 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 282 WREG32(mmVGA_HDP_CONTROL, tmp); 283 284 /* disable VGA render */ 285 tmp = RREG32(mmVGA_RENDER_CONTROL); 286 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 287 WREG32(mmVGA_RENDER_CONTROL, tmp); 288 } 289 /* Update configuration */ 290 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 291 adev->gmc.vram_start >> 12); 292 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 293 adev->gmc.vram_end >> 12); 294 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 295 adev->vram_scratch.gpu_addr >> 12); 296 WREG32(mmMC_VM_AGP_BASE, 0); 297 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); 298 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); 299 if (gmc_v7_0_wait_for_idle((void *)adev)) { 300 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 301 } 302 303 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 304 305 tmp = RREG32(mmHDP_MISC_CNTL); 306 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); 307 WREG32(mmHDP_MISC_CNTL, tmp); 308 309 tmp = RREG32(mmHDP_HOST_PATH_CNTL); 310 WREG32(mmHDP_HOST_PATH_CNTL, tmp); 311 } 312 313 /** 314 * gmc_v7_0_mc_init - initialize the memory controller driver params 315 * 316 * @adev: amdgpu_device pointer 317 * 318 * Look up the amount of vram, vram width, and decide how to place 319 * vram and gart within the GPU's physical address space (CIK). 320 * Returns 0 for success. 321 */ 322 static int gmc_v7_0_mc_init(struct amdgpu_device *adev) 323 { 324 int r; 325 326 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev); 327 if (!adev->gmc.vram_width) { 328 u32 tmp; 329 int chansize, numchan; 330 331 /* Get VRAM informations */ 332 tmp = RREG32(mmMC_ARB_RAMCFG); 333 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { 334 chansize = 64; 335 } else { 336 chansize = 32; 337 } 338 tmp = RREG32(mmMC_SHARED_CHMAP); 339 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 340 case 0: 341 default: 342 numchan = 1; 343 break; 344 case 1: 345 numchan = 2; 346 break; 347 case 2: 348 numchan = 4; 349 break; 350 case 3: 351 numchan = 8; 352 break; 353 case 4: 354 numchan = 3; 355 break; 356 case 5: 357 numchan = 6; 358 break; 359 case 6: 360 numchan = 10; 361 break; 362 case 7: 363 numchan = 12; 364 break; 365 case 8: 366 numchan = 16; 367 break; 368 } 369 adev->gmc.vram_width = numchan * chansize; 370 } 371 /* size in MB on si */ 372 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 373 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 374 375 if (!(adev->flags & AMD_IS_APU)) { 376 r = amdgpu_device_resize_fb_bar(adev); 377 if (r) 378 return r; 379 } 380 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 381 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 382 383 #ifdef CONFIG_X86_64 384 if (adev->flags & AMD_IS_APU && 385 adev->gmc.real_vram_size > adev->gmc.aper_size) { 386 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; 387 adev->gmc.aper_size = adev->gmc.real_vram_size; 388 } 389 #endif 390 391 /* In case the PCI BAR is larger than the actual amount of vram */ 392 adev->gmc.visible_vram_size = adev->gmc.aper_size; 393 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 394 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 395 396 /* set the gart size */ 397 if (amdgpu_gart_size == -1) { 398 switch (adev->asic_type) { 399 case CHIP_TOPAZ: /* no MM engines */ 400 default: 401 adev->gmc.gart_size = 256ULL << 20; 402 break; 403 #ifdef CONFIG_DRM_AMDGPU_CIK 404 case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */ 405 case CHIP_HAWAII: /* UVD, VCE do not support GPUVM */ 406 case CHIP_KAVERI: /* UVD, VCE do not support GPUVM */ 407 case CHIP_KABINI: /* UVD, VCE do not support GPUVM */ 408 case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */ 409 adev->gmc.gart_size = 1024ULL << 20; 410 break; 411 #endif 412 } 413 } else { 414 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 415 } 416 417 gmc_v7_0_vram_gtt_location(adev, &adev->gmc); 418 419 return 0; 420 } 421 422 /** 423 * gmc_v7_0_flush_gpu_tlb_pasid - tlb flush via pasid 424 * 425 * @adev: amdgpu_device pointer 426 * @pasid: pasid to be flush 427 * @flush_type: type of flush 428 * @all_hub: flush all hubs 429 * 430 * Flush the TLB for the requested pasid. 431 */ 432 static int gmc_v7_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 433 uint16_t pasid, uint32_t flush_type, 434 bool all_hub) 435 { 436 int vmid; 437 unsigned int tmp; 438 439 if (amdgpu_in_reset(adev)) 440 return -EIO; 441 442 for (vmid = 1; vmid < 16; vmid++) { 443 444 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); 445 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) && 446 (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) { 447 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 448 RREG32(mmVM_INVALIDATE_RESPONSE); 449 break; 450 } 451 } 452 453 return 0; 454 } 455 456 /* 457 * GART 458 * VMID 0 is the physical GPU addresses as used by the kernel. 459 * VMIDs 1-15 are used for userspace clients and are handled 460 * by the amdgpu vm/hsa code. 461 */ 462 463 /** 464 * gmc_v7_0_flush_gpu_tlb - gart tlb flush callback 465 * 466 * @adev: amdgpu_device pointer 467 * @vmid: vm instance to flush 468 * @vmhub: which hub to flush 469 * @flush_type: type of flush 470 * * 471 * Flush the TLB for the requested page table (CIK). 472 */ 473 static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 474 uint32_t vmhub, uint32_t flush_type) 475 { 476 /* bits 0-15 are the VM contexts0-15 */ 477 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 478 } 479 480 static uint64_t gmc_v7_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 481 unsigned vmid, uint64_t pd_addr) 482 { 483 uint32_t reg; 484 485 if (vmid < 8) 486 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; 487 else 488 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8; 489 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); 490 491 /* bits 0-15 are the VM contexts0-15 */ 492 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); 493 494 return pd_addr; 495 } 496 497 static void gmc_v7_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 498 unsigned pasid) 499 { 500 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); 501 } 502 503 static void gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, int level, 504 uint64_t *addr, uint64_t *flags) 505 { 506 BUG_ON(*addr & 0xFFFFFF0000000FFFULL); 507 } 508 509 static void gmc_v7_0_get_vm_pte(struct amdgpu_device *adev, 510 struct amdgpu_bo_va_mapping *mapping, 511 uint64_t *flags) 512 { 513 *flags &= ~AMDGPU_PTE_EXECUTABLE; 514 *flags &= ~AMDGPU_PTE_PRT; 515 } 516 517 /** 518 * gmc_v8_0_set_fault_enable_default - update VM fault handling 519 * 520 * @adev: amdgpu_device pointer 521 * @value: true redirects VM faults to the default page 522 */ 523 static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev, 524 bool value) 525 { 526 u32 tmp; 527 528 tmp = RREG32(mmVM_CONTEXT1_CNTL); 529 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 530 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 531 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 532 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 533 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 534 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 535 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 536 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 537 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 538 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 539 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 540 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 541 WREG32(mmVM_CONTEXT1_CNTL, tmp); 542 } 543 544 /** 545 * gmc_v7_0_set_prt - set PRT VM fault 546 * 547 * @adev: amdgpu_device pointer 548 * @enable: enable/disable VM fault handling for PRT 549 */ 550 static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable) 551 { 552 uint32_t tmp; 553 554 if (enable && !adev->gmc.prt_warning) { 555 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 556 adev->gmc.prt_warning = true; 557 } 558 559 tmp = RREG32(mmVM_PRT_CNTL); 560 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 561 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 562 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 563 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 564 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 565 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 566 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 567 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 568 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 569 L2_CACHE_STORE_INVALID_ENTRIES, enable); 570 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 571 L1_TLB_STORE_INVALID_ENTRIES, enable); 572 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 573 MASK_PDE0_FAULT, enable); 574 WREG32(mmVM_PRT_CNTL, tmp); 575 576 if (enable) { 577 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; 578 uint32_t high = adev->vm_manager.max_pfn - 579 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT); 580 581 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); 582 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); 583 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); 584 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); 585 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); 586 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); 587 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); 588 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); 589 } else { 590 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); 591 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); 592 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); 593 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); 594 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); 595 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); 596 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); 597 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); 598 } 599 } 600 601 /** 602 * gmc_v7_0_gart_enable - gart enable 603 * 604 * @adev: amdgpu_device pointer 605 * 606 * This sets up the TLBs, programs the page tables for VMID0, 607 * sets up the hw for VMIDs 1-15 which are allocated on 608 * demand, and sets up the global locations for the LDS, GDS, 609 * and GPUVM for FSA64 clients (CIK). 610 * Returns 0 for success, errors for failure. 611 */ 612 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev) 613 { 614 uint64_t table_addr; 615 int r, i; 616 u32 tmp, field; 617 618 if (adev->gart.bo == NULL) { 619 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 620 return -EINVAL; 621 } 622 r = amdgpu_gart_table_vram_pin(adev); 623 if (r) 624 return r; 625 626 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 627 628 /* Setup TLB control */ 629 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 630 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 631 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); 632 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 633 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); 634 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 635 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 636 /* Setup L2 cache */ 637 tmp = RREG32(mmVM_L2_CNTL); 638 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 639 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 640 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); 641 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); 642 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); 643 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 644 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 645 WREG32(mmVM_L2_CNTL, tmp); 646 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 647 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 648 WREG32(mmVM_L2_CNTL2, tmp); 649 650 field = adev->vm_manager.fragment_size; 651 tmp = RREG32(mmVM_L2_CNTL3); 652 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); 653 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); 654 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); 655 WREG32(mmVM_L2_CNTL3, tmp); 656 /* setup context0 */ 657 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); 658 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); 659 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12); 660 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 661 (u32)(adev->dummy_page_addr >> 12)); 662 WREG32(mmVM_CONTEXT0_CNTL2, 0); 663 tmp = RREG32(mmVM_CONTEXT0_CNTL); 664 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 665 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 666 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 667 WREG32(mmVM_CONTEXT0_CNTL, tmp); 668 669 WREG32(0x575, 0); 670 WREG32(0x576, 0); 671 WREG32(0x577, 0); 672 673 /* empty context1-15 */ 674 /* FIXME start with 4G, once using 2 level pt switch to full 675 * vm size space 676 */ 677 /* set vm size, must be a multiple of 4 */ 678 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 679 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 680 for (i = 1; i < 16; i++) { 681 if (i < 8) 682 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 683 table_addr >> 12); 684 else 685 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 686 table_addr >> 12); 687 } 688 689 /* enable context1-15 */ 690 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 691 (u32)(adev->dummy_page_addr >> 12)); 692 WREG32(mmVM_CONTEXT1_CNTL2, 4); 693 tmp = RREG32(mmVM_CONTEXT1_CNTL); 694 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 695 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); 696 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, 697 adev->vm_manager.block_size - 9); 698 WREG32(mmVM_CONTEXT1_CNTL, tmp); 699 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 700 gmc_v7_0_set_fault_enable_default(adev, false); 701 else 702 gmc_v7_0_set_fault_enable_default(adev, true); 703 704 if (adev->asic_type == CHIP_KAVERI) { 705 tmp = RREG32(mmCHUB_CONTROL); 706 tmp &= ~BYPASS_VM; 707 WREG32(mmCHUB_CONTROL, tmp); 708 } 709 710 gmc_v7_0_flush_gpu_tlb(adev, 0, 0, 0); 711 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 712 (unsigned)(adev->gmc.gart_size >> 20), 713 (unsigned long long)table_addr); 714 adev->gart.ready = true; 715 return 0; 716 } 717 718 static int gmc_v7_0_gart_init(struct amdgpu_device *adev) 719 { 720 int r; 721 722 if (adev->gart.bo) { 723 WARN(1, "R600 PCIE GART already initialized\n"); 724 return 0; 725 } 726 /* Initialize common gart structure */ 727 r = amdgpu_gart_init(adev); 728 if (r) 729 return r; 730 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 731 adev->gart.gart_pte_flags = 0; 732 return amdgpu_gart_table_vram_alloc(adev); 733 } 734 735 /** 736 * gmc_v7_0_gart_disable - gart disable 737 * 738 * @adev: amdgpu_device pointer 739 * 740 * This disables all VM page table (CIK). 741 */ 742 static void gmc_v7_0_gart_disable(struct amdgpu_device *adev) 743 { 744 u32 tmp; 745 746 /* Disable all tables */ 747 WREG32(mmVM_CONTEXT0_CNTL, 0); 748 WREG32(mmVM_CONTEXT1_CNTL, 0); 749 /* Setup TLB control */ 750 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 751 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 752 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); 753 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); 754 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 755 /* Setup L2 cache */ 756 tmp = RREG32(mmVM_L2_CNTL); 757 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 758 WREG32(mmVM_L2_CNTL, tmp); 759 WREG32(mmVM_L2_CNTL2, 0); 760 amdgpu_gart_table_vram_unpin(adev); 761 } 762 763 /** 764 * gmc_v7_0_vm_decode_fault - print human readable fault info 765 * 766 * @adev: amdgpu_device pointer 767 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value 768 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value 769 * @mc_client: VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT register value 770 * @pasid: debug logging only - no functional use 771 * 772 * Print human readable fault information (CIK). 773 */ 774 static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev, u32 status, 775 u32 addr, u32 mc_client, unsigned pasid) 776 { 777 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 778 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 779 PROTECTIONS); 780 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 781 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 782 u32 mc_id; 783 784 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 785 MEMORY_CLIENT_ID); 786 787 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 788 protections, vmid, pasid, addr, 789 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 790 MEMORY_CLIENT_RW) ? 791 "write" : "read", block, mc_client, mc_id); 792 } 793 794 795 static const u32 mc_cg_registers[] = { 796 mmMC_HUB_MISC_HUB_CG, 797 mmMC_HUB_MISC_SIP_CG, 798 mmMC_HUB_MISC_VM_CG, 799 mmMC_XPB_CLK_GAT, 800 mmATC_MISC_CG, 801 mmMC_CITF_MISC_WR_CG, 802 mmMC_CITF_MISC_RD_CG, 803 mmMC_CITF_MISC_VM_CG, 804 mmVM_L2_CG, 805 }; 806 807 static const u32 mc_cg_ls_en[] = { 808 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK, 809 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK, 810 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK, 811 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK, 812 ATC_MISC_CG__MEM_LS_ENABLE_MASK, 813 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK, 814 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK, 815 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK, 816 VM_L2_CG__MEM_LS_ENABLE_MASK, 817 }; 818 819 static const u32 mc_cg_en[] = { 820 MC_HUB_MISC_HUB_CG__ENABLE_MASK, 821 MC_HUB_MISC_SIP_CG__ENABLE_MASK, 822 MC_HUB_MISC_VM_CG__ENABLE_MASK, 823 MC_XPB_CLK_GAT__ENABLE_MASK, 824 ATC_MISC_CG__ENABLE_MASK, 825 MC_CITF_MISC_WR_CG__ENABLE_MASK, 826 MC_CITF_MISC_RD_CG__ENABLE_MASK, 827 MC_CITF_MISC_VM_CG__ENABLE_MASK, 828 VM_L2_CG__ENABLE_MASK, 829 }; 830 831 static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev, 832 bool enable) 833 { 834 int i; 835 u32 orig, data; 836 837 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 838 orig = data = RREG32(mc_cg_registers[i]); 839 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) 840 data |= mc_cg_ls_en[i]; 841 else 842 data &= ~mc_cg_ls_en[i]; 843 if (data != orig) 844 WREG32(mc_cg_registers[i], data); 845 } 846 } 847 848 static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev, 849 bool enable) 850 { 851 int i; 852 u32 orig, data; 853 854 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 855 orig = data = RREG32(mc_cg_registers[i]); 856 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) 857 data |= mc_cg_en[i]; 858 else 859 data &= ~mc_cg_en[i]; 860 if (data != orig) 861 WREG32(mc_cg_registers[i], data); 862 } 863 } 864 865 static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev, 866 bool enable) 867 { 868 u32 orig, data; 869 870 orig = data = RREG32_PCIE(ixPCIE_CNTL2); 871 872 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 873 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1); 874 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1); 875 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1); 876 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1); 877 } else { 878 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0); 879 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0); 880 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0); 881 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0); 882 } 883 884 if (orig != data) 885 WREG32_PCIE(ixPCIE_CNTL2, data); 886 } 887 888 static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev, 889 bool enable) 890 { 891 u32 orig, data; 892 893 orig = data = RREG32(mmHDP_HOST_PATH_CNTL); 894 895 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 896 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0); 897 else 898 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1); 899 900 if (orig != data) 901 WREG32(mmHDP_HOST_PATH_CNTL, data); 902 } 903 904 static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev, 905 bool enable) 906 { 907 u32 orig, data; 908 909 orig = data = RREG32(mmHDP_MEM_POWER_LS); 910 911 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 912 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1); 913 else 914 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0); 915 916 if (orig != data) 917 WREG32(mmHDP_MEM_POWER_LS, data); 918 } 919 920 static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type) 921 { 922 switch (mc_seq_vram_type) { 923 case MC_SEQ_MISC0__MT__GDDR1: 924 return AMDGPU_VRAM_TYPE_GDDR1; 925 case MC_SEQ_MISC0__MT__DDR2: 926 return AMDGPU_VRAM_TYPE_DDR2; 927 case MC_SEQ_MISC0__MT__GDDR3: 928 return AMDGPU_VRAM_TYPE_GDDR3; 929 case MC_SEQ_MISC0__MT__GDDR4: 930 return AMDGPU_VRAM_TYPE_GDDR4; 931 case MC_SEQ_MISC0__MT__GDDR5: 932 return AMDGPU_VRAM_TYPE_GDDR5; 933 case MC_SEQ_MISC0__MT__HBM: 934 return AMDGPU_VRAM_TYPE_HBM; 935 case MC_SEQ_MISC0__MT__DDR3: 936 return AMDGPU_VRAM_TYPE_DDR3; 937 default: 938 return AMDGPU_VRAM_TYPE_UNKNOWN; 939 } 940 } 941 942 static int gmc_v7_0_early_init(void *handle) 943 { 944 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 945 946 gmc_v7_0_set_gmc_funcs(adev); 947 gmc_v7_0_set_irq_funcs(adev); 948 949 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 950 adev->gmc.shared_aperture_end = 951 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 952 adev->gmc.private_aperture_start = 953 adev->gmc.shared_aperture_end + 1; 954 adev->gmc.private_aperture_end = 955 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 956 957 return 0; 958 } 959 960 static int gmc_v7_0_late_init(void *handle) 961 { 962 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 963 964 amdgpu_bo_late_init(adev); 965 966 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 967 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 968 else 969 return 0; 970 } 971 972 static unsigned gmc_v7_0_get_vbios_fb_size(struct amdgpu_device *adev) 973 { 974 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); 975 unsigned size; 976 977 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 978 size = AMDGPU_VBIOS_VGA_ALLOCATION; 979 } else { 980 u32 viewport = RREG32(mmVIEWPORT_SIZE); 981 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 982 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * 983 4); 984 } 985 986 return size; 987 } 988 989 static int gmc_v7_0_sw_init(void *handle) 990 { 991 int r; 992 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 993 994 adev->num_vmhubs = 1; 995 996 if (adev->flags & AMD_IS_APU) { 997 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 998 } else { 999 u32 tmp = RREG32(mmMC_SEQ_MISC0); 1000 tmp &= MC_SEQ_MISC0__MT__MASK; 1001 adev->gmc.vram_type = gmc_v7_0_convert_vram_type(tmp); 1002 } 1003 1004 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault); 1005 if (r) 1006 return r; 1007 1008 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault); 1009 if (r) 1010 return r; 1011 1012 /* Adjust VM size here. 1013 * Currently set to 4GB ((1 << 20) 4k pages). 1014 * Max GPUVM size for cayman and SI is 40 bits. 1015 */ 1016 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); 1017 1018 /* Set the internal MC address mask 1019 * This is the max address of the GPU's 1020 * internal address space. 1021 */ 1022 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1023 1024 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40)); 1025 if (r) { 1026 pr_warn("No suitable DMA available\n"); 1027 return r; 1028 } 1029 adev->need_swiotlb = drm_need_swiotlb(40); 1030 1031 r = gmc_v7_0_init_microcode(adev); 1032 if (r) { 1033 DRM_ERROR("Failed to load mc firmware!\n"); 1034 return r; 1035 } 1036 1037 r = gmc_v7_0_mc_init(adev); 1038 if (r) 1039 return r; 1040 1041 amdgpu_gmc_get_vbios_allocations(adev); 1042 1043 /* Memory manager */ 1044 r = amdgpu_bo_init(adev); 1045 if (r) 1046 return r; 1047 1048 r = gmc_v7_0_gart_init(adev); 1049 if (r) 1050 return r; 1051 1052 /* 1053 * number of VMs 1054 * VMID 0 is reserved for System 1055 * amdgpu graphics/compute will use VMIDs 1-7 1056 * amdkfd will use VMIDs 8-15 1057 */ 1058 adev->vm_manager.first_kfd_vmid = 8; 1059 amdgpu_vm_manager_init(adev); 1060 1061 /* base offset of vram pages */ 1062 if (adev->flags & AMD_IS_APU) { 1063 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 1064 1065 tmp <<= 22; 1066 adev->vm_manager.vram_base_offset = tmp; 1067 } else { 1068 adev->vm_manager.vram_base_offset = 0; 1069 } 1070 1071 adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info), 1072 GFP_KERNEL); 1073 if (!adev->gmc.vm_fault_info) 1074 return -ENOMEM; 1075 atomic_set(&adev->gmc.vm_fault_info_updated, 0); 1076 1077 return 0; 1078 } 1079 1080 static int gmc_v7_0_sw_fini(void *handle) 1081 { 1082 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1083 1084 amdgpu_gem_force_release(adev); 1085 amdgpu_vm_manager_fini(adev); 1086 kfree(adev->gmc.vm_fault_info); 1087 amdgpu_gart_table_vram_free(adev); 1088 amdgpu_bo_fini(adev); 1089 amdgpu_gart_fini(adev); 1090 release_firmware(adev->gmc.fw); 1091 adev->gmc.fw = NULL; 1092 1093 return 0; 1094 } 1095 1096 static int gmc_v7_0_hw_init(void *handle) 1097 { 1098 int r; 1099 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1100 1101 gmc_v7_0_init_golden_registers(adev); 1102 1103 gmc_v7_0_mc_program(adev); 1104 1105 if (!(adev->flags & AMD_IS_APU)) { 1106 r = gmc_v7_0_mc_load_microcode(adev); 1107 if (r) { 1108 DRM_ERROR("Failed to load MC firmware!\n"); 1109 return r; 1110 } 1111 } 1112 1113 r = gmc_v7_0_gart_enable(adev); 1114 if (r) 1115 return r; 1116 1117 return r; 1118 } 1119 1120 static int gmc_v7_0_hw_fini(void *handle) 1121 { 1122 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1123 1124 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1125 gmc_v7_0_gart_disable(adev); 1126 1127 return 0; 1128 } 1129 1130 static int gmc_v7_0_suspend(void *handle) 1131 { 1132 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1133 1134 gmc_v7_0_hw_fini(adev); 1135 1136 return 0; 1137 } 1138 1139 static int gmc_v7_0_resume(void *handle) 1140 { 1141 int r; 1142 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1143 1144 r = gmc_v7_0_hw_init(adev); 1145 if (r) 1146 return r; 1147 1148 amdgpu_vmid_reset_all(adev); 1149 1150 return 0; 1151 } 1152 1153 static bool gmc_v7_0_is_idle(void *handle) 1154 { 1155 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1156 u32 tmp = RREG32(mmSRBM_STATUS); 1157 1158 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1159 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 1160 return false; 1161 1162 return true; 1163 } 1164 1165 static int gmc_v7_0_wait_for_idle(void *handle) 1166 { 1167 unsigned i; 1168 u32 tmp; 1169 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1170 1171 for (i = 0; i < adev->usec_timeout; i++) { 1172 /* read MC_STATUS */ 1173 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | 1174 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1175 SRBM_STATUS__MCC_BUSY_MASK | 1176 SRBM_STATUS__MCD_BUSY_MASK | 1177 SRBM_STATUS__VMC_BUSY_MASK); 1178 if (!tmp) 1179 return 0; 1180 udelay(1); 1181 } 1182 return -ETIMEDOUT; 1183 1184 } 1185 1186 static int gmc_v7_0_soft_reset(void *handle) 1187 { 1188 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1189 u32 srbm_soft_reset = 0; 1190 u32 tmp = RREG32(mmSRBM_STATUS); 1191 1192 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1193 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1194 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 1195 1196 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1197 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 1198 if (!(adev->flags & AMD_IS_APU)) 1199 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1200 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1201 } 1202 1203 if (srbm_soft_reset) { 1204 gmc_v7_0_mc_stop(adev); 1205 if (gmc_v7_0_wait_for_idle((void *)adev)) { 1206 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1207 } 1208 1209 1210 tmp = RREG32(mmSRBM_SOFT_RESET); 1211 tmp |= srbm_soft_reset; 1212 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1213 WREG32(mmSRBM_SOFT_RESET, tmp); 1214 tmp = RREG32(mmSRBM_SOFT_RESET); 1215 1216 udelay(50); 1217 1218 tmp &= ~srbm_soft_reset; 1219 WREG32(mmSRBM_SOFT_RESET, tmp); 1220 tmp = RREG32(mmSRBM_SOFT_RESET); 1221 1222 /* Wait a little for things to settle down */ 1223 udelay(50); 1224 1225 gmc_v7_0_mc_resume(adev); 1226 udelay(50); 1227 } 1228 1229 return 0; 1230 } 1231 1232 static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1233 struct amdgpu_irq_src *src, 1234 unsigned type, 1235 enum amdgpu_interrupt_state state) 1236 { 1237 u32 tmp; 1238 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1239 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1240 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1241 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1242 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1243 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1244 1245 switch (state) { 1246 case AMDGPU_IRQ_STATE_DISABLE: 1247 /* system context */ 1248 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1249 tmp &= ~bits; 1250 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1251 /* VMs */ 1252 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1253 tmp &= ~bits; 1254 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1255 break; 1256 case AMDGPU_IRQ_STATE_ENABLE: 1257 /* system context */ 1258 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1259 tmp |= bits; 1260 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1261 /* VMs */ 1262 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1263 tmp |= bits; 1264 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1265 break; 1266 default: 1267 break; 1268 } 1269 1270 return 0; 1271 } 1272 1273 static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev, 1274 struct amdgpu_irq_src *source, 1275 struct amdgpu_iv_entry *entry) 1276 { 1277 u32 addr, status, mc_client, vmid; 1278 1279 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1280 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1281 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); 1282 /* reset addr and status */ 1283 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1284 1285 if (!addr && !status) 1286 return 0; 1287 1288 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1289 gmc_v7_0_set_fault_enable_default(adev, false); 1290 1291 if (printk_ratelimit()) { 1292 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1293 entry->src_id, entry->src_data[0]); 1294 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1295 addr); 1296 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1297 status); 1298 gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client, 1299 entry->pasid); 1300 } 1301 1302 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1303 VMID); 1304 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid) 1305 && !atomic_read(&adev->gmc.vm_fault_info_updated)) { 1306 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info; 1307 u32 protections = REG_GET_FIELD(status, 1308 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1309 PROTECTIONS); 1310 1311 info->vmid = vmid; 1312 info->mc_id = REG_GET_FIELD(status, 1313 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1314 MEMORY_CLIENT_ID); 1315 info->status = status; 1316 info->page_addr = addr; 1317 info->prot_valid = protections & 0x7 ? true : false; 1318 info->prot_read = protections & 0x8 ? true : false; 1319 info->prot_write = protections & 0x10 ? true : false; 1320 info->prot_exec = protections & 0x20 ? true : false; 1321 mb(); 1322 atomic_set(&adev->gmc.vm_fault_info_updated, 1); 1323 } 1324 1325 return 0; 1326 } 1327 1328 static int gmc_v7_0_set_clockgating_state(void *handle, 1329 enum amd_clockgating_state state) 1330 { 1331 bool gate = false; 1332 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1333 1334 if (state == AMD_CG_STATE_GATE) 1335 gate = true; 1336 1337 if (!(adev->flags & AMD_IS_APU)) { 1338 gmc_v7_0_enable_mc_mgcg(adev, gate); 1339 gmc_v7_0_enable_mc_ls(adev, gate); 1340 } 1341 gmc_v7_0_enable_bif_mgls(adev, gate); 1342 gmc_v7_0_enable_hdp_mgcg(adev, gate); 1343 gmc_v7_0_enable_hdp_ls(adev, gate); 1344 1345 return 0; 1346 } 1347 1348 static int gmc_v7_0_set_powergating_state(void *handle, 1349 enum amd_powergating_state state) 1350 { 1351 return 0; 1352 } 1353 1354 static const struct amd_ip_funcs gmc_v7_0_ip_funcs = { 1355 .name = "gmc_v7_0", 1356 .early_init = gmc_v7_0_early_init, 1357 .late_init = gmc_v7_0_late_init, 1358 .sw_init = gmc_v7_0_sw_init, 1359 .sw_fini = gmc_v7_0_sw_fini, 1360 .hw_init = gmc_v7_0_hw_init, 1361 .hw_fini = gmc_v7_0_hw_fini, 1362 .suspend = gmc_v7_0_suspend, 1363 .resume = gmc_v7_0_resume, 1364 .is_idle = gmc_v7_0_is_idle, 1365 .wait_for_idle = gmc_v7_0_wait_for_idle, 1366 .soft_reset = gmc_v7_0_soft_reset, 1367 .set_clockgating_state = gmc_v7_0_set_clockgating_state, 1368 .set_powergating_state = gmc_v7_0_set_powergating_state, 1369 }; 1370 1371 static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = { 1372 .flush_gpu_tlb = gmc_v7_0_flush_gpu_tlb, 1373 .flush_gpu_tlb_pasid = gmc_v7_0_flush_gpu_tlb_pasid, 1374 .emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb, 1375 .emit_pasid_mapping = gmc_v7_0_emit_pasid_mapping, 1376 .set_prt = gmc_v7_0_set_prt, 1377 .get_vm_pde = gmc_v7_0_get_vm_pde, 1378 .get_vm_pte = gmc_v7_0_get_vm_pte, 1379 .get_vbios_fb_size = gmc_v7_0_get_vbios_fb_size, 1380 }; 1381 1382 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = { 1383 .set = gmc_v7_0_vm_fault_interrupt_state, 1384 .process = gmc_v7_0_process_interrupt, 1385 }; 1386 1387 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev) 1388 { 1389 adev->gmc.gmc_funcs = &gmc_v7_0_gmc_funcs; 1390 } 1391 1392 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev) 1393 { 1394 adev->gmc.vm_fault.num_types = 1; 1395 adev->gmc.vm_fault.funcs = &gmc_v7_0_irq_funcs; 1396 } 1397 1398 const struct amdgpu_ip_block_version gmc_v7_0_ip_block = 1399 { 1400 .type = AMD_IP_BLOCK_TYPE_GMC, 1401 .major = 7, 1402 .minor = 0, 1403 .rev = 0, 1404 .funcs = &gmc_v7_0_ip_funcs, 1405 }; 1406 1407 const struct amdgpu_ip_block_version gmc_v7_4_ip_block = 1408 { 1409 .type = AMD_IP_BLOCK_TYPE_GMC, 1410 .major = 7, 1411 .minor = 4, 1412 .rev = 0, 1413 .funcs = &gmc_v7_0_ip_funcs, 1414 }; 1415