1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <drm/drmP.h> 25 #include <drm/drm_cache.h> 26 #include "amdgpu.h" 27 #include "cikd.h" 28 #include "cik.h" 29 #include "gmc_v7_0.h" 30 #include "amdgpu_ucode.h" 31 32 #include "bif/bif_4_1_d.h" 33 #include "bif/bif_4_1_sh_mask.h" 34 35 #include "gmc/gmc_7_1_d.h" 36 #include "gmc/gmc_7_1_sh_mask.h" 37 38 #include "oss/oss_2_0_d.h" 39 #include "oss/oss_2_0_sh_mask.h" 40 41 #include "dce/dce_8_0_d.h" 42 #include "dce/dce_8_0_sh_mask.h" 43 44 #include "amdgpu_atombios.h" 45 46 #include "ivsrcid/ivsrcid_vislands30.h" 47 48 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev); 49 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev); 50 static int gmc_v7_0_wait_for_idle(void *handle); 51 52 MODULE_FIRMWARE("amdgpu/bonaire_mc.bin"); 53 MODULE_FIRMWARE("amdgpu/hawaii_mc.bin"); 54 MODULE_FIRMWARE("amdgpu/topaz_mc.bin"); 55 56 static const u32 golden_settings_iceland_a11[] = 57 { 58 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 59 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 60 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 61 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 62 }; 63 64 static const u32 iceland_mgcg_cgcg_init[] = 65 { 66 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 67 }; 68 69 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev) 70 { 71 switch (adev->asic_type) { 72 case CHIP_TOPAZ: 73 amdgpu_device_program_register_sequence(adev, 74 iceland_mgcg_cgcg_init, 75 ARRAY_SIZE(iceland_mgcg_cgcg_init)); 76 amdgpu_device_program_register_sequence(adev, 77 golden_settings_iceland_a11, 78 ARRAY_SIZE(golden_settings_iceland_a11)); 79 break; 80 default: 81 break; 82 } 83 } 84 85 static void gmc_v7_0_mc_stop(struct amdgpu_device *adev) 86 { 87 u32 blackout; 88 89 gmc_v7_0_wait_for_idle((void *)adev); 90 91 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 92 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 93 /* Block CPU access */ 94 WREG32(mmBIF_FB_EN, 0); 95 /* blackout the MC */ 96 blackout = REG_SET_FIELD(blackout, 97 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 98 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); 99 } 100 /* wait for the MC to settle */ 101 udelay(100); 102 } 103 104 static void gmc_v7_0_mc_resume(struct amdgpu_device *adev) 105 { 106 u32 tmp; 107 108 /* unblackout the MC */ 109 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 110 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 111 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 112 /* allow CPU access */ 113 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 114 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 115 WREG32(mmBIF_FB_EN, tmp); 116 } 117 118 /** 119 * gmc_v7_0_init_microcode - load ucode images from disk 120 * 121 * @adev: amdgpu_device pointer 122 * 123 * Use the firmware interface to load the ucode images into 124 * the driver (not loaded into hw). 125 * Returns 0 on success, error on failure. 126 */ 127 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev) 128 { 129 const char *chip_name; 130 char fw_name[30]; 131 int err; 132 133 DRM_DEBUG("\n"); 134 135 switch (adev->asic_type) { 136 case CHIP_BONAIRE: 137 chip_name = "bonaire"; 138 break; 139 case CHIP_HAWAII: 140 chip_name = "hawaii"; 141 break; 142 case CHIP_TOPAZ: 143 chip_name = "topaz"; 144 break; 145 case CHIP_KAVERI: 146 case CHIP_KABINI: 147 case CHIP_MULLINS: 148 return 0; 149 default: BUG(); 150 } 151 152 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name); 153 154 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); 155 if (err) 156 goto out; 157 err = amdgpu_ucode_validate(adev->gmc.fw); 158 159 out: 160 if (err) { 161 pr_err("cik_mc: Failed to load firmware \"%s\"\n", fw_name); 162 release_firmware(adev->gmc.fw); 163 adev->gmc.fw = NULL; 164 } 165 return err; 166 } 167 168 /** 169 * gmc_v7_0_mc_load_microcode - load MC ucode into the hw 170 * 171 * @adev: amdgpu_device pointer 172 * 173 * Load the GDDR MC ucode into the hw (CIK). 174 * Returns 0 on success, error on failure. 175 */ 176 static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev) 177 { 178 const struct mc_firmware_header_v1_0 *hdr; 179 const __le32 *fw_data = NULL; 180 const __le32 *io_mc_regs = NULL; 181 u32 running; 182 int i, ucode_size, regs_size; 183 184 if (!adev->gmc.fw) 185 return -EINVAL; 186 187 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 188 amdgpu_ucode_print_mc_hdr(&hdr->header); 189 190 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 191 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 192 io_mc_regs = (const __le32 *) 193 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 194 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 195 fw_data = (const __le32 *) 196 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 197 198 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); 199 200 if (running == 0) { 201 /* reset the engine and set to writable */ 202 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 203 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 204 205 /* load mc io regs */ 206 for (i = 0; i < regs_size; i++) { 207 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 208 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 209 } 210 /* load the MC ucode */ 211 for (i = 0; i < ucode_size; i++) 212 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 213 214 /* put the engine back into the active state */ 215 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 216 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 217 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 218 219 /* wait for training to complete */ 220 for (i = 0; i < adev->usec_timeout; i++) { 221 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 222 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0)) 223 break; 224 udelay(1); 225 } 226 for (i = 0; i < adev->usec_timeout; i++) { 227 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 228 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1)) 229 break; 230 udelay(1); 231 } 232 } 233 234 return 0; 235 } 236 237 static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev, 238 struct amdgpu_gmc *mc) 239 { 240 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; 241 base <<= 24; 242 243 amdgpu_device_vram_location(adev, &adev->gmc, base); 244 amdgpu_device_gart_location(adev, mc); 245 } 246 247 /** 248 * gmc_v7_0_mc_program - program the GPU memory controller 249 * 250 * @adev: amdgpu_device pointer 251 * 252 * Set the location of vram, gart, and AGP in the GPU's 253 * physical address space (CIK). 254 */ 255 static void gmc_v7_0_mc_program(struct amdgpu_device *adev) 256 { 257 u32 tmp; 258 int i, j; 259 260 /* Initialize HDP */ 261 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 262 WREG32((0xb05 + j), 0x00000000); 263 WREG32((0xb06 + j), 0x00000000); 264 WREG32((0xb07 + j), 0x00000000); 265 WREG32((0xb08 + j), 0x00000000); 266 WREG32((0xb09 + j), 0x00000000); 267 } 268 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 269 270 if (gmc_v7_0_wait_for_idle((void *)adev)) { 271 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 272 } 273 if (adev->mode_info.num_crtc) { 274 /* Lockout access through VGA aperture*/ 275 tmp = RREG32(mmVGA_HDP_CONTROL); 276 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 277 WREG32(mmVGA_HDP_CONTROL, tmp); 278 279 /* disable VGA render */ 280 tmp = RREG32(mmVGA_RENDER_CONTROL); 281 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 282 WREG32(mmVGA_RENDER_CONTROL, tmp); 283 } 284 /* Update configuration */ 285 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 286 adev->gmc.vram_start >> 12); 287 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 288 adev->gmc.vram_end >> 12); 289 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 290 adev->vram_scratch.gpu_addr >> 12); 291 WREG32(mmMC_VM_AGP_BASE, 0); 292 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); 293 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); 294 if (gmc_v7_0_wait_for_idle((void *)adev)) { 295 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 296 } 297 298 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 299 300 tmp = RREG32(mmHDP_MISC_CNTL); 301 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); 302 WREG32(mmHDP_MISC_CNTL, tmp); 303 304 tmp = RREG32(mmHDP_HOST_PATH_CNTL); 305 WREG32(mmHDP_HOST_PATH_CNTL, tmp); 306 } 307 308 /** 309 * gmc_v7_0_mc_init - initialize the memory controller driver params 310 * 311 * @adev: amdgpu_device pointer 312 * 313 * Look up the amount of vram, vram width, and decide how to place 314 * vram and gart within the GPU's physical address space (CIK). 315 * Returns 0 for success. 316 */ 317 static int gmc_v7_0_mc_init(struct amdgpu_device *adev) 318 { 319 int r; 320 321 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev); 322 if (!adev->gmc.vram_width) { 323 u32 tmp; 324 int chansize, numchan; 325 326 /* Get VRAM informations */ 327 tmp = RREG32(mmMC_ARB_RAMCFG); 328 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { 329 chansize = 64; 330 } else { 331 chansize = 32; 332 } 333 tmp = RREG32(mmMC_SHARED_CHMAP); 334 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 335 case 0: 336 default: 337 numchan = 1; 338 break; 339 case 1: 340 numchan = 2; 341 break; 342 case 2: 343 numchan = 4; 344 break; 345 case 3: 346 numchan = 8; 347 break; 348 case 4: 349 numchan = 3; 350 break; 351 case 5: 352 numchan = 6; 353 break; 354 case 6: 355 numchan = 10; 356 break; 357 case 7: 358 numchan = 12; 359 break; 360 case 8: 361 numchan = 16; 362 break; 363 } 364 adev->gmc.vram_width = numchan * chansize; 365 } 366 /* size in MB on si */ 367 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 368 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 369 370 if (!(adev->flags & AMD_IS_APU)) { 371 r = amdgpu_device_resize_fb_bar(adev); 372 if (r) 373 return r; 374 } 375 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 376 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 377 378 #ifdef CONFIG_X86_64 379 if (adev->flags & AMD_IS_APU) { 380 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; 381 adev->gmc.aper_size = adev->gmc.real_vram_size; 382 } 383 #endif 384 385 /* In case the PCI BAR is larger than the actual amount of vram */ 386 adev->gmc.visible_vram_size = adev->gmc.aper_size; 387 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 388 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 389 390 /* set the gart size */ 391 if (amdgpu_gart_size == -1) { 392 switch (adev->asic_type) { 393 case CHIP_TOPAZ: /* no MM engines */ 394 default: 395 adev->gmc.gart_size = 256ULL << 20; 396 break; 397 #ifdef CONFIG_DRM_AMDGPU_CIK 398 case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */ 399 case CHIP_HAWAII: /* UVD, VCE do not support GPUVM */ 400 case CHIP_KAVERI: /* UVD, VCE do not support GPUVM */ 401 case CHIP_KABINI: /* UVD, VCE do not support GPUVM */ 402 case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */ 403 adev->gmc.gart_size = 1024ULL << 20; 404 break; 405 #endif 406 } 407 } else { 408 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 409 } 410 411 gmc_v7_0_vram_gtt_location(adev, &adev->gmc); 412 413 return 0; 414 } 415 416 /* 417 * GART 418 * VMID 0 is the physical GPU addresses as used by the kernel. 419 * VMIDs 1-15 are used for userspace clients and are handled 420 * by the amdgpu vm/hsa code. 421 */ 422 423 /** 424 * gmc_v7_0_flush_gpu_tlb - gart tlb flush callback 425 * 426 * @adev: amdgpu_device pointer 427 * @vmid: vm instance to flush 428 * 429 * Flush the TLB for the requested page table (CIK). 430 */ 431 static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid) 432 { 433 /* bits 0-15 are the VM contexts0-15 */ 434 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 435 } 436 437 static uint64_t gmc_v7_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 438 unsigned vmid, uint64_t pd_addr) 439 { 440 uint32_t reg; 441 442 if (vmid < 8) 443 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; 444 else 445 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8; 446 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); 447 448 /* bits 0-15 are the VM contexts0-15 */ 449 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); 450 451 return pd_addr; 452 } 453 454 static void gmc_v7_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 455 unsigned pasid) 456 { 457 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); 458 } 459 460 /** 461 * gmc_v7_0_set_pte_pde - update the page tables using MMIO 462 * 463 * @adev: amdgpu_device pointer 464 * @cpu_pt_addr: cpu address of the page table 465 * @gpu_page_idx: entry in the page table to update 466 * @addr: dst addr to write into pte/pde 467 * @flags: access flags 468 * 469 * Update the page tables using the CPU. 470 */ 471 static int gmc_v7_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 472 uint32_t gpu_page_idx, uint64_t addr, 473 uint64_t flags) 474 { 475 void __iomem *ptr = (void *)cpu_pt_addr; 476 uint64_t value; 477 478 value = addr & 0xFFFFFFFFFFFFF000ULL; 479 value |= flags; 480 writeq(value, ptr + (gpu_page_idx * 8)); 481 482 return 0; 483 } 484 485 static uint64_t gmc_v7_0_get_vm_pte_flags(struct amdgpu_device *adev, 486 uint32_t flags) 487 { 488 uint64_t pte_flag = 0; 489 490 if (flags & AMDGPU_VM_PAGE_READABLE) 491 pte_flag |= AMDGPU_PTE_READABLE; 492 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 493 pte_flag |= AMDGPU_PTE_WRITEABLE; 494 if (flags & AMDGPU_VM_PAGE_PRT) 495 pte_flag |= AMDGPU_PTE_PRT; 496 497 return pte_flag; 498 } 499 500 static void gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, int level, 501 uint64_t *addr, uint64_t *flags) 502 { 503 BUG_ON(*addr & 0xFFFFFF0000000FFFULL); 504 } 505 506 /** 507 * gmc_v8_0_set_fault_enable_default - update VM fault handling 508 * 509 * @adev: amdgpu_device pointer 510 * @value: true redirects VM faults to the default page 511 */ 512 static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev, 513 bool value) 514 { 515 u32 tmp; 516 517 tmp = RREG32(mmVM_CONTEXT1_CNTL); 518 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 519 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 520 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 521 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 522 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 523 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 524 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 525 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 526 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 527 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 528 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 529 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 530 WREG32(mmVM_CONTEXT1_CNTL, tmp); 531 } 532 533 /** 534 * gmc_v7_0_set_prt - set PRT VM fault 535 * 536 * @adev: amdgpu_device pointer 537 * @enable: enable/disable VM fault handling for PRT 538 */ 539 static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable) 540 { 541 uint32_t tmp; 542 543 if (enable && !adev->gmc.prt_warning) { 544 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 545 adev->gmc.prt_warning = true; 546 } 547 548 tmp = RREG32(mmVM_PRT_CNTL); 549 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 550 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 551 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 552 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 553 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 554 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 555 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 556 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 557 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 558 L2_CACHE_STORE_INVALID_ENTRIES, enable); 559 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 560 L1_TLB_STORE_INVALID_ENTRIES, enable); 561 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 562 MASK_PDE0_FAULT, enable); 563 WREG32(mmVM_PRT_CNTL, tmp); 564 565 if (enable) { 566 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; 567 uint32_t high = adev->vm_manager.max_pfn - 568 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT); 569 570 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); 571 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); 572 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); 573 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); 574 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); 575 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); 576 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); 577 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); 578 } else { 579 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); 580 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); 581 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); 582 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); 583 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); 584 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); 585 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); 586 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); 587 } 588 } 589 590 /** 591 * gmc_v7_0_gart_enable - gart enable 592 * 593 * @adev: amdgpu_device pointer 594 * 595 * This sets up the TLBs, programs the page tables for VMID0, 596 * sets up the hw for VMIDs 1-15 which are allocated on 597 * demand, and sets up the global locations for the LDS, GDS, 598 * and GPUVM for FSA64 clients (CIK). 599 * Returns 0 for success, errors for failure. 600 */ 601 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev) 602 { 603 int r, i; 604 u32 tmp, field; 605 606 if (adev->gart.robj == NULL) { 607 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 608 return -EINVAL; 609 } 610 r = amdgpu_gart_table_vram_pin(adev); 611 if (r) 612 return r; 613 /* Setup TLB control */ 614 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 615 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 616 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); 617 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 618 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); 619 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 620 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 621 /* Setup L2 cache */ 622 tmp = RREG32(mmVM_L2_CNTL); 623 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 624 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 625 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); 626 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); 627 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); 628 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 629 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 630 WREG32(mmVM_L2_CNTL, tmp); 631 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 632 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 633 WREG32(mmVM_L2_CNTL2, tmp); 634 635 field = adev->vm_manager.fragment_size; 636 tmp = RREG32(mmVM_L2_CNTL3); 637 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); 638 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); 639 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); 640 WREG32(mmVM_L2_CNTL3, tmp); 641 /* setup context0 */ 642 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); 643 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); 644 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); 645 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 646 (u32)(adev->dummy_page_addr >> 12)); 647 WREG32(mmVM_CONTEXT0_CNTL2, 0); 648 tmp = RREG32(mmVM_CONTEXT0_CNTL); 649 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 650 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 651 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 652 WREG32(mmVM_CONTEXT0_CNTL, tmp); 653 654 WREG32(0x575, 0); 655 WREG32(0x576, 0); 656 WREG32(0x577, 0); 657 658 /* empty context1-15 */ 659 /* FIXME start with 4G, once using 2 level pt switch to full 660 * vm size space 661 */ 662 /* set vm size, must be a multiple of 4 */ 663 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 664 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 665 for (i = 1; i < 16; i++) { 666 if (i < 8) 667 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 668 adev->gart.table_addr >> 12); 669 else 670 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 671 adev->gart.table_addr >> 12); 672 } 673 674 /* enable context1-15 */ 675 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 676 (u32)(adev->dummy_page_addr >> 12)); 677 WREG32(mmVM_CONTEXT1_CNTL2, 4); 678 tmp = RREG32(mmVM_CONTEXT1_CNTL); 679 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 680 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); 681 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, 682 adev->vm_manager.block_size - 9); 683 WREG32(mmVM_CONTEXT1_CNTL, tmp); 684 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 685 gmc_v7_0_set_fault_enable_default(adev, false); 686 else 687 gmc_v7_0_set_fault_enable_default(adev, true); 688 689 if (adev->asic_type == CHIP_KAVERI) { 690 tmp = RREG32(mmCHUB_CONTROL); 691 tmp &= ~BYPASS_VM; 692 WREG32(mmCHUB_CONTROL, tmp); 693 } 694 695 gmc_v7_0_flush_gpu_tlb(adev, 0); 696 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 697 (unsigned)(adev->gmc.gart_size >> 20), 698 (unsigned long long)adev->gart.table_addr); 699 adev->gart.ready = true; 700 return 0; 701 } 702 703 static int gmc_v7_0_gart_init(struct amdgpu_device *adev) 704 { 705 int r; 706 707 if (adev->gart.robj) { 708 WARN(1, "R600 PCIE GART already initialized\n"); 709 return 0; 710 } 711 /* Initialize common gart structure */ 712 r = amdgpu_gart_init(adev); 713 if (r) 714 return r; 715 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 716 adev->gart.gart_pte_flags = 0; 717 return amdgpu_gart_table_vram_alloc(adev); 718 } 719 720 /** 721 * gmc_v7_0_gart_disable - gart disable 722 * 723 * @adev: amdgpu_device pointer 724 * 725 * This disables all VM page table (CIK). 726 */ 727 static void gmc_v7_0_gart_disable(struct amdgpu_device *adev) 728 { 729 u32 tmp; 730 731 /* Disable all tables */ 732 WREG32(mmVM_CONTEXT0_CNTL, 0); 733 WREG32(mmVM_CONTEXT1_CNTL, 0); 734 /* Setup TLB control */ 735 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 736 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 737 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); 738 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); 739 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 740 /* Setup L2 cache */ 741 tmp = RREG32(mmVM_L2_CNTL); 742 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 743 WREG32(mmVM_L2_CNTL, tmp); 744 WREG32(mmVM_L2_CNTL2, 0); 745 amdgpu_gart_table_vram_unpin(adev); 746 } 747 748 /** 749 * gmc_v7_0_gart_fini - vm fini callback 750 * 751 * @adev: amdgpu_device pointer 752 * 753 * Tears down the driver GART/VM setup (CIK). 754 */ 755 static void gmc_v7_0_gart_fini(struct amdgpu_device *adev) 756 { 757 amdgpu_gart_table_vram_free(adev); 758 amdgpu_gart_fini(adev); 759 } 760 761 /** 762 * gmc_v7_0_vm_decode_fault - print human readable fault info 763 * 764 * @adev: amdgpu_device pointer 765 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value 766 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value 767 * 768 * Print human readable fault information (CIK). 769 */ 770 static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev, u32 status, 771 u32 addr, u32 mc_client, unsigned pasid) 772 { 773 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 774 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 775 PROTECTIONS); 776 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 777 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 778 u32 mc_id; 779 780 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 781 MEMORY_CLIENT_ID); 782 783 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 784 protections, vmid, pasid, addr, 785 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 786 MEMORY_CLIENT_RW) ? 787 "write" : "read", block, mc_client, mc_id); 788 } 789 790 791 static const u32 mc_cg_registers[] = { 792 mmMC_HUB_MISC_HUB_CG, 793 mmMC_HUB_MISC_SIP_CG, 794 mmMC_HUB_MISC_VM_CG, 795 mmMC_XPB_CLK_GAT, 796 mmATC_MISC_CG, 797 mmMC_CITF_MISC_WR_CG, 798 mmMC_CITF_MISC_RD_CG, 799 mmMC_CITF_MISC_VM_CG, 800 mmVM_L2_CG, 801 }; 802 803 static const u32 mc_cg_ls_en[] = { 804 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK, 805 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK, 806 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK, 807 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK, 808 ATC_MISC_CG__MEM_LS_ENABLE_MASK, 809 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK, 810 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK, 811 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK, 812 VM_L2_CG__MEM_LS_ENABLE_MASK, 813 }; 814 815 static const u32 mc_cg_en[] = { 816 MC_HUB_MISC_HUB_CG__ENABLE_MASK, 817 MC_HUB_MISC_SIP_CG__ENABLE_MASK, 818 MC_HUB_MISC_VM_CG__ENABLE_MASK, 819 MC_XPB_CLK_GAT__ENABLE_MASK, 820 ATC_MISC_CG__ENABLE_MASK, 821 MC_CITF_MISC_WR_CG__ENABLE_MASK, 822 MC_CITF_MISC_RD_CG__ENABLE_MASK, 823 MC_CITF_MISC_VM_CG__ENABLE_MASK, 824 VM_L2_CG__ENABLE_MASK, 825 }; 826 827 static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev, 828 bool enable) 829 { 830 int i; 831 u32 orig, data; 832 833 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 834 orig = data = RREG32(mc_cg_registers[i]); 835 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) 836 data |= mc_cg_ls_en[i]; 837 else 838 data &= ~mc_cg_ls_en[i]; 839 if (data != orig) 840 WREG32(mc_cg_registers[i], data); 841 } 842 } 843 844 static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev, 845 bool enable) 846 { 847 int i; 848 u32 orig, data; 849 850 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 851 orig = data = RREG32(mc_cg_registers[i]); 852 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) 853 data |= mc_cg_en[i]; 854 else 855 data &= ~mc_cg_en[i]; 856 if (data != orig) 857 WREG32(mc_cg_registers[i], data); 858 } 859 } 860 861 static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev, 862 bool enable) 863 { 864 u32 orig, data; 865 866 orig = data = RREG32_PCIE(ixPCIE_CNTL2); 867 868 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 869 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1); 870 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1); 871 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1); 872 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1); 873 } else { 874 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0); 875 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0); 876 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0); 877 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0); 878 } 879 880 if (orig != data) 881 WREG32_PCIE(ixPCIE_CNTL2, data); 882 } 883 884 static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev, 885 bool enable) 886 { 887 u32 orig, data; 888 889 orig = data = RREG32(mmHDP_HOST_PATH_CNTL); 890 891 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 892 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0); 893 else 894 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1); 895 896 if (orig != data) 897 WREG32(mmHDP_HOST_PATH_CNTL, data); 898 } 899 900 static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev, 901 bool enable) 902 { 903 u32 orig, data; 904 905 orig = data = RREG32(mmHDP_MEM_POWER_LS); 906 907 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 908 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1); 909 else 910 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0); 911 912 if (orig != data) 913 WREG32(mmHDP_MEM_POWER_LS, data); 914 } 915 916 static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type) 917 { 918 switch (mc_seq_vram_type) { 919 case MC_SEQ_MISC0__MT__GDDR1: 920 return AMDGPU_VRAM_TYPE_GDDR1; 921 case MC_SEQ_MISC0__MT__DDR2: 922 return AMDGPU_VRAM_TYPE_DDR2; 923 case MC_SEQ_MISC0__MT__GDDR3: 924 return AMDGPU_VRAM_TYPE_GDDR3; 925 case MC_SEQ_MISC0__MT__GDDR4: 926 return AMDGPU_VRAM_TYPE_GDDR4; 927 case MC_SEQ_MISC0__MT__GDDR5: 928 return AMDGPU_VRAM_TYPE_GDDR5; 929 case MC_SEQ_MISC0__MT__HBM: 930 return AMDGPU_VRAM_TYPE_HBM; 931 case MC_SEQ_MISC0__MT__DDR3: 932 return AMDGPU_VRAM_TYPE_DDR3; 933 default: 934 return AMDGPU_VRAM_TYPE_UNKNOWN; 935 } 936 } 937 938 static int gmc_v7_0_early_init(void *handle) 939 { 940 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 941 942 gmc_v7_0_set_gmc_funcs(adev); 943 gmc_v7_0_set_irq_funcs(adev); 944 945 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 946 adev->gmc.shared_aperture_end = 947 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 948 adev->gmc.private_aperture_start = 949 adev->gmc.shared_aperture_end + 1; 950 adev->gmc.private_aperture_end = 951 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 952 953 return 0; 954 } 955 956 static int gmc_v7_0_late_init(void *handle) 957 { 958 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 959 960 amdgpu_bo_late_init(adev); 961 962 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 963 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 964 else 965 return 0; 966 } 967 968 static unsigned gmc_v7_0_get_vbios_fb_size(struct amdgpu_device *adev) 969 { 970 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); 971 unsigned size; 972 973 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 974 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */ 975 } else { 976 u32 viewport = RREG32(mmVIEWPORT_SIZE); 977 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 978 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * 979 4); 980 } 981 /* return 0 if the pre-OS buffer uses up most of vram */ 982 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 983 return 0; 984 return size; 985 } 986 987 static int gmc_v7_0_sw_init(void *handle) 988 { 989 int r; 990 int dma_bits; 991 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 992 993 if (adev->flags & AMD_IS_APU) { 994 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 995 } else { 996 u32 tmp = RREG32(mmMC_SEQ_MISC0); 997 tmp &= MC_SEQ_MISC0__MT__MASK; 998 adev->gmc.vram_type = gmc_v7_0_convert_vram_type(tmp); 999 } 1000 1001 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault); 1002 if (r) 1003 return r; 1004 1005 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault); 1006 if (r) 1007 return r; 1008 1009 /* Adjust VM size here. 1010 * Currently set to 4GB ((1 << 20) 4k pages). 1011 * Max GPUVM size for cayman and SI is 40 bits. 1012 */ 1013 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); 1014 1015 /* Set the internal MC address mask 1016 * This is the max address of the GPU's 1017 * internal address space. 1018 */ 1019 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1020 1021 /* set DMA mask + need_dma32 flags. 1022 * PCIE - can handle 40-bits. 1023 * IGP - can handle 40-bits 1024 * PCI - dma32 for legacy pci gart, 40 bits on newer asics 1025 */ 1026 adev->need_dma32 = false; 1027 dma_bits = adev->need_dma32 ? 32 : 40; 1028 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 1029 if (r) { 1030 adev->need_dma32 = true; 1031 dma_bits = 32; 1032 pr_warn("amdgpu: No suitable DMA available\n"); 1033 } 1034 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 1035 if (r) { 1036 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); 1037 pr_warn("amdgpu: No coherent DMA available\n"); 1038 } 1039 adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits); 1040 1041 r = gmc_v7_0_init_microcode(adev); 1042 if (r) { 1043 DRM_ERROR("Failed to load mc firmware!\n"); 1044 return r; 1045 } 1046 1047 r = gmc_v7_0_mc_init(adev); 1048 if (r) 1049 return r; 1050 1051 adev->gmc.stolen_size = gmc_v7_0_get_vbios_fb_size(adev); 1052 1053 /* Memory manager */ 1054 r = amdgpu_bo_init(adev); 1055 if (r) 1056 return r; 1057 1058 r = gmc_v7_0_gart_init(adev); 1059 if (r) 1060 return r; 1061 1062 /* 1063 * number of VMs 1064 * VMID 0 is reserved for System 1065 * amdgpu graphics/compute will use VMIDs 1-7 1066 * amdkfd will use VMIDs 8-15 1067 */ 1068 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; 1069 amdgpu_vm_manager_init(adev); 1070 1071 /* base offset of vram pages */ 1072 if (adev->flags & AMD_IS_APU) { 1073 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 1074 1075 tmp <<= 22; 1076 adev->vm_manager.vram_base_offset = tmp; 1077 } else { 1078 adev->vm_manager.vram_base_offset = 0; 1079 } 1080 1081 return 0; 1082 } 1083 1084 static int gmc_v7_0_sw_fini(void *handle) 1085 { 1086 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1087 1088 amdgpu_gem_force_release(adev); 1089 amdgpu_vm_manager_fini(adev); 1090 gmc_v7_0_gart_fini(adev); 1091 amdgpu_bo_fini(adev); 1092 release_firmware(adev->gmc.fw); 1093 adev->gmc.fw = NULL; 1094 1095 return 0; 1096 } 1097 1098 static int gmc_v7_0_hw_init(void *handle) 1099 { 1100 int r; 1101 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1102 1103 gmc_v7_0_init_golden_registers(adev); 1104 1105 gmc_v7_0_mc_program(adev); 1106 1107 if (!(adev->flags & AMD_IS_APU)) { 1108 r = gmc_v7_0_mc_load_microcode(adev); 1109 if (r) { 1110 DRM_ERROR("Failed to load MC firmware!\n"); 1111 return r; 1112 } 1113 } 1114 1115 r = gmc_v7_0_gart_enable(adev); 1116 if (r) 1117 return r; 1118 1119 return r; 1120 } 1121 1122 static int gmc_v7_0_hw_fini(void *handle) 1123 { 1124 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1125 1126 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1127 gmc_v7_0_gart_disable(adev); 1128 1129 return 0; 1130 } 1131 1132 static int gmc_v7_0_suspend(void *handle) 1133 { 1134 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1135 1136 gmc_v7_0_hw_fini(adev); 1137 1138 return 0; 1139 } 1140 1141 static int gmc_v7_0_resume(void *handle) 1142 { 1143 int r; 1144 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1145 1146 r = gmc_v7_0_hw_init(adev); 1147 if (r) 1148 return r; 1149 1150 amdgpu_vmid_reset_all(adev); 1151 1152 return 0; 1153 } 1154 1155 static bool gmc_v7_0_is_idle(void *handle) 1156 { 1157 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1158 u32 tmp = RREG32(mmSRBM_STATUS); 1159 1160 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1161 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 1162 return false; 1163 1164 return true; 1165 } 1166 1167 static int gmc_v7_0_wait_for_idle(void *handle) 1168 { 1169 unsigned i; 1170 u32 tmp; 1171 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1172 1173 for (i = 0; i < adev->usec_timeout; i++) { 1174 /* read MC_STATUS */ 1175 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | 1176 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1177 SRBM_STATUS__MCC_BUSY_MASK | 1178 SRBM_STATUS__MCD_BUSY_MASK | 1179 SRBM_STATUS__VMC_BUSY_MASK); 1180 if (!tmp) 1181 return 0; 1182 udelay(1); 1183 } 1184 return -ETIMEDOUT; 1185 1186 } 1187 1188 static int gmc_v7_0_soft_reset(void *handle) 1189 { 1190 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1191 u32 srbm_soft_reset = 0; 1192 u32 tmp = RREG32(mmSRBM_STATUS); 1193 1194 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1195 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1196 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 1197 1198 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1199 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 1200 if (!(adev->flags & AMD_IS_APU)) 1201 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1202 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1203 } 1204 1205 if (srbm_soft_reset) { 1206 gmc_v7_0_mc_stop(adev); 1207 if (gmc_v7_0_wait_for_idle((void *)adev)) { 1208 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1209 } 1210 1211 1212 tmp = RREG32(mmSRBM_SOFT_RESET); 1213 tmp |= srbm_soft_reset; 1214 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1215 WREG32(mmSRBM_SOFT_RESET, tmp); 1216 tmp = RREG32(mmSRBM_SOFT_RESET); 1217 1218 udelay(50); 1219 1220 tmp &= ~srbm_soft_reset; 1221 WREG32(mmSRBM_SOFT_RESET, tmp); 1222 tmp = RREG32(mmSRBM_SOFT_RESET); 1223 1224 /* Wait a little for things to settle down */ 1225 udelay(50); 1226 1227 gmc_v7_0_mc_resume(adev); 1228 udelay(50); 1229 } 1230 1231 return 0; 1232 } 1233 1234 static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1235 struct amdgpu_irq_src *src, 1236 unsigned type, 1237 enum amdgpu_interrupt_state state) 1238 { 1239 u32 tmp; 1240 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1241 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1242 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1243 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1244 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1245 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1246 1247 switch (state) { 1248 case AMDGPU_IRQ_STATE_DISABLE: 1249 /* system context */ 1250 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1251 tmp &= ~bits; 1252 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1253 /* VMs */ 1254 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1255 tmp &= ~bits; 1256 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1257 break; 1258 case AMDGPU_IRQ_STATE_ENABLE: 1259 /* system context */ 1260 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1261 tmp |= bits; 1262 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1263 /* VMs */ 1264 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1265 tmp |= bits; 1266 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1267 break; 1268 default: 1269 break; 1270 } 1271 1272 return 0; 1273 } 1274 1275 static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev, 1276 struct amdgpu_irq_src *source, 1277 struct amdgpu_iv_entry *entry) 1278 { 1279 u32 addr, status, mc_client; 1280 1281 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1282 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1283 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); 1284 /* reset addr and status */ 1285 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1286 1287 if (!addr && !status) 1288 return 0; 1289 1290 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1291 gmc_v7_0_set_fault_enable_default(adev, false); 1292 1293 if (printk_ratelimit()) { 1294 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1295 entry->src_id, entry->src_data[0]); 1296 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1297 addr); 1298 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1299 status); 1300 gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client, 1301 entry->pasid); 1302 } 1303 1304 return 0; 1305 } 1306 1307 static int gmc_v7_0_set_clockgating_state(void *handle, 1308 enum amd_clockgating_state state) 1309 { 1310 bool gate = false; 1311 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1312 1313 if (state == AMD_CG_STATE_GATE) 1314 gate = true; 1315 1316 if (!(adev->flags & AMD_IS_APU)) { 1317 gmc_v7_0_enable_mc_mgcg(adev, gate); 1318 gmc_v7_0_enable_mc_ls(adev, gate); 1319 } 1320 gmc_v7_0_enable_bif_mgls(adev, gate); 1321 gmc_v7_0_enable_hdp_mgcg(adev, gate); 1322 gmc_v7_0_enable_hdp_ls(adev, gate); 1323 1324 return 0; 1325 } 1326 1327 static int gmc_v7_0_set_powergating_state(void *handle, 1328 enum amd_powergating_state state) 1329 { 1330 return 0; 1331 } 1332 1333 static const struct amd_ip_funcs gmc_v7_0_ip_funcs = { 1334 .name = "gmc_v7_0", 1335 .early_init = gmc_v7_0_early_init, 1336 .late_init = gmc_v7_0_late_init, 1337 .sw_init = gmc_v7_0_sw_init, 1338 .sw_fini = gmc_v7_0_sw_fini, 1339 .hw_init = gmc_v7_0_hw_init, 1340 .hw_fini = gmc_v7_0_hw_fini, 1341 .suspend = gmc_v7_0_suspend, 1342 .resume = gmc_v7_0_resume, 1343 .is_idle = gmc_v7_0_is_idle, 1344 .wait_for_idle = gmc_v7_0_wait_for_idle, 1345 .soft_reset = gmc_v7_0_soft_reset, 1346 .set_clockgating_state = gmc_v7_0_set_clockgating_state, 1347 .set_powergating_state = gmc_v7_0_set_powergating_state, 1348 }; 1349 1350 static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = { 1351 .flush_gpu_tlb = gmc_v7_0_flush_gpu_tlb, 1352 .emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb, 1353 .emit_pasid_mapping = gmc_v7_0_emit_pasid_mapping, 1354 .set_pte_pde = gmc_v7_0_set_pte_pde, 1355 .set_prt = gmc_v7_0_set_prt, 1356 .get_vm_pte_flags = gmc_v7_0_get_vm_pte_flags, 1357 .get_vm_pde = gmc_v7_0_get_vm_pde 1358 }; 1359 1360 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = { 1361 .set = gmc_v7_0_vm_fault_interrupt_state, 1362 .process = gmc_v7_0_process_interrupt, 1363 }; 1364 1365 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev) 1366 { 1367 if (adev->gmc.gmc_funcs == NULL) 1368 adev->gmc.gmc_funcs = &gmc_v7_0_gmc_funcs; 1369 } 1370 1371 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev) 1372 { 1373 adev->gmc.vm_fault.num_types = 1; 1374 adev->gmc.vm_fault.funcs = &gmc_v7_0_irq_funcs; 1375 } 1376 1377 const struct amdgpu_ip_block_version gmc_v7_0_ip_block = 1378 { 1379 .type = AMD_IP_BLOCK_TYPE_GMC, 1380 .major = 7, 1381 .minor = 0, 1382 .rev = 0, 1383 .funcs = &gmc_v7_0_ip_funcs, 1384 }; 1385 1386 const struct amdgpu_ip_block_version gmc_v7_4_ip_block = 1387 { 1388 .type = AMD_IP_BLOCK_TYPE_GMC, 1389 .major = 7, 1390 .minor = 4, 1391 .rev = 0, 1392 .funcs = &gmc_v7_0_ip_funcs, 1393 }; 1394