1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/drm_cache.h> 29 #include "amdgpu.h" 30 #include "cikd.h" 31 #include "cik.h" 32 #include "gmc_v7_0.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_amdkfd.h" 35 #include "amdgpu_gem.h" 36 37 #include "bif/bif_4_1_d.h" 38 #include "bif/bif_4_1_sh_mask.h" 39 40 #include "gmc/gmc_7_1_d.h" 41 #include "gmc/gmc_7_1_sh_mask.h" 42 43 #include "oss/oss_2_0_d.h" 44 #include "oss/oss_2_0_sh_mask.h" 45 46 #include "dce/dce_8_0_d.h" 47 #include "dce/dce_8_0_sh_mask.h" 48 49 #include "amdgpu_atombios.h" 50 51 #include "ivsrcid/ivsrcid_vislands30.h" 52 53 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev); 54 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev); 55 static int gmc_v7_0_wait_for_idle(void *handle); 56 57 MODULE_FIRMWARE("amdgpu/bonaire_mc.bin"); 58 MODULE_FIRMWARE("amdgpu/hawaii_mc.bin"); 59 MODULE_FIRMWARE("amdgpu/topaz_mc.bin"); 60 61 static const u32 golden_settings_iceland_a11[] = 62 { 63 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 64 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 65 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 66 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 67 }; 68 69 static const u32 iceland_mgcg_cgcg_init[] = 70 { 71 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 72 }; 73 74 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev) 75 { 76 switch (adev->asic_type) { 77 case CHIP_TOPAZ: 78 amdgpu_device_program_register_sequence(adev, 79 iceland_mgcg_cgcg_init, 80 ARRAY_SIZE(iceland_mgcg_cgcg_init)); 81 amdgpu_device_program_register_sequence(adev, 82 golden_settings_iceland_a11, 83 ARRAY_SIZE(golden_settings_iceland_a11)); 84 break; 85 default: 86 break; 87 } 88 } 89 90 static void gmc_v7_0_mc_stop(struct amdgpu_device *adev) 91 { 92 u32 blackout; 93 94 gmc_v7_0_wait_for_idle((void *)adev); 95 96 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 97 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 98 /* Block CPU access */ 99 WREG32(mmBIF_FB_EN, 0); 100 /* blackout the MC */ 101 blackout = REG_SET_FIELD(blackout, 102 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 103 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); 104 } 105 /* wait for the MC to settle */ 106 udelay(100); 107 } 108 109 static void gmc_v7_0_mc_resume(struct amdgpu_device *adev) 110 { 111 u32 tmp; 112 113 /* unblackout the MC */ 114 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 115 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 116 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 117 /* allow CPU access */ 118 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 119 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 120 WREG32(mmBIF_FB_EN, tmp); 121 } 122 123 /** 124 * gmc_v7_0_init_microcode - load ucode images from disk 125 * 126 * @adev: amdgpu_device pointer 127 * 128 * Use the firmware interface to load the ucode images into 129 * the driver (not loaded into hw). 130 * Returns 0 on success, error on failure. 131 */ 132 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev) 133 { 134 const char *chip_name; 135 char fw_name[30]; 136 int err; 137 138 DRM_DEBUG("\n"); 139 140 switch (adev->asic_type) { 141 case CHIP_BONAIRE: 142 chip_name = "bonaire"; 143 break; 144 case CHIP_HAWAII: 145 chip_name = "hawaii"; 146 break; 147 case CHIP_TOPAZ: 148 chip_name = "topaz"; 149 break; 150 case CHIP_KAVERI: 151 case CHIP_KABINI: 152 case CHIP_MULLINS: 153 return 0; 154 default: BUG(); 155 } 156 157 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name); 158 159 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); 160 if (err) 161 goto out; 162 err = amdgpu_ucode_validate(adev->gmc.fw); 163 164 out: 165 if (err) { 166 pr_err("cik_mc: Failed to load firmware \"%s\"\n", fw_name); 167 release_firmware(adev->gmc.fw); 168 adev->gmc.fw = NULL; 169 } 170 return err; 171 } 172 173 /** 174 * gmc_v7_0_mc_load_microcode - load MC ucode into the hw 175 * 176 * @adev: amdgpu_device pointer 177 * 178 * Load the GDDR MC ucode into the hw (CIK). 179 * Returns 0 on success, error on failure. 180 */ 181 static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev) 182 { 183 const struct mc_firmware_header_v1_0 *hdr; 184 const __le32 *fw_data = NULL; 185 const __le32 *io_mc_regs = NULL; 186 u32 running; 187 int i, ucode_size, regs_size; 188 189 if (!adev->gmc.fw) 190 return -EINVAL; 191 192 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 193 amdgpu_ucode_print_mc_hdr(&hdr->header); 194 195 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 196 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 197 io_mc_regs = (const __le32 *) 198 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 199 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 200 fw_data = (const __le32 *) 201 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 202 203 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); 204 205 if (running == 0) { 206 /* reset the engine and set to writable */ 207 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 208 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 209 210 /* load mc io regs */ 211 for (i = 0; i < regs_size; i++) { 212 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 213 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 214 } 215 /* load the MC ucode */ 216 for (i = 0; i < ucode_size; i++) 217 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 218 219 /* put the engine back into the active state */ 220 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 221 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 222 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 223 224 /* wait for training to complete */ 225 for (i = 0; i < adev->usec_timeout; i++) { 226 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 227 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0)) 228 break; 229 udelay(1); 230 } 231 for (i = 0; i < adev->usec_timeout; i++) { 232 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 233 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1)) 234 break; 235 udelay(1); 236 } 237 } 238 239 return 0; 240 } 241 242 static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev, 243 struct amdgpu_gmc *mc) 244 { 245 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; 246 base <<= 24; 247 248 amdgpu_gmc_vram_location(adev, mc, base); 249 amdgpu_gmc_gart_location(adev, mc); 250 } 251 252 /** 253 * gmc_v7_0_mc_program - program the GPU memory controller 254 * 255 * @adev: amdgpu_device pointer 256 * 257 * Set the location of vram, gart, and AGP in the GPU's 258 * physical address space (CIK). 259 */ 260 static void gmc_v7_0_mc_program(struct amdgpu_device *adev) 261 { 262 u32 tmp; 263 int i, j; 264 265 /* Initialize HDP */ 266 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 267 WREG32((0xb05 + j), 0x00000000); 268 WREG32((0xb06 + j), 0x00000000); 269 WREG32((0xb07 + j), 0x00000000); 270 WREG32((0xb08 + j), 0x00000000); 271 WREG32((0xb09 + j), 0x00000000); 272 } 273 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 274 275 if (gmc_v7_0_wait_for_idle((void *)adev)) { 276 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 277 } 278 if (adev->mode_info.num_crtc) { 279 /* Lockout access through VGA aperture*/ 280 tmp = RREG32(mmVGA_HDP_CONTROL); 281 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 282 WREG32(mmVGA_HDP_CONTROL, tmp); 283 284 /* disable VGA render */ 285 tmp = RREG32(mmVGA_RENDER_CONTROL); 286 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 287 WREG32(mmVGA_RENDER_CONTROL, tmp); 288 } 289 /* Update configuration */ 290 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 291 adev->gmc.vram_start >> 12); 292 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 293 adev->gmc.vram_end >> 12); 294 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 295 adev->vram_scratch.gpu_addr >> 12); 296 WREG32(mmMC_VM_AGP_BASE, 0); 297 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); 298 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); 299 if (gmc_v7_0_wait_for_idle((void *)adev)) { 300 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 301 } 302 303 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 304 305 tmp = RREG32(mmHDP_MISC_CNTL); 306 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); 307 WREG32(mmHDP_MISC_CNTL, tmp); 308 309 tmp = RREG32(mmHDP_HOST_PATH_CNTL); 310 WREG32(mmHDP_HOST_PATH_CNTL, tmp); 311 } 312 313 /** 314 * gmc_v7_0_mc_init - initialize the memory controller driver params 315 * 316 * @adev: amdgpu_device pointer 317 * 318 * Look up the amount of vram, vram width, and decide how to place 319 * vram and gart within the GPU's physical address space (CIK). 320 * Returns 0 for success. 321 */ 322 static int gmc_v7_0_mc_init(struct amdgpu_device *adev) 323 { 324 int r; 325 326 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev); 327 if (!adev->gmc.vram_width) { 328 u32 tmp; 329 int chansize, numchan; 330 331 /* Get VRAM informations */ 332 tmp = RREG32(mmMC_ARB_RAMCFG); 333 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { 334 chansize = 64; 335 } else { 336 chansize = 32; 337 } 338 tmp = RREG32(mmMC_SHARED_CHMAP); 339 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 340 case 0: 341 default: 342 numchan = 1; 343 break; 344 case 1: 345 numchan = 2; 346 break; 347 case 2: 348 numchan = 4; 349 break; 350 case 3: 351 numchan = 8; 352 break; 353 case 4: 354 numchan = 3; 355 break; 356 case 5: 357 numchan = 6; 358 break; 359 case 6: 360 numchan = 10; 361 break; 362 case 7: 363 numchan = 12; 364 break; 365 case 8: 366 numchan = 16; 367 break; 368 } 369 adev->gmc.vram_width = numchan * chansize; 370 } 371 /* size in MB on si */ 372 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 373 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 374 375 if (!(adev->flags & AMD_IS_APU)) { 376 r = amdgpu_device_resize_fb_bar(adev); 377 if (r) 378 return r; 379 } 380 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 381 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 382 383 #ifdef CONFIG_X86_64 384 if (adev->flags & AMD_IS_APU) { 385 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; 386 adev->gmc.aper_size = adev->gmc.real_vram_size; 387 } 388 #endif 389 390 /* In case the PCI BAR is larger than the actual amount of vram */ 391 adev->gmc.visible_vram_size = adev->gmc.aper_size; 392 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 393 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 394 395 /* set the gart size */ 396 if (amdgpu_gart_size == -1) { 397 switch (adev->asic_type) { 398 case CHIP_TOPAZ: /* no MM engines */ 399 default: 400 adev->gmc.gart_size = 256ULL << 20; 401 break; 402 #ifdef CONFIG_DRM_AMDGPU_CIK 403 case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */ 404 case CHIP_HAWAII: /* UVD, VCE do not support GPUVM */ 405 case CHIP_KAVERI: /* UVD, VCE do not support GPUVM */ 406 case CHIP_KABINI: /* UVD, VCE do not support GPUVM */ 407 case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */ 408 adev->gmc.gart_size = 1024ULL << 20; 409 break; 410 #endif 411 } 412 } else { 413 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 414 } 415 416 gmc_v7_0_vram_gtt_location(adev, &adev->gmc); 417 418 return 0; 419 } 420 421 /* 422 * GART 423 * VMID 0 is the physical GPU addresses as used by the kernel. 424 * VMIDs 1-15 are used for userspace clients and are handled 425 * by the amdgpu vm/hsa code. 426 */ 427 428 /** 429 * gmc_v7_0_flush_gpu_tlb - gart tlb flush callback 430 * 431 * @adev: amdgpu_device pointer 432 * @vmid: vm instance to flush 433 * 434 * Flush the TLB for the requested page table (CIK). 435 */ 436 static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 437 uint32_t vmhub, uint32_t flush_type) 438 { 439 /* bits 0-15 are the VM contexts0-15 */ 440 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 441 } 442 443 static uint64_t gmc_v7_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 444 unsigned vmid, uint64_t pd_addr) 445 { 446 uint32_t reg; 447 448 if (vmid < 8) 449 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; 450 else 451 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8; 452 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); 453 454 /* bits 0-15 are the VM contexts0-15 */ 455 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); 456 457 return pd_addr; 458 } 459 460 static void gmc_v7_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 461 unsigned pasid) 462 { 463 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); 464 } 465 466 static void gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, int level, 467 uint64_t *addr, uint64_t *flags) 468 { 469 BUG_ON(*addr & 0xFFFFFF0000000FFFULL); 470 } 471 472 static void gmc_v7_0_get_vm_pte(struct amdgpu_device *adev, 473 struct amdgpu_bo_va_mapping *mapping, 474 uint64_t *flags) 475 { 476 *flags &= ~AMDGPU_PTE_EXECUTABLE; 477 *flags &= ~AMDGPU_PTE_PRT; 478 } 479 480 /** 481 * gmc_v8_0_set_fault_enable_default - update VM fault handling 482 * 483 * @adev: amdgpu_device pointer 484 * @value: true redirects VM faults to the default page 485 */ 486 static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev, 487 bool value) 488 { 489 u32 tmp; 490 491 tmp = RREG32(mmVM_CONTEXT1_CNTL); 492 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 493 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 494 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 495 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 496 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 497 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 498 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 499 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 500 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 501 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 502 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 503 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 504 WREG32(mmVM_CONTEXT1_CNTL, tmp); 505 } 506 507 /** 508 * gmc_v7_0_set_prt - set PRT VM fault 509 * 510 * @adev: amdgpu_device pointer 511 * @enable: enable/disable VM fault handling for PRT 512 */ 513 static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable) 514 { 515 uint32_t tmp; 516 517 if (enable && !adev->gmc.prt_warning) { 518 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 519 adev->gmc.prt_warning = true; 520 } 521 522 tmp = RREG32(mmVM_PRT_CNTL); 523 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 524 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 525 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 526 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 527 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 528 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 529 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 530 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 531 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 532 L2_CACHE_STORE_INVALID_ENTRIES, enable); 533 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 534 L1_TLB_STORE_INVALID_ENTRIES, enable); 535 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 536 MASK_PDE0_FAULT, enable); 537 WREG32(mmVM_PRT_CNTL, tmp); 538 539 if (enable) { 540 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; 541 uint32_t high = adev->vm_manager.max_pfn - 542 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT); 543 544 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); 545 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); 546 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); 547 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); 548 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); 549 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); 550 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); 551 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); 552 } else { 553 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); 554 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); 555 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); 556 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); 557 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); 558 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); 559 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); 560 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); 561 } 562 } 563 564 /** 565 * gmc_v7_0_gart_enable - gart enable 566 * 567 * @adev: amdgpu_device pointer 568 * 569 * This sets up the TLBs, programs the page tables for VMID0, 570 * sets up the hw for VMIDs 1-15 which are allocated on 571 * demand, and sets up the global locations for the LDS, GDS, 572 * and GPUVM for FSA64 clients (CIK). 573 * Returns 0 for success, errors for failure. 574 */ 575 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev) 576 { 577 uint64_t table_addr; 578 int r, i; 579 u32 tmp, field; 580 581 if (adev->gart.bo == NULL) { 582 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 583 return -EINVAL; 584 } 585 r = amdgpu_gart_table_vram_pin(adev); 586 if (r) 587 return r; 588 589 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 590 591 /* Setup TLB control */ 592 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 593 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 594 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); 595 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 596 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); 597 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 598 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 599 /* Setup L2 cache */ 600 tmp = RREG32(mmVM_L2_CNTL); 601 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 602 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 603 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); 604 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); 605 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); 606 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 607 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 608 WREG32(mmVM_L2_CNTL, tmp); 609 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 610 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 611 WREG32(mmVM_L2_CNTL2, tmp); 612 613 field = adev->vm_manager.fragment_size; 614 tmp = RREG32(mmVM_L2_CNTL3); 615 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); 616 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); 617 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); 618 WREG32(mmVM_L2_CNTL3, tmp); 619 /* setup context0 */ 620 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); 621 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); 622 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12); 623 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 624 (u32)(adev->dummy_page_addr >> 12)); 625 WREG32(mmVM_CONTEXT0_CNTL2, 0); 626 tmp = RREG32(mmVM_CONTEXT0_CNTL); 627 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 628 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 629 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 630 WREG32(mmVM_CONTEXT0_CNTL, tmp); 631 632 WREG32(0x575, 0); 633 WREG32(0x576, 0); 634 WREG32(0x577, 0); 635 636 /* empty context1-15 */ 637 /* FIXME start with 4G, once using 2 level pt switch to full 638 * vm size space 639 */ 640 /* set vm size, must be a multiple of 4 */ 641 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 642 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 643 for (i = 1; i < 16; i++) { 644 if (i < 8) 645 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 646 table_addr >> 12); 647 else 648 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 649 table_addr >> 12); 650 } 651 652 /* enable context1-15 */ 653 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 654 (u32)(adev->dummy_page_addr >> 12)); 655 WREG32(mmVM_CONTEXT1_CNTL2, 4); 656 tmp = RREG32(mmVM_CONTEXT1_CNTL); 657 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 658 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); 659 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, 660 adev->vm_manager.block_size - 9); 661 WREG32(mmVM_CONTEXT1_CNTL, tmp); 662 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 663 gmc_v7_0_set_fault_enable_default(adev, false); 664 else 665 gmc_v7_0_set_fault_enable_default(adev, true); 666 667 if (adev->asic_type == CHIP_KAVERI) { 668 tmp = RREG32(mmCHUB_CONTROL); 669 tmp &= ~BYPASS_VM; 670 WREG32(mmCHUB_CONTROL, tmp); 671 } 672 673 gmc_v7_0_flush_gpu_tlb(adev, 0, 0, 0); 674 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 675 (unsigned)(adev->gmc.gart_size >> 20), 676 (unsigned long long)table_addr); 677 adev->gart.ready = true; 678 return 0; 679 } 680 681 static int gmc_v7_0_gart_init(struct amdgpu_device *adev) 682 { 683 int r; 684 685 if (adev->gart.bo) { 686 WARN(1, "R600 PCIE GART already initialized\n"); 687 return 0; 688 } 689 /* Initialize common gart structure */ 690 r = amdgpu_gart_init(adev); 691 if (r) 692 return r; 693 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 694 adev->gart.gart_pte_flags = 0; 695 return amdgpu_gart_table_vram_alloc(adev); 696 } 697 698 /** 699 * gmc_v7_0_gart_disable - gart disable 700 * 701 * @adev: amdgpu_device pointer 702 * 703 * This disables all VM page table (CIK). 704 */ 705 static void gmc_v7_0_gart_disable(struct amdgpu_device *adev) 706 { 707 u32 tmp; 708 709 /* Disable all tables */ 710 WREG32(mmVM_CONTEXT0_CNTL, 0); 711 WREG32(mmVM_CONTEXT1_CNTL, 0); 712 /* Setup TLB control */ 713 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 714 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 715 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); 716 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); 717 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 718 /* Setup L2 cache */ 719 tmp = RREG32(mmVM_L2_CNTL); 720 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 721 WREG32(mmVM_L2_CNTL, tmp); 722 WREG32(mmVM_L2_CNTL2, 0); 723 amdgpu_gart_table_vram_unpin(adev); 724 } 725 726 /** 727 * gmc_v7_0_vm_decode_fault - print human readable fault info 728 * 729 * @adev: amdgpu_device pointer 730 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value 731 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value 732 * 733 * Print human readable fault information (CIK). 734 */ 735 static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev, u32 status, 736 u32 addr, u32 mc_client, unsigned pasid) 737 { 738 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 739 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 740 PROTECTIONS); 741 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 742 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 743 u32 mc_id; 744 745 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 746 MEMORY_CLIENT_ID); 747 748 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 749 protections, vmid, pasid, addr, 750 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 751 MEMORY_CLIENT_RW) ? 752 "write" : "read", block, mc_client, mc_id); 753 } 754 755 756 static const u32 mc_cg_registers[] = { 757 mmMC_HUB_MISC_HUB_CG, 758 mmMC_HUB_MISC_SIP_CG, 759 mmMC_HUB_MISC_VM_CG, 760 mmMC_XPB_CLK_GAT, 761 mmATC_MISC_CG, 762 mmMC_CITF_MISC_WR_CG, 763 mmMC_CITF_MISC_RD_CG, 764 mmMC_CITF_MISC_VM_CG, 765 mmVM_L2_CG, 766 }; 767 768 static const u32 mc_cg_ls_en[] = { 769 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK, 770 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK, 771 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK, 772 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK, 773 ATC_MISC_CG__MEM_LS_ENABLE_MASK, 774 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK, 775 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK, 776 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK, 777 VM_L2_CG__MEM_LS_ENABLE_MASK, 778 }; 779 780 static const u32 mc_cg_en[] = { 781 MC_HUB_MISC_HUB_CG__ENABLE_MASK, 782 MC_HUB_MISC_SIP_CG__ENABLE_MASK, 783 MC_HUB_MISC_VM_CG__ENABLE_MASK, 784 MC_XPB_CLK_GAT__ENABLE_MASK, 785 ATC_MISC_CG__ENABLE_MASK, 786 MC_CITF_MISC_WR_CG__ENABLE_MASK, 787 MC_CITF_MISC_RD_CG__ENABLE_MASK, 788 MC_CITF_MISC_VM_CG__ENABLE_MASK, 789 VM_L2_CG__ENABLE_MASK, 790 }; 791 792 static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev, 793 bool enable) 794 { 795 int i; 796 u32 orig, data; 797 798 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 799 orig = data = RREG32(mc_cg_registers[i]); 800 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) 801 data |= mc_cg_ls_en[i]; 802 else 803 data &= ~mc_cg_ls_en[i]; 804 if (data != orig) 805 WREG32(mc_cg_registers[i], data); 806 } 807 } 808 809 static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev, 810 bool enable) 811 { 812 int i; 813 u32 orig, data; 814 815 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 816 orig = data = RREG32(mc_cg_registers[i]); 817 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) 818 data |= mc_cg_en[i]; 819 else 820 data &= ~mc_cg_en[i]; 821 if (data != orig) 822 WREG32(mc_cg_registers[i], data); 823 } 824 } 825 826 static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev, 827 bool enable) 828 { 829 u32 orig, data; 830 831 orig = data = RREG32_PCIE(ixPCIE_CNTL2); 832 833 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 834 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1); 835 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1); 836 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1); 837 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1); 838 } else { 839 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0); 840 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0); 841 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0); 842 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0); 843 } 844 845 if (orig != data) 846 WREG32_PCIE(ixPCIE_CNTL2, data); 847 } 848 849 static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev, 850 bool enable) 851 { 852 u32 orig, data; 853 854 orig = data = RREG32(mmHDP_HOST_PATH_CNTL); 855 856 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 857 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0); 858 else 859 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1); 860 861 if (orig != data) 862 WREG32(mmHDP_HOST_PATH_CNTL, data); 863 } 864 865 static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev, 866 bool enable) 867 { 868 u32 orig, data; 869 870 orig = data = RREG32(mmHDP_MEM_POWER_LS); 871 872 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 873 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1); 874 else 875 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0); 876 877 if (orig != data) 878 WREG32(mmHDP_MEM_POWER_LS, data); 879 } 880 881 static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type) 882 { 883 switch (mc_seq_vram_type) { 884 case MC_SEQ_MISC0__MT__GDDR1: 885 return AMDGPU_VRAM_TYPE_GDDR1; 886 case MC_SEQ_MISC0__MT__DDR2: 887 return AMDGPU_VRAM_TYPE_DDR2; 888 case MC_SEQ_MISC0__MT__GDDR3: 889 return AMDGPU_VRAM_TYPE_GDDR3; 890 case MC_SEQ_MISC0__MT__GDDR4: 891 return AMDGPU_VRAM_TYPE_GDDR4; 892 case MC_SEQ_MISC0__MT__GDDR5: 893 return AMDGPU_VRAM_TYPE_GDDR5; 894 case MC_SEQ_MISC0__MT__HBM: 895 return AMDGPU_VRAM_TYPE_HBM; 896 case MC_SEQ_MISC0__MT__DDR3: 897 return AMDGPU_VRAM_TYPE_DDR3; 898 default: 899 return AMDGPU_VRAM_TYPE_UNKNOWN; 900 } 901 } 902 903 static int gmc_v7_0_early_init(void *handle) 904 { 905 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 906 907 gmc_v7_0_set_gmc_funcs(adev); 908 gmc_v7_0_set_irq_funcs(adev); 909 910 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 911 adev->gmc.shared_aperture_end = 912 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 913 adev->gmc.private_aperture_start = 914 adev->gmc.shared_aperture_end + 1; 915 adev->gmc.private_aperture_end = 916 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 917 918 return 0; 919 } 920 921 static int gmc_v7_0_late_init(void *handle) 922 { 923 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 924 925 amdgpu_bo_late_init(adev); 926 927 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 928 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 929 else 930 return 0; 931 } 932 933 static unsigned gmc_v7_0_get_vbios_fb_size(struct amdgpu_device *adev) 934 { 935 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); 936 unsigned size; 937 938 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 939 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */ 940 } else { 941 u32 viewport = RREG32(mmVIEWPORT_SIZE); 942 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 943 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * 944 4); 945 } 946 /* return 0 if the pre-OS buffer uses up most of vram */ 947 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 948 return 0; 949 return size; 950 } 951 952 static int gmc_v7_0_sw_init(void *handle) 953 { 954 int r; 955 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 956 957 adev->num_vmhubs = 1; 958 959 if (adev->flags & AMD_IS_APU) { 960 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 961 } else { 962 u32 tmp = RREG32(mmMC_SEQ_MISC0); 963 tmp &= MC_SEQ_MISC0__MT__MASK; 964 adev->gmc.vram_type = gmc_v7_0_convert_vram_type(tmp); 965 } 966 967 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault); 968 if (r) 969 return r; 970 971 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault); 972 if (r) 973 return r; 974 975 /* Adjust VM size here. 976 * Currently set to 4GB ((1 << 20) 4k pages). 977 * Max GPUVM size for cayman and SI is 40 bits. 978 */ 979 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); 980 981 /* Set the internal MC address mask 982 * This is the max address of the GPU's 983 * internal address space. 984 */ 985 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 986 987 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40)); 988 if (r) { 989 pr_warn("amdgpu: No suitable DMA available\n"); 990 return r; 991 } 992 adev->need_swiotlb = drm_need_swiotlb(40); 993 994 r = gmc_v7_0_init_microcode(adev); 995 if (r) { 996 DRM_ERROR("Failed to load mc firmware!\n"); 997 return r; 998 } 999 1000 r = gmc_v7_0_mc_init(adev); 1001 if (r) 1002 return r; 1003 1004 adev->gmc.stolen_size = gmc_v7_0_get_vbios_fb_size(adev); 1005 1006 /* Memory manager */ 1007 r = amdgpu_bo_init(adev); 1008 if (r) 1009 return r; 1010 1011 r = gmc_v7_0_gart_init(adev); 1012 if (r) 1013 return r; 1014 1015 /* 1016 * number of VMs 1017 * VMID 0 is reserved for System 1018 * amdgpu graphics/compute will use VMIDs 1-7 1019 * amdkfd will use VMIDs 8-15 1020 */ 1021 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; 1022 amdgpu_vm_manager_init(adev); 1023 1024 /* base offset of vram pages */ 1025 if (adev->flags & AMD_IS_APU) { 1026 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 1027 1028 tmp <<= 22; 1029 adev->vm_manager.vram_base_offset = tmp; 1030 } else { 1031 adev->vm_manager.vram_base_offset = 0; 1032 } 1033 1034 adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info), 1035 GFP_KERNEL); 1036 if (!adev->gmc.vm_fault_info) 1037 return -ENOMEM; 1038 atomic_set(&adev->gmc.vm_fault_info_updated, 0); 1039 1040 return 0; 1041 } 1042 1043 static int gmc_v7_0_sw_fini(void *handle) 1044 { 1045 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1046 1047 amdgpu_gem_force_release(adev); 1048 amdgpu_vm_manager_fini(adev); 1049 kfree(adev->gmc.vm_fault_info); 1050 amdgpu_gart_table_vram_free(adev); 1051 amdgpu_bo_fini(adev); 1052 amdgpu_gart_fini(adev); 1053 release_firmware(adev->gmc.fw); 1054 adev->gmc.fw = NULL; 1055 1056 return 0; 1057 } 1058 1059 static int gmc_v7_0_hw_init(void *handle) 1060 { 1061 int r; 1062 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1063 1064 gmc_v7_0_init_golden_registers(adev); 1065 1066 gmc_v7_0_mc_program(adev); 1067 1068 if (!(adev->flags & AMD_IS_APU)) { 1069 r = gmc_v7_0_mc_load_microcode(adev); 1070 if (r) { 1071 DRM_ERROR("Failed to load MC firmware!\n"); 1072 return r; 1073 } 1074 } 1075 1076 r = gmc_v7_0_gart_enable(adev); 1077 if (r) 1078 return r; 1079 1080 return r; 1081 } 1082 1083 static int gmc_v7_0_hw_fini(void *handle) 1084 { 1085 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1086 1087 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1088 gmc_v7_0_gart_disable(adev); 1089 1090 return 0; 1091 } 1092 1093 static int gmc_v7_0_suspend(void *handle) 1094 { 1095 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1096 1097 gmc_v7_0_hw_fini(adev); 1098 1099 return 0; 1100 } 1101 1102 static int gmc_v7_0_resume(void *handle) 1103 { 1104 int r; 1105 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1106 1107 r = gmc_v7_0_hw_init(adev); 1108 if (r) 1109 return r; 1110 1111 amdgpu_vmid_reset_all(adev); 1112 1113 return 0; 1114 } 1115 1116 static bool gmc_v7_0_is_idle(void *handle) 1117 { 1118 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1119 u32 tmp = RREG32(mmSRBM_STATUS); 1120 1121 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1122 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 1123 return false; 1124 1125 return true; 1126 } 1127 1128 static int gmc_v7_0_wait_for_idle(void *handle) 1129 { 1130 unsigned i; 1131 u32 tmp; 1132 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1133 1134 for (i = 0; i < adev->usec_timeout; i++) { 1135 /* read MC_STATUS */ 1136 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | 1137 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1138 SRBM_STATUS__MCC_BUSY_MASK | 1139 SRBM_STATUS__MCD_BUSY_MASK | 1140 SRBM_STATUS__VMC_BUSY_MASK); 1141 if (!tmp) 1142 return 0; 1143 udelay(1); 1144 } 1145 return -ETIMEDOUT; 1146 1147 } 1148 1149 static int gmc_v7_0_soft_reset(void *handle) 1150 { 1151 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1152 u32 srbm_soft_reset = 0; 1153 u32 tmp = RREG32(mmSRBM_STATUS); 1154 1155 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1156 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1157 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 1158 1159 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1160 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 1161 if (!(adev->flags & AMD_IS_APU)) 1162 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1163 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1164 } 1165 1166 if (srbm_soft_reset) { 1167 gmc_v7_0_mc_stop(adev); 1168 if (gmc_v7_0_wait_for_idle((void *)adev)) { 1169 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1170 } 1171 1172 1173 tmp = RREG32(mmSRBM_SOFT_RESET); 1174 tmp |= srbm_soft_reset; 1175 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1176 WREG32(mmSRBM_SOFT_RESET, tmp); 1177 tmp = RREG32(mmSRBM_SOFT_RESET); 1178 1179 udelay(50); 1180 1181 tmp &= ~srbm_soft_reset; 1182 WREG32(mmSRBM_SOFT_RESET, tmp); 1183 tmp = RREG32(mmSRBM_SOFT_RESET); 1184 1185 /* Wait a little for things to settle down */ 1186 udelay(50); 1187 1188 gmc_v7_0_mc_resume(adev); 1189 udelay(50); 1190 } 1191 1192 return 0; 1193 } 1194 1195 static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1196 struct amdgpu_irq_src *src, 1197 unsigned type, 1198 enum amdgpu_interrupt_state state) 1199 { 1200 u32 tmp; 1201 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1202 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1203 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1204 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1205 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1206 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1207 1208 switch (state) { 1209 case AMDGPU_IRQ_STATE_DISABLE: 1210 /* system context */ 1211 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1212 tmp &= ~bits; 1213 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1214 /* VMs */ 1215 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1216 tmp &= ~bits; 1217 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1218 break; 1219 case AMDGPU_IRQ_STATE_ENABLE: 1220 /* system context */ 1221 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1222 tmp |= bits; 1223 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1224 /* VMs */ 1225 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1226 tmp |= bits; 1227 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1228 break; 1229 default: 1230 break; 1231 } 1232 1233 return 0; 1234 } 1235 1236 static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev, 1237 struct amdgpu_irq_src *source, 1238 struct amdgpu_iv_entry *entry) 1239 { 1240 u32 addr, status, mc_client, vmid; 1241 1242 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1243 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1244 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); 1245 /* reset addr and status */ 1246 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1247 1248 if (!addr && !status) 1249 return 0; 1250 1251 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1252 gmc_v7_0_set_fault_enable_default(adev, false); 1253 1254 if (printk_ratelimit()) { 1255 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1256 entry->src_id, entry->src_data[0]); 1257 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1258 addr); 1259 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1260 status); 1261 gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client, 1262 entry->pasid); 1263 } 1264 1265 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1266 VMID); 1267 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid) 1268 && !atomic_read(&adev->gmc.vm_fault_info_updated)) { 1269 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info; 1270 u32 protections = REG_GET_FIELD(status, 1271 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1272 PROTECTIONS); 1273 1274 info->vmid = vmid; 1275 info->mc_id = REG_GET_FIELD(status, 1276 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1277 MEMORY_CLIENT_ID); 1278 info->status = status; 1279 info->page_addr = addr; 1280 info->prot_valid = protections & 0x7 ? true : false; 1281 info->prot_read = protections & 0x8 ? true : false; 1282 info->prot_write = protections & 0x10 ? true : false; 1283 info->prot_exec = protections & 0x20 ? true : false; 1284 mb(); 1285 atomic_set(&adev->gmc.vm_fault_info_updated, 1); 1286 } 1287 1288 return 0; 1289 } 1290 1291 static int gmc_v7_0_set_clockgating_state(void *handle, 1292 enum amd_clockgating_state state) 1293 { 1294 bool gate = false; 1295 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1296 1297 if (state == AMD_CG_STATE_GATE) 1298 gate = true; 1299 1300 if (!(adev->flags & AMD_IS_APU)) { 1301 gmc_v7_0_enable_mc_mgcg(adev, gate); 1302 gmc_v7_0_enable_mc_ls(adev, gate); 1303 } 1304 gmc_v7_0_enable_bif_mgls(adev, gate); 1305 gmc_v7_0_enable_hdp_mgcg(adev, gate); 1306 gmc_v7_0_enable_hdp_ls(adev, gate); 1307 1308 return 0; 1309 } 1310 1311 static int gmc_v7_0_set_powergating_state(void *handle, 1312 enum amd_powergating_state state) 1313 { 1314 return 0; 1315 } 1316 1317 static const struct amd_ip_funcs gmc_v7_0_ip_funcs = { 1318 .name = "gmc_v7_0", 1319 .early_init = gmc_v7_0_early_init, 1320 .late_init = gmc_v7_0_late_init, 1321 .sw_init = gmc_v7_0_sw_init, 1322 .sw_fini = gmc_v7_0_sw_fini, 1323 .hw_init = gmc_v7_0_hw_init, 1324 .hw_fini = gmc_v7_0_hw_fini, 1325 .suspend = gmc_v7_0_suspend, 1326 .resume = gmc_v7_0_resume, 1327 .is_idle = gmc_v7_0_is_idle, 1328 .wait_for_idle = gmc_v7_0_wait_for_idle, 1329 .soft_reset = gmc_v7_0_soft_reset, 1330 .set_clockgating_state = gmc_v7_0_set_clockgating_state, 1331 .set_powergating_state = gmc_v7_0_set_powergating_state, 1332 }; 1333 1334 static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = { 1335 .flush_gpu_tlb = gmc_v7_0_flush_gpu_tlb, 1336 .emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb, 1337 .emit_pasid_mapping = gmc_v7_0_emit_pasid_mapping, 1338 .set_prt = gmc_v7_0_set_prt, 1339 .get_vm_pde = gmc_v7_0_get_vm_pde, 1340 .get_vm_pte = gmc_v7_0_get_vm_pte 1341 }; 1342 1343 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = { 1344 .set = gmc_v7_0_vm_fault_interrupt_state, 1345 .process = gmc_v7_0_process_interrupt, 1346 }; 1347 1348 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev) 1349 { 1350 adev->gmc.gmc_funcs = &gmc_v7_0_gmc_funcs; 1351 } 1352 1353 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev) 1354 { 1355 adev->gmc.vm_fault.num_types = 1; 1356 adev->gmc.vm_fault.funcs = &gmc_v7_0_irq_funcs; 1357 } 1358 1359 const struct amdgpu_ip_block_version gmc_v7_0_ip_block = 1360 { 1361 .type = AMD_IP_BLOCK_TYPE_GMC, 1362 .major = 7, 1363 .minor = 0, 1364 .rev = 0, 1365 .funcs = &gmc_v7_0_ip_funcs, 1366 }; 1367 1368 const struct amdgpu_ip_block_version gmc_v7_4_ip_block = 1369 { 1370 .type = AMD_IP_BLOCK_TYPE_GMC, 1371 .major = 7, 1372 .minor = 4, 1373 .rev = 0, 1374 .funcs = &gmc_v7_0_ip_funcs, 1375 }; 1376