1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/drm_cache.h> 29 #include "amdgpu.h" 30 #include "cikd.h" 31 #include "cik.h" 32 #include "gmc_v7_0.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_amdkfd.h" 35 #include "amdgpu_gem.h" 36 37 #include "bif/bif_4_1_d.h" 38 #include "bif/bif_4_1_sh_mask.h" 39 40 #include "gmc/gmc_7_1_d.h" 41 #include "gmc/gmc_7_1_sh_mask.h" 42 43 #include "oss/oss_2_0_d.h" 44 #include "oss/oss_2_0_sh_mask.h" 45 46 #include "dce/dce_8_0_d.h" 47 #include "dce/dce_8_0_sh_mask.h" 48 49 #include "amdgpu_atombios.h" 50 51 #include "ivsrcid/ivsrcid_vislands30.h" 52 53 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev); 54 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev); 55 static int gmc_v7_0_wait_for_idle(void *handle); 56 57 MODULE_FIRMWARE("amdgpu/bonaire_mc.bin"); 58 MODULE_FIRMWARE("amdgpu/hawaii_mc.bin"); 59 MODULE_FIRMWARE("amdgpu/topaz_mc.bin"); 60 61 static const u32 golden_settings_iceland_a11[] = 62 { 63 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 64 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 65 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 66 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 67 }; 68 69 static const u32 iceland_mgcg_cgcg_init[] = 70 { 71 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 72 }; 73 74 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev) 75 { 76 switch (adev->asic_type) { 77 case CHIP_TOPAZ: 78 amdgpu_device_program_register_sequence(adev, 79 iceland_mgcg_cgcg_init, 80 ARRAY_SIZE(iceland_mgcg_cgcg_init)); 81 amdgpu_device_program_register_sequence(adev, 82 golden_settings_iceland_a11, 83 ARRAY_SIZE(golden_settings_iceland_a11)); 84 break; 85 default: 86 break; 87 } 88 } 89 90 static void gmc_v7_0_mc_stop(struct amdgpu_device *adev) 91 { 92 u32 blackout; 93 94 gmc_v7_0_wait_for_idle((void *)adev); 95 96 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 97 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 98 /* Block CPU access */ 99 WREG32(mmBIF_FB_EN, 0); 100 /* blackout the MC */ 101 blackout = REG_SET_FIELD(blackout, 102 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 103 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); 104 } 105 /* wait for the MC to settle */ 106 udelay(100); 107 } 108 109 static void gmc_v7_0_mc_resume(struct amdgpu_device *adev) 110 { 111 u32 tmp; 112 113 /* unblackout the MC */ 114 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 115 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 116 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 117 /* allow CPU access */ 118 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 119 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 120 WREG32(mmBIF_FB_EN, tmp); 121 } 122 123 /** 124 * gmc_v7_0_init_microcode - load ucode images from disk 125 * 126 * @adev: amdgpu_device pointer 127 * 128 * Use the firmware interface to load the ucode images into 129 * the driver (not loaded into hw). 130 * Returns 0 on success, error on failure. 131 */ 132 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev) 133 { 134 const char *chip_name; 135 char fw_name[30]; 136 int err; 137 138 DRM_DEBUG("\n"); 139 140 switch (adev->asic_type) { 141 case CHIP_BONAIRE: 142 chip_name = "bonaire"; 143 break; 144 case CHIP_HAWAII: 145 chip_name = "hawaii"; 146 break; 147 case CHIP_TOPAZ: 148 chip_name = "topaz"; 149 break; 150 case CHIP_KAVERI: 151 case CHIP_KABINI: 152 case CHIP_MULLINS: 153 return 0; 154 default: BUG(); 155 } 156 157 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name); 158 159 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); 160 if (err) 161 goto out; 162 err = amdgpu_ucode_validate(adev->gmc.fw); 163 164 out: 165 if (err) { 166 pr_err("cik_mc: Failed to load firmware \"%s\"\n", fw_name); 167 release_firmware(adev->gmc.fw); 168 adev->gmc.fw = NULL; 169 } 170 return err; 171 } 172 173 /** 174 * gmc_v7_0_mc_load_microcode - load MC ucode into the hw 175 * 176 * @adev: amdgpu_device pointer 177 * 178 * Load the GDDR MC ucode into the hw (CIK). 179 * Returns 0 on success, error on failure. 180 */ 181 static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev) 182 { 183 const struct mc_firmware_header_v1_0 *hdr; 184 const __le32 *fw_data = NULL; 185 const __le32 *io_mc_regs = NULL; 186 u32 running; 187 int i, ucode_size, regs_size; 188 189 if (!adev->gmc.fw) 190 return -EINVAL; 191 192 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 193 amdgpu_ucode_print_mc_hdr(&hdr->header); 194 195 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 196 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 197 io_mc_regs = (const __le32 *) 198 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 199 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 200 fw_data = (const __le32 *) 201 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 202 203 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); 204 205 if (running == 0) { 206 /* reset the engine and set to writable */ 207 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 208 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 209 210 /* load mc io regs */ 211 for (i = 0; i < regs_size; i++) { 212 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 213 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 214 } 215 /* load the MC ucode */ 216 for (i = 0; i < ucode_size; i++) 217 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 218 219 /* put the engine back into the active state */ 220 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 221 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 222 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 223 224 /* wait for training to complete */ 225 for (i = 0; i < adev->usec_timeout; i++) { 226 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 227 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0)) 228 break; 229 udelay(1); 230 } 231 for (i = 0; i < adev->usec_timeout; i++) { 232 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 233 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1)) 234 break; 235 udelay(1); 236 } 237 } 238 239 return 0; 240 } 241 242 static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev, 243 struct amdgpu_gmc *mc) 244 { 245 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; 246 base <<= 24; 247 248 amdgpu_gmc_vram_location(adev, mc, base); 249 amdgpu_gmc_gart_location(adev, mc); 250 } 251 252 /** 253 * gmc_v7_0_mc_program - program the GPU memory controller 254 * 255 * @adev: amdgpu_device pointer 256 * 257 * Set the location of vram, gart, and AGP in the GPU's 258 * physical address space (CIK). 259 */ 260 static void gmc_v7_0_mc_program(struct amdgpu_device *adev) 261 { 262 u32 tmp; 263 int i, j; 264 265 /* Initialize HDP */ 266 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 267 WREG32((0xb05 + j), 0x00000000); 268 WREG32((0xb06 + j), 0x00000000); 269 WREG32((0xb07 + j), 0x00000000); 270 WREG32((0xb08 + j), 0x00000000); 271 WREG32((0xb09 + j), 0x00000000); 272 } 273 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 274 275 if (gmc_v7_0_wait_for_idle((void *)adev)) { 276 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 277 } 278 if (adev->mode_info.num_crtc) { 279 /* Lockout access through VGA aperture*/ 280 tmp = RREG32(mmVGA_HDP_CONTROL); 281 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 282 WREG32(mmVGA_HDP_CONTROL, tmp); 283 284 /* disable VGA render */ 285 tmp = RREG32(mmVGA_RENDER_CONTROL); 286 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 287 WREG32(mmVGA_RENDER_CONTROL, tmp); 288 } 289 /* Update configuration */ 290 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 291 adev->gmc.vram_start >> 12); 292 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 293 adev->gmc.vram_end >> 12); 294 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 295 adev->vram_scratch.gpu_addr >> 12); 296 WREG32(mmMC_VM_AGP_BASE, 0); 297 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); 298 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); 299 if (gmc_v7_0_wait_for_idle((void *)adev)) { 300 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 301 } 302 303 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 304 305 tmp = RREG32(mmHDP_MISC_CNTL); 306 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); 307 WREG32(mmHDP_MISC_CNTL, tmp); 308 309 tmp = RREG32(mmHDP_HOST_PATH_CNTL); 310 WREG32(mmHDP_HOST_PATH_CNTL, tmp); 311 } 312 313 /** 314 * gmc_v7_0_mc_init - initialize the memory controller driver params 315 * 316 * @adev: amdgpu_device pointer 317 * 318 * Look up the amount of vram, vram width, and decide how to place 319 * vram and gart within the GPU's physical address space (CIK). 320 * Returns 0 for success. 321 */ 322 static int gmc_v7_0_mc_init(struct amdgpu_device *adev) 323 { 324 int r; 325 326 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev); 327 if (!adev->gmc.vram_width) { 328 u32 tmp; 329 int chansize, numchan; 330 331 /* Get VRAM informations */ 332 tmp = RREG32(mmMC_ARB_RAMCFG); 333 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { 334 chansize = 64; 335 } else { 336 chansize = 32; 337 } 338 tmp = RREG32(mmMC_SHARED_CHMAP); 339 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 340 case 0: 341 default: 342 numchan = 1; 343 break; 344 case 1: 345 numchan = 2; 346 break; 347 case 2: 348 numchan = 4; 349 break; 350 case 3: 351 numchan = 8; 352 break; 353 case 4: 354 numchan = 3; 355 break; 356 case 5: 357 numchan = 6; 358 break; 359 case 6: 360 numchan = 10; 361 break; 362 case 7: 363 numchan = 12; 364 break; 365 case 8: 366 numchan = 16; 367 break; 368 } 369 adev->gmc.vram_width = numchan * chansize; 370 } 371 /* size in MB on si */ 372 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 373 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 374 375 if (!(adev->flags & AMD_IS_APU)) { 376 r = amdgpu_device_resize_fb_bar(adev); 377 if (r) 378 return r; 379 } 380 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 381 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 382 383 #ifdef CONFIG_X86_64 384 if (adev->flags & AMD_IS_APU && 385 adev->gmc.real_vram_size > adev->gmc.aper_size) { 386 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; 387 adev->gmc.aper_size = adev->gmc.real_vram_size; 388 } 389 #endif 390 391 /* In case the PCI BAR is larger than the actual amount of vram */ 392 adev->gmc.visible_vram_size = adev->gmc.aper_size; 393 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 394 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 395 396 /* set the gart size */ 397 if (amdgpu_gart_size == -1) { 398 switch (adev->asic_type) { 399 case CHIP_TOPAZ: /* no MM engines */ 400 default: 401 adev->gmc.gart_size = 256ULL << 20; 402 break; 403 #ifdef CONFIG_DRM_AMDGPU_CIK 404 case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */ 405 case CHIP_HAWAII: /* UVD, VCE do not support GPUVM */ 406 case CHIP_KAVERI: /* UVD, VCE do not support GPUVM */ 407 case CHIP_KABINI: /* UVD, VCE do not support GPUVM */ 408 case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */ 409 adev->gmc.gart_size = 1024ULL << 20; 410 break; 411 #endif 412 } 413 } else { 414 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 415 } 416 417 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; 418 gmc_v7_0_vram_gtt_location(adev, &adev->gmc); 419 420 return 0; 421 } 422 423 /** 424 * gmc_v7_0_flush_gpu_tlb_pasid - tlb flush via pasid 425 * 426 * @adev: amdgpu_device pointer 427 * @pasid: pasid to be flush 428 * @flush_type: type of flush 429 * @all_hub: flush all hubs 430 * 431 * Flush the TLB for the requested pasid. 432 */ 433 static int gmc_v7_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 434 uint16_t pasid, uint32_t flush_type, 435 bool all_hub) 436 { 437 int vmid; 438 unsigned int tmp; 439 440 if (amdgpu_in_reset(adev)) 441 return -EIO; 442 443 for (vmid = 1; vmid < 16; vmid++) { 444 445 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); 446 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) && 447 (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) { 448 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 449 RREG32(mmVM_INVALIDATE_RESPONSE); 450 break; 451 } 452 } 453 454 return 0; 455 } 456 457 /* 458 * GART 459 * VMID 0 is the physical GPU addresses as used by the kernel. 460 * VMIDs 1-15 are used for userspace clients and are handled 461 * by the amdgpu vm/hsa code. 462 */ 463 464 /** 465 * gmc_v7_0_flush_gpu_tlb - gart tlb flush callback 466 * 467 * @adev: amdgpu_device pointer 468 * @vmid: vm instance to flush 469 * @vmhub: which hub to flush 470 * @flush_type: type of flush 471 * * 472 * Flush the TLB for the requested page table (CIK). 473 */ 474 static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 475 uint32_t vmhub, uint32_t flush_type) 476 { 477 /* bits 0-15 are the VM contexts0-15 */ 478 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 479 } 480 481 static uint64_t gmc_v7_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 482 unsigned vmid, uint64_t pd_addr) 483 { 484 uint32_t reg; 485 486 if (vmid < 8) 487 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; 488 else 489 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8; 490 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); 491 492 /* bits 0-15 are the VM contexts0-15 */ 493 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); 494 495 return pd_addr; 496 } 497 498 static void gmc_v7_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 499 unsigned pasid) 500 { 501 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); 502 } 503 504 static void gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, int level, 505 uint64_t *addr, uint64_t *flags) 506 { 507 BUG_ON(*addr & 0xFFFFFF0000000FFFULL); 508 } 509 510 static void gmc_v7_0_get_vm_pte(struct amdgpu_device *adev, 511 struct amdgpu_bo_va_mapping *mapping, 512 uint64_t *flags) 513 { 514 *flags &= ~AMDGPU_PTE_EXECUTABLE; 515 *flags &= ~AMDGPU_PTE_PRT; 516 } 517 518 /** 519 * gmc_v7_0_set_fault_enable_default - update VM fault handling 520 * 521 * @adev: amdgpu_device pointer 522 * @value: true redirects VM faults to the default page 523 */ 524 static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev, 525 bool value) 526 { 527 u32 tmp; 528 529 tmp = RREG32(mmVM_CONTEXT1_CNTL); 530 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 531 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 532 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 533 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 534 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 535 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 536 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 537 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 538 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 539 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 540 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 541 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 542 WREG32(mmVM_CONTEXT1_CNTL, tmp); 543 } 544 545 /** 546 * gmc_v7_0_set_prt - set PRT VM fault 547 * 548 * @adev: amdgpu_device pointer 549 * @enable: enable/disable VM fault handling for PRT 550 */ 551 static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable) 552 { 553 uint32_t tmp; 554 555 if (enable && !adev->gmc.prt_warning) { 556 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 557 adev->gmc.prt_warning = true; 558 } 559 560 tmp = RREG32(mmVM_PRT_CNTL); 561 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 562 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 563 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 564 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 565 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 566 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 567 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 568 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 569 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 570 L2_CACHE_STORE_INVALID_ENTRIES, enable); 571 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 572 L1_TLB_STORE_INVALID_ENTRIES, enable); 573 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 574 MASK_PDE0_FAULT, enable); 575 WREG32(mmVM_PRT_CNTL, tmp); 576 577 if (enable) { 578 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; 579 uint32_t high = adev->vm_manager.max_pfn - 580 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT); 581 582 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); 583 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); 584 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); 585 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); 586 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); 587 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); 588 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); 589 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); 590 } else { 591 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); 592 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); 593 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); 594 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); 595 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); 596 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); 597 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); 598 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); 599 } 600 } 601 602 /** 603 * gmc_v7_0_gart_enable - gart enable 604 * 605 * @adev: amdgpu_device pointer 606 * 607 * This sets up the TLBs, programs the page tables for VMID0, 608 * sets up the hw for VMIDs 1-15 which are allocated on 609 * demand, and sets up the global locations for the LDS, GDS, 610 * and GPUVM for FSA64 clients (CIK). 611 * Returns 0 for success, errors for failure. 612 */ 613 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev) 614 { 615 uint64_t table_addr; 616 int r, i; 617 u32 tmp, field; 618 619 if (adev->gart.bo == NULL) { 620 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 621 return -EINVAL; 622 } 623 r = amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 624 if (r) 625 return r; 626 627 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 628 629 /* Setup TLB control */ 630 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 631 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 632 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); 633 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 634 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); 635 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 636 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 637 /* Setup L2 cache */ 638 tmp = RREG32(mmVM_L2_CNTL); 639 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 640 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 641 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); 642 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); 643 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); 644 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 645 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 646 WREG32(mmVM_L2_CNTL, tmp); 647 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 648 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 649 WREG32(mmVM_L2_CNTL2, tmp); 650 651 field = adev->vm_manager.fragment_size; 652 tmp = RREG32(mmVM_L2_CNTL3); 653 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); 654 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); 655 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); 656 WREG32(mmVM_L2_CNTL3, tmp); 657 /* setup context0 */ 658 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); 659 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); 660 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12); 661 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 662 (u32)(adev->dummy_page_addr >> 12)); 663 WREG32(mmVM_CONTEXT0_CNTL2, 0); 664 tmp = RREG32(mmVM_CONTEXT0_CNTL); 665 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 666 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 667 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 668 WREG32(mmVM_CONTEXT0_CNTL, tmp); 669 670 WREG32(0x575, 0); 671 WREG32(0x576, 0); 672 WREG32(0x577, 0); 673 674 /* empty context1-15 */ 675 /* FIXME start with 4G, once using 2 level pt switch to full 676 * vm size space 677 */ 678 /* set vm size, must be a multiple of 4 */ 679 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 680 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 681 for (i = 1; i < AMDGPU_NUM_VMID; i++) { 682 if (i < 8) 683 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 684 table_addr >> 12); 685 else 686 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 687 table_addr >> 12); 688 } 689 690 /* enable context1-15 */ 691 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 692 (u32)(adev->dummy_page_addr >> 12)); 693 WREG32(mmVM_CONTEXT1_CNTL2, 4); 694 tmp = RREG32(mmVM_CONTEXT1_CNTL); 695 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 696 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); 697 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, 698 adev->vm_manager.block_size - 9); 699 WREG32(mmVM_CONTEXT1_CNTL, tmp); 700 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 701 gmc_v7_0_set_fault_enable_default(adev, false); 702 else 703 gmc_v7_0_set_fault_enable_default(adev, true); 704 705 if (adev->asic_type == CHIP_KAVERI) { 706 tmp = RREG32(mmCHUB_CONTROL); 707 tmp &= ~BYPASS_VM; 708 WREG32(mmCHUB_CONTROL, tmp); 709 } 710 711 gmc_v7_0_flush_gpu_tlb(adev, 0, 0, 0); 712 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 713 (unsigned)(adev->gmc.gart_size >> 20), 714 (unsigned long long)table_addr); 715 adev->gart.ready = true; 716 return 0; 717 } 718 719 static int gmc_v7_0_gart_init(struct amdgpu_device *adev) 720 { 721 int r; 722 723 if (adev->gart.bo) { 724 WARN(1, "R600 PCIE GART already initialized\n"); 725 return 0; 726 } 727 /* Initialize common gart structure */ 728 r = amdgpu_gart_init(adev); 729 if (r) 730 return r; 731 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 732 adev->gart.gart_pte_flags = 0; 733 return amdgpu_gart_table_vram_alloc(adev); 734 } 735 736 /** 737 * gmc_v7_0_gart_disable - gart disable 738 * 739 * @adev: amdgpu_device pointer 740 * 741 * This disables all VM page table (CIK). 742 */ 743 static void gmc_v7_0_gart_disable(struct amdgpu_device *adev) 744 { 745 u32 tmp; 746 747 /* Disable all tables */ 748 WREG32(mmVM_CONTEXT0_CNTL, 0); 749 WREG32(mmVM_CONTEXT1_CNTL, 0); 750 /* Setup TLB control */ 751 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 752 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 753 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); 754 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); 755 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 756 /* Setup L2 cache */ 757 tmp = RREG32(mmVM_L2_CNTL); 758 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 759 WREG32(mmVM_L2_CNTL, tmp); 760 WREG32(mmVM_L2_CNTL2, 0); 761 } 762 763 /** 764 * gmc_v7_0_vm_decode_fault - print human readable fault info 765 * 766 * @adev: amdgpu_device pointer 767 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value 768 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value 769 * @mc_client: VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT register value 770 * @pasid: debug logging only - no functional use 771 * 772 * Print human readable fault information (CIK). 773 */ 774 static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev, u32 status, 775 u32 addr, u32 mc_client, unsigned pasid) 776 { 777 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 778 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 779 PROTECTIONS); 780 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 781 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 782 u32 mc_id; 783 784 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 785 MEMORY_CLIENT_ID); 786 787 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 788 protections, vmid, pasid, addr, 789 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 790 MEMORY_CLIENT_RW) ? 791 "write" : "read", block, mc_client, mc_id); 792 } 793 794 795 static const u32 mc_cg_registers[] = { 796 mmMC_HUB_MISC_HUB_CG, 797 mmMC_HUB_MISC_SIP_CG, 798 mmMC_HUB_MISC_VM_CG, 799 mmMC_XPB_CLK_GAT, 800 mmATC_MISC_CG, 801 mmMC_CITF_MISC_WR_CG, 802 mmMC_CITF_MISC_RD_CG, 803 mmMC_CITF_MISC_VM_CG, 804 mmVM_L2_CG, 805 }; 806 807 static const u32 mc_cg_ls_en[] = { 808 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK, 809 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK, 810 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK, 811 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK, 812 ATC_MISC_CG__MEM_LS_ENABLE_MASK, 813 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK, 814 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK, 815 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK, 816 VM_L2_CG__MEM_LS_ENABLE_MASK, 817 }; 818 819 static const u32 mc_cg_en[] = { 820 MC_HUB_MISC_HUB_CG__ENABLE_MASK, 821 MC_HUB_MISC_SIP_CG__ENABLE_MASK, 822 MC_HUB_MISC_VM_CG__ENABLE_MASK, 823 MC_XPB_CLK_GAT__ENABLE_MASK, 824 ATC_MISC_CG__ENABLE_MASK, 825 MC_CITF_MISC_WR_CG__ENABLE_MASK, 826 MC_CITF_MISC_RD_CG__ENABLE_MASK, 827 MC_CITF_MISC_VM_CG__ENABLE_MASK, 828 VM_L2_CG__ENABLE_MASK, 829 }; 830 831 static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev, 832 bool enable) 833 { 834 int i; 835 u32 orig, data; 836 837 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 838 orig = data = RREG32(mc_cg_registers[i]); 839 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) 840 data |= mc_cg_ls_en[i]; 841 else 842 data &= ~mc_cg_ls_en[i]; 843 if (data != orig) 844 WREG32(mc_cg_registers[i], data); 845 } 846 } 847 848 static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev, 849 bool enable) 850 { 851 int i; 852 u32 orig, data; 853 854 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 855 orig = data = RREG32(mc_cg_registers[i]); 856 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) 857 data |= mc_cg_en[i]; 858 else 859 data &= ~mc_cg_en[i]; 860 if (data != orig) 861 WREG32(mc_cg_registers[i], data); 862 } 863 } 864 865 static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev, 866 bool enable) 867 { 868 u32 orig, data; 869 870 orig = data = RREG32_PCIE(ixPCIE_CNTL2); 871 872 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 873 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1); 874 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1); 875 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1); 876 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1); 877 } else { 878 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0); 879 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0); 880 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0); 881 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0); 882 } 883 884 if (orig != data) 885 WREG32_PCIE(ixPCIE_CNTL2, data); 886 } 887 888 static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev, 889 bool enable) 890 { 891 u32 orig, data; 892 893 orig = data = RREG32(mmHDP_HOST_PATH_CNTL); 894 895 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 896 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0); 897 else 898 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1); 899 900 if (orig != data) 901 WREG32(mmHDP_HOST_PATH_CNTL, data); 902 } 903 904 static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev, 905 bool enable) 906 { 907 u32 orig, data; 908 909 orig = data = RREG32(mmHDP_MEM_POWER_LS); 910 911 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 912 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1); 913 else 914 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0); 915 916 if (orig != data) 917 WREG32(mmHDP_MEM_POWER_LS, data); 918 } 919 920 static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type) 921 { 922 switch (mc_seq_vram_type) { 923 case MC_SEQ_MISC0__MT__GDDR1: 924 return AMDGPU_VRAM_TYPE_GDDR1; 925 case MC_SEQ_MISC0__MT__DDR2: 926 return AMDGPU_VRAM_TYPE_DDR2; 927 case MC_SEQ_MISC0__MT__GDDR3: 928 return AMDGPU_VRAM_TYPE_GDDR3; 929 case MC_SEQ_MISC0__MT__GDDR4: 930 return AMDGPU_VRAM_TYPE_GDDR4; 931 case MC_SEQ_MISC0__MT__GDDR5: 932 return AMDGPU_VRAM_TYPE_GDDR5; 933 case MC_SEQ_MISC0__MT__HBM: 934 return AMDGPU_VRAM_TYPE_HBM; 935 case MC_SEQ_MISC0__MT__DDR3: 936 return AMDGPU_VRAM_TYPE_DDR3; 937 default: 938 return AMDGPU_VRAM_TYPE_UNKNOWN; 939 } 940 } 941 942 static int gmc_v7_0_early_init(void *handle) 943 { 944 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 945 946 gmc_v7_0_set_gmc_funcs(adev); 947 gmc_v7_0_set_irq_funcs(adev); 948 949 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 950 adev->gmc.shared_aperture_end = 951 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 952 adev->gmc.private_aperture_start = 953 adev->gmc.shared_aperture_end + 1; 954 adev->gmc.private_aperture_end = 955 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 956 957 return 0; 958 } 959 960 static int gmc_v7_0_late_init(void *handle) 961 { 962 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 963 964 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 965 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 966 else 967 return 0; 968 } 969 970 static unsigned gmc_v7_0_get_vbios_fb_size(struct amdgpu_device *adev) 971 { 972 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); 973 unsigned size; 974 975 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 976 size = AMDGPU_VBIOS_VGA_ALLOCATION; 977 } else { 978 u32 viewport = RREG32(mmVIEWPORT_SIZE); 979 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 980 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * 981 4); 982 } 983 984 return size; 985 } 986 987 static int gmc_v7_0_sw_init(void *handle) 988 { 989 int r; 990 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 991 992 adev->num_vmhubs = 1; 993 994 if (adev->flags & AMD_IS_APU) { 995 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 996 } else { 997 u32 tmp = RREG32(mmMC_SEQ_MISC0); 998 tmp &= MC_SEQ_MISC0__MT__MASK; 999 adev->gmc.vram_type = gmc_v7_0_convert_vram_type(tmp); 1000 } 1001 1002 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault); 1003 if (r) 1004 return r; 1005 1006 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault); 1007 if (r) 1008 return r; 1009 1010 /* Adjust VM size here. 1011 * Currently set to 4GB ((1 << 20) 4k pages). 1012 * Max GPUVM size for cayman and SI is 40 bits. 1013 */ 1014 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); 1015 1016 /* Set the internal MC address mask 1017 * This is the max address of the GPU's 1018 * internal address space. 1019 */ 1020 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1021 1022 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40)); 1023 if (r) { 1024 pr_warn("No suitable DMA available\n"); 1025 return r; 1026 } 1027 adev->need_swiotlb = drm_need_swiotlb(40); 1028 1029 r = gmc_v7_0_init_microcode(adev); 1030 if (r) { 1031 DRM_ERROR("Failed to load mc firmware!\n"); 1032 return r; 1033 } 1034 1035 r = gmc_v7_0_mc_init(adev); 1036 if (r) 1037 return r; 1038 1039 amdgpu_gmc_get_vbios_allocations(adev); 1040 1041 /* Memory manager */ 1042 r = amdgpu_bo_init(adev); 1043 if (r) 1044 return r; 1045 1046 r = gmc_v7_0_gart_init(adev); 1047 if (r) 1048 return r; 1049 1050 /* 1051 * number of VMs 1052 * VMID 0 is reserved for System 1053 * amdgpu graphics/compute will use VMIDs 1-7 1054 * amdkfd will use VMIDs 8-15 1055 */ 1056 adev->vm_manager.first_kfd_vmid = 8; 1057 amdgpu_vm_manager_init(adev); 1058 1059 /* base offset of vram pages */ 1060 if (adev->flags & AMD_IS_APU) { 1061 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 1062 1063 tmp <<= 22; 1064 adev->vm_manager.vram_base_offset = tmp; 1065 } else { 1066 adev->vm_manager.vram_base_offset = 0; 1067 } 1068 1069 adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info), 1070 GFP_KERNEL); 1071 if (!adev->gmc.vm_fault_info) 1072 return -ENOMEM; 1073 atomic_set(&adev->gmc.vm_fault_info_updated, 0); 1074 1075 return 0; 1076 } 1077 1078 static int gmc_v7_0_sw_fini(void *handle) 1079 { 1080 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1081 1082 amdgpu_gem_force_release(adev); 1083 amdgpu_vm_manager_fini(adev); 1084 kfree(adev->gmc.vm_fault_info); 1085 amdgpu_gart_table_vram_free(adev); 1086 amdgpu_bo_fini(adev); 1087 release_firmware(adev->gmc.fw); 1088 adev->gmc.fw = NULL; 1089 1090 return 0; 1091 } 1092 1093 static int gmc_v7_0_hw_init(void *handle) 1094 { 1095 int r; 1096 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1097 1098 gmc_v7_0_init_golden_registers(adev); 1099 1100 gmc_v7_0_mc_program(adev); 1101 1102 if (!(adev->flags & AMD_IS_APU)) { 1103 r = gmc_v7_0_mc_load_microcode(adev); 1104 if (r) { 1105 DRM_ERROR("Failed to load MC firmware!\n"); 1106 return r; 1107 } 1108 } 1109 1110 r = gmc_v7_0_gart_enable(adev); 1111 if (r) 1112 return r; 1113 1114 return r; 1115 } 1116 1117 static int gmc_v7_0_hw_fini(void *handle) 1118 { 1119 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1120 1121 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1122 gmc_v7_0_gart_disable(adev); 1123 1124 return 0; 1125 } 1126 1127 static int gmc_v7_0_suspend(void *handle) 1128 { 1129 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1130 1131 gmc_v7_0_hw_fini(adev); 1132 1133 return 0; 1134 } 1135 1136 static int gmc_v7_0_resume(void *handle) 1137 { 1138 int r; 1139 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1140 1141 r = gmc_v7_0_hw_init(adev); 1142 if (r) 1143 return r; 1144 1145 amdgpu_vmid_reset_all(adev); 1146 1147 return 0; 1148 } 1149 1150 static bool gmc_v7_0_is_idle(void *handle) 1151 { 1152 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1153 u32 tmp = RREG32(mmSRBM_STATUS); 1154 1155 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1156 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 1157 return false; 1158 1159 return true; 1160 } 1161 1162 static int gmc_v7_0_wait_for_idle(void *handle) 1163 { 1164 unsigned i; 1165 u32 tmp; 1166 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1167 1168 for (i = 0; i < adev->usec_timeout; i++) { 1169 /* read MC_STATUS */ 1170 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | 1171 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1172 SRBM_STATUS__MCC_BUSY_MASK | 1173 SRBM_STATUS__MCD_BUSY_MASK | 1174 SRBM_STATUS__VMC_BUSY_MASK); 1175 if (!tmp) 1176 return 0; 1177 udelay(1); 1178 } 1179 return -ETIMEDOUT; 1180 1181 } 1182 1183 static int gmc_v7_0_soft_reset(void *handle) 1184 { 1185 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1186 u32 srbm_soft_reset = 0; 1187 u32 tmp = RREG32(mmSRBM_STATUS); 1188 1189 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1190 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1191 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 1192 1193 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1194 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 1195 if (!(adev->flags & AMD_IS_APU)) 1196 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1197 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1198 } 1199 1200 if (srbm_soft_reset) { 1201 gmc_v7_0_mc_stop(adev); 1202 if (gmc_v7_0_wait_for_idle((void *)adev)) { 1203 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1204 } 1205 1206 1207 tmp = RREG32(mmSRBM_SOFT_RESET); 1208 tmp |= srbm_soft_reset; 1209 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1210 WREG32(mmSRBM_SOFT_RESET, tmp); 1211 tmp = RREG32(mmSRBM_SOFT_RESET); 1212 1213 udelay(50); 1214 1215 tmp &= ~srbm_soft_reset; 1216 WREG32(mmSRBM_SOFT_RESET, tmp); 1217 tmp = RREG32(mmSRBM_SOFT_RESET); 1218 1219 /* Wait a little for things to settle down */ 1220 udelay(50); 1221 1222 gmc_v7_0_mc_resume(adev); 1223 udelay(50); 1224 } 1225 1226 return 0; 1227 } 1228 1229 static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1230 struct amdgpu_irq_src *src, 1231 unsigned type, 1232 enum amdgpu_interrupt_state state) 1233 { 1234 u32 tmp; 1235 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1236 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1237 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1238 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1239 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1240 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1241 1242 switch (state) { 1243 case AMDGPU_IRQ_STATE_DISABLE: 1244 /* system context */ 1245 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1246 tmp &= ~bits; 1247 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1248 /* VMs */ 1249 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1250 tmp &= ~bits; 1251 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1252 break; 1253 case AMDGPU_IRQ_STATE_ENABLE: 1254 /* system context */ 1255 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1256 tmp |= bits; 1257 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1258 /* VMs */ 1259 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1260 tmp |= bits; 1261 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1262 break; 1263 default: 1264 break; 1265 } 1266 1267 return 0; 1268 } 1269 1270 static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev, 1271 struct amdgpu_irq_src *source, 1272 struct amdgpu_iv_entry *entry) 1273 { 1274 u32 addr, status, mc_client, vmid; 1275 1276 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1277 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1278 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); 1279 /* reset addr and status */ 1280 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1281 1282 if (!addr && !status) 1283 return 0; 1284 1285 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1286 gmc_v7_0_set_fault_enable_default(adev, false); 1287 1288 if (printk_ratelimit()) { 1289 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1290 entry->src_id, entry->src_data[0]); 1291 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1292 addr); 1293 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1294 status); 1295 gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client, 1296 entry->pasid); 1297 } 1298 1299 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1300 VMID); 1301 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid) 1302 && !atomic_read(&adev->gmc.vm_fault_info_updated)) { 1303 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info; 1304 u32 protections = REG_GET_FIELD(status, 1305 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1306 PROTECTIONS); 1307 1308 info->vmid = vmid; 1309 info->mc_id = REG_GET_FIELD(status, 1310 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1311 MEMORY_CLIENT_ID); 1312 info->status = status; 1313 info->page_addr = addr; 1314 info->prot_valid = protections & 0x7 ? true : false; 1315 info->prot_read = protections & 0x8 ? true : false; 1316 info->prot_write = protections & 0x10 ? true : false; 1317 info->prot_exec = protections & 0x20 ? true : false; 1318 mb(); 1319 atomic_set(&adev->gmc.vm_fault_info_updated, 1); 1320 } 1321 1322 return 0; 1323 } 1324 1325 static int gmc_v7_0_set_clockgating_state(void *handle, 1326 enum amd_clockgating_state state) 1327 { 1328 bool gate = false; 1329 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1330 1331 if (state == AMD_CG_STATE_GATE) 1332 gate = true; 1333 1334 if (!(adev->flags & AMD_IS_APU)) { 1335 gmc_v7_0_enable_mc_mgcg(adev, gate); 1336 gmc_v7_0_enable_mc_ls(adev, gate); 1337 } 1338 gmc_v7_0_enable_bif_mgls(adev, gate); 1339 gmc_v7_0_enable_hdp_mgcg(adev, gate); 1340 gmc_v7_0_enable_hdp_ls(adev, gate); 1341 1342 return 0; 1343 } 1344 1345 static int gmc_v7_0_set_powergating_state(void *handle, 1346 enum amd_powergating_state state) 1347 { 1348 return 0; 1349 } 1350 1351 static const struct amd_ip_funcs gmc_v7_0_ip_funcs = { 1352 .name = "gmc_v7_0", 1353 .early_init = gmc_v7_0_early_init, 1354 .late_init = gmc_v7_0_late_init, 1355 .sw_init = gmc_v7_0_sw_init, 1356 .sw_fini = gmc_v7_0_sw_fini, 1357 .hw_init = gmc_v7_0_hw_init, 1358 .hw_fini = gmc_v7_0_hw_fini, 1359 .suspend = gmc_v7_0_suspend, 1360 .resume = gmc_v7_0_resume, 1361 .is_idle = gmc_v7_0_is_idle, 1362 .wait_for_idle = gmc_v7_0_wait_for_idle, 1363 .soft_reset = gmc_v7_0_soft_reset, 1364 .set_clockgating_state = gmc_v7_0_set_clockgating_state, 1365 .set_powergating_state = gmc_v7_0_set_powergating_state, 1366 }; 1367 1368 static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = { 1369 .flush_gpu_tlb = gmc_v7_0_flush_gpu_tlb, 1370 .flush_gpu_tlb_pasid = gmc_v7_0_flush_gpu_tlb_pasid, 1371 .emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb, 1372 .emit_pasid_mapping = gmc_v7_0_emit_pasid_mapping, 1373 .set_prt = gmc_v7_0_set_prt, 1374 .get_vm_pde = gmc_v7_0_get_vm_pde, 1375 .get_vm_pte = gmc_v7_0_get_vm_pte, 1376 .get_vbios_fb_size = gmc_v7_0_get_vbios_fb_size, 1377 }; 1378 1379 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = { 1380 .set = gmc_v7_0_vm_fault_interrupt_state, 1381 .process = gmc_v7_0_process_interrupt, 1382 }; 1383 1384 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev) 1385 { 1386 adev->gmc.gmc_funcs = &gmc_v7_0_gmc_funcs; 1387 } 1388 1389 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev) 1390 { 1391 adev->gmc.vm_fault.num_types = 1; 1392 adev->gmc.vm_fault.funcs = &gmc_v7_0_irq_funcs; 1393 } 1394 1395 const struct amdgpu_ip_block_version gmc_v7_0_ip_block = 1396 { 1397 .type = AMD_IP_BLOCK_TYPE_GMC, 1398 .major = 7, 1399 .minor = 0, 1400 .rev = 0, 1401 .funcs = &gmc_v7_0_ip_funcs, 1402 }; 1403 1404 const struct amdgpu_ip_block_version gmc_v7_4_ip_block = 1405 { 1406 .type = AMD_IP_BLOCK_TYPE_GMC, 1407 .major = 7, 1408 .minor = 4, 1409 .rev = 0, 1410 .funcs = &gmc_v7_0_ip_funcs, 1411 }; 1412