1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/drm_cache.h> 29 #include "amdgpu.h" 30 #include "cikd.h" 31 #include "cik.h" 32 #include "gmc_v7_0.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_amdkfd.h" 35 #include "amdgpu_gem.h" 36 37 #include "bif/bif_4_1_d.h" 38 #include "bif/bif_4_1_sh_mask.h" 39 40 #include "gmc/gmc_7_1_d.h" 41 #include "gmc/gmc_7_1_sh_mask.h" 42 43 #include "oss/oss_2_0_d.h" 44 #include "oss/oss_2_0_sh_mask.h" 45 46 #include "dce/dce_8_0_d.h" 47 #include "dce/dce_8_0_sh_mask.h" 48 49 #include "amdgpu_atombios.h" 50 51 #include "ivsrcid/ivsrcid_vislands30.h" 52 53 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev); 54 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev); 55 static int gmc_v7_0_wait_for_idle(void *handle); 56 57 MODULE_FIRMWARE("amdgpu/bonaire_mc.bin"); 58 MODULE_FIRMWARE("amdgpu/hawaii_mc.bin"); 59 MODULE_FIRMWARE("amdgpu/topaz_mc.bin"); 60 61 static const u32 golden_settings_iceland_a11[] = 62 { 63 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 64 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 65 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 66 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 67 }; 68 69 static const u32 iceland_mgcg_cgcg_init[] = 70 { 71 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 72 }; 73 74 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev) 75 { 76 switch (adev->asic_type) { 77 case CHIP_TOPAZ: 78 amdgpu_device_program_register_sequence(adev, 79 iceland_mgcg_cgcg_init, 80 ARRAY_SIZE(iceland_mgcg_cgcg_init)); 81 amdgpu_device_program_register_sequence(adev, 82 golden_settings_iceland_a11, 83 ARRAY_SIZE(golden_settings_iceland_a11)); 84 break; 85 default: 86 break; 87 } 88 } 89 90 static void gmc_v7_0_mc_stop(struct amdgpu_device *adev) 91 { 92 u32 blackout; 93 94 gmc_v7_0_wait_for_idle((void *)adev); 95 96 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 97 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 98 /* Block CPU access */ 99 WREG32(mmBIF_FB_EN, 0); 100 /* blackout the MC */ 101 blackout = REG_SET_FIELD(blackout, 102 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 103 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); 104 } 105 /* wait for the MC to settle */ 106 udelay(100); 107 } 108 109 static void gmc_v7_0_mc_resume(struct amdgpu_device *adev) 110 { 111 u32 tmp; 112 113 /* unblackout the MC */ 114 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 115 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 116 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 117 /* allow CPU access */ 118 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 119 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 120 WREG32(mmBIF_FB_EN, tmp); 121 } 122 123 /** 124 * gmc_v7_0_init_microcode - load ucode images from disk 125 * 126 * @adev: amdgpu_device pointer 127 * 128 * Use the firmware interface to load the ucode images into 129 * the driver (not loaded into hw). 130 * Returns 0 on success, error on failure. 131 */ 132 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev) 133 { 134 const char *chip_name; 135 char fw_name[30]; 136 int err; 137 138 DRM_DEBUG("\n"); 139 140 switch (adev->asic_type) { 141 case CHIP_BONAIRE: 142 chip_name = "bonaire"; 143 break; 144 case CHIP_HAWAII: 145 chip_name = "hawaii"; 146 break; 147 case CHIP_TOPAZ: 148 chip_name = "topaz"; 149 break; 150 case CHIP_KAVERI: 151 case CHIP_KABINI: 152 case CHIP_MULLINS: 153 return 0; 154 default: BUG(); 155 } 156 157 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name); 158 159 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); 160 if (err) 161 goto out; 162 err = amdgpu_ucode_validate(adev->gmc.fw); 163 164 out: 165 if (err) { 166 pr_err("cik_mc: Failed to load firmware \"%s\"\n", fw_name); 167 release_firmware(adev->gmc.fw); 168 adev->gmc.fw = NULL; 169 } 170 return err; 171 } 172 173 /** 174 * gmc_v7_0_mc_load_microcode - load MC ucode into the hw 175 * 176 * @adev: amdgpu_device pointer 177 * 178 * Load the GDDR MC ucode into the hw (CIK). 179 * Returns 0 on success, error on failure. 180 */ 181 static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev) 182 { 183 const struct mc_firmware_header_v1_0 *hdr; 184 const __le32 *fw_data = NULL; 185 const __le32 *io_mc_regs = NULL; 186 u32 running; 187 int i, ucode_size, regs_size; 188 189 if (!adev->gmc.fw) 190 return -EINVAL; 191 192 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 193 amdgpu_ucode_print_mc_hdr(&hdr->header); 194 195 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 196 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 197 io_mc_regs = (const __le32 *) 198 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 199 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 200 fw_data = (const __le32 *) 201 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 202 203 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); 204 205 if (running == 0) { 206 /* reset the engine and set to writable */ 207 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 208 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 209 210 /* load mc io regs */ 211 for (i = 0; i < regs_size; i++) { 212 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 213 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 214 } 215 /* load the MC ucode */ 216 for (i = 0; i < ucode_size; i++) 217 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 218 219 /* put the engine back into the active state */ 220 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 221 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 222 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 223 224 /* wait for training to complete */ 225 for (i = 0; i < adev->usec_timeout; i++) { 226 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 227 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0)) 228 break; 229 udelay(1); 230 } 231 for (i = 0; i < adev->usec_timeout; i++) { 232 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 233 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1)) 234 break; 235 udelay(1); 236 } 237 } 238 239 return 0; 240 } 241 242 static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev, 243 struct amdgpu_gmc *mc) 244 { 245 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; 246 base <<= 24; 247 248 amdgpu_gmc_vram_location(adev, mc, base); 249 amdgpu_gmc_gart_location(adev, mc); 250 } 251 252 /** 253 * gmc_v7_0_mc_program - program the GPU memory controller 254 * 255 * @adev: amdgpu_device pointer 256 * 257 * Set the location of vram, gart, and AGP in the GPU's 258 * physical address space (CIK). 259 */ 260 static void gmc_v7_0_mc_program(struct amdgpu_device *adev) 261 { 262 u32 tmp; 263 int i, j; 264 265 /* Initialize HDP */ 266 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 267 WREG32((0xb05 + j), 0x00000000); 268 WREG32((0xb06 + j), 0x00000000); 269 WREG32((0xb07 + j), 0x00000000); 270 WREG32((0xb08 + j), 0x00000000); 271 WREG32((0xb09 + j), 0x00000000); 272 } 273 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 274 275 if (gmc_v7_0_wait_for_idle((void *)adev)) { 276 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 277 } 278 if (adev->mode_info.num_crtc) { 279 /* Lockout access through VGA aperture*/ 280 tmp = RREG32(mmVGA_HDP_CONTROL); 281 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 282 WREG32(mmVGA_HDP_CONTROL, tmp); 283 284 /* disable VGA render */ 285 tmp = RREG32(mmVGA_RENDER_CONTROL); 286 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 287 WREG32(mmVGA_RENDER_CONTROL, tmp); 288 } 289 /* Update configuration */ 290 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 291 adev->gmc.vram_start >> 12); 292 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 293 adev->gmc.vram_end >> 12); 294 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 295 adev->vram_scratch.gpu_addr >> 12); 296 WREG32(mmMC_VM_AGP_BASE, 0); 297 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); 298 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); 299 if (gmc_v7_0_wait_for_idle((void *)adev)) { 300 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 301 } 302 303 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 304 305 tmp = RREG32(mmHDP_MISC_CNTL); 306 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); 307 WREG32(mmHDP_MISC_CNTL, tmp); 308 309 tmp = RREG32(mmHDP_HOST_PATH_CNTL); 310 WREG32(mmHDP_HOST_PATH_CNTL, tmp); 311 } 312 313 /** 314 * gmc_v7_0_mc_init - initialize the memory controller driver params 315 * 316 * @adev: amdgpu_device pointer 317 * 318 * Look up the amount of vram, vram width, and decide how to place 319 * vram and gart within the GPU's physical address space (CIK). 320 * Returns 0 for success. 321 */ 322 static int gmc_v7_0_mc_init(struct amdgpu_device *adev) 323 { 324 int r; 325 326 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev); 327 if (!adev->gmc.vram_width) { 328 u32 tmp; 329 int chansize, numchan; 330 331 /* Get VRAM informations */ 332 tmp = RREG32(mmMC_ARB_RAMCFG); 333 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { 334 chansize = 64; 335 } else { 336 chansize = 32; 337 } 338 tmp = RREG32(mmMC_SHARED_CHMAP); 339 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 340 case 0: 341 default: 342 numchan = 1; 343 break; 344 case 1: 345 numchan = 2; 346 break; 347 case 2: 348 numchan = 4; 349 break; 350 case 3: 351 numchan = 8; 352 break; 353 case 4: 354 numchan = 3; 355 break; 356 case 5: 357 numchan = 6; 358 break; 359 case 6: 360 numchan = 10; 361 break; 362 case 7: 363 numchan = 12; 364 break; 365 case 8: 366 numchan = 16; 367 break; 368 } 369 adev->gmc.vram_width = numchan * chansize; 370 } 371 /* size in MB on si */ 372 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 373 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 374 375 if (!(adev->flags & AMD_IS_APU)) { 376 r = amdgpu_device_resize_fb_bar(adev); 377 if (r) 378 return r; 379 } 380 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 381 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 382 383 #ifdef CONFIG_X86_64 384 if (adev->flags & AMD_IS_APU) { 385 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; 386 adev->gmc.aper_size = adev->gmc.real_vram_size; 387 } 388 #endif 389 390 /* In case the PCI BAR is larger than the actual amount of vram */ 391 adev->gmc.visible_vram_size = adev->gmc.aper_size; 392 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 393 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 394 395 /* set the gart size */ 396 if (amdgpu_gart_size == -1) { 397 switch (adev->asic_type) { 398 case CHIP_TOPAZ: /* no MM engines */ 399 default: 400 adev->gmc.gart_size = 256ULL << 20; 401 break; 402 #ifdef CONFIG_DRM_AMDGPU_CIK 403 case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */ 404 case CHIP_HAWAII: /* UVD, VCE do not support GPUVM */ 405 case CHIP_KAVERI: /* UVD, VCE do not support GPUVM */ 406 case CHIP_KABINI: /* UVD, VCE do not support GPUVM */ 407 case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */ 408 adev->gmc.gart_size = 1024ULL << 20; 409 break; 410 #endif 411 } 412 } else { 413 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 414 } 415 416 gmc_v7_0_vram_gtt_location(adev, &adev->gmc); 417 418 return 0; 419 } 420 421 /* 422 * GART 423 * VMID 0 is the physical GPU addresses as used by the kernel. 424 * VMIDs 1-15 are used for userspace clients and are handled 425 * by the amdgpu vm/hsa code. 426 */ 427 428 /** 429 * gmc_v7_0_flush_gpu_tlb - gart tlb flush callback 430 * 431 * @adev: amdgpu_device pointer 432 * @vmid: vm instance to flush 433 * 434 * Flush the TLB for the requested page table (CIK). 435 */ 436 static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, 437 uint32_t vmid, uint32_t flush_type) 438 { 439 /* bits 0-15 are the VM contexts0-15 */ 440 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 441 } 442 443 static uint64_t gmc_v7_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 444 unsigned vmid, uint64_t pd_addr) 445 { 446 uint32_t reg; 447 448 if (vmid < 8) 449 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; 450 else 451 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8; 452 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); 453 454 /* bits 0-15 are the VM contexts0-15 */ 455 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); 456 457 return pd_addr; 458 } 459 460 static void gmc_v7_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 461 unsigned pasid) 462 { 463 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); 464 } 465 466 static uint64_t gmc_v7_0_get_vm_pte_flags(struct amdgpu_device *adev, 467 uint32_t flags) 468 { 469 uint64_t pte_flag = 0; 470 471 if (flags & AMDGPU_VM_PAGE_READABLE) 472 pte_flag |= AMDGPU_PTE_READABLE; 473 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 474 pte_flag |= AMDGPU_PTE_WRITEABLE; 475 if (flags & AMDGPU_VM_PAGE_PRT) 476 pte_flag |= AMDGPU_PTE_PRT; 477 478 return pte_flag; 479 } 480 481 static void gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, int level, 482 uint64_t *addr, uint64_t *flags) 483 { 484 BUG_ON(*addr & 0xFFFFFF0000000FFFULL); 485 } 486 487 /** 488 * gmc_v8_0_set_fault_enable_default - update VM fault handling 489 * 490 * @adev: amdgpu_device pointer 491 * @value: true redirects VM faults to the default page 492 */ 493 static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev, 494 bool value) 495 { 496 u32 tmp; 497 498 tmp = RREG32(mmVM_CONTEXT1_CNTL); 499 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 500 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 501 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 502 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 503 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 504 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 505 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 506 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 507 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 508 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 509 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 510 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 511 WREG32(mmVM_CONTEXT1_CNTL, tmp); 512 } 513 514 /** 515 * gmc_v7_0_set_prt - set PRT VM fault 516 * 517 * @adev: amdgpu_device pointer 518 * @enable: enable/disable VM fault handling for PRT 519 */ 520 static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable) 521 { 522 uint32_t tmp; 523 524 if (enable && !adev->gmc.prt_warning) { 525 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 526 adev->gmc.prt_warning = true; 527 } 528 529 tmp = RREG32(mmVM_PRT_CNTL); 530 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 531 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 532 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 533 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 534 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 535 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 536 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 537 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 538 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 539 L2_CACHE_STORE_INVALID_ENTRIES, enable); 540 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 541 L1_TLB_STORE_INVALID_ENTRIES, enable); 542 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 543 MASK_PDE0_FAULT, enable); 544 WREG32(mmVM_PRT_CNTL, tmp); 545 546 if (enable) { 547 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; 548 uint32_t high = adev->vm_manager.max_pfn - 549 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT); 550 551 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); 552 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); 553 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); 554 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); 555 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); 556 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); 557 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); 558 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); 559 } else { 560 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); 561 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); 562 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); 563 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); 564 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); 565 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); 566 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); 567 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); 568 } 569 } 570 571 /** 572 * gmc_v7_0_gart_enable - gart enable 573 * 574 * @adev: amdgpu_device pointer 575 * 576 * This sets up the TLBs, programs the page tables for VMID0, 577 * sets up the hw for VMIDs 1-15 which are allocated on 578 * demand, and sets up the global locations for the LDS, GDS, 579 * and GPUVM for FSA64 clients (CIK). 580 * Returns 0 for success, errors for failure. 581 */ 582 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev) 583 { 584 uint64_t table_addr; 585 int r, i; 586 u32 tmp, field; 587 588 if (adev->gart.bo == NULL) { 589 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 590 return -EINVAL; 591 } 592 r = amdgpu_gart_table_vram_pin(adev); 593 if (r) 594 return r; 595 596 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 597 598 /* Setup TLB control */ 599 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 600 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 601 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); 602 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 603 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); 604 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 605 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 606 /* Setup L2 cache */ 607 tmp = RREG32(mmVM_L2_CNTL); 608 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 609 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 610 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); 611 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); 612 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); 613 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 614 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 615 WREG32(mmVM_L2_CNTL, tmp); 616 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 617 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 618 WREG32(mmVM_L2_CNTL2, tmp); 619 620 field = adev->vm_manager.fragment_size; 621 tmp = RREG32(mmVM_L2_CNTL3); 622 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); 623 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); 624 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); 625 WREG32(mmVM_L2_CNTL3, tmp); 626 /* setup context0 */ 627 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); 628 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); 629 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12); 630 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 631 (u32)(adev->dummy_page_addr >> 12)); 632 WREG32(mmVM_CONTEXT0_CNTL2, 0); 633 tmp = RREG32(mmVM_CONTEXT0_CNTL); 634 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 635 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 636 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 637 WREG32(mmVM_CONTEXT0_CNTL, tmp); 638 639 WREG32(0x575, 0); 640 WREG32(0x576, 0); 641 WREG32(0x577, 0); 642 643 /* empty context1-15 */ 644 /* FIXME start with 4G, once using 2 level pt switch to full 645 * vm size space 646 */ 647 /* set vm size, must be a multiple of 4 */ 648 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 649 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 650 for (i = 1; i < 16; i++) { 651 if (i < 8) 652 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 653 table_addr >> 12); 654 else 655 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 656 table_addr >> 12); 657 } 658 659 /* enable context1-15 */ 660 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 661 (u32)(adev->dummy_page_addr >> 12)); 662 WREG32(mmVM_CONTEXT1_CNTL2, 4); 663 tmp = RREG32(mmVM_CONTEXT1_CNTL); 664 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 665 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); 666 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, 667 adev->vm_manager.block_size - 9); 668 WREG32(mmVM_CONTEXT1_CNTL, tmp); 669 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 670 gmc_v7_0_set_fault_enable_default(adev, false); 671 else 672 gmc_v7_0_set_fault_enable_default(adev, true); 673 674 if (adev->asic_type == CHIP_KAVERI) { 675 tmp = RREG32(mmCHUB_CONTROL); 676 tmp &= ~BYPASS_VM; 677 WREG32(mmCHUB_CONTROL, tmp); 678 } 679 680 gmc_v7_0_flush_gpu_tlb(adev, 0, 0); 681 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 682 (unsigned)(adev->gmc.gart_size >> 20), 683 (unsigned long long)table_addr); 684 adev->gart.ready = true; 685 return 0; 686 } 687 688 static int gmc_v7_0_gart_init(struct amdgpu_device *adev) 689 { 690 int r; 691 692 if (adev->gart.bo) { 693 WARN(1, "R600 PCIE GART already initialized\n"); 694 return 0; 695 } 696 /* Initialize common gart structure */ 697 r = amdgpu_gart_init(adev); 698 if (r) 699 return r; 700 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 701 adev->gart.gart_pte_flags = 0; 702 return amdgpu_gart_table_vram_alloc(adev); 703 } 704 705 /** 706 * gmc_v7_0_gart_disable - gart disable 707 * 708 * @adev: amdgpu_device pointer 709 * 710 * This disables all VM page table (CIK). 711 */ 712 static void gmc_v7_0_gart_disable(struct amdgpu_device *adev) 713 { 714 u32 tmp; 715 716 /* Disable all tables */ 717 WREG32(mmVM_CONTEXT0_CNTL, 0); 718 WREG32(mmVM_CONTEXT1_CNTL, 0); 719 /* Setup TLB control */ 720 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 721 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 722 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); 723 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); 724 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 725 /* Setup L2 cache */ 726 tmp = RREG32(mmVM_L2_CNTL); 727 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 728 WREG32(mmVM_L2_CNTL, tmp); 729 WREG32(mmVM_L2_CNTL2, 0); 730 amdgpu_gart_table_vram_unpin(adev); 731 } 732 733 /** 734 * gmc_v7_0_vm_decode_fault - print human readable fault info 735 * 736 * @adev: amdgpu_device pointer 737 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value 738 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value 739 * 740 * Print human readable fault information (CIK). 741 */ 742 static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev, u32 status, 743 u32 addr, u32 mc_client, unsigned pasid) 744 { 745 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 746 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 747 PROTECTIONS); 748 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 749 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 750 u32 mc_id; 751 752 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 753 MEMORY_CLIENT_ID); 754 755 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 756 protections, vmid, pasid, addr, 757 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 758 MEMORY_CLIENT_RW) ? 759 "write" : "read", block, mc_client, mc_id); 760 } 761 762 763 static const u32 mc_cg_registers[] = { 764 mmMC_HUB_MISC_HUB_CG, 765 mmMC_HUB_MISC_SIP_CG, 766 mmMC_HUB_MISC_VM_CG, 767 mmMC_XPB_CLK_GAT, 768 mmATC_MISC_CG, 769 mmMC_CITF_MISC_WR_CG, 770 mmMC_CITF_MISC_RD_CG, 771 mmMC_CITF_MISC_VM_CG, 772 mmVM_L2_CG, 773 }; 774 775 static const u32 mc_cg_ls_en[] = { 776 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK, 777 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK, 778 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK, 779 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK, 780 ATC_MISC_CG__MEM_LS_ENABLE_MASK, 781 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK, 782 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK, 783 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK, 784 VM_L2_CG__MEM_LS_ENABLE_MASK, 785 }; 786 787 static const u32 mc_cg_en[] = { 788 MC_HUB_MISC_HUB_CG__ENABLE_MASK, 789 MC_HUB_MISC_SIP_CG__ENABLE_MASK, 790 MC_HUB_MISC_VM_CG__ENABLE_MASK, 791 MC_XPB_CLK_GAT__ENABLE_MASK, 792 ATC_MISC_CG__ENABLE_MASK, 793 MC_CITF_MISC_WR_CG__ENABLE_MASK, 794 MC_CITF_MISC_RD_CG__ENABLE_MASK, 795 MC_CITF_MISC_VM_CG__ENABLE_MASK, 796 VM_L2_CG__ENABLE_MASK, 797 }; 798 799 static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev, 800 bool enable) 801 { 802 int i; 803 u32 orig, data; 804 805 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 806 orig = data = RREG32(mc_cg_registers[i]); 807 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) 808 data |= mc_cg_ls_en[i]; 809 else 810 data &= ~mc_cg_ls_en[i]; 811 if (data != orig) 812 WREG32(mc_cg_registers[i], data); 813 } 814 } 815 816 static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev, 817 bool enable) 818 { 819 int i; 820 u32 orig, data; 821 822 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 823 orig = data = RREG32(mc_cg_registers[i]); 824 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) 825 data |= mc_cg_en[i]; 826 else 827 data &= ~mc_cg_en[i]; 828 if (data != orig) 829 WREG32(mc_cg_registers[i], data); 830 } 831 } 832 833 static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev, 834 bool enable) 835 { 836 u32 orig, data; 837 838 orig = data = RREG32_PCIE(ixPCIE_CNTL2); 839 840 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 841 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1); 842 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1); 843 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1); 844 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1); 845 } else { 846 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0); 847 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0); 848 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0); 849 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0); 850 } 851 852 if (orig != data) 853 WREG32_PCIE(ixPCIE_CNTL2, data); 854 } 855 856 static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev, 857 bool enable) 858 { 859 u32 orig, data; 860 861 orig = data = RREG32(mmHDP_HOST_PATH_CNTL); 862 863 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 864 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0); 865 else 866 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1); 867 868 if (orig != data) 869 WREG32(mmHDP_HOST_PATH_CNTL, data); 870 } 871 872 static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev, 873 bool enable) 874 { 875 u32 orig, data; 876 877 orig = data = RREG32(mmHDP_MEM_POWER_LS); 878 879 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 880 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1); 881 else 882 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0); 883 884 if (orig != data) 885 WREG32(mmHDP_MEM_POWER_LS, data); 886 } 887 888 static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type) 889 { 890 switch (mc_seq_vram_type) { 891 case MC_SEQ_MISC0__MT__GDDR1: 892 return AMDGPU_VRAM_TYPE_GDDR1; 893 case MC_SEQ_MISC0__MT__DDR2: 894 return AMDGPU_VRAM_TYPE_DDR2; 895 case MC_SEQ_MISC0__MT__GDDR3: 896 return AMDGPU_VRAM_TYPE_GDDR3; 897 case MC_SEQ_MISC0__MT__GDDR4: 898 return AMDGPU_VRAM_TYPE_GDDR4; 899 case MC_SEQ_MISC0__MT__GDDR5: 900 return AMDGPU_VRAM_TYPE_GDDR5; 901 case MC_SEQ_MISC0__MT__HBM: 902 return AMDGPU_VRAM_TYPE_HBM; 903 case MC_SEQ_MISC0__MT__DDR3: 904 return AMDGPU_VRAM_TYPE_DDR3; 905 default: 906 return AMDGPU_VRAM_TYPE_UNKNOWN; 907 } 908 } 909 910 static int gmc_v7_0_early_init(void *handle) 911 { 912 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 913 914 gmc_v7_0_set_gmc_funcs(adev); 915 gmc_v7_0_set_irq_funcs(adev); 916 917 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 918 adev->gmc.shared_aperture_end = 919 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 920 adev->gmc.private_aperture_start = 921 adev->gmc.shared_aperture_end + 1; 922 adev->gmc.private_aperture_end = 923 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 924 925 return 0; 926 } 927 928 static int gmc_v7_0_late_init(void *handle) 929 { 930 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 931 932 amdgpu_bo_late_init(adev); 933 934 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 935 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 936 else 937 return 0; 938 } 939 940 static unsigned gmc_v7_0_get_vbios_fb_size(struct amdgpu_device *adev) 941 { 942 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); 943 unsigned size; 944 945 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 946 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */ 947 } else { 948 u32 viewport = RREG32(mmVIEWPORT_SIZE); 949 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 950 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * 951 4); 952 } 953 /* return 0 if the pre-OS buffer uses up most of vram */ 954 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 955 return 0; 956 return size; 957 } 958 959 static int gmc_v7_0_sw_init(void *handle) 960 { 961 int r; 962 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 963 964 if (adev->flags & AMD_IS_APU) { 965 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 966 } else { 967 u32 tmp = RREG32(mmMC_SEQ_MISC0); 968 tmp &= MC_SEQ_MISC0__MT__MASK; 969 adev->gmc.vram_type = gmc_v7_0_convert_vram_type(tmp); 970 } 971 972 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault); 973 if (r) 974 return r; 975 976 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault); 977 if (r) 978 return r; 979 980 /* Adjust VM size here. 981 * Currently set to 4GB ((1 << 20) 4k pages). 982 * Max GPUVM size for cayman and SI is 40 bits. 983 */ 984 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); 985 986 /* Set the internal MC address mask 987 * This is the max address of the GPU's 988 * internal address space. 989 */ 990 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 991 992 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40)); 993 if (r) { 994 pr_warn("amdgpu: No suitable DMA available\n"); 995 return r; 996 } 997 adev->need_swiotlb = drm_need_swiotlb(40); 998 999 r = gmc_v7_0_init_microcode(adev); 1000 if (r) { 1001 DRM_ERROR("Failed to load mc firmware!\n"); 1002 return r; 1003 } 1004 1005 r = gmc_v7_0_mc_init(adev); 1006 if (r) 1007 return r; 1008 1009 adev->gmc.stolen_size = gmc_v7_0_get_vbios_fb_size(adev); 1010 1011 /* Memory manager */ 1012 r = amdgpu_bo_init(adev); 1013 if (r) 1014 return r; 1015 1016 r = gmc_v7_0_gart_init(adev); 1017 if (r) 1018 return r; 1019 1020 /* 1021 * number of VMs 1022 * VMID 0 is reserved for System 1023 * amdgpu graphics/compute will use VMIDs 1-7 1024 * amdkfd will use VMIDs 8-15 1025 */ 1026 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; 1027 amdgpu_vm_manager_init(adev); 1028 1029 /* base offset of vram pages */ 1030 if (adev->flags & AMD_IS_APU) { 1031 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 1032 1033 tmp <<= 22; 1034 adev->vm_manager.vram_base_offset = tmp; 1035 } else { 1036 adev->vm_manager.vram_base_offset = 0; 1037 } 1038 1039 adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info), 1040 GFP_KERNEL); 1041 if (!adev->gmc.vm_fault_info) 1042 return -ENOMEM; 1043 atomic_set(&adev->gmc.vm_fault_info_updated, 0); 1044 1045 return 0; 1046 } 1047 1048 static int gmc_v7_0_sw_fini(void *handle) 1049 { 1050 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1051 1052 amdgpu_gem_force_release(adev); 1053 amdgpu_vm_manager_fini(adev); 1054 kfree(adev->gmc.vm_fault_info); 1055 amdgpu_gart_table_vram_free(adev); 1056 amdgpu_bo_fini(adev); 1057 amdgpu_gart_fini(adev); 1058 release_firmware(adev->gmc.fw); 1059 adev->gmc.fw = NULL; 1060 1061 return 0; 1062 } 1063 1064 static int gmc_v7_0_hw_init(void *handle) 1065 { 1066 int r; 1067 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1068 1069 gmc_v7_0_init_golden_registers(adev); 1070 1071 gmc_v7_0_mc_program(adev); 1072 1073 if (!(adev->flags & AMD_IS_APU)) { 1074 r = gmc_v7_0_mc_load_microcode(adev); 1075 if (r) { 1076 DRM_ERROR("Failed to load MC firmware!\n"); 1077 return r; 1078 } 1079 } 1080 1081 r = gmc_v7_0_gart_enable(adev); 1082 if (r) 1083 return r; 1084 1085 return r; 1086 } 1087 1088 static int gmc_v7_0_hw_fini(void *handle) 1089 { 1090 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1091 1092 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1093 gmc_v7_0_gart_disable(adev); 1094 1095 return 0; 1096 } 1097 1098 static int gmc_v7_0_suspend(void *handle) 1099 { 1100 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1101 1102 gmc_v7_0_hw_fini(adev); 1103 1104 return 0; 1105 } 1106 1107 static int gmc_v7_0_resume(void *handle) 1108 { 1109 int r; 1110 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1111 1112 r = gmc_v7_0_hw_init(adev); 1113 if (r) 1114 return r; 1115 1116 amdgpu_vmid_reset_all(adev); 1117 1118 return 0; 1119 } 1120 1121 static bool gmc_v7_0_is_idle(void *handle) 1122 { 1123 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1124 u32 tmp = RREG32(mmSRBM_STATUS); 1125 1126 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1127 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 1128 return false; 1129 1130 return true; 1131 } 1132 1133 static int gmc_v7_0_wait_for_idle(void *handle) 1134 { 1135 unsigned i; 1136 u32 tmp; 1137 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1138 1139 for (i = 0; i < adev->usec_timeout; i++) { 1140 /* read MC_STATUS */ 1141 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | 1142 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1143 SRBM_STATUS__MCC_BUSY_MASK | 1144 SRBM_STATUS__MCD_BUSY_MASK | 1145 SRBM_STATUS__VMC_BUSY_MASK); 1146 if (!tmp) 1147 return 0; 1148 udelay(1); 1149 } 1150 return -ETIMEDOUT; 1151 1152 } 1153 1154 static int gmc_v7_0_soft_reset(void *handle) 1155 { 1156 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1157 u32 srbm_soft_reset = 0; 1158 u32 tmp = RREG32(mmSRBM_STATUS); 1159 1160 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1161 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1162 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 1163 1164 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1165 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 1166 if (!(adev->flags & AMD_IS_APU)) 1167 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1168 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1169 } 1170 1171 if (srbm_soft_reset) { 1172 gmc_v7_0_mc_stop(adev); 1173 if (gmc_v7_0_wait_for_idle((void *)adev)) { 1174 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1175 } 1176 1177 1178 tmp = RREG32(mmSRBM_SOFT_RESET); 1179 tmp |= srbm_soft_reset; 1180 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1181 WREG32(mmSRBM_SOFT_RESET, tmp); 1182 tmp = RREG32(mmSRBM_SOFT_RESET); 1183 1184 udelay(50); 1185 1186 tmp &= ~srbm_soft_reset; 1187 WREG32(mmSRBM_SOFT_RESET, tmp); 1188 tmp = RREG32(mmSRBM_SOFT_RESET); 1189 1190 /* Wait a little for things to settle down */ 1191 udelay(50); 1192 1193 gmc_v7_0_mc_resume(adev); 1194 udelay(50); 1195 } 1196 1197 return 0; 1198 } 1199 1200 static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1201 struct amdgpu_irq_src *src, 1202 unsigned type, 1203 enum amdgpu_interrupt_state state) 1204 { 1205 u32 tmp; 1206 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1207 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1208 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1209 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1210 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1211 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1212 1213 switch (state) { 1214 case AMDGPU_IRQ_STATE_DISABLE: 1215 /* system context */ 1216 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1217 tmp &= ~bits; 1218 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1219 /* VMs */ 1220 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1221 tmp &= ~bits; 1222 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1223 break; 1224 case AMDGPU_IRQ_STATE_ENABLE: 1225 /* system context */ 1226 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1227 tmp |= bits; 1228 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1229 /* VMs */ 1230 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1231 tmp |= bits; 1232 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1233 break; 1234 default: 1235 break; 1236 } 1237 1238 return 0; 1239 } 1240 1241 static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev, 1242 struct amdgpu_irq_src *source, 1243 struct amdgpu_iv_entry *entry) 1244 { 1245 u32 addr, status, mc_client, vmid; 1246 1247 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1248 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1249 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); 1250 /* reset addr and status */ 1251 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1252 1253 if (!addr && !status) 1254 return 0; 1255 1256 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1257 gmc_v7_0_set_fault_enable_default(adev, false); 1258 1259 if (printk_ratelimit()) { 1260 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1261 entry->src_id, entry->src_data[0]); 1262 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1263 addr); 1264 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1265 status); 1266 gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client, 1267 entry->pasid); 1268 } 1269 1270 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1271 VMID); 1272 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid) 1273 && !atomic_read(&adev->gmc.vm_fault_info_updated)) { 1274 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info; 1275 u32 protections = REG_GET_FIELD(status, 1276 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1277 PROTECTIONS); 1278 1279 info->vmid = vmid; 1280 info->mc_id = REG_GET_FIELD(status, 1281 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1282 MEMORY_CLIENT_ID); 1283 info->status = status; 1284 info->page_addr = addr; 1285 info->prot_valid = protections & 0x7 ? true : false; 1286 info->prot_read = protections & 0x8 ? true : false; 1287 info->prot_write = protections & 0x10 ? true : false; 1288 info->prot_exec = protections & 0x20 ? true : false; 1289 mb(); 1290 atomic_set(&adev->gmc.vm_fault_info_updated, 1); 1291 } 1292 1293 return 0; 1294 } 1295 1296 static int gmc_v7_0_set_clockgating_state(void *handle, 1297 enum amd_clockgating_state state) 1298 { 1299 bool gate = false; 1300 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1301 1302 if (state == AMD_CG_STATE_GATE) 1303 gate = true; 1304 1305 if (!(adev->flags & AMD_IS_APU)) { 1306 gmc_v7_0_enable_mc_mgcg(adev, gate); 1307 gmc_v7_0_enable_mc_ls(adev, gate); 1308 } 1309 gmc_v7_0_enable_bif_mgls(adev, gate); 1310 gmc_v7_0_enable_hdp_mgcg(adev, gate); 1311 gmc_v7_0_enable_hdp_ls(adev, gate); 1312 1313 return 0; 1314 } 1315 1316 static int gmc_v7_0_set_powergating_state(void *handle, 1317 enum amd_powergating_state state) 1318 { 1319 return 0; 1320 } 1321 1322 static const struct amd_ip_funcs gmc_v7_0_ip_funcs = { 1323 .name = "gmc_v7_0", 1324 .early_init = gmc_v7_0_early_init, 1325 .late_init = gmc_v7_0_late_init, 1326 .sw_init = gmc_v7_0_sw_init, 1327 .sw_fini = gmc_v7_0_sw_fini, 1328 .hw_init = gmc_v7_0_hw_init, 1329 .hw_fini = gmc_v7_0_hw_fini, 1330 .suspend = gmc_v7_0_suspend, 1331 .resume = gmc_v7_0_resume, 1332 .is_idle = gmc_v7_0_is_idle, 1333 .wait_for_idle = gmc_v7_0_wait_for_idle, 1334 .soft_reset = gmc_v7_0_soft_reset, 1335 .set_clockgating_state = gmc_v7_0_set_clockgating_state, 1336 .set_powergating_state = gmc_v7_0_set_powergating_state, 1337 }; 1338 1339 static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = { 1340 .flush_gpu_tlb = gmc_v7_0_flush_gpu_tlb, 1341 .emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb, 1342 .emit_pasid_mapping = gmc_v7_0_emit_pasid_mapping, 1343 .set_prt = gmc_v7_0_set_prt, 1344 .get_vm_pte_flags = gmc_v7_0_get_vm_pte_flags, 1345 .get_vm_pde = gmc_v7_0_get_vm_pde 1346 }; 1347 1348 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = { 1349 .set = gmc_v7_0_vm_fault_interrupt_state, 1350 .process = gmc_v7_0_process_interrupt, 1351 }; 1352 1353 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev) 1354 { 1355 adev->gmc.gmc_funcs = &gmc_v7_0_gmc_funcs; 1356 } 1357 1358 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev) 1359 { 1360 adev->gmc.vm_fault.num_types = 1; 1361 adev->gmc.vm_fault.funcs = &gmc_v7_0_irq_funcs; 1362 } 1363 1364 const struct amdgpu_ip_block_version gmc_v7_0_ip_block = 1365 { 1366 .type = AMD_IP_BLOCK_TYPE_GMC, 1367 .major = 7, 1368 .minor = 0, 1369 .rev = 0, 1370 .funcs = &gmc_v7_0_ip_funcs, 1371 }; 1372 1373 const struct amdgpu_ip_block_version gmc_v7_4_ip_block = 1374 { 1375 .type = AMD_IP_BLOCK_TYPE_GMC, 1376 .major = 7, 1377 .minor = 4, 1378 .rev = 0, 1379 .funcs = &gmc_v7_0_ip_funcs, 1380 }; 1381