1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <drm/drmP.h> 25 #include <drm/drm_cache.h> 26 #include "amdgpu.h" 27 #include "cikd.h" 28 #include "cik.h" 29 #include "gmc_v7_0.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_amdkfd.h" 32 #include "amdgpu_gem.h" 33 34 #include "bif/bif_4_1_d.h" 35 #include "bif/bif_4_1_sh_mask.h" 36 37 #include "gmc/gmc_7_1_d.h" 38 #include "gmc/gmc_7_1_sh_mask.h" 39 40 #include "oss/oss_2_0_d.h" 41 #include "oss/oss_2_0_sh_mask.h" 42 43 #include "dce/dce_8_0_d.h" 44 #include "dce/dce_8_0_sh_mask.h" 45 46 #include "amdgpu_atombios.h" 47 48 #include "ivsrcid/ivsrcid_vislands30.h" 49 50 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev); 51 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev); 52 static int gmc_v7_0_wait_for_idle(void *handle); 53 54 MODULE_FIRMWARE("amdgpu/bonaire_mc.bin"); 55 MODULE_FIRMWARE("amdgpu/hawaii_mc.bin"); 56 MODULE_FIRMWARE("amdgpu/topaz_mc.bin"); 57 58 static const u32 golden_settings_iceland_a11[] = 59 { 60 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 61 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 62 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 63 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 64 }; 65 66 static const u32 iceland_mgcg_cgcg_init[] = 67 { 68 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 69 }; 70 71 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev) 72 { 73 switch (adev->asic_type) { 74 case CHIP_TOPAZ: 75 amdgpu_device_program_register_sequence(adev, 76 iceland_mgcg_cgcg_init, 77 ARRAY_SIZE(iceland_mgcg_cgcg_init)); 78 amdgpu_device_program_register_sequence(adev, 79 golden_settings_iceland_a11, 80 ARRAY_SIZE(golden_settings_iceland_a11)); 81 break; 82 default: 83 break; 84 } 85 } 86 87 static void gmc_v7_0_mc_stop(struct amdgpu_device *adev) 88 { 89 u32 blackout; 90 91 gmc_v7_0_wait_for_idle((void *)adev); 92 93 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 94 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 95 /* Block CPU access */ 96 WREG32(mmBIF_FB_EN, 0); 97 /* blackout the MC */ 98 blackout = REG_SET_FIELD(blackout, 99 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 100 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); 101 } 102 /* wait for the MC to settle */ 103 udelay(100); 104 } 105 106 static void gmc_v7_0_mc_resume(struct amdgpu_device *adev) 107 { 108 u32 tmp; 109 110 /* unblackout the MC */ 111 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 112 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 113 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 114 /* allow CPU access */ 115 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 116 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 117 WREG32(mmBIF_FB_EN, tmp); 118 } 119 120 /** 121 * gmc_v7_0_init_microcode - load ucode images from disk 122 * 123 * @adev: amdgpu_device pointer 124 * 125 * Use the firmware interface to load the ucode images into 126 * the driver (not loaded into hw). 127 * Returns 0 on success, error on failure. 128 */ 129 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev) 130 { 131 const char *chip_name; 132 char fw_name[30]; 133 int err; 134 135 DRM_DEBUG("\n"); 136 137 switch (adev->asic_type) { 138 case CHIP_BONAIRE: 139 chip_name = "bonaire"; 140 break; 141 case CHIP_HAWAII: 142 chip_name = "hawaii"; 143 break; 144 case CHIP_TOPAZ: 145 chip_name = "topaz"; 146 break; 147 case CHIP_KAVERI: 148 case CHIP_KABINI: 149 case CHIP_MULLINS: 150 return 0; 151 default: BUG(); 152 } 153 154 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name); 155 156 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); 157 if (err) 158 goto out; 159 err = amdgpu_ucode_validate(adev->gmc.fw); 160 161 out: 162 if (err) { 163 pr_err("cik_mc: Failed to load firmware \"%s\"\n", fw_name); 164 release_firmware(adev->gmc.fw); 165 adev->gmc.fw = NULL; 166 } 167 return err; 168 } 169 170 /** 171 * gmc_v7_0_mc_load_microcode - load MC ucode into the hw 172 * 173 * @adev: amdgpu_device pointer 174 * 175 * Load the GDDR MC ucode into the hw (CIK). 176 * Returns 0 on success, error on failure. 177 */ 178 static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev) 179 { 180 const struct mc_firmware_header_v1_0 *hdr; 181 const __le32 *fw_data = NULL; 182 const __le32 *io_mc_regs = NULL; 183 u32 running; 184 int i, ucode_size, regs_size; 185 186 if (!adev->gmc.fw) 187 return -EINVAL; 188 189 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 190 amdgpu_ucode_print_mc_hdr(&hdr->header); 191 192 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 193 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 194 io_mc_regs = (const __le32 *) 195 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 196 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 197 fw_data = (const __le32 *) 198 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 199 200 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); 201 202 if (running == 0) { 203 /* reset the engine and set to writable */ 204 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 205 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 206 207 /* load mc io regs */ 208 for (i = 0; i < regs_size; i++) { 209 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 210 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 211 } 212 /* load the MC ucode */ 213 for (i = 0; i < ucode_size; i++) 214 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 215 216 /* put the engine back into the active state */ 217 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 218 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 219 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 220 221 /* wait for training to complete */ 222 for (i = 0; i < adev->usec_timeout; i++) { 223 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 224 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0)) 225 break; 226 udelay(1); 227 } 228 for (i = 0; i < adev->usec_timeout; i++) { 229 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 230 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1)) 231 break; 232 udelay(1); 233 } 234 } 235 236 return 0; 237 } 238 239 static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev, 240 struct amdgpu_gmc *mc) 241 { 242 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; 243 base <<= 24; 244 245 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 246 amdgpu_gmc_gart_location(adev, mc); 247 } 248 249 /** 250 * gmc_v7_0_mc_program - program the GPU memory controller 251 * 252 * @adev: amdgpu_device pointer 253 * 254 * Set the location of vram, gart, and AGP in the GPU's 255 * physical address space (CIK). 256 */ 257 static void gmc_v7_0_mc_program(struct amdgpu_device *adev) 258 { 259 u32 tmp; 260 int i, j; 261 262 /* Initialize HDP */ 263 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 264 WREG32((0xb05 + j), 0x00000000); 265 WREG32((0xb06 + j), 0x00000000); 266 WREG32((0xb07 + j), 0x00000000); 267 WREG32((0xb08 + j), 0x00000000); 268 WREG32((0xb09 + j), 0x00000000); 269 } 270 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 271 272 if (gmc_v7_0_wait_for_idle((void *)adev)) { 273 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 274 } 275 if (adev->mode_info.num_crtc) { 276 /* Lockout access through VGA aperture*/ 277 tmp = RREG32(mmVGA_HDP_CONTROL); 278 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 279 WREG32(mmVGA_HDP_CONTROL, tmp); 280 281 /* disable VGA render */ 282 tmp = RREG32(mmVGA_RENDER_CONTROL); 283 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 284 WREG32(mmVGA_RENDER_CONTROL, tmp); 285 } 286 /* Update configuration */ 287 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 288 adev->gmc.vram_start >> 12); 289 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 290 adev->gmc.vram_end >> 12); 291 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 292 adev->vram_scratch.gpu_addr >> 12); 293 WREG32(mmMC_VM_AGP_BASE, 0); 294 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); 295 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); 296 if (gmc_v7_0_wait_for_idle((void *)adev)) { 297 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 298 } 299 300 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 301 302 tmp = RREG32(mmHDP_MISC_CNTL); 303 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); 304 WREG32(mmHDP_MISC_CNTL, tmp); 305 306 tmp = RREG32(mmHDP_HOST_PATH_CNTL); 307 WREG32(mmHDP_HOST_PATH_CNTL, tmp); 308 } 309 310 /** 311 * gmc_v7_0_mc_init - initialize the memory controller driver params 312 * 313 * @adev: amdgpu_device pointer 314 * 315 * Look up the amount of vram, vram width, and decide how to place 316 * vram and gart within the GPU's physical address space (CIK). 317 * Returns 0 for success. 318 */ 319 static int gmc_v7_0_mc_init(struct amdgpu_device *adev) 320 { 321 int r; 322 323 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev); 324 if (!adev->gmc.vram_width) { 325 u32 tmp; 326 int chansize, numchan; 327 328 /* Get VRAM informations */ 329 tmp = RREG32(mmMC_ARB_RAMCFG); 330 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { 331 chansize = 64; 332 } else { 333 chansize = 32; 334 } 335 tmp = RREG32(mmMC_SHARED_CHMAP); 336 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 337 case 0: 338 default: 339 numchan = 1; 340 break; 341 case 1: 342 numchan = 2; 343 break; 344 case 2: 345 numchan = 4; 346 break; 347 case 3: 348 numchan = 8; 349 break; 350 case 4: 351 numchan = 3; 352 break; 353 case 5: 354 numchan = 6; 355 break; 356 case 6: 357 numchan = 10; 358 break; 359 case 7: 360 numchan = 12; 361 break; 362 case 8: 363 numchan = 16; 364 break; 365 } 366 adev->gmc.vram_width = numchan * chansize; 367 } 368 /* size in MB on si */ 369 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 370 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 371 372 if (!(adev->flags & AMD_IS_APU)) { 373 r = amdgpu_device_resize_fb_bar(adev); 374 if (r) 375 return r; 376 } 377 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 378 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 379 380 #ifdef CONFIG_X86_64 381 if (adev->flags & AMD_IS_APU) { 382 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; 383 adev->gmc.aper_size = adev->gmc.real_vram_size; 384 } 385 #endif 386 387 /* In case the PCI BAR is larger than the actual amount of vram */ 388 adev->gmc.visible_vram_size = adev->gmc.aper_size; 389 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 390 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 391 392 /* set the gart size */ 393 if (amdgpu_gart_size == -1) { 394 switch (adev->asic_type) { 395 case CHIP_TOPAZ: /* no MM engines */ 396 default: 397 adev->gmc.gart_size = 256ULL << 20; 398 break; 399 #ifdef CONFIG_DRM_AMDGPU_CIK 400 case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */ 401 case CHIP_HAWAII: /* UVD, VCE do not support GPUVM */ 402 case CHIP_KAVERI: /* UVD, VCE do not support GPUVM */ 403 case CHIP_KABINI: /* UVD, VCE do not support GPUVM */ 404 case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */ 405 adev->gmc.gart_size = 1024ULL << 20; 406 break; 407 #endif 408 } 409 } else { 410 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 411 } 412 413 gmc_v7_0_vram_gtt_location(adev, &adev->gmc); 414 415 return 0; 416 } 417 418 /* 419 * GART 420 * VMID 0 is the physical GPU addresses as used by the kernel. 421 * VMIDs 1-15 are used for userspace clients and are handled 422 * by the amdgpu vm/hsa code. 423 */ 424 425 /** 426 * gmc_v7_0_flush_gpu_tlb - gart tlb flush callback 427 * 428 * @adev: amdgpu_device pointer 429 * @vmid: vm instance to flush 430 * 431 * Flush the TLB for the requested page table (CIK). 432 */ 433 static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, 434 uint32_t vmid, uint32_t flush_type) 435 { 436 /* bits 0-15 are the VM contexts0-15 */ 437 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 438 } 439 440 static uint64_t gmc_v7_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 441 unsigned vmid, uint64_t pd_addr) 442 { 443 uint32_t reg; 444 445 if (vmid < 8) 446 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; 447 else 448 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8; 449 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); 450 451 /* bits 0-15 are the VM contexts0-15 */ 452 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); 453 454 return pd_addr; 455 } 456 457 static void gmc_v7_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 458 unsigned pasid) 459 { 460 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); 461 } 462 463 /** 464 * gmc_v7_0_set_pte_pde - update the page tables using MMIO 465 * 466 * @adev: amdgpu_device pointer 467 * @cpu_pt_addr: cpu address of the page table 468 * @gpu_page_idx: entry in the page table to update 469 * @addr: dst addr to write into pte/pde 470 * @flags: access flags 471 * 472 * Update the page tables using the CPU. 473 */ 474 static int gmc_v7_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 475 uint32_t gpu_page_idx, uint64_t addr, 476 uint64_t flags) 477 { 478 void __iomem *ptr = (void *)cpu_pt_addr; 479 uint64_t value; 480 481 value = addr & 0xFFFFFFFFFFFFF000ULL; 482 value |= flags; 483 writeq(value, ptr + (gpu_page_idx * 8)); 484 485 return 0; 486 } 487 488 static uint64_t gmc_v7_0_get_vm_pte_flags(struct amdgpu_device *adev, 489 uint32_t flags) 490 { 491 uint64_t pte_flag = 0; 492 493 if (flags & AMDGPU_VM_PAGE_READABLE) 494 pte_flag |= AMDGPU_PTE_READABLE; 495 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 496 pte_flag |= AMDGPU_PTE_WRITEABLE; 497 if (flags & AMDGPU_VM_PAGE_PRT) 498 pte_flag |= AMDGPU_PTE_PRT; 499 500 return pte_flag; 501 } 502 503 static void gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, int level, 504 uint64_t *addr, uint64_t *flags) 505 { 506 BUG_ON(*addr & 0xFFFFFF0000000FFFULL); 507 } 508 509 /** 510 * gmc_v8_0_set_fault_enable_default - update VM fault handling 511 * 512 * @adev: amdgpu_device pointer 513 * @value: true redirects VM faults to the default page 514 */ 515 static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev, 516 bool value) 517 { 518 u32 tmp; 519 520 tmp = RREG32(mmVM_CONTEXT1_CNTL); 521 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 522 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 523 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 524 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 525 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 526 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 527 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 528 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 529 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 530 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 531 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 532 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 533 WREG32(mmVM_CONTEXT1_CNTL, tmp); 534 } 535 536 /** 537 * gmc_v7_0_set_prt - set PRT VM fault 538 * 539 * @adev: amdgpu_device pointer 540 * @enable: enable/disable VM fault handling for PRT 541 */ 542 static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable) 543 { 544 uint32_t tmp; 545 546 if (enable && !adev->gmc.prt_warning) { 547 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 548 adev->gmc.prt_warning = true; 549 } 550 551 tmp = RREG32(mmVM_PRT_CNTL); 552 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 553 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 554 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 555 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 556 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 557 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 558 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 559 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 560 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 561 L2_CACHE_STORE_INVALID_ENTRIES, enable); 562 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 563 L1_TLB_STORE_INVALID_ENTRIES, enable); 564 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 565 MASK_PDE0_FAULT, enable); 566 WREG32(mmVM_PRT_CNTL, tmp); 567 568 if (enable) { 569 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; 570 uint32_t high = adev->vm_manager.max_pfn - 571 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT); 572 573 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); 574 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); 575 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); 576 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); 577 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); 578 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); 579 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); 580 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); 581 } else { 582 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); 583 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); 584 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); 585 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); 586 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); 587 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); 588 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); 589 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); 590 } 591 } 592 593 /** 594 * gmc_v7_0_gart_enable - gart enable 595 * 596 * @adev: amdgpu_device pointer 597 * 598 * This sets up the TLBs, programs the page tables for VMID0, 599 * sets up the hw for VMIDs 1-15 which are allocated on 600 * demand, and sets up the global locations for the LDS, GDS, 601 * and GPUVM for FSA64 clients (CIK). 602 * Returns 0 for success, errors for failure. 603 */ 604 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev) 605 { 606 uint64_t table_addr; 607 int r, i; 608 u32 tmp, field; 609 610 if (adev->gart.bo == NULL) { 611 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 612 return -EINVAL; 613 } 614 r = amdgpu_gart_table_vram_pin(adev); 615 if (r) 616 return r; 617 618 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 619 620 /* Setup TLB control */ 621 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 622 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 623 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); 624 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 625 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); 626 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 627 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 628 /* Setup L2 cache */ 629 tmp = RREG32(mmVM_L2_CNTL); 630 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 631 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 632 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); 633 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); 634 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); 635 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 636 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 637 WREG32(mmVM_L2_CNTL, tmp); 638 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 639 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 640 WREG32(mmVM_L2_CNTL2, tmp); 641 642 field = adev->vm_manager.fragment_size; 643 tmp = RREG32(mmVM_L2_CNTL3); 644 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); 645 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); 646 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); 647 WREG32(mmVM_L2_CNTL3, tmp); 648 /* setup context0 */ 649 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); 650 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); 651 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12); 652 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 653 (u32)(adev->dummy_page_addr >> 12)); 654 WREG32(mmVM_CONTEXT0_CNTL2, 0); 655 tmp = RREG32(mmVM_CONTEXT0_CNTL); 656 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 657 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 658 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 659 WREG32(mmVM_CONTEXT0_CNTL, tmp); 660 661 WREG32(0x575, 0); 662 WREG32(0x576, 0); 663 WREG32(0x577, 0); 664 665 /* empty context1-15 */ 666 /* FIXME start with 4G, once using 2 level pt switch to full 667 * vm size space 668 */ 669 /* set vm size, must be a multiple of 4 */ 670 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 671 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 672 for (i = 1; i < 16; i++) { 673 if (i < 8) 674 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 675 table_addr >> 12); 676 else 677 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 678 table_addr >> 12); 679 } 680 681 /* enable context1-15 */ 682 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 683 (u32)(adev->dummy_page_addr >> 12)); 684 WREG32(mmVM_CONTEXT1_CNTL2, 4); 685 tmp = RREG32(mmVM_CONTEXT1_CNTL); 686 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 687 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); 688 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, 689 adev->vm_manager.block_size - 9); 690 WREG32(mmVM_CONTEXT1_CNTL, tmp); 691 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 692 gmc_v7_0_set_fault_enable_default(adev, false); 693 else 694 gmc_v7_0_set_fault_enable_default(adev, true); 695 696 if (adev->asic_type == CHIP_KAVERI) { 697 tmp = RREG32(mmCHUB_CONTROL); 698 tmp &= ~BYPASS_VM; 699 WREG32(mmCHUB_CONTROL, tmp); 700 } 701 702 gmc_v7_0_flush_gpu_tlb(adev, 0, 0); 703 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 704 (unsigned)(adev->gmc.gart_size >> 20), 705 (unsigned long long)table_addr); 706 adev->gart.ready = true; 707 return 0; 708 } 709 710 static int gmc_v7_0_gart_init(struct amdgpu_device *adev) 711 { 712 int r; 713 714 if (adev->gart.bo) { 715 WARN(1, "R600 PCIE GART already initialized\n"); 716 return 0; 717 } 718 /* Initialize common gart structure */ 719 r = amdgpu_gart_init(adev); 720 if (r) 721 return r; 722 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 723 adev->gart.gart_pte_flags = 0; 724 return amdgpu_gart_table_vram_alloc(adev); 725 } 726 727 /** 728 * gmc_v7_0_gart_disable - gart disable 729 * 730 * @adev: amdgpu_device pointer 731 * 732 * This disables all VM page table (CIK). 733 */ 734 static void gmc_v7_0_gart_disable(struct amdgpu_device *adev) 735 { 736 u32 tmp; 737 738 /* Disable all tables */ 739 WREG32(mmVM_CONTEXT0_CNTL, 0); 740 WREG32(mmVM_CONTEXT1_CNTL, 0); 741 /* Setup TLB control */ 742 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 743 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 744 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); 745 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); 746 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 747 /* Setup L2 cache */ 748 tmp = RREG32(mmVM_L2_CNTL); 749 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 750 WREG32(mmVM_L2_CNTL, tmp); 751 WREG32(mmVM_L2_CNTL2, 0); 752 amdgpu_gart_table_vram_unpin(adev); 753 } 754 755 /** 756 * gmc_v7_0_vm_decode_fault - print human readable fault info 757 * 758 * @adev: amdgpu_device pointer 759 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value 760 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value 761 * 762 * Print human readable fault information (CIK). 763 */ 764 static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev, u32 status, 765 u32 addr, u32 mc_client, unsigned pasid) 766 { 767 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 768 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 769 PROTECTIONS); 770 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 771 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 772 u32 mc_id; 773 774 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 775 MEMORY_CLIENT_ID); 776 777 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 778 protections, vmid, pasid, addr, 779 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 780 MEMORY_CLIENT_RW) ? 781 "write" : "read", block, mc_client, mc_id); 782 } 783 784 785 static const u32 mc_cg_registers[] = { 786 mmMC_HUB_MISC_HUB_CG, 787 mmMC_HUB_MISC_SIP_CG, 788 mmMC_HUB_MISC_VM_CG, 789 mmMC_XPB_CLK_GAT, 790 mmATC_MISC_CG, 791 mmMC_CITF_MISC_WR_CG, 792 mmMC_CITF_MISC_RD_CG, 793 mmMC_CITF_MISC_VM_CG, 794 mmVM_L2_CG, 795 }; 796 797 static const u32 mc_cg_ls_en[] = { 798 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK, 799 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK, 800 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK, 801 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK, 802 ATC_MISC_CG__MEM_LS_ENABLE_MASK, 803 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK, 804 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK, 805 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK, 806 VM_L2_CG__MEM_LS_ENABLE_MASK, 807 }; 808 809 static const u32 mc_cg_en[] = { 810 MC_HUB_MISC_HUB_CG__ENABLE_MASK, 811 MC_HUB_MISC_SIP_CG__ENABLE_MASK, 812 MC_HUB_MISC_VM_CG__ENABLE_MASK, 813 MC_XPB_CLK_GAT__ENABLE_MASK, 814 ATC_MISC_CG__ENABLE_MASK, 815 MC_CITF_MISC_WR_CG__ENABLE_MASK, 816 MC_CITF_MISC_RD_CG__ENABLE_MASK, 817 MC_CITF_MISC_VM_CG__ENABLE_MASK, 818 VM_L2_CG__ENABLE_MASK, 819 }; 820 821 static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev, 822 bool enable) 823 { 824 int i; 825 u32 orig, data; 826 827 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 828 orig = data = RREG32(mc_cg_registers[i]); 829 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) 830 data |= mc_cg_ls_en[i]; 831 else 832 data &= ~mc_cg_ls_en[i]; 833 if (data != orig) 834 WREG32(mc_cg_registers[i], data); 835 } 836 } 837 838 static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev, 839 bool enable) 840 { 841 int i; 842 u32 orig, data; 843 844 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 845 orig = data = RREG32(mc_cg_registers[i]); 846 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) 847 data |= mc_cg_en[i]; 848 else 849 data &= ~mc_cg_en[i]; 850 if (data != orig) 851 WREG32(mc_cg_registers[i], data); 852 } 853 } 854 855 static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev, 856 bool enable) 857 { 858 u32 orig, data; 859 860 orig = data = RREG32_PCIE(ixPCIE_CNTL2); 861 862 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 863 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1); 864 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1); 865 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1); 866 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1); 867 } else { 868 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0); 869 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0); 870 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0); 871 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0); 872 } 873 874 if (orig != data) 875 WREG32_PCIE(ixPCIE_CNTL2, data); 876 } 877 878 static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev, 879 bool enable) 880 { 881 u32 orig, data; 882 883 orig = data = RREG32(mmHDP_HOST_PATH_CNTL); 884 885 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 886 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0); 887 else 888 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1); 889 890 if (orig != data) 891 WREG32(mmHDP_HOST_PATH_CNTL, data); 892 } 893 894 static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev, 895 bool enable) 896 { 897 u32 orig, data; 898 899 orig = data = RREG32(mmHDP_MEM_POWER_LS); 900 901 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 902 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1); 903 else 904 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0); 905 906 if (orig != data) 907 WREG32(mmHDP_MEM_POWER_LS, data); 908 } 909 910 static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type) 911 { 912 switch (mc_seq_vram_type) { 913 case MC_SEQ_MISC0__MT__GDDR1: 914 return AMDGPU_VRAM_TYPE_GDDR1; 915 case MC_SEQ_MISC0__MT__DDR2: 916 return AMDGPU_VRAM_TYPE_DDR2; 917 case MC_SEQ_MISC0__MT__GDDR3: 918 return AMDGPU_VRAM_TYPE_GDDR3; 919 case MC_SEQ_MISC0__MT__GDDR4: 920 return AMDGPU_VRAM_TYPE_GDDR4; 921 case MC_SEQ_MISC0__MT__GDDR5: 922 return AMDGPU_VRAM_TYPE_GDDR5; 923 case MC_SEQ_MISC0__MT__HBM: 924 return AMDGPU_VRAM_TYPE_HBM; 925 case MC_SEQ_MISC0__MT__DDR3: 926 return AMDGPU_VRAM_TYPE_DDR3; 927 default: 928 return AMDGPU_VRAM_TYPE_UNKNOWN; 929 } 930 } 931 932 static int gmc_v7_0_early_init(void *handle) 933 { 934 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 935 936 gmc_v7_0_set_gmc_funcs(adev); 937 gmc_v7_0_set_irq_funcs(adev); 938 939 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 940 adev->gmc.shared_aperture_end = 941 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 942 adev->gmc.private_aperture_start = 943 adev->gmc.shared_aperture_end + 1; 944 adev->gmc.private_aperture_end = 945 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 946 947 return 0; 948 } 949 950 static int gmc_v7_0_late_init(void *handle) 951 { 952 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 953 954 amdgpu_bo_late_init(adev); 955 956 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 957 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 958 else 959 return 0; 960 } 961 962 static unsigned gmc_v7_0_get_vbios_fb_size(struct amdgpu_device *adev) 963 { 964 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); 965 unsigned size; 966 967 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 968 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */ 969 } else { 970 u32 viewport = RREG32(mmVIEWPORT_SIZE); 971 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 972 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * 973 4); 974 } 975 /* return 0 if the pre-OS buffer uses up most of vram */ 976 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 977 return 0; 978 return size; 979 } 980 981 static int gmc_v7_0_sw_init(void *handle) 982 { 983 int r; 984 int dma_bits; 985 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 986 987 if (adev->flags & AMD_IS_APU) { 988 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 989 } else { 990 u32 tmp = RREG32(mmMC_SEQ_MISC0); 991 tmp &= MC_SEQ_MISC0__MT__MASK; 992 adev->gmc.vram_type = gmc_v7_0_convert_vram_type(tmp); 993 } 994 995 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault); 996 if (r) 997 return r; 998 999 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault); 1000 if (r) 1001 return r; 1002 1003 /* Adjust VM size here. 1004 * Currently set to 4GB ((1 << 20) 4k pages). 1005 * Max GPUVM size for cayman and SI is 40 bits. 1006 */ 1007 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); 1008 1009 /* Set the internal MC address mask 1010 * This is the max address of the GPU's 1011 * internal address space. 1012 */ 1013 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1014 1015 /* set DMA mask + need_dma32 flags. 1016 * PCIE - can handle 40-bits. 1017 * IGP - can handle 40-bits 1018 * PCI - dma32 for legacy pci gart, 40 bits on newer asics 1019 */ 1020 adev->need_dma32 = false; 1021 dma_bits = adev->need_dma32 ? 32 : 40; 1022 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 1023 if (r) { 1024 adev->need_dma32 = true; 1025 dma_bits = 32; 1026 pr_warn("amdgpu: No suitable DMA available\n"); 1027 } 1028 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 1029 if (r) { 1030 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); 1031 pr_warn("amdgpu: No coherent DMA available\n"); 1032 } 1033 adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits); 1034 1035 r = gmc_v7_0_init_microcode(adev); 1036 if (r) { 1037 DRM_ERROR("Failed to load mc firmware!\n"); 1038 return r; 1039 } 1040 1041 r = gmc_v7_0_mc_init(adev); 1042 if (r) 1043 return r; 1044 1045 adev->gmc.stolen_size = gmc_v7_0_get_vbios_fb_size(adev); 1046 1047 /* Memory manager */ 1048 r = amdgpu_bo_init(adev); 1049 if (r) 1050 return r; 1051 1052 r = gmc_v7_0_gart_init(adev); 1053 if (r) 1054 return r; 1055 1056 /* 1057 * number of VMs 1058 * VMID 0 is reserved for System 1059 * amdgpu graphics/compute will use VMIDs 1-7 1060 * amdkfd will use VMIDs 8-15 1061 */ 1062 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; 1063 amdgpu_vm_manager_init(adev); 1064 1065 /* base offset of vram pages */ 1066 if (adev->flags & AMD_IS_APU) { 1067 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 1068 1069 tmp <<= 22; 1070 adev->vm_manager.vram_base_offset = tmp; 1071 } else { 1072 adev->vm_manager.vram_base_offset = 0; 1073 } 1074 1075 adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info), 1076 GFP_KERNEL); 1077 if (!adev->gmc.vm_fault_info) 1078 return -ENOMEM; 1079 atomic_set(&adev->gmc.vm_fault_info_updated, 0); 1080 1081 return 0; 1082 } 1083 1084 static int gmc_v7_0_sw_fini(void *handle) 1085 { 1086 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1087 1088 amdgpu_gem_force_release(adev); 1089 amdgpu_vm_manager_fini(adev); 1090 kfree(adev->gmc.vm_fault_info); 1091 amdgpu_gart_table_vram_free(adev); 1092 amdgpu_bo_fini(adev); 1093 amdgpu_gart_fini(adev); 1094 release_firmware(adev->gmc.fw); 1095 adev->gmc.fw = NULL; 1096 1097 return 0; 1098 } 1099 1100 static int gmc_v7_0_hw_init(void *handle) 1101 { 1102 int r; 1103 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1104 1105 gmc_v7_0_init_golden_registers(adev); 1106 1107 gmc_v7_0_mc_program(adev); 1108 1109 if (!(adev->flags & AMD_IS_APU)) { 1110 r = gmc_v7_0_mc_load_microcode(adev); 1111 if (r) { 1112 DRM_ERROR("Failed to load MC firmware!\n"); 1113 return r; 1114 } 1115 } 1116 1117 r = gmc_v7_0_gart_enable(adev); 1118 if (r) 1119 return r; 1120 1121 return r; 1122 } 1123 1124 static int gmc_v7_0_hw_fini(void *handle) 1125 { 1126 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1127 1128 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1129 gmc_v7_0_gart_disable(adev); 1130 1131 return 0; 1132 } 1133 1134 static int gmc_v7_0_suspend(void *handle) 1135 { 1136 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1137 1138 gmc_v7_0_hw_fini(adev); 1139 1140 return 0; 1141 } 1142 1143 static int gmc_v7_0_resume(void *handle) 1144 { 1145 int r; 1146 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1147 1148 r = gmc_v7_0_hw_init(adev); 1149 if (r) 1150 return r; 1151 1152 amdgpu_vmid_reset_all(adev); 1153 1154 return 0; 1155 } 1156 1157 static bool gmc_v7_0_is_idle(void *handle) 1158 { 1159 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1160 u32 tmp = RREG32(mmSRBM_STATUS); 1161 1162 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1163 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 1164 return false; 1165 1166 return true; 1167 } 1168 1169 static int gmc_v7_0_wait_for_idle(void *handle) 1170 { 1171 unsigned i; 1172 u32 tmp; 1173 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1174 1175 for (i = 0; i < adev->usec_timeout; i++) { 1176 /* read MC_STATUS */ 1177 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | 1178 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1179 SRBM_STATUS__MCC_BUSY_MASK | 1180 SRBM_STATUS__MCD_BUSY_MASK | 1181 SRBM_STATUS__VMC_BUSY_MASK); 1182 if (!tmp) 1183 return 0; 1184 udelay(1); 1185 } 1186 return -ETIMEDOUT; 1187 1188 } 1189 1190 static int gmc_v7_0_soft_reset(void *handle) 1191 { 1192 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1193 u32 srbm_soft_reset = 0; 1194 u32 tmp = RREG32(mmSRBM_STATUS); 1195 1196 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1197 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1198 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 1199 1200 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1201 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 1202 if (!(adev->flags & AMD_IS_APU)) 1203 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1204 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1205 } 1206 1207 if (srbm_soft_reset) { 1208 gmc_v7_0_mc_stop(adev); 1209 if (gmc_v7_0_wait_for_idle((void *)adev)) { 1210 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1211 } 1212 1213 1214 tmp = RREG32(mmSRBM_SOFT_RESET); 1215 tmp |= srbm_soft_reset; 1216 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1217 WREG32(mmSRBM_SOFT_RESET, tmp); 1218 tmp = RREG32(mmSRBM_SOFT_RESET); 1219 1220 udelay(50); 1221 1222 tmp &= ~srbm_soft_reset; 1223 WREG32(mmSRBM_SOFT_RESET, tmp); 1224 tmp = RREG32(mmSRBM_SOFT_RESET); 1225 1226 /* Wait a little for things to settle down */ 1227 udelay(50); 1228 1229 gmc_v7_0_mc_resume(adev); 1230 udelay(50); 1231 } 1232 1233 return 0; 1234 } 1235 1236 static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1237 struct amdgpu_irq_src *src, 1238 unsigned type, 1239 enum amdgpu_interrupt_state state) 1240 { 1241 u32 tmp; 1242 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1243 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1244 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1245 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1246 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1247 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1248 1249 switch (state) { 1250 case AMDGPU_IRQ_STATE_DISABLE: 1251 /* system context */ 1252 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1253 tmp &= ~bits; 1254 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1255 /* VMs */ 1256 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1257 tmp &= ~bits; 1258 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1259 break; 1260 case AMDGPU_IRQ_STATE_ENABLE: 1261 /* system context */ 1262 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1263 tmp |= bits; 1264 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1265 /* VMs */ 1266 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1267 tmp |= bits; 1268 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1269 break; 1270 default: 1271 break; 1272 } 1273 1274 return 0; 1275 } 1276 1277 static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev, 1278 struct amdgpu_irq_src *source, 1279 struct amdgpu_iv_entry *entry) 1280 { 1281 u32 addr, status, mc_client, vmid; 1282 1283 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1284 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1285 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); 1286 /* reset addr and status */ 1287 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1288 1289 if (!addr && !status) 1290 return 0; 1291 1292 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1293 gmc_v7_0_set_fault_enable_default(adev, false); 1294 1295 if (printk_ratelimit()) { 1296 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1297 entry->src_id, entry->src_data[0]); 1298 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1299 addr); 1300 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1301 status); 1302 gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client, 1303 entry->pasid); 1304 } 1305 1306 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1307 VMID); 1308 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid) 1309 && !atomic_read(&adev->gmc.vm_fault_info_updated)) { 1310 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info; 1311 u32 protections = REG_GET_FIELD(status, 1312 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1313 PROTECTIONS); 1314 1315 info->vmid = vmid; 1316 info->mc_id = REG_GET_FIELD(status, 1317 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1318 MEMORY_CLIENT_ID); 1319 info->status = status; 1320 info->page_addr = addr; 1321 info->prot_valid = protections & 0x7 ? true : false; 1322 info->prot_read = protections & 0x8 ? true : false; 1323 info->prot_write = protections & 0x10 ? true : false; 1324 info->prot_exec = protections & 0x20 ? true : false; 1325 mb(); 1326 atomic_set(&adev->gmc.vm_fault_info_updated, 1); 1327 } 1328 1329 return 0; 1330 } 1331 1332 static int gmc_v7_0_set_clockgating_state(void *handle, 1333 enum amd_clockgating_state state) 1334 { 1335 bool gate = false; 1336 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1337 1338 if (state == AMD_CG_STATE_GATE) 1339 gate = true; 1340 1341 if (!(adev->flags & AMD_IS_APU)) { 1342 gmc_v7_0_enable_mc_mgcg(adev, gate); 1343 gmc_v7_0_enable_mc_ls(adev, gate); 1344 } 1345 gmc_v7_0_enable_bif_mgls(adev, gate); 1346 gmc_v7_0_enable_hdp_mgcg(adev, gate); 1347 gmc_v7_0_enable_hdp_ls(adev, gate); 1348 1349 return 0; 1350 } 1351 1352 static int gmc_v7_0_set_powergating_state(void *handle, 1353 enum amd_powergating_state state) 1354 { 1355 return 0; 1356 } 1357 1358 static const struct amd_ip_funcs gmc_v7_0_ip_funcs = { 1359 .name = "gmc_v7_0", 1360 .early_init = gmc_v7_0_early_init, 1361 .late_init = gmc_v7_0_late_init, 1362 .sw_init = gmc_v7_0_sw_init, 1363 .sw_fini = gmc_v7_0_sw_fini, 1364 .hw_init = gmc_v7_0_hw_init, 1365 .hw_fini = gmc_v7_0_hw_fini, 1366 .suspend = gmc_v7_0_suspend, 1367 .resume = gmc_v7_0_resume, 1368 .is_idle = gmc_v7_0_is_idle, 1369 .wait_for_idle = gmc_v7_0_wait_for_idle, 1370 .soft_reset = gmc_v7_0_soft_reset, 1371 .set_clockgating_state = gmc_v7_0_set_clockgating_state, 1372 .set_powergating_state = gmc_v7_0_set_powergating_state, 1373 }; 1374 1375 static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = { 1376 .flush_gpu_tlb = gmc_v7_0_flush_gpu_tlb, 1377 .emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb, 1378 .emit_pasid_mapping = gmc_v7_0_emit_pasid_mapping, 1379 .set_pte_pde = gmc_v7_0_set_pte_pde, 1380 .set_prt = gmc_v7_0_set_prt, 1381 .get_vm_pte_flags = gmc_v7_0_get_vm_pte_flags, 1382 .get_vm_pde = gmc_v7_0_get_vm_pde 1383 }; 1384 1385 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = { 1386 .set = gmc_v7_0_vm_fault_interrupt_state, 1387 .process = gmc_v7_0_process_interrupt, 1388 }; 1389 1390 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev) 1391 { 1392 adev->gmc.gmc_funcs = &gmc_v7_0_gmc_funcs; 1393 } 1394 1395 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev) 1396 { 1397 adev->gmc.vm_fault.num_types = 1; 1398 adev->gmc.vm_fault.funcs = &gmc_v7_0_irq_funcs; 1399 } 1400 1401 const struct amdgpu_ip_block_version gmc_v7_0_ip_block = 1402 { 1403 .type = AMD_IP_BLOCK_TYPE_GMC, 1404 .major = 7, 1405 .minor = 0, 1406 .rev = 0, 1407 .funcs = &gmc_v7_0_ip_funcs, 1408 }; 1409 1410 const struct amdgpu_ip_block_version gmc_v7_4_ip_block = 1411 { 1412 .type = AMD_IP_BLOCK_TYPE_GMC, 1413 .major = 7, 1414 .minor = 4, 1415 .rev = 0, 1416 .funcs = &gmc_v7_0_ip_funcs, 1417 }; 1418