1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <drm/drmP.h> 25 #include <drm/drm_cache.h> 26 #include "amdgpu.h" 27 #include "cikd.h" 28 #include "cik.h" 29 #include "gmc_v7_0.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_amdkfd.h" 32 #include "amdgpu_gem.h" 33 34 #include "bif/bif_4_1_d.h" 35 #include "bif/bif_4_1_sh_mask.h" 36 37 #include "gmc/gmc_7_1_d.h" 38 #include "gmc/gmc_7_1_sh_mask.h" 39 40 #include "oss/oss_2_0_d.h" 41 #include "oss/oss_2_0_sh_mask.h" 42 43 #include "dce/dce_8_0_d.h" 44 #include "dce/dce_8_0_sh_mask.h" 45 46 #include "amdgpu_atombios.h" 47 48 #include "ivsrcid/ivsrcid_vislands30.h" 49 50 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev); 51 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev); 52 static int gmc_v7_0_wait_for_idle(void *handle); 53 54 MODULE_FIRMWARE("amdgpu/bonaire_mc.bin"); 55 MODULE_FIRMWARE("amdgpu/hawaii_mc.bin"); 56 MODULE_FIRMWARE("amdgpu/topaz_mc.bin"); 57 58 static const u32 golden_settings_iceland_a11[] = 59 { 60 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 61 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 62 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 63 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 64 }; 65 66 static const u32 iceland_mgcg_cgcg_init[] = 67 { 68 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 69 }; 70 71 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev) 72 { 73 switch (adev->asic_type) { 74 case CHIP_TOPAZ: 75 amdgpu_device_program_register_sequence(adev, 76 iceland_mgcg_cgcg_init, 77 ARRAY_SIZE(iceland_mgcg_cgcg_init)); 78 amdgpu_device_program_register_sequence(adev, 79 golden_settings_iceland_a11, 80 ARRAY_SIZE(golden_settings_iceland_a11)); 81 break; 82 default: 83 break; 84 } 85 } 86 87 static void gmc_v7_0_mc_stop(struct amdgpu_device *adev) 88 { 89 u32 blackout; 90 91 gmc_v7_0_wait_for_idle((void *)adev); 92 93 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 94 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 95 /* Block CPU access */ 96 WREG32(mmBIF_FB_EN, 0); 97 /* blackout the MC */ 98 blackout = REG_SET_FIELD(blackout, 99 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 100 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); 101 } 102 /* wait for the MC to settle */ 103 udelay(100); 104 } 105 106 static void gmc_v7_0_mc_resume(struct amdgpu_device *adev) 107 { 108 u32 tmp; 109 110 /* unblackout the MC */ 111 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 112 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 113 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 114 /* allow CPU access */ 115 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 116 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 117 WREG32(mmBIF_FB_EN, tmp); 118 } 119 120 /** 121 * gmc_v7_0_init_microcode - load ucode images from disk 122 * 123 * @adev: amdgpu_device pointer 124 * 125 * Use the firmware interface to load the ucode images into 126 * the driver (not loaded into hw). 127 * Returns 0 on success, error on failure. 128 */ 129 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev) 130 { 131 const char *chip_name; 132 char fw_name[30]; 133 int err; 134 135 DRM_DEBUG("\n"); 136 137 switch (adev->asic_type) { 138 case CHIP_BONAIRE: 139 chip_name = "bonaire"; 140 break; 141 case CHIP_HAWAII: 142 chip_name = "hawaii"; 143 break; 144 case CHIP_TOPAZ: 145 chip_name = "topaz"; 146 break; 147 case CHIP_KAVERI: 148 case CHIP_KABINI: 149 case CHIP_MULLINS: 150 return 0; 151 default: BUG(); 152 } 153 154 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name); 155 156 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); 157 if (err) 158 goto out; 159 err = amdgpu_ucode_validate(adev->gmc.fw); 160 161 out: 162 if (err) { 163 pr_err("cik_mc: Failed to load firmware \"%s\"\n", fw_name); 164 release_firmware(adev->gmc.fw); 165 adev->gmc.fw = NULL; 166 } 167 return err; 168 } 169 170 /** 171 * gmc_v7_0_mc_load_microcode - load MC ucode into the hw 172 * 173 * @adev: amdgpu_device pointer 174 * 175 * Load the GDDR MC ucode into the hw (CIK). 176 * Returns 0 on success, error on failure. 177 */ 178 static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev) 179 { 180 const struct mc_firmware_header_v1_0 *hdr; 181 const __le32 *fw_data = NULL; 182 const __le32 *io_mc_regs = NULL; 183 u32 running; 184 int i, ucode_size, regs_size; 185 186 if (!adev->gmc.fw) 187 return -EINVAL; 188 189 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 190 amdgpu_ucode_print_mc_hdr(&hdr->header); 191 192 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 193 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 194 io_mc_regs = (const __le32 *) 195 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 196 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 197 fw_data = (const __le32 *) 198 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 199 200 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); 201 202 if (running == 0) { 203 /* reset the engine and set to writable */ 204 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 205 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 206 207 /* load mc io regs */ 208 for (i = 0; i < regs_size; i++) { 209 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 210 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 211 } 212 /* load the MC ucode */ 213 for (i = 0; i < ucode_size; i++) 214 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 215 216 /* put the engine back into the active state */ 217 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 218 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 219 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 220 221 /* wait for training to complete */ 222 for (i = 0; i < adev->usec_timeout; i++) { 223 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 224 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0)) 225 break; 226 udelay(1); 227 } 228 for (i = 0; i < adev->usec_timeout; i++) { 229 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 230 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1)) 231 break; 232 udelay(1); 233 } 234 } 235 236 return 0; 237 } 238 239 static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev, 240 struct amdgpu_gmc *mc) 241 { 242 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; 243 base <<= 24; 244 245 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 246 amdgpu_gmc_gart_location(adev, mc); 247 } 248 249 /** 250 * gmc_v7_0_mc_program - program the GPU memory controller 251 * 252 * @adev: amdgpu_device pointer 253 * 254 * Set the location of vram, gart, and AGP in the GPU's 255 * physical address space (CIK). 256 */ 257 static void gmc_v7_0_mc_program(struct amdgpu_device *adev) 258 { 259 u32 tmp; 260 int i, j; 261 262 /* Initialize HDP */ 263 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 264 WREG32((0xb05 + j), 0x00000000); 265 WREG32((0xb06 + j), 0x00000000); 266 WREG32((0xb07 + j), 0x00000000); 267 WREG32((0xb08 + j), 0x00000000); 268 WREG32((0xb09 + j), 0x00000000); 269 } 270 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 271 272 if (gmc_v7_0_wait_for_idle((void *)adev)) { 273 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 274 } 275 if (adev->mode_info.num_crtc) { 276 /* Lockout access through VGA aperture*/ 277 tmp = RREG32(mmVGA_HDP_CONTROL); 278 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 279 WREG32(mmVGA_HDP_CONTROL, tmp); 280 281 /* disable VGA render */ 282 tmp = RREG32(mmVGA_RENDER_CONTROL); 283 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 284 WREG32(mmVGA_RENDER_CONTROL, tmp); 285 } 286 /* Update configuration */ 287 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 288 adev->gmc.vram_start >> 12); 289 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 290 adev->gmc.vram_end >> 12); 291 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 292 adev->vram_scratch.gpu_addr >> 12); 293 WREG32(mmMC_VM_AGP_BASE, 0); 294 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); 295 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); 296 if (gmc_v7_0_wait_for_idle((void *)adev)) { 297 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 298 } 299 300 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 301 302 tmp = RREG32(mmHDP_MISC_CNTL); 303 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); 304 WREG32(mmHDP_MISC_CNTL, tmp); 305 306 tmp = RREG32(mmHDP_HOST_PATH_CNTL); 307 WREG32(mmHDP_HOST_PATH_CNTL, tmp); 308 } 309 310 /** 311 * gmc_v7_0_mc_init - initialize the memory controller driver params 312 * 313 * @adev: amdgpu_device pointer 314 * 315 * Look up the amount of vram, vram width, and decide how to place 316 * vram and gart within the GPU's physical address space (CIK). 317 * Returns 0 for success. 318 */ 319 static int gmc_v7_0_mc_init(struct amdgpu_device *adev) 320 { 321 int r; 322 323 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev); 324 if (!adev->gmc.vram_width) { 325 u32 tmp; 326 int chansize, numchan; 327 328 /* Get VRAM informations */ 329 tmp = RREG32(mmMC_ARB_RAMCFG); 330 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { 331 chansize = 64; 332 } else { 333 chansize = 32; 334 } 335 tmp = RREG32(mmMC_SHARED_CHMAP); 336 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 337 case 0: 338 default: 339 numchan = 1; 340 break; 341 case 1: 342 numchan = 2; 343 break; 344 case 2: 345 numchan = 4; 346 break; 347 case 3: 348 numchan = 8; 349 break; 350 case 4: 351 numchan = 3; 352 break; 353 case 5: 354 numchan = 6; 355 break; 356 case 6: 357 numchan = 10; 358 break; 359 case 7: 360 numchan = 12; 361 break; 362 case 8: 363 numchan = 16; 364 break; 365 } 366 adev->gmc.vram_width = numchan * chansize; 367 } 368 /* size in MB on si */ 369 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 370 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 371 372 if (!(adev->flags & AMD_IS_APU)) { 373 r = amdgpu_device_resize_fb_bar(adev); 374 if (r) 375 return r; 376 } 377 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 378 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 379 380 #ifdef CONFIG_X86_64 381 if (adev->flags & AMD_IS_APU) { 382 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; 383 adev->gmc.aper_size = adev->gmc.real_vram_size; 384 } 385 #endif 386 387 /* In case the PCI BAR is larger than the actual amount of vram */ 388 adev->gmc.visible_vram_size = adev->gmc.aper_size; 389 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 390 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 391 392 /* set the gart size */ 393 if (amdgpu_gart_size == -1) { 394 switch (adev->asic_type) { 395 case CHIP_TOPAZ: /* no MM engines */ 396 default: 397 adev->gmc.gart_size = 256ULL << 20; 398 break; 399 #ifdef CONFIG_DRM_AMDGPU_CIK 400 case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */ 401 case CHIP_HAWAII: /* UVD, VCE do not support GPUVM */ 402 case CHIP_KAVERI: /* UVD, VCE do not support GPUVM */ 403 case CHIP_KABINI: /* UVD, VCE do not support GPUVM */ 404 case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */ 405 adev->gmc.gart_size = 1024ULL << 20; 406 break; 407 #endif 408 } 409 } else { 410 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 411 } 412 413 gmc_v7_0_vram_gtt_location(adev, &adev->gmc); 414 415 return 0; 416 } 417 418 /* 419 * GART 420 * VMID 0 is the physical GPU addresses as used by the kernel. 421 * VMIDs 1-15 are used for userspace clients and are handled 422 * by the amdgpu vm/hsa code. 423 */ 424 425 /** 426 * gmc_v7_0_flush_gpu_tlb - gart tlb flush callback 427 * 428 * @adev: amdgpu_device pointer 429 * @vmid: vm instance to flush 430 * 431 * Flush the TLB for the requested page table (CIK). 432 */ 433 static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid) 434 { 435 /* bits 0-15 are the VM contexts0-15 */ 436 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 437 } 438 439 static uint64_t gmc_v7_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 440 unsigned vmid, uint64_t pd_addr) 441 { 442 uint32_t reg; 443 444 if (vmid < 8) 445 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; 446 else 447 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8; 448 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); 449 450 /* bits 0-15 are the VM contexts0-15 */ 451 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); 452 453 return pd_addr; 454 } 455 456 static void gmc_v7_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 457 unsigned pasid) 458 { 459 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); 460 } 461 462 /** 463 * gmc_v7_0_set_pte_pde - update the page tables using MMIO 464 * 465 * @adev: amdgpu_device pointer 466 * @cpu_pt_addr: cpu address of the page table 467 * @gpu_page_idx: entry in the page table to update 468 * @addr: dst addr to write into pte/pde 469 * @flags: access flags 470 * 471 * Update the page tables using the CPU. 472 */ 473 static int gmc_v7_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 474 uint32_t gpu_page_idx, uint64_t addr, 475 uint64_t flags) 476 { 477 void __iomem *ptr = (void *)cpu_pt_addr; 478 uint64_t value; 479 480 value = addr & 0xFFFFFFFFFFFFF000ULL; 481 value |= flags; 482 writeq(value, ptr + (gpu_page_idx * 8)); 483 484 return 0; 485 } 486 487 static uint64_t gmc_v7_0_get_vm_pte_flags(struct amdgpu_device *adev, 488 uint32_t flags) 489 { 490 uint64_t pte_flag = 0; 491 492 if (flags & AMDGPU_VM_PAGE_READABLE) 493 pte_flag |= AMDGPU_PTE_READABLE; 494 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 495 pte_flag |= AMDGPU_PTE_WRITEABLE; 496 if (flags & AMDGPU_VM_PAGE_PRT) 497 pte_flag |= AMDGPU_PTE_PRT; 498 499 return pte_flag; 500 } 501 502 static void gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, int level, 503 uint64_t *addr, uint64_t *flags) 504 { 505 BUG_ON(*addr & 0xFFFFFF0000000FFFULL); 506 } 507 508 /** 509 * gmc_v8_0_set_fault_enable_default - update VM fault handling 510 * 511 * @adev: amdgpu_device pointer 512 * @value: true redirects VM faults to the default page 513 */ 514 static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev, 515 bool value) 516 { 517 u32 tmp; 518 519 tmp = RREG32(mmVM_CONTEXT1_CNTL); 520 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 521 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 522 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 523 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 524 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 525 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 526 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 527 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 528 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 529 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 530 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 531 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 532 WREG32(mmVM_CONTEXT1_CNTL, tmp); 533 } 534 535 /** 536 * gmc_v7_0_set_prt - set PRT VM fault 537 * 538 * @adev: amdgpu_device pointer 539 * @enable: enable/disable VM fault handling for PRT 540 */ 541 static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable) 542 { 543 uint32_t tmp; 544 545 if (enable && !adev->gmc.prt_warning) { 546 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 547 adev->gmc.prt_warning = true; 548 } 549 550 tmp = RREG32(mmVM_PRT_CNTL); 551 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 552 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 553 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 554 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 555 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 556 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 557 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 558 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 559 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 560 L2_CACHE_STORE_INVALID_ENTRIES, enable); 561 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 562 L1_TLB_STORE_INVALID_ENTRIES, enable); 563 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 564 MASK_PDE0_FAULT, enable); 565 WREG32(mmVM_PRT_CNTL, tmp); 566 567 if (enable) { 568 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; 569 uint32_t high = adev->vm_manager.max_pfn - 570 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT); 571 572 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); 573 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); 574 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); 575 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); 576 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); 577 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); 578 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); 579 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); 580 } else { 581 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); 582 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); 583 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); 584 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); 585 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); 586 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); 587 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); 588 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); 589 } 590 } 591 592 /** 593 * gmc_v7_0_gart_enable - gart enable 594 * 595 * @adev: amdgpu_device pointer 596 * 597 * This sets up the TLBs, programs the page tables for VMID0, 598 * sets up the hw for VMIDs 1-15 which are allocated on 599 * demand, and sets up the global locations for the LDS, GDS, 600 * and GPUVM for FSA64 clients (CIK). 601 * Returns 0 for success, errors for failure. 602 */ 603 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev) 604 { 605 uint64_t table_addr; 606 int r, i; 607 u32 tmp, field; 608 609 if (adev->gart.bo == NULL) { 610 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 611 return -EINVAL; 612 } 613 r = amdgpu_gart_table_vram_pin(adev); 614 if (r) 615 return r; 616 617 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 618 619 /* Setup TLB control */ 620 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 621 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 622 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); 623 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 624 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); 625 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 626 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 627 /* Setup L2 cache */ 628 tmp = RREG32(mmVM_L2_CNTL); 629 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 630 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 631 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); 632 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); 633 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); 634 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 635 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 636 WREG32(mmVM_L2_CNTL, tmp); 637 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 638 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 639 WREG32(mmVM_L2_CNTL2, tmp); 640 641 field = adev->vm_manager.fragment_size; 642 tmp = RREG32(mmVM_L2_CNTL3); 643 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); 644 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); 645 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); 646 WREG32(mmVM_L2_CNTL3, tmp); 647 /* setup context0 */ 648 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); 649 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); 650 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12); 651 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 652 (u32)(adev->dummy_page_addr >> 12)); 653 WREG32(mmVM_CONTEXT0_CNTL2, 0); 654 tmp = RREG32(mmVM_CONTEXT0_CNTL); 655 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 656 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 657 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 658 WREG32(mmVM_CONTEXT0_CNTL, tmp); 659 660 WREG32(0x575, 0); 661 WREG32(0x576, 0); 662 WREG32(0x577, 0); 663 664 /* empty context1-15 */ 665 /* FIXME start with 4G, once using 2 level pt switch to full 666 * vm size space 667 */ 668 /* set vm size, must be a multiple of 4 */ 669 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 670 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 671 for (i = 1; i < 16; i++) { 672 if (i < 8) 673 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 674 table_addr >> 12); 675 else 676 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 677 table_addr >> 12); 678 } 679 680 /* enable context1-15 */ 681 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 682 (u32)(adev->dummy_page_addr >> 12)); 683 WREG32(mmVM_CONTEXT1_CNTL2, 4); 684 tmp = RREG32(mmVM_CONTEXT1_CNTL); 685 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 686 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); 687 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, 688 adev->vm_manager.block_size - 9); 689 WREG32(mmVM_CONTEXT1_CNTL, tmp); 690 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 691 gmc_v7_0_set_fault_enable_default(adev, false); 692 else 693 gmc_v7_0_set_fault_enable_default(adev, true); 694 695 if (adev->asic_type == CHIP_KAVERI) { 696 tmp = RREG32(mmCHUB_CONTROL); 697 tmp &= ~BYPASS_VM; 698 WREG32(mmCHUB_CONTROL, tmp); 699 } 700 701 gmc_v7_0_flush_gpu_tlb(adev, 0); 702 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 703 (unsigned)(adev->gmc.gart_size >> 20), 704 (unsigned long long)table_addr); 705 adev->gart.ready = true; 706 return 0; 707 } 708 709 static int gmc_v7_0_gart_init(struct amdgpu_device *adev) 710 { 711 int r; 712 713 if (adev->gart.bo) { 714 WARN(1, "R600 PCIE GART already initialized\n"); 715 return 0; 716 } 717 /* Initialize common gart structure */ 718 r = amdgpu_gart_init(adev); 719 if (r) 720 return r; 721 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 722 adev->gart.gart_pte_flags = 0; 723 return amdgpu_gart_table_vram_alloc(adev); 724 } 725 726 /** 727 * gmc_v7_0_gart_disable - gart disable 728 * 729 * @adev: amdgpu_device pointer 730 * 731 * This disables all VM page table (CIK). 732 */ 733 static void gmc_v7_0_gart_disable(struct amdgpu_device *adev) 734 { 735 u32 tmp; 736 737 /* Disable all tables */ 738 WREG32(mmVM_CONTEXT0_CNTL, 0); 739 WREG32(mmVM_CONTEXT1_CNTL, 0); 740 /* Setup TLB control */ 741 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 742 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 743 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); 744 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); 745 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 746 /* Setup L2 cache */ 747 tmp = RREG32(mmVM_L2_CNTL); 748 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 749 WREG32(mmVM_L2_CNTL, tmp); 750 WREG32(mmVM_L2_CNTL2, 0); 751 amdgpu_gart_table_vram_unpin(adev); 752 } 753 754 /** 755 * gmc_v7_0_vm_decode_fault - print human readable fault info 756 * 757 * @adev: amdgpu_device pointer 758 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value 759 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value 760 * 761 * Print human readable fault information (CIK). 762 */ 763 static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev, u32 status, 764 u32 addr, u32 mc_client, unsigned pasid) 765 { 766 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 767 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 768 PROTECTIONS); 769 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 770 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 771 u32 mc_id; 772 773 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 774 MEMORY_CLIENT_ID); 775 776 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 777 protections, vmid, pasid, addr, 778 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 779 MEMORY_CLIENT_RW) ? 780 "write" : "read", block, mc_client, mc_id); 781 } 782 783 784 static const u32 mc_cg_registers[] = { 785 mmMC_HUB_MISC_HUB_CG, 786 mmMC_HUB_MISC_SIP_CG, 787 mmMC_HUB_MISC_VM_CG, 788 mmMC_XPB_CLK_GAT, 789 mmATC_MISC_CG, 790 mmMC_CITF_MISC_WR_CG, 791 mmMC_CITF_MISC_RD_CG, 792 mmMC_CITF_MISC_VM_CG, 793 mmVM_L2_CG, 794 }; 795 796 static const u32 mc_cg_ls_en[] = { 797 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK, 798 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK, 799 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK, 800 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK, 801 ATC_MISC_CG__MEM_LS_ENABLE_MASK, 802 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK, 803 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK, 804 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK, 805 VM_L2_CG__MEM_LS_ENABLE_MASK, 806 }; 807 808 static const u32 mc_cg_en[] = { 809 MC_HUB_MISC_HUB_CG__ENABLE_MASK, 810 MC_HUB_MISC_SIP_CG__ENABLE_MASK, 811 MC_HUB_MISC_VM_CG__ENABLE_MASK, 812 MC_XPB_CLK_GAT__ENABLE_MASK, 813 ATC_MISC_CG__ENABLE_MASK, 814 MC_CITF_MISC_WR_CG__ENABLE_MASK, 815 MC_CITF_MISC_RD_CG__ENABLE_MASK, 816 MC_CITF_MISC_VM_CG__ENABLE_MASK, 817 VM_L2_CG__ENABLE_MASK, 818 }; 819 820 static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev, 821 bool enable) 822 { 823 int i; 824 u32 orig, data; 825 826 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 827 orig = data = RREG32(mc_cg_registers[i]); 828 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) 829 data |= mc_cg_ls_en[i]; 830 else 831 data &= ~mc_cg_ls_en[i]; 832 if (data != orig) 833 WREG32(mc_cg_registers[i], data); 834 } 835 } 836 837 static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev, 838 bool enable) 839 { 840 int i; 841 u32 orig, data; 842 843 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 844 orig = data = RREG32(mc_cg_registers[i]); 845 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) 846 data |= mc_cg_en[i]; 847 else 848 data &= ~mc_cg_en[i]; 849 if (data != orig) 850 WREG32(mc_cg_registers[i], data); 851 } 852 } 853 854 static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev, 855 bool enable) 856 { 857 u32 orig, data; 858 859 orig = data = RREG32_PCIE(ixPCIE_CNTL2); 860 861 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 862 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1); 863 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1); 864 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1); 865 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1); 866 } else { 867 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0); 868 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0); 869 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0); 870 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0); 871 } 872 873 if (orig != data) 874 WREG32_PCIE(ixPCIE_CNTL2, data); 875 } 876 877 static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev, 878 bool enable) 879 { 880 u32 orig, data; 881 882 orig = data = RREG32(mmHDP_HOST_PATH_CNTL); 883 884 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 885 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0); 886 else 887 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1); 888 889 if (orig != data) 890 WREG32(mmHDP_HOST_PATH_CNTL, data); 891 } 892 893 static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev, 894 bool enable) 895 { 896 u32 orig, data; 897 898 orig = data = RREG32(mmHDP_MEM_POWER_LS); 899 900 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 901 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1); 902 else 903 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0); 904 905 if (orig != data) 906 WREG32(mmHDP_MEM_POWER_LS, data); 907 } 908 909 static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type) 910 { 911 switch (mc_seq_vram_type) { 912 case MC_SEQ_MISC0__MT__GDDR1: 913 return AMDGPU_VRAM_TYPE_GDDR1; 914 case MC_SEQ_MISC0__MT__DDR2: 915 return AMDGPU_VRAM_TYPE_DDR2; 916 case MC_SEQ_MISC0__MT__GDDR3: 917 return AMDGPU_VRAM_TYPE_GDDR3; 918 case MC_SEQ_MISC0__MT__GDDR4: 919 return AMDGPU_VRAM_TYPE_GDDR4; 920 case MC_SEQ_MISC0__MT__GDDR5: 921 return AMDGPU_VRAM_TYPE_GDDR5; 922 case MC_SEQ_MISC0__MT__HBM: 923 return AMDGPU_VRAM_TYPE_HBM; 924 case MC_SEQ_MISC0__MT__DDR3: 925 return AMDGPU_VRAM_TYPE_DDR3; 926 default: 927 return AMDGPU_VRAM_TYPE_UNKNOWN; 928 } 929 } 930 931 static int gmc_v7_0_early_init(void *handle) 932 { 933 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 934 935 gmc_v7_0_set_gmc_funcs(adev); 936 gmc_v7_0_set_irq_funcs(adev); 937 938 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 939 adev->gmc.shared_aperture_end = 940 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 941 adev->gmc.private_aperture_start = 942 adev->gmc.shared_aperture_end + 1; 943 adev->gmc.private_aperture_end = 944 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 945 946 return 0; 947 } 948 949 static int gmc_v7_0_late_init(void *handle) 950 { 951 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 952 953 amdgpu_bo_late_init(adev); 954 955 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 956 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 957 else 958 return 0; 959 } 960 961 static unsigned gmc_v7_0_get_vbios_fb_size(struct amdgpu_device *adev) 962 { 963 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); 964 unsigned size; 965 966 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 967 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */ 968 } else { 969 u32 viewport = RREG32(mmVIEWPORT_SIZE); 970 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 971 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * 972 4); 973 } 974 /* return 0 if the pre-OS buffer uses up most of vram */ 975 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 976 return 0; 977 return size; 978 } 979 980 static int gmc_v7_0_sw_init(void *handle) 981 { 982 int r; 983 int dma_bits; 984 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 985 986 if (adev->flags & AMD_IS_APU) { 987 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 988 } else { 989 u32 tmp = RREG32(mmMC_SEQ_MISC0); 990 tmp &= MC_SEQ_MISC0__MT__MASK; 991 adev->gmc.vram_type = gmc_v7_0_convert_vram_type(tmp); 992 } 993 994 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault); 995 if (r) 996 return r; 997 998 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault); 999 if (r) 1000 return r; 1001 1002 /* Adjust VM size here. 1003 * Currently set to 4GB ((1 << 20) 4k pages). 1004 * Max GPUVM size for cayman and SI is 40 bits. 1005 */ 1006 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); 1007 1008 /* Set the internal MC address mask 1009 * This is the max address of the GPU's 1010 * internal address space. 1011 */ 1012 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1013 1014 /* set DMA mask + need_dma32 flags. 1015 * PCIE - can handle 40-bits. 1016 * IGP - can handle 40-bits 1017 * PCI - dma32 for legacy pci gart, 40 bits on newer asics 1018 */ 1019 adev->need_dma32 = false; 1020 dma_bits = adev->need_dma32 ? 32 : 40; 1021 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 1022 if (r) { 1023 adev->need_dma32 = true; 1024 dma_bits = 32; 1025 pr_warn("amdgpu: No suitable DMA available\n"); 1026 } 1027 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 1028 if (r) { 1029 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); 1030 pr_warn("amdgpu: No coherent DMA available\n"); 1031 } 1032 adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits); 1033 1034 r = gmc_v7_0_init_microcode(adev); 1035 if (r) { 1036 DRM_ERROR("Failed to load mc firmware!\n"); 1037 return r; 1038 } 1039 1040 r = gmc_v7_0_mc_init(adev); 1041 if (r) 1042 return r; 1043 1044 adev->gmc.stolen_size = gmc_v7_0_get_vbios_fb_size(adev); 1045 1046 /* Memory manager */ 1047 r = amdgpu_bo_init(adev); 1048 if (r) 1049 return r; 1050 1051 r = gmc_v7_0_gart_init(adev); 1052 if (r) 1053 return r; 1054 1055 /* 1056 * number of VMs 1057 * VMID 0 is reserved for System 1058 * amdgpu graphics/compute will use VMIDs 1-7 1059 * amdkfd will use VMIDs 8-15 1060 */ 1061 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; 1062 amdgpu_vm_manager_init(adev); 1063 1064 /* base offset of vram pages */ 1065 if (adev->flags & AMD_IS_APU) { 1066 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 1067 1068 tmp <<= 22; 1069 adev->vm_manager.vram_base_offset = tmp; 1070 } else { 1071 adev->vm_manager.vram_base_offset = 0; 1072 } 1073 1074 adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info), 1075 GFP_KERNEL); 1076 if (!adev->gmc.vm_fault_info) 1077 return -ENOMEM; 1078 atomic_set(&adev->gmc.vm_fault_info_updated, 0); 1079 1080 return 0; 1081 } 1082 1083 static int gmc_v7_0_sw_fini(void *handle) 1084 { 1085 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1086 1087 amdgpu_gem_force_release(adev); 1088 amdgpu_vm_manager_fini(adev); 1089 kfree(adev->gmc.vm_fault_info); 1090 amdgpu_gart_table_vram_free(adev); 1091 amdgpu_bo_fini(adev); 1092 amdgpu_gart_fini(adev); 1093 release_firmware(adev->gmc.fw); 1094 adev->gmc.fw = NULL; 1095 1096 return 0; 1097 } 1098 1099 static int gmc_v7_0_hw_init(void *handle) 1100 { 1101 int r; 1102 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1103 1104 gmc_v7_0_init_golden_registers(adev); 1105 1106 gmc_v7_0_mc_program(adev); 1107 1108 if (!(adev->flags & AMD_IS_APU)) { 1109 r = gmc_v7_0_mc_load_microcode(adev); 1110 if (r) { 1111 DRM_ERROR("Failed to load MC firmware!\n"); 1112 return r; 1113 } 1114 } 1115 1116 r = gmc_v7_0_gart_enable(adev); 1117 if (r) 1118 return r; 1119 1120 return r; 1121 } 1122 1123 static int gmc_v7_0_hw_fini(void *handle) 1124 { 1125 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1126 1127 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1128 gmc_v7_0_gart_disable(adev); 1129 1130 return 0; 1131 } 1132 1133 static int gmc_v7_0_suspend(void *handle) 1134 { 1135 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1136 1137 gmc_v7_0_hw_fini(adev); 1138 1139 return 0; 1140 } 1141 1142 static int gmc_v7_0_resume(void *handle) 1143 { 1144 int r; 1145 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1146 1147 r = gmc_v7_0_hw_init(adev); 1148 if (r) 1149 return r; 1150 1151 amdgpu_vmid_reset_all(adev); 1152 1153 return 0; 1154 } 1155 1156 static bool gmc_v7_0_is_idle(void *handle) 1157 { 1158 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1159 u32 tmp = RREG32(mmSRBM_STATUS); 1160 1161 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1162 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 1163 return false; 1164 1165 return true; 1166 } 1167 1168 static int gmc_v7_0_wait_for_idle(void *handle) 1169 { 1170 unsigned i; 1171 u32 tmp; 1172 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1173 1174 for (i = 0; i < adev->usec_timeout; i++) { 1175 /* read MC_STATUS */ 1176 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | 1177 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1178 SRBM_STATUS__MCC_BUSY_MASK | 1179 SRBM_STATUS__MCD_BUSY_MASK | 1180 SRBM_STATUS__VMC_BUSY_MASK); 1181 if (!tmp) 1182 return 0; 1183 udelay(1); 1184 } 1185 return -ETIMEDOUT; 1186 1187 } 1188 1189 static int gmc_v7_0_soft_reset(void *handle) 1190 { 1191 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1192 u32 srbm_soft_reset = 0; 1193 u32 tmp = RREG32(mmSRBM_STATUS); 1194 1195 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1196 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1197 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 1198 1199 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1200 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 1201 if (!(adev->flags & AMD_IS_APU)) 1202 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1203 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1204 } 1205 1206 if (srbm_soft_reset) { 1207 gmc_v7_0_mc_stop(adev); 1208 if (gmc_v7_0_wait_for_idle((void *)adev)) { 1209 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1210 } 1211 1212 1213 tmp = RREG32(mmSRBM_SOFT_RESET); 1214 tmp |= srbm_soft_reset; 1215 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1216 WREG32(mmSRBM_SOFT_RESET, tmp); 1217 tmp = RREG32(mmSRBM_SOFT_RESET); 1218 1219 udelay(50); 1220 1221 tmp &= ~srbm_soft_reset; 1222 WREG32(mmSRBM_SOFT_RESET, tmp); 1223 tmp = RREG32(mmSRBM_SOFT_RESET); 1224 1225 /* Wait a little for things to settle down */ 1226 udelay(50); 1227 1228 gmc_v7_0_mc_resume(adev); 1229 udelay(50); 1230 } 1231 1232 return 0; 1233 } 1234 1235 static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1236 struct amdgpu_irq_src *src, 1237 unsigned type, 1238 enum amdgpu_interrupt_state state) 1239 { 1240 u32 tmp; 1241 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1242 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1243 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1244 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1245 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1246 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1247 1248 switch (state) { 1249 case AMDGPU_IRQ_STATE_DISABLE: 1250 /* system context */ 1251 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1252 tmp &= ~bits; 1253 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1254 /* VMs */ 1255 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1256 tmp &= ~bits; 1257 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1258 break; 1259 case AMDGPU_IRQ_STATE_ENABLE: 1260 /* system context */ 1261 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1262 tmp |= bits; 1263 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1264 /* VMs */ 1265 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1266 tmp |= bits; 1267 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1268 break; 1269 default: 1270 break; 1271 } 1272 1273 return 0; 1274 } 1275 1276 static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev, 1277 struct amdgpu_irq_src *source, 1278 struct amdgpu_iv_entry *entry) 1279 { 1280 u32 addr, status, mc_client, vmid; 1281 1282 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1283 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1284 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); 1285 /* reset addr and status */ 1286 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1287 1288 if (!addr && !status) 1289 return 0; 1290 1291 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1292 gmc_v7_0_set_fault_enable_default(adev, false); 1293 1294 if (printk_ratelimit()) { 1295 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1296 entry->src_id, entry->src_data[0]); 1297 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1298 addr); 1299 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1300 status); 1301 gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client, 1302 entry->pasid); 1303 } 1304 1305 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1306 VMID); 1307 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid) 1308 && !atomic_read(&adev->gmc.vm_fault_info_updated)) { 1309 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info; 1310 u32 protections = REG_GET_FIELD(status, 1311 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1312 PROTECTIONS); 1313 1314 info->vmid = vmid; 1315 info->mc_id = REG_GET_FIELD(status, 1316 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1317 MEMORY_CLIENT_ID); 1318 info->status = status; 1319 info->page_addr = addr; 1320 info->prot_valid = protections & 0x7 ? true : false; 1321 info->prot_read = protections & 0x8 ? true : false; 1322 info->prot_write = protections & 0x10 ? true : false; 1323 info->prot_exec = protections & 0x20 ? true : false; 1324 mb(); 1325 atomic_set(&adev->gmc.vm_fault_info_updated, 1); 1326 } 1327 1328 return 0; 1329 } 1330 1331 static int gmc_v7_0_set_clockgating_state(void *handle, 1332 enum amd_clockgating_state state) 1333 { 1334 bool gate = false; 1335 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1336 1337 if (state == AMD_CG_STATE_GATE) 1338 gate = true; 1339 1340 if (!(adev->flags & AMD_IS_APU)) { 1341 gmc_v7_0_enable_mc_mgcg(adev, gate); 1342 gmc_v7_0_enable_mc_ls(adev, gate); 1343 } 1344 gmc_v7_0_enable_bif_mgls(adev, gate); 1345 gmc_v7_0_enable_hdp_mgcg(adev, gate); 1346 gmc_v7_0_enable_hdp_ls(adev, gate); 1347 1348 return 0; 1349 } 1350 1351 static int gmc_v7_0_set_powergating_state(void *handle, 1352 enum amd_powergating_state state) 1353 { 1354 return 0; 1355 } 1356 1357 static const struct amd_ip_funcs gmc_v7_0_ip_funcs = { 1358 .name = "gmc_v7_0", 1359 .early_init = gmc_v7_0_early_init, 1360 .late_init = gmc_v7_0_late_init, 1361 .sw_init = gmc_v7_0_sw_init, 1362 .sw_fini = gmc_v7_0_sw_fini, 1363 .hw_init = gmc_v7_0_hw_init, 1364 .hw_fini = gmc_v7_0_hw_fini, 1365 .suspend = gmc_v7_0_suspend, 1366 .resume = gmc_v7_0_resume, 1367 .is_idle = gmc_v7_0_is_idle, 1368 .wait_for_idle = gmc_v7_0_wait_for_idle, 1369 .soft_reset = gmc_v7_0_soft_reset, 1370 .set_clockgating_state = gmc_v7_0_set_clockgating_state, 1371 .set_powergating_state = gmc_v7_0_set_powergating_state, 1372 }; 1373 1374 static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = { 1375 .flush_gpu_tlb = gmc_v7_0_flush_gpu_tlb, 1376 .emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb, 1377 .emit_pasid_mapping = gmc_v7_0_emit_pasid_mapping, 1378 .set_pte_pde = gmc_v7_0_set_pte_pde, 1379 .set_prt = gmc_v7_0_set_prt, 1380 .get_vm_pte_flags = gmc_v7_0_get_vm_pte_flags, 1381 .get_vm_pde = gmc_v7_0_get_vm_pde 1382 }; 1383 1384 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = { 1385 .set = gmc_v7_0_vm_fault_interrupt_state, 1386 .process = gmc_v7_0_process_interrupt, 1387 }; 1388 1389 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev) 1390 { 1391 adev->gmc.gmc_funcs = &gmc_v7_0_gmc_funcs; 1392 } 1393 1394 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev) 1395 { 1396 adev->gmc.vm_fault.num_types = 1; 1397 adev->gmc.vm_fault.funcs = &gmc_v7_0_irq_funcs; 1398 } 1399 1400 const struct amdgpu_ip_block_version gmc_v7_0_ip_block = 1401 { 1402 .type = AMD_IP_BLOCK_TYPE_GMC, 1403 .major = 7, 1404 .minor = 0, 1405 .rev = 0, 1406 .funcs = &gmc_v7_0_ip_funcs, 1407 }; 1408 1409 const struct amdgpu_ip_block_version gmc_v7_4_ip_block = 1410 { 1411 .type = AMD_IP_BLOCK_TYPE_GMC, 1412 .major = 7, 1413 .minor = 4, 1414 .rev = 0, 1415 .funcs = &gmc_v7_0_ip_funcs, 1416 }; 1417