1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <drm/drmP.h> 25 #include "amdgpu.h" 26 #include "gmc_v6_0.h" 27 #include "amdgpu_ucode.h" 28 29 #include "bif/bif_3_0_d.h" 30 #include "bif/bif_3_0_sh_mask.h" 31 #include "oss/oss_1_0_d.h" 32 #include "oss/oss_1_0_sh_mask.h" 33 #include "gmc/gmc_6_0_d.h" 34 #include "gmc/gmc_6_0_sh_mask.h" 35 #include "dce/dce_6_0_d.h" 36 #include "dce/dce_6_0_sh_mask.h" 37 #include "si_enums.h" 38 39 static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev); 40 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev); 41 static int gmc_v6_0_wait_for_idle(void *handle); 42 43 MODULE_FIRMWARE("radeon/tahiti_mc.bin"); 44 MODULE_FIRMWARE("radeon/pitcairn_mc.bin"); 45 MODULE_FIRMWARE("radeon/verde_mc.bin"); 46 MODULE_FIRMWARE("radeon/oland_mc.bin"); 47 MODULE_FIRMWARE("radeon/si58_mc.bin"); 48 49 #define MC_SEQ_MISC0__MT__MASK 0xf0000000 50 #define MC_SEQ_MISC0__MT__GDDR1 0x10000000 51 #define MC_SEQ_MISC0__MT__DDR2 0x20000000 52 #define MC_SEQ_MISC0__MT__GDDR3 0x30000000 53 #define MC_SEQ_MISC0__MT__GDDR4 0x40000000 54 #define MC_SEQ_MISC0__MT__GDDR5 0x50000000 55 #define MC_SEQ_MISC0__MT__HBM 0x60000000 56 #define MC_SEQ_MISC0__MT__DDR3 0xB0000000 57 58 59 static const u32 crtc_offsets[6] = 60 { 61 SI_CRTC0_REGISTER_OFFSET, 62 SI_CRTC1_REGISTER_OFFSET, 63 SI_CRTC2_REGISTER_OFFSET, 64 SI_CRTC3_REGISTER_OFFSET, 65 SI_CRTC4_REGISTER_OFFSET, 66 SI_CRTC5_REGISTER_OFFSET 67 }; 68 69 static void gmc_v6_0_mc_stop(struct amdgpu_device *adev) 70 { 71 u32 blackout; 72 73 gmc_v6_0_wait_for_idle((void *)adev); 74 75 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 76 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 77 /* Block CPU access */ 78 WREG32(mmBIF_FB_EN, 0); 79 /* blackout the MC */ 80 blackout = REG_SET_FIELD(blackout, 81 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 82 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); 83 } 84 /* wait for the MC to settle */ 85 udelay(100); 86 87 } 88 89 static void gmc_v6_0_mc_resume(struct amdgpu_device *adev) 90 { 91 u32 tmp; 92 93 /* unblackout the MC */ 94 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 95 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 96 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 97 /* allow CPU access */ 98 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 99 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 100 WREG32(mmBIF_FB_EN, tmp); 101 } 102 103 static int gmc_v6_0_init_microcode(struct amdgpu_device *adev) 104 { 105 const char *chip_name; 106 char fw_name[30]; 107 int err; 108 bool is_58_fw = false; 109 110 DRM_DEBUG("\n"); 111 112 switch (adev->asic_type) { 113 case CHIP_TAHITI: 114 chip_name = "tahiti"; 115 break; 116 case CHIP_PITCAIRN: 117 chip_name = "pitcairn"; 118 break; 119 case CHIP_VERDE: 120 chip_name = "verde"; 121 break; 122 case CHIP_OLAND: 123 chip_name = "oland"; 124 break; 125 case CHIP_HAINAN: 126 chip_name = "hainan"; 127 break; 128 default: BUG(); 129 } 130 131 /* this memory configuration requires special firmware */ 132 if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58) 133 is_58_fw = true; 134 135 if (is_58_fw) 136 snprintf(fw_name, sizeof(fw_name), "radeon/si58_mc.bin"); 137 else 138 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); 139 err = request_firmware(&adev->mc.fw, fw_name, adev->dev); 140 if (err) 141 goto out; 142 143 err = amdgpu_ucode_validate(adev->mc.fw); 144 145 out: 146 if (err) { 147 dev_err(adev->dev, 148 "si_mc: Failed to load firmware \"%s\"\n", 149 fw_name); 150 release_firmware(adev->mc.fw); 151 adev->mc.fw = NULL; 152 } 153 return err; 154 } 155 156 static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev) 157 { 158 const __le32 *new_fw_data = NULL; 159 u32 running; 160 const __le32 *new_io_mc_regs = NULL; 161 int i, regs_size, ucode_size; 162 const struct mc_firmware_header_v1_0 *hdr; 163 164 if (!adev->mc.fw) 165 return -EINVAL; 166 167 hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data; 168 169 amdgpu_ucode_print_mc_hdr(&hdr->header); 170 171 adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version); 172 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 173 new_io_mc_regs = (const __le32 *) 174 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 175 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 176 new_fw_data = (const __le32 *) 177 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 178 179 running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK; 180 181 if (running == 0) { 182 183 /* reset the engine and set to writable */ 184 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 185 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 186 187 /* load mc io regs */ 188 for (i = 0; i < regs_size; i++) { 189 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); 190 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); 191 } 192 /* load the MC ucode */ 193 for (i = 0; i < ucode_size; i++) { 194 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); 195 } 196 197 /* put the engine back into the active state */ 198 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 199 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 200 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 201 202 /* wait for training to complete */ 203 for (i = 0; i < adev->usec_timeout; i++) { 204 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK) 205 break; 206 udelay(1); 207 } 208 for (i = 0; i < adev->usec_timeout; i++) { 209 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK) 210 break; 211 udelay(1); 212 } 213 214 } 215 216 return 0; 217 } 218 219 static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev, 220 struct amdgpu_mc *mc) 221 { 222 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; 223 base <<= 24; 224 225 amdgpu_device_vram_location(adev, &adev->mc, base); 226 amdgpu_device_gart_location(adev, mc); 227 } 228 229 static void gmc_v6_0_mc_program(struct amdgpu_device *adev) 230 { 231 int i, j; 232 233 /* Initialize HDP */ 234 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 235 WREG32((0xb05 + j), 0x00000000); 236 WREG32((0xb06 + j), 0x00000000); 237 WREG32((0xb07 + j), 0x00000000); 238 WREG32((0xb08 + j), 0x00000000); 239 WREG32((0xb09 + j), 0x00000000); 240 } 241 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 242 243 if (gmc_v6_0_wait_for_idle((void *)adev)) { 244 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 245 } 246 247 if (adev->mode_info.num_crtc) { 248 u32 tmp; 249 250 /* Lockout access through VGA aperture*/ 251 tmp = RREG32(mmVGA_HDP_CONTROL); 252 tmp |= VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK; 253 WREG32(mmVGA_HDP_CONTROL, tmp); 254 255 /* disable VGA render */ 256 tmp = RREG32(mmVGA_RENDER_CONTROL); 257 tmp &= ~VGA_VSTATUS_CNTL; 258 WREG32(mmVGA_RENDER_CONTROL, tmp); 259 } 260 /* Update configuration */ 261 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 262 adev->mc.vram_start >> 12); 263 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 264 adev->mc.vram_end >> 12); 265 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 266 adev->vram_scratch.gpu_addr >> 12); 267 WREG32(mmMC_VM_AGP_BASE, 0); 268 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); 269 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); 270 271 if (gmc_v6_0_wait_for_idle((void *)adev)) { 272 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 273 } 274 } 275 276 static int gmc_v6_0_mc_init(struct amdgpu_device *adev) 277 { 278 279 u32 tmp; 280 int chansize, numchan; 281 int r; 282 283 tmp = RREG32(mmMC_ARB_RAMCFG); 284 if (tmp & (1 << 11)) { 285 chansize = 16; 286 } else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK) { 287 chansize = 64; 288 } else { 289 chansize = 32; 290 } 291 tmp = RREG32(mmMC_SHARED_CHMAP); 292 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) { 293 case 0: 294 default: 295 numchan = 1; 296 break; 297 case 1: 298 numchan = 2; 299 break; 300 case 2: 301 numchan = 4; 302 break; 303 case 3: 304 numchan = 8; 305 break; 306 case 4: 307 numchan = 3; 308 break; 309 case 5: 310 numchan = 6; 311 break; 312 case 6: 313 numchan = 10; 314 break; 315 case 7: 316 numchan = 12; 317 break; 318 case 8: 319 numchan = 16; 320 break; 321 } 322 adev->mc.vram_width = numchan * chansize; 323 /* size in MB on si */ 324 adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 325 adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 326 327 if (!(adev->flags & AMD_IS_APU)) { 328 r = amdgpu_device_resize_fb_bar(adev); 329 if (r) 330 return r; 331 } 332 adev->mc.aper_base = pci_resource_start(adev->pdev, 0); 333 adev->mc.aper_size = pci_resource_len(adev->pdev, 0); 334 adev->mc.visible_vram_size = adev->mc.aper_size; 335 336 /* set the gart size */ 337 if (amdgpu_gart_size == -1) { 338 switch (adev->asic_type) { 339 case CHIP_HAINAN: /* no MM engines */ 340 default: 341 adev->mc.gart_size = 256ULL << 20; 342 break; 343 case CHIP_VERDE: /* UVD, VCE do not support GPUVM */ 344 case CHIP_TAHITI: /* UVD, VCE do not support GPUVM */ 345 case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */ 346 case CHIP_OLAND: /* UVD, VCE do not support GPUVM */ 347 adev->mc.gart_size = 1024ULL << 20; 348 break; 349 } 350 } else { 351 adev->mc.gart_size = (u64)amdgpu_gart_size << 20; 352 } 353 354 gmc_v6_0_vram_gtt_location(adev, &adev->mc); 355 356 return 0; 357 } 358 359 static void gmc_v6_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, 360 uint32_t vmid) 361 { 362 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0); 363 364 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 365 } 366 367 static int gmc_v6_0_gart_set_pte_pde(struct amdgpu_device *adev, 368 void *cpu_pt_addr, 369 uint32_t gpu_page_idx, 370 uint64_t addr, 371 uint64_t flags) 372 { 373 void __iomem *ptr = (void *)cpu_pt_addr; 374 uint64_t value; 375 376 value = addr & 0xFFFFFFFFFFFFF000ULL; 377 value |= flags; 378 writeq(value, ptr + (gpu_page_idx * 8)); 379 380 return 0; 381 } 382 383 static uint64_t gmc_v6_0_get_vm_pte_flags(struct amdgpu_device *adev, 384 uint32_t flags) 385 { 386 uint64_t pte_flag = 0; 387 388 if (flags & AMDGPU_VM_PAGE_READABLE) 389 pte_flag |= AMDGPU_PTE_READABLE; 390 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 391 pte_flag |= AMDGPU_PTE_WRITEABLE; 392 if (flags & AMDGPU_VM_PAGE_PRT) 393 pte_flag |= AMDGPU_PTE_PRT; 394 395 return pte_flag; 396 } 397 398 static void gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, int level, 399 uint64_t *addr, uint64_t *flags) 400 { 401 BUG_ON(*addr & 0xFFFFFF0000000FFFULL); 402 } 403 404 static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev, 405 bool value) 406 { 407 u32 tmp; 408 409 tmp = RREG32(mmVM_CONTEXT1_CNTL); 410 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 411 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 412 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 413 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 414 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 415 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 416 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 417 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 418 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 419 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 420 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 421 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 422 WREG32(mmVM_CONTEXT1_CNTL, tmp); 423 } 424 425 /** 426 + * gmc_v8_0_set_prt - set PRT VM fault 427 + * 428 + * @adev: amdgpu_device pointer 429 + * @enable: enable/disable VM fault handling for PRT 430 +*/ 431 static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable) 432 { 433 u32 tmp; 434 435 if (enable && !adev->mc.prt_warning) { 436 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 437 adev->mc.prt_warning = true; 438 } 439 440 tmp = RREG32(mmVM_PRT_CNTL); 441 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 442 CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS, 443 enable); 444 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 445 TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS, 446 enable); 447 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 448 L2_CACHE_STORE_INVALID_ENTRIES, 449 enable); 450 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 451 L1_TLB_STORE_INVALID_ENTRIES, 452 enable); 453 WREG32(mmVM_PRT_CNTL, tmp); 454 455 if (enable) { 456 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; 457 uint32_t high = adev->vm_manager.max_pfn; 458 459 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); 460 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); 461 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); 462 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); 463 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); 464 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); 465 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); 466 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); 467 } else { 468 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); 469 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); 470 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); 471 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); 472 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); 473 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); 474 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); 475 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); 476 } 477 } 478 479 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) 480 { 481 int r, i; 482 u32 field; 483 484 if (adev->gart.robj == NULL) { 485 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 486 return -EINVAL; 487 } 488 r = amdgpu_gart_table_vram_pin(adev); 489 if (r) 490 return r; 491 /* Setup TLB control */ 492 WREG32(mmMC_VM_MX_L1_TLB_CNTL, 493 (0xA << 7) | 494 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK | 495 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK | 496 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK | 497 MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK | 498 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT)); 499 /* Setup L2 cache */ 500 WREG32(mmVM_L2_CNTL, 501 VM_L2_CNTL__ENABLE_L2_CACHE_MASK | 502 VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK | 503 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK | 504 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK | 505 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) | 506 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT)); 507 WREG32(mmVM_L2_CNTL2, 508 VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK | 509 VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK); 510 511 field = adev->vm_manager.fragment_size; 512 WREG32(mmVM_L2_CNTL3, 513 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK | 514 (field << VM_L2_CNTL3__BANK_SELECT__SHIFT) | 515 (field << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT)); 516 /* setup context0 */ 517 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gart_start >> 12); 518 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gart_end >> 12); 519 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); 520 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 521 (u32)(adev->dummy_page.addr >> 12)); 522 WREG32(mmVM_CONTEXT0_CNTL2, 0); 523 WREG32(mmVM_CONTEXT0_CNTL, 524 VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK | 525 (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) | 526 VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK); 527 528 WREG32(0x575, 0); 529 WREG32(0x576, 0); 530 WREG32(0x577, 0); 531 532 /* empty context1-15 */ 533 /* set vm size, must be a multiple of 4 */ 534 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 535 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 536 /* Assign the pt base to something valid for now; the pts used for 537 * the VMs are determined by the application and setup and assigned 538 * on the fly in the vm part of radeon_gart.c 539 */ 540 for (i = 1; i < 16; i++) { 541 if (i < 8) 542 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 543 adev->gart.table_addr >> 12); 544 else 545 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 546 adev->gart.table_addr >> 12); 547 } 548 549 /* enable context1-15 */ 550 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 551 (u32)(adev->dummy_page.addr >> 12)); 552 WREG32(mmVM_CONTEXT1_CNTL2, 4); 553 WREG32(mmVM_CONTEXT1_CNTL, 554 VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK | 555 (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) | 556 ((adev->vm_manager.block_size - 9) 557 << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT)); 558 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 559 gmc_v6_0_set_fault_enable_default(adev, false); 560 else 561 gmc_v6_0_set_fault_enable_default(adev, true); 562 563 gmc_v6_0_gart_flush_gpu_tlb(adev, 0); 564 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n", 565 (unsigned)(adev->mc.gart_size >> 20), 566 (unsigned long long)adev->gart.table_addr); 567 adev->gart.ready = true; 568 return 0; 569 } 570 571 static int gmc_v6_0_gart_init(struct amdgpu_device *adev) 572 { 573 int r; 574 575 if (adev->gart.robj) { 576 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n"); 577 return 0; 578 } 579 r = amdgpu_gart_init(adev); 580 if (r) 581 return r; 582 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 583 adev->gart.gart_pte_flags = 0; 584 return amdgpu_gart_table_vram_alloc(adev); 585 } 586 587 static void gmc_v6_0_gart_disable(struct amdgpu_device *adev) 588 { 589 /*unsigned i; 590 591 for (i = 1; i < 16; ++i) { 592 uint32_t reg; 593 if (i < 8) 594 reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i ; 595 else 596 reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (i - 8); 597 adev->vm_manager.saved_table_addr[i] = RREG32(reg); 598 }*/ 599 600 /* Disable all tables */ 601 WREG32(mmVM_CONTEXT0_CNTL, 0); 602 WREG32(mmVM_CONTEXT1_CNTL, 0); 603 /* Setup TLB control */ 604 WREG32(mmMC_VM_MX_L1_TLB_CNTL, 605 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK | 606 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT)); 607 /* Setup L2 cache */ 608 WREG32(mmVM_L2_CNTL, 609 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK | 610 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK | 611 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) | 612 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT)); 613 WREG32(mmVM_L2_CNTL2, 0); 614 WREG32(mmVM_L2_CNTL3, 615 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK | 616 (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT)); 617 amdgpu_gart_table_vram_unpin(adev); 618 } 619 620 static void gmc_v6_0_gart_fini(struct amdgpu_device *adev) 621 { 622 amdgpu_gart_table_vram_free(adev); 623 amdgpu_gart_fini(adev); 624 } 625 626 static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev, 627 u32 status, u32 addr, u32 mc_client) 628 { 629 u32 mc_id; 630 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 631 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 632 PROTECTIONS); 633 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 634 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 635 636 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 637 MEMORY_CLIENT_ID); 638 639 dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 640 protections, vmid, addr, 641 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 642 MEMORY_CLIENT_RW) ? 643 "write" : "read", block, mc_client, mc_id); 644 } 645 646 /* 647 static const u32 mc_cg_registers[] = { 648 MC_HUB_MISC_HUB_CG, 649 MC_HUB_MISC_SIP_CG, 650 MC_HUB_MISC_VM_CG, 651 MC_XPB_CLK_GAT, 652 ATC_MISC_CG, 653 MC_CITF_MISC_WR_CG, 654 MC_CITF_MISC_RD_CG, 655 MC_CITF_MISC_VM_CG, 656 VM_L2_CG, 657 }; 658 659 static const u32 mc_cg_ls_en[] = { 660 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK, 661 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK, 662 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK, 663 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK, 664 ATC_MISC_CG__MEM_LS_ENABLE_MASK, 665 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK, 666 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK, 667 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK, 668 VM_L2_CG__MEM_LS_ENABLE_MASK, 669 }; 670 671 static const u32 mc_cg_en[] = { 672 MC_HUB_MISC_HUB_CG__ENABLE_MASK, 673 MC_HUB_MISC_SIP_CG__ENABLE_MASK, 674 MC_HUB_MISC_VM_CG__ENABLE_MASK, 675 MC_XPB_CLK_GAT__ENABLE_MASK, 676 ATC_MISC_CG__ENABLE_MASK, 677 MC_CITF_MISC_WR_CG__ENABLE_MASK, 678 MC_CITF_MISC_RD_CG__ENABLE_MASK, 679 MC_CITF_MISC_VM_CG__ENABLE_MASK, 680 VM_L2_CG__ENABLE_MASK, 681 }; 682 683 static void gmc_v6_0_enable_mc_ls(struct amdgpu_device *adev, 684 bool enable) 685 { 686 int i; 687 u32 orig, data; 688 689 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 690 orig = data = RREG32(mc_cg_registers[i]); 691 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS)) 692 data |= mc_cg_ls_en[i]; 693 else 694 data &= ~mc_cg_ls_en[i]; 695 if (data != orig) 696 WREG32(mc_cg_registers[i], data); 697 } 698 } 699 700 static void gmc_v6_0_enable_mc_mgcg(struct amdgpu_device *adev, 701 bool enable) 702 { 703 int i; 704 u32 orig, data; 705 706 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 707 orig = data = RREG32(mc_cg_registers[i]); 708 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG)) 709 data |= mc_cg_en[i]; 710 else 711 data &= ~mc_cg_en[i]; 712 if (data != orig) 713 WREG32(mc_cg_registers[i], data); 714 } 715 } 716 717 static void gmc_v6_0_enable_bif_mgls(struct amdgpu_device *adev, 718 bool enable) 719 { 720 u32 orig, data; 721 722 orig = data = RREG32_PCIE(ixPCIE_CNTL2); 723 724 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) { 725 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1); 726 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1); 727 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1); 728 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1); 729 } else { 730 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0); 731 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0); 732 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0); 733 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0); 734 } 735 736 if (orig != data) 737 WREG32_PCIE(ixPCIE_CNTL2, data); 738 } 739 740 static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev, 741 bool enable) 742 { 743 u32 orig, data; 744 745 orig = data = RREG32(mmHDP_HOST_PATH_CNTL); 746 747 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG)) 748 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0); 749 else 750 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1); 751 752 if (orig != data) 753 WREG32(mmHDP_HOST_PATH_CNTL, data); 754 } 755 756 static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev, 757 bool enable) 758 { 759 u32 orig, data; 760 761 orig = data = RREG32(mmHDP_MEM_POWER_LS); 762 763 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS)) 764 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1); 765 else 766 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0); 767 768 if (orig != data) 769 WREG32(mmHDP_MEM_POWER_LS, data); 770 } 771 */ 772 773 static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type) 774 { 775 switch (mc_seq_vram_type) { 776 case MC_SEQ_MISC0__MT__GDDR1: 777 return AMDGPU_VRAM_TYPE_GDDR1; 778 case MC_SEQ_MISC0__MT__DDR2: 779 return AMDGPU_VRAM_TYPE_DDR2; 780 case MC_SEQ_MISC0__MT__GDDR3: 781 return AMDGPU_VRAM_TYPE_GDDR3; 782 case MC_SEQ_MISC0__MT__GDDR4: 783 return AMDGPU_VRAM_TYPE_GDDR4; 784 case MC_SEQ_MISC0__MT__GDDR5: 785 return AMDGPU_VRAM_TYPE_GDDR5; 786 case MC_SEQ_MISC0__MT__DDR3: 787 return AMDGPU_VRAM_TYPE_DDR3; 788 default: 789 return AMDGPU_VRAM_TYPE_UNKNOWN; 790 } 791 } 792 793 static int gmc_v6_0_early_init(void *handle) 794 { 795 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 796 797 gmc_v6_0_set_gart_funcs(adev); 798 gmc_v6_0_set_irq_funcs(adev); 799 800 return 0; 801 } 802 803 static int gmc_v6_0_late_init(void *handle) 804 { 805 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 806 807 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 808 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0); 809 else 810 return 0; 811 } 812 813 static int gmc_v6_0_sw_init(void *handle) 814 { 815 int r; 816 int dma_bits; 817 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 818 819 if (adev->flags & AMD_IS_APU) { 820 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 821 } else { 822 u32 tmp = RREG32(mmMC_SEQ_MISC0); 823 tmp &= MC_SEQ_MISC0__MT__MASK; 824 adev->mc.vram_type = gmc_v6_0_convert_vram_type(tmp); 825 } 826 827 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault); 828 if (r) 829 return r; 830 831 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault); 832 if (r) 833 return r; 834 835 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); 836 837 adev->mc.mc_mask = 0xffffffffffULL; 838 839 adev->mc.stolen_size = 256 * 1024; 840 841 adev->need_dma32 = false; 842 dma_bits = adev->need_dma32 ? 32 : 40; 843 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 844 if (r) { 845 adev->need_dma32 = true; 846 dma_bits = 32; 847 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); 848 } 849 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 850 if (r) { 851 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); 852 dev_warn(adev->dev, "amdgpu: No coherent DMA available.\n"); 853 } 854 855 r = gmc_v6_0_init_microcode(adev); 856 if (r) { 857 dev_err(adev->dev, "Failed to load mc firmware!\n"); 858 return r; 859 } 860 861 r = gmc_v6_0_mc_init(adev); 862 if (r) 863 return r; 864 865 r = amdgpu_bo_init(adev); 866 if (r) 867 return r; 868 869 r = gmc_v6_0_gart_init(adev); 870 if (r) 871 return r; 872 873 /* 874 * number of VMs 875 * VMID 0 is reserved for System 876 * amdgpu graphics/compute will use VMIDs 1-7 877 * amdkfd will use VMIDs 8-15 878 */ 879 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; 880 amdgpu_vm_manager_init(adev); 881 882 /* base offset of vram pages */ 883 if (adev->flags & AMD_IS_APU) { 884 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 885 886 tmp <<= 22; 887 adev->vm_manager.vram_base_offset = tmp; 888 } else { 889 adev->vm_manager.vram_base_offset = 0; 890 } 891 892 return 0; 893 } 894 895 static int gmc_v6_0_sw_fini(void *handle) 896 { 897 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 898 899 amdgpu_gem_force_release(adev); 900 amdgpu_vm_manager_fini(adev); 901 gmc_v6_0_gart_fini(adev); 902 amdgpu_bo_fini(adev); 903 release_firmware(adev->mc.fw); 904 adev->mc.fw = NULL; 905 906 return 0; 907 } 908 909 static int gmc_v6_0_hw_init(void *handle) 910 { 911 int r; 912 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 913 914 gmc_v6_0_mc_program(adev); 915 916 if (!(adev->flags & AMD_IS_APU)) { 917 r = gmc_v6_0_mc_load_microcode(adev); 918 if (r) { 919 dev_err(adev->dev, "Failed to load MC firmware!\n"); 920 return r; 921 } 922 } 923 924 r = gmc_v6_0_gart_enable(adev); 925 if (r) 926 return r; 927 928 return r; 929 } 930 931 static int gmc_v6_0_hw_fini(void *handle) 932 { 933 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 934 935 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0); 936 gmc_v6_0_gart_disable(adev); 937 938 return 0; 939 } 940 941 static int gmc_v6_0_suspend(void *handle) 942 { 943 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 944 945 gmc_v6_0_hw_fini(adev); 946 947 return 0; 948 } 949 950 static int gmc_v6_0_resume(void *handle) 951 { 952 int r; 953 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 954 955 r = gmc_v6_0_hw_init(adev); 956 if (r) 957 return r; 958 959 amdgpu_vmid_reset_all(adev); 960 961 return 0; 962 } 963 964 static bool gmc_v6_0_is_idle(void *handle) 965 { 966 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 967 u32 tmp = RREG32(mmSRBM_STATUS); 968 969 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 970 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 971 return false; 972 973 return true; 974 } 975 976 static int gmc_v6_0_wait_for_idle(void *handle) 977 { 978 unsigned i; 979 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 980 981 for (i = 0; i < adev->usec_timeout; i++) { 982 if (gmc_v6_0_is_idle(handle)) 983 return 0; 984 udelay(1); 985 } 986 return -ETIMEDOUT; 987 988 } 989 990 static int gmc_v6_0_soft_reset(void *handle) 991 { 992 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 993 u32 srbm_soft_reset = 0; 994 u32 tmp = RREG32(mmSRBM_STATUS); 995 996 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 997 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 998 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 999 1000 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1001 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 1002 if (!(adev->flags & AMD_IS_APU)) 1003 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1004 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1005 } 1006 1007 if (srbm_soft_reset) { 1008 gmc_v6_0_mc_stop(adev); 1009 if (gmc_v6_0_wait_for_idle(adev)) { 1010 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1011 } 1012 1013 1014 tmp = RREG32(mmSRBM_SOFT_RESET); 1015 tmp |= srbm_soft_reset; 1016 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1017 WREG32(mmSRBM_SOFT_RESET, tmp); 1018 tmp = RREG32(mmSRBM_SOFT_RESET); 1019 1020 udelay(50); 1021 1022 tmp &= ~srbm_soft_reset; 1023 WREG32(mmSRBM_SOFT_RESET, tmp); 1024 tmp = RREG32(mmSRBM_SOFT_RESET); 1025 1026 udelay(50); 1027 1028 gmc_v6_0_mc_resume(adev); 1029 udelay(50); 1030 } 1031 1032 return 0; 1033 } 1034 1035 static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1036 struct amdgpu_irq_src *src, 1037 unsigned type, 1038 enum amdgpu_interrupt_state state) 1039 { 1040 u32 tmp; 1041 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1042 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1043 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1044 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1045 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1046 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1047 1048 switch (state) { 1049 case AMDGPU_IRQ_STATE_DISABLE: 1050 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1051 tmp &= ~bits; 1052 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1053 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1054 tmp &= ~bits; 1055 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1056 break; 1057 case AMDGPU_IRQ_STATE_ENABLE: 1058 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1059 tmp |= bits; 1060 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1061 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1062 tmp |= bits; 1063 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1064 break; 1065 default: 1066 break; 1067 } 1068 1069 return 0; 1070 } 1071 1072 static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev, 1073 struct amdgpu_irq_src *source, 1074 struct amdgpu_iv_entry *entry) 1075 { 1076 u32 addr, status; 1077 1078 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1079 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1080 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1081 1082 if (!addr && !status) 1083 return 0; 1084 1085 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1086 gmc_v6_0_set_fault_enable_default(adev, false); 1087 1088 if (printk_ratelimit()) { 1089 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1090 entry->src_id, entry->src_data[0]); 1091 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1092 addr); 1093 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1094 status); 1095 gmc_v6_0_vm_decode_fault(adev, status, addr, 0); 1096 } 1097 1098 return 0; 1099 } 1100 1101 static int gmc_v6_0_set_clockgating_state(void *handle, 1102 enum amd_clockgating_state state) 1103 { 1104 return 0; 1105 } 1106 1107 static int gmc_v6_0_set_powergating_state(void *handle, 1108 enum amd_powergating_state state) 1109 { 1110 return 0; 1111 } 1112 1113 static const struct amd_ip_funcs gmc_v6_0_ip_funcs = { 1114 .name = "gmc_v6_0", 1115 .early_init = gmc_v6_0_early_init, 1116 .late_init = gmc_v6_0_late_init, 1117 .sw_init = gmc_v6_0_sw_init, 1118 .sw_fini = gmc_v6_0_sw_fini, 1119 .hw_init = gmc_v6_0_hw_init, 1120 .hw_fini = gmc_v6_0_hw_fini, 1121 .suspend = gmc_v6_0_suspend, 1122 .resume = gmc_v6_0_resume, 1123 .is_idle = gmc_v6_0_is_idle, 1124 .wait_for_idle = gmc_v6_0_wait_for_idle, 1125 .soft_reset = gmc_v6_0_soft_reset, 1126 .set_clockgating_state = gmc_v6_0_set_clockgating_state, 1127 .set_powergating_state = gmc_v6_0_set_powergating_state, 1128 }; 1129 1130 static const struct amdgpu_gart_funcs gmc_v6_0_gart_funcs = { 1131 .flush_gpu_tlb = gmc_v6_0_gart_flush_gpu_tlb, 1132 .set_pte_pde = gmc_v6_0_gart_set_pte_pde, 1133 .set_prt = gmc_v6_0_set_prt, 1134 .get_vm_pde = gmc_v6_0_get_vm_pde, 1135 .get_vm_pte_flags = gmc_v6_0_get_vm_pte_flags 1136 }; 1137 1138 static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = { 1139 .set = gmc_v6_0_vm_fault_interrupt_state, 1140 .process = gmc_v6_0_process_interrupt, 1141 }; 1142 1143 static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev) 1144 { 1145 if (adev->gart.gart_funcs == NULL) 1146 adev->gart.gart_funcs = &gmc_v6_0_gart_funcs; 1147 } 1148 1149 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev) 1150 { 1151 adev->mc.vm_fault.num_types = 1; 1152 adev->mc.vm_fault.funcs = &gmc_v6_0_irq_funcs; 1153 } 1154 1155 const struct amdgpu_ip_block_version gmc_v6_0_ip_block = 1156 { 1157 .type = AMD_IP_BLOCK_TYPE_GMC, 1158 .major = 6, 1159 .minor = 0, 1160 .rev = 0, 1161 .funcs = &gmc_v6_0_ip_funcs, 1162 }; 1163