1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <drm/drmP.h> 25 #include <drm/drm_cache.h> 26 #include "amdgpu.h" 27 #include "gmc_v6_0.h" 28 #include "amdgpu_ucode.h" 29 #include "amdgpu_gem.h" 30 31 #include "bif/bif_3_0_d.h" 32 #include "bif/bif_3_0_sh_mask.h" 33 #include "oss/oss_1_0_d.h" 34 #include "oss/oss_1_0_sh_mask.h" 35 #include "gmc/gmc_6_0_d.h" 36 #include "gmc/gmc_6_0_sh_mask.h" 37 #include "dce/dce_6_0_d.h" 38 #include "dce/dce_6_0_sh_mask.h" 39 #include "si_enums.h" 40 41 static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev); 42 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev); 43 static int gmc_v6_0_wait_for_idle(void *handle); 44 45 MODULE_FIRMWARE("amdgpu/tahiti_mc.bin"); 46 MODULE_FIRMWARE("amdgpu/pitcairn_mc.bin"); 47 MODULE_FIRMWARE("amdgpu/verde_mc.bin"); 48 MODULE_FIRMWARE("amdgpu/oland_mc.bin"); 49 MODULE_FIRMWARE("amdgpu/si58_mc.bin"); 50 51 #define MC_SEQ_MISC0__MT__MASK 0xf0000000 52 #define MC_SEQ_MISC0__MT__GDDR1 0x10000000 53 #define MC_SEQ_MISC0__MT__DDR2 0x20000000 54 #define MC_SEQ_MISC0__MT__GDDR3 0x30000000 55 #define MC_SEQ_MISC0__MT__GDDR4 0x40000000 56 #define MC_SEQ_MISC0__MT__GDDR5 0x50000000 57 #define MC_SEQ_MISC0__MT__HBM 0x60000000 58 #define MC_SEQ_MISC0__MT__DDR3 0xB0000000 59 60 61 static const u32 crtc_offsets[6] = 62 { 63 SI_CRTC0_REGISTER_OFFSET, 64 SI_CRTC1_REGISTER_OFFSET, 65 SI_CRTC2_REGISTER_OFFSET, 66 SI_CRTC3_REGISTER_OFFSET, 67 SI_CRTC4_REGISTER_OFFSET, 68 SI_CRTC5_REGISTER_OFFSET 69 }; 70 71 static void gmc_v6_0_mc_stop(struct amdgpu_device *adev) 72 { 73 u32 blackout; 74 75 gmc_v6_0_wait_for_idle((void *)adev); 76 77 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 78 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 79 /* Block CPU access */ 80 WREG32(mmBIF_FB_EN, 0); 81 /* blackout the MC */ 82 blackout = REG_SET_FIELD(blackout, 83 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 84 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); 85 } 86 /* wait for the MC to settle */ 87 udelay(100); 88 89 } 90 91 static void gmc_v6_0_mc_resume(struct amdgpu_device *adev) 92 { 93 u32 tmp; 94 95 /* unblackout the MC */ 96 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 97 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 98 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 99 /* allow CPU access */ 100 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 101 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 102 WREG32(mmBIF_FB_EN, tmp); 103 } 104 105 static int gmc_v6_0_init_microcode(struct amdgpu_device *adev) 106 { 107 const char *chip_name; 108 char fw_name[30]; 109 int err; 110 bool is_58_fw = false; 111 112 DRM_DEBUG("\n"); 113 114 switch (adev->asic_type) { 115 case CHIP_TAHITI: 116 chip_name = "tahiti"; 117 break; 118 case CHIP_PITCAIRN: 119 chip_name = "pitcairn"; 120 break; 121 case CHIP_VERDE: 122 chip_name = "verde"; 123 break; 124 case CHIP_OLAND: 125 chip_name = "oland"; 126 break; 127 case CHIP_HAINAN: 128 chip_name = "hainan"; 129 break; 130 default: BUG(); 131 } 132 133 /* this memory configuration requires special firmware */ 134 if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58) 135 is_58_fw = true; 136 137 if (is_58_fw) 138 snprintf(fw_name, sizeof(fw_name), "amdgpu/si58_mc.bin"); 139 else 140 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name); 141 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); 142 if (err) 143 goto out; 144 145 err = amdgpu_ucode_validate(adev->gmc.fw); 146 147 out: 148 if (err) { 149 dev_err(adev->dev, 150 "si_mc: Failed to load firmware \"%s\"\n", 151 fw_name); 152 release_firmware(adev->gmc.fw); 153 adev->gmc.fw = NULL; 154 } 155 return err; 156 } 157 158 static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev) 159 { 160 const __le32 *new_fw_data = NULL; 161 u32 running; 162 const __le32 *new_io_mc_regs = NULL; 163 int i, regs_size, ucode_size; 164 const struct mc_firmware_header_v1_0 *hdr; 165 166 if (!adev->gmc.fw) 167 return -EINVAL; 168 169 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 170 171 amdgpu_ucode_print_mc_hdr(&hdr->header); 172 173 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 174 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 175 new_io_mc_regs = (const __le32 *) 176 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 177 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 178 new_fw_data = (const __le32 *) 179 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 180 181 running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK; 182 183 if (running == 0) { 184 185 /* reset the engine and set to writable */ 186 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 187 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 188 189 /* load mc io regs */ 190 for (i = 0; i < regs_size; i++) { 191 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); 192 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); 193 } 194 /* load the MC ucode */ 195 for (i = 0; i < ucode_size; i++) { 196 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); 197 } 198 199 /* put the engine back into the active state */ 200 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 201 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 202 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 203 204 /* wait for training to complete */ 205 for (i = 0; i < adev->usec_timeout; i++) { 206 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK) 207 break; 208 udelay(1); 209 } 210 for (i = 0; i < adev->usec_timeout; i++) { 211 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK) 212 break; 213 udelay(1); 214 } 215 216 } 217 218 return 0; 219 } 220 221 static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev, 222 struct amdgpu_gmc *mc) 223 { 224 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; 225 base <<= 24; 226 227 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 228 amdgpu_gmc_gart_location(adev, mc); 229 } 230 231 static void gmc_v6_0_mc_program(struct amdgpu_device *adev) 232 { 233 int i, j; 234 235 /* Initialize HDP */ 236 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 237 WREG32((0xb05 + j), 0x00000000); 238 WREG32((0xb06 + j), 0x00000000); 239 WREG32((0xb07 + j), 0x00000000); 240 WREG32((0xb08 + j), 0x00000000); 241 WREG32((0xb09 + j), 0x00000000); 242 } 243 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 244 245 if (gmc_v6_0_wait_for_idle((void *)adev)) { 246 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 247 } 248 249 if (adev->mode_info.num_crtc) { 250 u32 tmp; 251 252 /* Lockout access through VGA aperture*/ 253 tmp = RREG32(mmVGA_HDP_CONTROL); 254 tmp |= VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK; 255 WREG32(mmVGA_HDP_CONTROL, tmp); 256 257 /* disable VGA render */ 258 tmp = RREG32(mmVGA_RENDER_CONTROL); 259 tmp &= ~VGA_VSTATUS_CNTL; 260 WREG32(mmVGA_RENDER_CONTROL, tmp); 261 } 262 /* Update configuration */ 263 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 264 adev->gmc.vram_start >> 12); 265 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 266 adev->gmc.vram_end >> 12); 267 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 268 adev->vram_scratch.gpu_addr >> 12); 269 WREG32(mmMC_VM_AGP_BASE, 0); 270 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); 271 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); 272 273 if (gmc_v6_0_wait_for_idle((void *)adev)) { 274 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 275 } 276 } 277 278 static int gmc_v6_0_mc_init(struct amdgpu_device *adev) 279 { 280 281 u32 tmp; 282 int chansize, numchan; 283 int r; 284 285 tmp = RREG32(mmMC_ARB_RAMCFG); 286 if (tmp & (1 << 11)) { 287 chansize = 16; 288 } else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK) { 289 chansize = 64; 290 } else { 291 chansize = 32; 292 } 293 tmp = RREG32(mmMC_SHARED_CHMAP); 294 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) { 295 case 0: 296 default: 297 numchan = 1; 298 break; 299 case 1: 300 numchan = 2; 301 break; 302 case 2: 303 numchan = 4; 304 break; 305 case 3: 306 numchan = 8; 307 break; 308 case 4: 309 numchan = 3; 310 break; 311 case 5: 312 numchan = 6; 313 break; 314 case 6: 315 numchan = 10; 316 break; 317 case 7: 318 numchan = 12; 319 break; 320 case 8: 321 numchan = 16; 322 break; 323 } 324 adev->gmc.vram_width = numchan * chansize; 325 /* size in MB on si */ 326 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 327 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 328 329 if (!(adev->flags & AMD_IS_APU)) { 330 r = amdgpu_device_resize_fb_bar(adev); 331 if (r) 332 return r; 333 } 334 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 335 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 336 adev->gmc.visible_vram_size = adev->gmc.aper_size; 337 338 /* set the gart size */ 339 if (amdgpu_gart_size == -1) { 340 switch (adev->asic_type) { 341 case CHIP_HAINAN: /* no MM engines */ 342 default: 343 adev->gmc.gart_size = 256ULL << 20; 344 break; 345 case CHIP_VERDE: /* UVD, VCE do not support GPUVM */ 346 case CHIP_TAHITI: /* UVD, VCE do not support GPUVM */ 347 case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */ 348 case CHIP_OLAND: /* UVD, VCE do not support GPUVM */ 349 adev->gmc.gart_size = 1024ULL << 20; 350 break; 351 } 352 } else { 353 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 354 } 355 356 gmc_v6_0_vram_gtt_location(adev, &adev->gmc); 357 358 return 0; 359 } 360 361 static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid) 362 { 363 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 364 } 365 366 static uint64_t gmc_v6_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 367 unsigned vmid, uint64_t pd_addr) 368 { 369 uint32_t reg; 370 371 /* write new base address */ 372 if (vmid < 8) 373 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; 374 else 375 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vmid - 8); 376 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); 377 378 /* bits 0-15 are the VM contexts0-15 */ 379 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); 380 381 return pd_addr; 382 } 383 384 static int gmc_v6_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 385 uint32_t gpu_page_idx, uint64_t addr, 386 uint64_t flags) 387 { 388 void __iomem *ptr = (void *)cpu_pt_addr; 389 uint64_t value; 390 391 value = addr & 0xFFFFFFFFFFFFF000ULL; 392 value |= flags; 393 writeq(value, ptr + (gpu_page_idx * 8)); 394 395 return 0; 396 } 397 398 static uint64_t gmc_v6_0_get_vm_pte_flags(struct amdgpu_device *adev, 399 uint32_t flags) 400 { 401 uint64_t pte_flag = 0; 402 403 if (flags & AMDGPU_VM_PAGE_READABLE) 404 pte_flag |= AMDGPU_PTE_READABLE; 405 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 406 pte_flag |= AMDGPU_PTE_WRITEABLE; 407 if (flags & AMDGPU_VM_PAGE_PRT) 408 pte_flag |= AMDGPU_PTE_PRT; 409 410 return pte_flag; 411 } 412 413 static void gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, int level, 414 uint64_t *addr, uint64_t *flags) 415 { 416 BUG_ON(*addr & 0xFFFFFF0000000FFFULL); 417 } 418 419 static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev, 420 bool value) 421 { 422 u32 tmp; 423 424 tmp = RREG32(mmVM_CONTEXT1_CNTL); 425 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 426 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 427 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 428 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 429 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 430 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 431 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 432 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 433 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 434 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 435 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 436 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 437 WREG32(mmVM_CONTEXT1_CNTL, tmp); 438 } 439 440 /** 441 + * gmc_v8_0_set_prt - set PRT VM fault 442 + * 443 + * @adev: amdgpu_device pointer 444 + * @enable: enable/disable VM fault handling for PRT 445 +*/ 446 static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable) 447 { 448 u32 tmp; 449 450 if (enable && !adev->gmc.prt_warning) { 451 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 452 adev->gmc.prt_warning = true; 453 } 454 455 tmp = RREG32(mmVM_PRT_CNTL); 456 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 457 CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS, 458 enable); 459 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 460 TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS, 461 enable); 462 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 463 L2_CACHE_STORE_INVALID_ENTRIES, 464 enable); 465 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 466 L1_TLB_STORE_INVALID_ENTRIES, 467 enable); 468 WREG32(mmVM_PRT_CNTL, tmp); 469 470 if (enable) { 471 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; 472 uint32_t high = adev->vm_manager.max_pfn - 473 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT); 474 475 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); 476 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); 477 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); 478 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); 479 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); 480 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); 481 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); 482 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); 483 } else { 484 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); 485 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); 486 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); 487 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); 488 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); 489 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); 490 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); 491 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); 492 } 493 } 494 495 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) 496 { 497 uint64_t table_addr; 498 int r, i; 499 u32 field; 500 501 if (adev->gart.bo == NULL) { 502 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 503 return -EINVAL; 504 } 505 r = amdgpu_gart_table_vram_pin(adev); 506 if (r) 507 return r; 508 509 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 510 511 /* Setup TLB control */ 512 WREG32(mmMC_VM_MX_L1_TLB_CNTL, 513 (0xA << 7) | 514 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK | 515 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK | 516 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK | 517 MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK | 518 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT)); 519 /* Setup L2 cache */ 520 WREG32(mmVM_L2_CNTL, 521 VM_L2_CNTL__ENABLE_L2_CACHE_MASK | 522 VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK | 523 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK | 524 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK | 525 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) | 526 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT)); 527 WREG32(mmVM_L2_CNTL2, 528 VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK | 529 VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK); 530 531 field = adev->vm_manager.fragment_size; 532 WREG32(mmVM_L2_CNTL3, 533 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK | 534 (field << VM_L2_CNTL3__BANK_SELECT__SHIFT) | 535 (field << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT)); 536 /* setup context0 */ 537 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); 538 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); 539 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12); 540 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 541 (u32)(adev->dummy_page_addr >> 12)); 542 WREG32(mmVM_CONTEXT0_CNTL2, 0); 543 WREG32(mmVM_CONTEXT0_CNTL, 544 VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK | 545 (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) | 546 VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK); 547 548 WREG32(0x575, 0); 549 WREG32(0x576, 0); 550 WREG32(0x577, 0); 551 552 /* empty context1-15 */ 553 /* set vm size, must be a multiple of 4 */ 554 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 555 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 556 /* Assign the pt base to something valid for now; the pts used for 557 * the VMs are determined by the application and setup and assigned 558 * on the fly in the vm part of radeon_gart.c 559 */ 560 for (i = 1; i < 16; i++) { 561 if (i < 8) 562 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 563 table_addr >> 12); 564 else 565 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 566 table_addr >> 12); 567 } 568 569 /* enable context1-15 */ 570 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 571 (u32)(adev->dummy_page_addr >> 12)); 572 WREG32(mmVM_CONTEXT1_CNTL2, 4); 573 WREG32(mmVM_CONTEXT1_CNTL, 574 VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK | 575 (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) | 576 ((adev->vm_manager.block_size - 9) 577 << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT)); 578 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 579 gmc_v6_0_set_fault_enable_default(adev, false); 580 else 581 gmc_v6_0_set_fault_enable_default(adev, true); 582 583 gmc_v6_0_flush_gpu_tlb(adev, 0); 584 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n", 585 (unsigned)(adev->gmc.gart_size >> 20), 586 (unsigned long long)table_addr); 587 adev->gart.ready = true; 588 return 0; 589 } 590 591 static int gmc_v6_0_gart_init(struct amdgpu_device *adev) 592 { 593 int r; 594 595 if (adev->gart.bo) { 596 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n"); 597 return 0; 598 } 599 r = amdgpu_gart_init(adev); 600 if (r) 601 return r; 602 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 603 adev->gart.gart_pte_flags = 0; 604 return amdgpu_gart_table_vram_alloc(adev); 605 } 606 607 static void gmc_v6_0_gart_disable(struct amdgpu_device *adev) 608 { 609 /*unsigned i; 610 611 for (i = 1; i < 16; ++i) { 612 uint32_t reg; 613 if (i < 8) 614 reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i ; 615 else 616 reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (i - 8); 617 adev->vm_manager.saved_table_addr[i] = RREG32(reg); 618 }*/ 619 620 /* Disable all tables */ 621 WREG32(mmVM_CONTEXT0_CNTL, 0); 622 WREG32(mmVM_CONTEXT1_CNTL, 0); 623 /* Setup TLB control */ 624 WREG32(mmMC_VM_MX_L1_TLB_CNTL, 625 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK | 626 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT)); 627 /* Setup L2 cache */ 628 WREG32(mmVM_L2_CNTL, 629 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK | 630 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK | 631 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) | 632 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT)); 633 WREG32(mmVM_L2_CNTL2, 0); 634 WREG32(mmVM_L2_CNTL3, 635 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK | 636 (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT)); 637 amdgpu_gart_table_vram_unpin(adev); 638 } 639 640 static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev, 641 u32 status, u32 addr, u32 mc_client) 642 { 643 u32 mc_id; 644 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 645 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 646 PROTECTIONS); 647 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 648 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 649 650 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 651 MEMORY_CLIENT_ID); 652 653 dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 654 protections, vmid, addr, 655 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 656 MEMORY_CLIENT_RW) ? 657 "write" : "read", block, mc_client, mc_id); 658 } 659 660 /* 661 static const u32 mc_cg_registers[] = { 662 MC_HUB_MISC_HUB_CG, 663 MC_HUB_MISC_SIP_CG, 664 MC_HUB_MISC_VM_CG, 665 MC_XPB_CLK_GAT, 666 ATC_MISC_CG, 667 MC_CITF_MISC_WR_CG, 668 MC_CITF_MISC_RD_CG, 669 MC_CITF_MISC_VM_CG, 670 VM_L2_CG, 671 }; 672 673 static const u32 mc_cg_ls_en[] = { 674 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK, 675 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK, 676 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK, 677 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK, 678 ATC_MISC_CG__MEM_LS_ENABLE_MASK, 679 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK, 680 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK, 681 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK, 682 VM_L2_CG__MEM_LS_ENABLE_MASK, 683 }; 684 685 static const u32 mc_cg_en[] = { 686 MC_HUB_MISC_HUB_CG__ENABLE_MASK, 687 MC_HUB_MISC_SIP_CG__ENABLE_MASK, 688 MC_HUB_MISC_VM_CG__ENABLE_MASK, 689 MC_XPB_CLK_GAT__ENABLE_MASK, 690 ATC_MISC_CG__ENABLE_MASK, 691 MC_CITF_MISC_WR_CG__ENABLE_MASK, 692 MC_CITF_MISC_RD_CG__ENABLE_MASK, 693 MC_CITF_MISC_VM_CG__ENABLE_MASK, 694 VM_L2_CG__ENABLE_MASK, 695 }; 696 697 static void gmc_v6_0_enable_mc_ls(struct amdgpu_device *adev, 698 bool enable) 699 { 700 int i; 701 u32 orig, data; 702 703 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 704 orig = data = RREG32(mc_cg_registers[i]); 705 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS)) 706 data |= mc_cg_ls_en[i]; 707 else 708 data &= ~mc_cg_ls_en[i]; 709 if (data != orig) 710 WREG32(mc_cg_registers[i], data); 711 } 712 } 713 714 static void gmc_v6_0_enable_mc_mgcg(struct amdgpu_device *adev, 715 bool enable) 716 { 717 int i; 718 u32 orig, data; 719 720 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 721 orig = data = RREG32(mc_cg_registers[i]); 722 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG)) 723 data |= mc_cg_en[i]; 724 else 725 data &= ~mc_cg_en[i]; 726 if (data != orig) 727 WREG32(mc_cg_registers[i], data); 728 } 729 } 730 731 static void gmc_v6_0_enable_bif_mgls(struct amdgpu_device *adev, 732 bool enable) 733 { 734 u32 orig, data; 735 736 orig = data = RREG32_PCIE(ixPCIE_CNTL2); 737 738 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) { 739 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1); 740 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1); 741 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1); 742 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1); 743 } else { 744 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0); 745 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0); 746 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0); 747 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0); 748 } 749 750 if (orig != data) 751 WREG32_PCIE(ixPCIE_CNTL2, data); 752 } 753 754 static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev, 755 bool enable) 756 { 757 u32 orig, data; 758 759 orig = data = RREG32(mmHDP_HOST_PATH_CNTL); 760 761 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG)) 762 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0); 763 else 764 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1); 765 766 if (orig != data) 767 WREG32(mmHDP_HOST_PATH_CNTL, data); 768 } 769 770 static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev, 771 bool enable) 772 { 773 u32 orig, data; 774 775 orig = data = RREG32(mmHDP_MEM_POWER_LS); 776 777 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS)) 778 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1); 779 else 780 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0); 781 782 if (orig != data) 783 WREG32(mmHDP_MEM_POWER_LS, data); 784 } 785 */ 786 787 static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type) 788 { 789 switch (mc_seq_vram_type) { 790 case MC_SEQ_MISC0__MT__GDDR1: 791 return AMDGPU_VRAM_TYPE_GDDR1; 792 case MC_SEQ_MISC0__MT__DDR2: 793 return AMDGPU_VRAM_TYPE_DDR2; 794 case MC_SEQ_MISC0__MT__GDDR3: 795 return AMDGPU_VRAM_TYPE_GDDR3; 796 case MC_SEQ_MISC0__MT__GDDR4: 797 return AMDGPU_VRAM_TYPE_GDDR4; 798 case MC_SEQ_MISC0__MT__GDDR5: 799 return AMDGPU_VRAM_TYPE_GDDR5; 800 case MC_SEQ_MISC0__MT__DDR3: 801 return AMDGPU_VRAM_TYPE_DDR3; 802 default: 803 return AMDGPU_VRAM_TYPE_UNKNOWN; 804 } 805 } 806 807 static int gmc_v6_0_early_init(void *handle) 808 { 809 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 810 811 gmc_v6_0_set_gmc_funcs(adev); 812 gmc_v6_0_set_irq_funcs(adev); 813 814 return 0; 815 } 816 817 static int gmc_v6_0_late_init(void *handle) 818 { 819 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 820 821 amdgpu_bo_late_init(adev); 822 823 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 824 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 825 else 826 return 0; 827 } 828 829 static unsigned gmc_v6_0_get_vbios_fb_size(struct amdgpu_device *adev) 830 { 831 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); 832 unsigned size; 833 834 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 835 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */ 836 } else { 837 u32 viewport = RREG32(mmVIEWPORT_SIZE); 838 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 839 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * 840 4); 841 } 842 /* return 0 if the pre-OS buffer uses up most of vram */ 843 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 844 return 0; 845 return size; 846 } 847 848 static int gmc_v6_0_sw_init(void *handle) 849 { 850 int r; 851 int dma_bits; 852 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 853 854 if (adev->flags & AMD_IS_APU) { 855 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 856 } else { 857 u32 tmp = RREG32(mmMC_SEQ_MISC0); 858 tmp &= MC_SEQ_MISC0__MT__MASK; 859 adev->gmc.vram_type = gmc_v6_0_convert_vram_type(tmp); 860 } 861 862 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault); 863 if (r) 864 return r; 865 866 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault); 867 if (r) 868 return r; 869 870 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); 871 872 adev->gmc.mc_mask = 0xffffffffffULL; 873 874 adev->need_dma32 = false; 875 dma_bits = adev->need_dma32 ? 32 : 40; 876 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 877 if (r) { 878 adev->need_dma32 = true; 879 dma_bits = 32; 880 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); 881 } 882 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 883 if (r) { 884 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); 885 dev_warn(adev->dev, "amdgpu: No coherent DMA available.\n"); 886 } 887 adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits); 888 889 r = gmc_v6_0_init_microcode(adev); 890 if (r) { 891 dev_err(adev->dev, "Failed to load mc firmware!\n"); 892 return r; 893 } 894 895 r = gmc_v6_0_mc_init(adev); 896 if (r) 897 return r; 898 899 adev->gmc.stolen_size = gmc_v6_0_get_vbios_fb_size(adev); 900 901 r = amdgpu_bo_init(adev); 902 if (r) 903 return r; 904 905 r = gmc_v6_0_gart_init(adev); 906 if (r) 907 return r; 908 909 /* 910 * number of VMs 911 * VMID 0 is reserved for System 912 * amdgpu graphics/compute will use VMIDs 1-7 913 * amdkfd will use VMIDs 8-15 914 */ 915 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; 916 amdgpu_vm_manager_init(adev); 917 918 /* base offset of vram pages */ 919 if (adev->flags & AMD_IS_APU) { 920 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 921 922 tmp <<= 22; 923 adev->vm_manager.vram_base_offset = tmp; 924 } else { 925 adev->vm_manager.vram_base_offset = 0; 926 } 927 928 return 0; 929 } 930 931 static int gmc_v6_0_sw_fini(void *handle) 932 { 933 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 934 935 amdgpu_gem_force_release(adev); 936 amdgpu_vm_manager_fini(adev); 937 amdgpu_gart_table_vram_free(adev); 938 amdgpu_bo_fini(adev); 939 amdgpu_gart_fini(adev); 940 release_firmware(adev->gmc.fw); 941 adev->gmc.fw = NULL; 942 943 return 0; 944 } 945 946 static int gmc_v6_0_hw_init(void *handle) 947 { 948 int r; 949 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 950 951 gmc_v6_0_mc_program(adev); 952 953 if (!(adev->flags & AMD_IS_APU)) { 954 r = gmc_v6_0_mc_load_microcode(adev); 955 if (r) { 956 dev_err(adev->dev, "Failed to load MC firmware!\n"); 957 return r; 958 } 959 } 960 961 r = gmc_v6_0_gart_enable(adev); 962 if (r) 963 return r; 964 965 return r; 966 } 967 968 static int gmc_v6_0_hw_fini(void *handle) 969 { 970 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 971 972 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 973 gmc_v6_0_gart_disable(adev); 974 975 return 0; 976 } 977 978 static int gmc_v6_0_suspend(void *handle) 979 { 980 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 981 982 gmc_v6_0_hw_fini(adev); 983 984 return 0; 985 } 986 987 static int gmc_v6_0_resume(void *handle) 988 { 989 int r; 990 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 991 992 r = gmc_v6_0_hw_init(adev); 993 if (r) 994 return r; 995 996 amdgpu_vmid_reset_all(adev); 997 998 return 0; 999 } 1000 1001 static bool gmc_v6_0_is_idle(void *handle) 1002 { 1003 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1004 u32 tmp = RREG32(mmSRBM_STATUS); 1005 1006 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1007 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 1008 return false; 1009 1010 return true; 1011 } 1012 1013 static int gmc_v6_0_wait_for_idle(void *handle) 1014 { 1015 unsigned i; 1016 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1017 1018 for (i = 0; i < adev->usec_timeout; i++) { 1019 if (gmc_v6_0_is_idle(handle)) 1020 return 0; 1021 udelay(1); 1022 } 1023 return -ETIMEDOUT; 1024 1025 } 1026 1027 static int gmc_v6_0_soft_reset(void *handle) 1028 { 1029 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1030 u32 srbm_soft_reset = 0; 1031 u32 tmp = RREG32(mmSRBM_STATUS); 1032 1033 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1034 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1035 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 1036 1037 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1038 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 1039 if (!(adev->flags & AMD_IS_APU)) 1040 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1041 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1042 } 1043 1044 if (srbm_soft_reset) { 1045 gmc_v6_0_mc_stop(adev); 1046 if (gmc_v6_0_wait_for_idle(adev)) { 1047 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1048 } 1049 1050 1051 tmp = RREG32(mmSRBM_SOFT_RESET); 1052 tmp |= srbm_soft_reset; 1053 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1054 WREG32(mmSRBM_SOFT_RESET, tmp); 1055 tmp = RREG32(mmSRBM_SOFT_RESET); 1056 1057 udelay(50); 1058 1059 tmp &= ~srbm_soft_reset; 1060 WREG32(mmSRBM_SOFT_RESET, tmp); 1061 tmp = RREG32(mmSRBM_SOFT_RESET); 1062 1063 udelay(50); 1064 1065 gmc_v6_0_mc_resume(adev); 1066 udelay(50); 1067 } 1068 1069 return 0; 1070 } 1071 1072 static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1073 struct amdgpu_irq_src *src, 1074 unsigned type, 1075 enum amdgpu_interrupt_state state) 1076 { 1077 u32 tmp; 1078 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1079 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1080 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1081 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1082 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1083 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1084 1085 switch (state) { 1086 case AMDGPU_IRQ_STATE_DISABLE: 1087 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1088 tmp &= ~bits; 1089 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1090 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1091 tmp &= ~bits; 1092 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1093 break; 1094 case AMDGPU_IRQ_STATE_ENABLE: 1095 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1096 tmp |= bits; 1097 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1098 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1099 tmp |= bits; 1100 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1101 break; 1102 default: 1103 break; 1104 } 1105 1106 return 0; 1107 } 1108 1109 static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev, 1110 struct amdgpu_irq_src *source, 1111 struct amdgpu_iv_entry *entry) 1112 { 1113 u32 addr, status; 1114 1115 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1116 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1117 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1118 1119 if (!addr && !status) 1120 return 0; 1121 1122 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1123 gmc_v6_0_set_fault_enable_default(adev, false); 1124 1125 if (printk_ratelimit()) { 1126 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1127 entry->src_id, entry->src_data[0]); 1128 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1129 addr); 1130 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1131 status); 1132 gmc_v6_0_vm_decode_fault(adev, status, addr, 0); 1133 } 1134 1135 return 0; 1136 } 1137 1138 static int gmc_v6_0_set_clockgating_state(void *handle, 1139 enum amd_clockgating_state state) 1140 { 1141 return 0; 1142 } 1143 1144 static int gmc_v6_0_set_powergating_state(void *handle, 1145 enum amd_powergating_state state) 1146 { 1147 return 0; 1148 } 1149 1150 static const struct amd_ip_funcs gmc_v6_0_ip_funcs = { 1151 .name = "gmc_v6_0", 1152 .early_init = gmc_v6_0_early_init, 1153 .late_init = gmc_v6_0_late_init, 1154 .sw_init = gmc_v6_0_sw_init, 1155 .sw_fini = gmc_v6_0_sw_fini, 1156 .hw_init = gmc_v6_0_hw_init, 1157 .hw_fini = gmc_v6_0_hw_fini, 1158 .suspend = gmc_v6_0_suspend, 1159 .resume = gmc_v6_0_resume, 1160 .is_idle = gmc_v6_0_is_idle, 1161 .wait_for_idle = gmc_v6_0_wait_for_idle, 1162 .soft_reset = gmc_v6_0_soft_reset, 1163 .set_clockgating_state = gmc_v6_0_set_clockgating_state, 1164 .set_powergating_state = gmc_v6_0_set_powergating_state, 1165 }; 1166 1167 static const struct amdgpu_gmc_funcs gmc_v6_0_gmc_funcs = { 1168 .flush_gpu_tlb = gmc_v6_0_flush_gpu_tlb, 1169 .emit_flush_gpu_tlb = gmc_v6_0_emit_flush_gpu_tlb, 1170 .set_pte_pde = gmc_v6_0_set_pte_pde, 1171 .set_prt = gmc_v6_0_set_prt, 1172 .get_vm_pde = gmc_v6_0_get_vm_pde, 1173 .get_vm_pte_flags = gmc_v6_0_get_vm_pte_flags 1174 }; 1175 1176 static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = { 1177 .set = gmc_v6_0_vm_fault_interrupt_state, 1178 .process = gmc_v6_0_process_interrupt, 1179 }; 1180 1181 static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev) 1182 { 1183 adev->gmc.gmc_funcs = &gmc_v6_0_gmc_funcs; 1184 } 1185 1186 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev) 1187 { 1188 adev->gmc.vm_fault.num_types = 1; 1189 adev->gmc.vm_fault.funcs = &gmc_v6_0_irq_funcs; 1190 } 1191 1192 const struct amdgpu_ip_block_version gmc_v6_0_ip_block = 1193 { 1194 .type = AMD_IP_BLOCK_TYPE_GMC, 1195 .major = 6, 1196 .minor = 0, 1197 .rev = 0, 1198 .funcs = &gmc_v6_0_ip_funcs, 1199 }; 1200