1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <drm/drmP.h> 25 #include "amdgpu.h" 26 #include "gmc_v6_0.h" 27 #include "amdgpu_ucode.h" 28 29 #include "bif/bif_3_0_d.h" 30 #include "bif/bif_3_0_sh_mask.h" 31 #include "oss/oss_1_0_d.h" 32 #include "oss/oss_1_0_sh_mask.h" 33 #include "gmc/gmc_6_0_d.h" 34 #include "gmc/gmc_6_0_sh_mask.h" 35 #include "dce/dce_6_0_d.h" 36 #include "dce/dce_6_0_sh_mask.h" 37 #include "si_enums.h" 38 39 static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev); 40 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev); 41 static int gmc_v6_0_wait_for_idle(void *handle); 42 43 MODULE_FIRMWARE("radeon/tahiti_mc.bin"); 44 MODULE_FIRMWARE("radeon/pitcairn_mc.bin"); 45 MODULE_FIRMWARE("radeon/verde_mc.bin"); 46 MODULE_FIRMWARE("radeon/oland_mc.bin"); 47 MODULE_FIRMWARE("radeon/si58_mc.bin"); 48 49 #define MC_SEQ_MISC0__MT__MASK 0xf0000000 50 #define MC_SEQ_MISC0__MT__GDDR1 0x10000000 51 #define MC_SEQ_MISC0__MT__DDR2 0x20000000 52 #define MC_SEQ_MISC0__MT__GDDR3 0x30000000 53 #define MC_SEQ_MISC0__MT__GDDR4 0x40000000 54 #define MC_SEQ_MISC0__MT__GDDR5 0x50000000 55 #define MC_SEQ_MISC0__MT__HBM 0x60000000 56 #define MC_SEQ_MISC0__MT__DDR3 0xB0000000 57 58 59 static const u32 crtc_offsets[6] = 60 { 61 SI_CRTC0_REGISTER_OFFSET, 62 SI_CRTC1_REGISTER_OFFSET, 63 SI_CRTC2_REGISTER_OFFSET, 64 SI_CRTC3_REGISTER_OFFSET, 65 SI_CRTC4_REGISTER_OFFSET, 66 SI_CRTC5_REGISTER_OFFSET 67 }; 68 69 static void gmc_v6_0_mc_stop(struct amdgpu_device *adev) 70 { 71 u32 blackout; 72 73 gmc_v6_0_wait_for_idle((void *)adev); 74 75 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 76 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 77 /* Block CPU access */ 78 WREG32(mmBIF_FB_EN, 0); 79 /* blackout the MC */ 80 blackout = REG_SET_FIELD(blackout, 81 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 82 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); 83 } 84 /* wait for the MC to settle */ 85 udelay(100); 86 87 } 88 89 static void gmc_v6_0_mc_resume(struct amdgpu_device *adev) 90 { 91 u32 tmp; 92 93 /* unblackout the MC */ 94 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 95 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 96 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 97 /* allow CPU access */ 98 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 99 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 100 WREG32(mmBIF_FB_EN, tmp); 101 } 102 103 static int gmc_v6_0_init_microcode(struct amdgpu_device *adev) 104 { 105 const char *chip_name; 106 char fw_name[30]; 107 int err; 108 bool is_58_fw = false; 109 110 DRM_DEBUG("\n"); 111 112 switch (adev->asic_type) { 113 case CHIP_TAHITI: 114 chip_name = "tahiti"; 115 break; 116 case CHIP_PITCAIRN: 117 chip_name = "pitcairn"; 118 break; 119 case CHIP_VERDE: 120 chip_name = "verde"; 121 break; 122 case CHIP_OLAND: 123 chip_name = "oland"; 124 break; 125 case CHIP_HAINAN: 126 chip_name = "hainan"; 127 break; 128 default: BUG(); 129 } 130 131 /* this memory configuration requires special firmware */ 132 if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58) 133 is_58_fw = true; 134 135 if (is_58_fw) 136 snprintf(fw_name, sizeof(fw_name), "radeon/si58_mc.bin"); 137 else 138 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); 139 err = request_firmware(&adev->mc.fw, fw_name, adev->dev); 140 if (err) 141 goto out; 142 143 err = amdgpu_ucode_validate(adev->mc.fw); 144 145 out: 146 if (err) { 147 dev_err(adev->dev, 148 "si_mc: Failed to load firmware \"%s\"\n", 149 fw_name); 150 release_firmware(adev->mc.fw); 151 adev->mc.fw = NULL; 152 } 153 return err; 154 } 155 156 static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev) 157 { 158 const __le32 *new_fw_data = NULL; 159 u32 running; 160 const __le32 *new_io_mc_regs = NULL; 161 int i, regs_size, ucode_size; 162 const struct mc_firmware_header_v1_0 *hdr; 163 164 if (!adev->mc.fw) 165 return -EINVAL; 166 167 hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data; 168 169 amdgpu_ucode_print_mc_hdr(&hdr->header); 170 171 adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version); 172 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 173 new_io_mc_regs = (const __le32 *) 174 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 175 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 176 new_fw_data = (const __le32 *) 177 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 178 179 running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK; 180 181 if (running == 0) { 182 183 /* reset the engine and set to writable */ 184 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 185 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 186 187 /* load mc io regs */ 188 for (i = 0; i < regs_size; i++) { 189 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); 190 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); 191 } 192 /* load the MC ucode */ 193 for (i = 0; i < ucode_size; i++) { 194 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); 195 } 196 197 /* put the engine back into the active state */ 198 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 199 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 200 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 201 202 /* wait for training to complete */ 203 for (i = 0; i < adev->usec_timeout; i++) { 204 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK) 205 break; 206 udelay(1); 207 } 208 for (i = 0; i < adev->usec_timeout; i++) { 209 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK) 210 break; 211 udelay(1); 212 } 213 214 } 215 216 return 0; 217 } 218 219 static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev, 220 struct amdgpu_mc *mc) 221 { 222 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; 223 base <<= 24; 224 225 if (mc->mc_vram_size > 0xFFC0000000ULL) { 226 dev_warn(adev->dev, "limiting VRAM\n"); 227 mc->real_vram_size = 0xFFC0000000ULL; 228 mc->mc_vram_size = 0xFFC0000000ULL; 229 } 230 amdgpu_vram_location(adev, &adev->mc, base); 231 amdgpu_gart_location(adev, mc); 232 } 233 234 static void gmc_v6_0_mc_program(struct amdgpu_device *adev) 235 { 236 int i, j; 237 238 /* Initialize HDP */ 239 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 240 WREG32((0xb05 + j), 0x00000000); 241 WREG32((0xb06 + j), 0x00000000); 242 WREG32((0xb07 + j), 0x00000000); 243 WREG32((0xb08 + j), 0x00000000); 244 WREG32((0xb09 + j), 0x00000000); 245 } 246 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 247 248 if (gmc_v6_0_wait_for_idle((void *)adev)) { 249 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 250 } 251 252 if (adev->mode_info.num_crtc) { 253 u32 tmp; 254 255 /* Lockout access through VGA aperture*/ 256 tmp = RREG32(mmVGA_HDP_CONTROL); 257 tmp |= VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK; 258 WREG32(mmVGA_HDP_CONTROL, tmp); 259 260 /* disable VGA render */ 261 tmp = RREG32(mmVGA_RENDER_CONTROL); 262 tmp &= ~VGA_VSTATUS_CNTL; 263 WREG32(mmVGA_RENDER_CONTROL, tmp); 264 } 265 /* Update configuration */ 266 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 267 adev->mc.vram_start >> 12); 268 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 269 adev->mc.vram_end >> 12); 270 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 271 adev->vram_scratch.gpu_addr >> 12); 272 WREG32(mmMC_VM_AGP_BASE, 0); 273 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); 274 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); 275 276 if (gmc_v6_0_wait_for_idle((void *)adev)) { 277 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 278 } 279 } 280 281 static int gmc_v6_0_mc_init(struct amdgpu_device *adev) 282 { 283 284 u32 tmp; 285 int chansize, numchan; 286 287 tmp = RREG32(mmMC_ARB_RAMCFG); 288 if (tmp & (1 << 11)) { 289 chansize = 16; 290 } else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK) { 291 chansize = 64; 292 } else { 293 chansize = 32; 294 } 295 tmp = RREG32(mmMC_SHARED_CHMAP); 296 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) { 297 case 0: 298 default: 299 numchan = 1; 300 break; 301 case 1: 302 numchan = 2; 303 break; 304 case 2: 305 numchan = 4; 306 break; 307 case 3: 308 numchan = 8; 309 break; 310 case 4: 311 numchan = 3; 312 break; 313 case 5: 314 numchan = 6; 315 break; 316 case 6: 317 numchan = 10; 318 break; 319 case 7: 320 numchan = 12; 321 break; 322 case 8: 323 numchan = 16; 324 break; 325 } 326 adev->mc.vram_width = numchan * chansize; 327 /* Could aper size report 0 ? */ 328 adev->mc.aper_base = pci_resource_start(adev->pdev, 0); 329 adev->mc.aper_size = pci_resource_len(adev->pdev, 0); 330 /* size in MB on si */ 331 adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 332 adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 333 adev->mc.visible_vram_size = adev->mc.aper_size; 334 335 amdgpu_gart_set_defaults(adev); 336 gmc_v6_0_vram_gtt_location(adev, &adev->mc); 337 338 return 0; 339 } 340 341 static void gmc_v6_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, 342 uint32_t vmid) 343 { 344 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0); 345 346 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 347 } 348 349 static int gmc_v6_0_gart_set_pte_pde(struct amdgpu_device *adev, 350 void *cpu_pt_addr, 351 uint32_t gpu_page_idx, 352 uint64_t addr, 353 uint64_t flags) 354 { 355 void __iomem *ptr = (void *)cpu_pt_addr; 356 uint64_t value; 357 358 value = addr & 0xFFFFFFFFFFFFF000ULL; 359 value |= flags; 360 writeq(value, ptr + (gpu_page_idx * 8)); 361 362 return 0; 363 } 364 365 static uint64_t gmc_v6_0_get_vm_pte_flags(struct amdgpu_device *adev, 366 uint32_t flags) 367 { 368 uint64_t pte_flag = 0; 369 370 if (flags & AMDGPU_VM_PAGE_READABLE) 371 pte_flag |= AMDGPU_PTE_READABLE; 372 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 373 pte_flag |= AMDGPU_PTE_WRITEABLE; 374 if (flags & AMDGPU_VM_PAGE_PRT) 375 pte_flag |= AMDGPU_PTE_PRT; 376 377 return pte_flag; 378 } 379 380 static uint64_t gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, uint64_t addr) 381 { 382 BUG_ON(addr & 0xFFFFFF0000000FFFULL); 383 return addr; 384 } 385 386 static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev, 387 bool value) 388 { 389 u32 tmp; 390 391 tmp = RREG32(mmVM_CONTEXT1_CNTL); 392 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 393 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 394 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 395 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 396 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 397 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 398 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 399 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 400 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 401 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 402 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 403 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 404 WREG32(mmVM_CONTEXT1_CNTL, tmp); 405 } 406 407 /** 408 + * gmc_v8_0_set_prt - set PRT VM fault 409 + * 410 + * @adev: amdgpu_device pointer 411 + * @enable: enable/disable VM fault handling for PRT 412 +*/ 413 static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable) 414 { 415 u32 tmp; 416 417 if (enable && !adev->mc.prt_warning) { 418 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 419 adev->mc.prt_warning = true; 420 } 421 422 tmp = RREG32(mmVM_PRT_CNTL); 423 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 424 CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS, 425 enable); 426 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 427 TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS, 428 enable); 429 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 430 L2_CACHE_STORE_INVALID_ENTRIES, 431 enable); 432 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 433 L1_TLB_STORE_INVALID_ENTRIES, 434 enable); 435 WREG32(mmVM_PRT_CNTL, tmp); 436 437 if (enable) { 438 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; 439 uint32_t high = adev->vm_manager.max_pfn; 440 441 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); 442 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); 443 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); 444 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); 445 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); 446 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); 447 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); 448 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); 449 } else { 450 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); 451 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); 452 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); 453 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); 454 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); 455 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); 456 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); 457 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); 458 } 459 } 460 461 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) 462 { 463 int r, i; 464 u32 field; 465 466 if (adev->gart.robj == NULL) { 467 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 468 return -EINVAL; 469 } 470 r = amdgpu_gart_table_vram_pin(adev); 471 if (r) 472 return r; 473 /* Setup TLB control */ 474 WREG32(mmMC_VM_MX_L1_TLB_CNTL, 475 (0xA << 7) | 476 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK | 477 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK | 478 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK | 479 MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK | 480 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT)); 481 /* Setup L2 cache */ 482 WREG32(mmVM_L2_CNTL, 483 VM_L2_CNTL__ENABLE_L2_CACHE_MASK | 484 VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK | 485 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK | 486 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK | 487 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) | 488 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT)); 489 WREG32(mmVM_L2_CNTL2, 490 VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK | 491 VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK); 492 493 field = adev->vm_manager.fragment_size; 494 WREG32(mmVM_L2_CNTL3, 495 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK | 496 (field << VM_L2_CNTL3__BANK_SELECT__SHIFT) | 497 (field << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT)); 498 /* setup context0 */ 499 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gart_start >> 12); 500 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gart_end >> 12); 501 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); 502 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 503 (u32)(adev->dummy_page.addr >> 12)); 504 WREG32(mmVM_CONTEXT0_CNTL2, 0); 505 WREG32(mmVM_CONTEXT0_CNTL, 506 VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK | 507 (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) | 508 VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK); 509 510 WREG32(0x575, 0); 511 WREG32(0x576, 0); 512 WREG32(0x577, 0); 513 514 /* empty context1-15 */ 515 /* set vm size, must be a multiple of 4 */ 516 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 517 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 518 /* Assign the pt base to something valid for now; the pts used for 519 * the VMs are determined by the application and setup and assigned 520 * on the fly in the vm part of radeon_gart.c 521 */ 522 for (i = 1; i < 16; i++) { 523 if (i < 8) 524 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 525 adev->gart.table_addr >> 12); 526 else 527 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 528 adev->gart.table_addr >> 12); 529 } 530 531 /* enable context1-15 */ 532 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 533 (u32)(adev->dummy_page.addr >> 12)); 534 WREG32(mmVM_CONTEXT1_CNTL2, 4); 535 WREG32(mmVM_CONTEXT1_CNTL, 536 VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK | 537 (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) | 538 ((adev->vm_manager.block_size - 9) 539 << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT)); 540 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 541 gmc_v6_0_set_fault_enable_default(adev, false); 542 else 543 gmc_v6_0_set_fault_enable_default(adev, true); 544 545 gmc_v6_0_gart_flush_gpu_tlb(adev, 0); 546 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n", 547 (unsigned)(adev->mc.gart_size >> 20), 548 (unsigned long long)adev->gart.table_addr); 549 adev->gart.ready = true; 550 return 0; 551 } 552 553 static int gmc_v6_0_gart_init(struct amdgpu_device *adev) 554 { 555 int r; 556 557 if (adev->gart.robj) { 558 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n"); 559 return 0; 560 } 561 r = amdgpu_gart_init(adev); 562 if (r) 563 return r; 564 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 565 adev->gart.gart_pte_flags = 0; 566 return amdgpu_gart_table_vram_alloc(adev); 567 } 568 569 static void gmc_v6_0_gart_disable(struct amdgpu_device *adev) 570 { 571 /*unsigned i; 572 573 for (i = 1; i < 16; ++i) { 574 uint32_t reg; 575 if (i < 8) 576 reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i ; 577 else 578 reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (i - 8); 579 adev->vm_manager.saved_table_addr[i] = RREG32(reg); 580 }*/ 581 582 /* Disable all tables */ 583 WREG32(mmVM_CONTEXT0_CNTL, 0); 584 WREG32(mmVM_CONTEXT1_CNTL, 0); 585 /* Setup TLB control */ 586 WREG32(mmMC_VM_MX_L1_TLB_CNTL, 587 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK | 588 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT)); 589 /* Setup L2 cache */ 590 WREG32(mmVM_L2_CNTL, 591 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK | 592 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK | 593 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) | 594 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT)); 595 WREG32(mmVM_L2_CNTL2, 0); 596 WREG32(mmVM_L2_CNTL3, 597 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK | 598 (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT)); 599 amdgpu_gart_table_vram_unpin(adev); 600 } 601 602 static void gmc_v6_0_gart_fini(struct amdgpu_device *adev) 603 { 604 amdgpu_gart_table_vram_free(adev); 605 amdgpu_gart_fini(adev); 606 } 607 608 static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev, 609 u32 status, u32 addr, u32 mc_client) 610 { 611 u32 mc_id; 612 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 613 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 614 PROTECTIONS); 615 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 616 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 617 618 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 619 MEMORY_CLIENT_ID); 620 621 dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 622 protections, vmid, addr, 623 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 624 MEMORY_CLIENT_RW) ? 625 "write" : "read", block, mc_client, mc_id); 626 } 627 628 /* 629 static const u32 mc_cg_registers[] = { 630 MC_HUB_MISC_HUB_CG, 631 MC_HUB_MISC_SIP_CG, 632 MC_HUB_MISC_VM_CG, 633 MC_XPB_CLK_GAT, 634 ATC_MISC_CG, 635 MC_CITF_MISC_WR_CG, 636 MC_CITF_MISC_RD_CG, 637 MC_CITF_MISC_VM_CG, 638 VM_L2_CG, 639 }; 640 641 static const u32 mc_cg_ls_en[] = { 642 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK, 643 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK, 644 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK, 645 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK, 646 ATC_MISC_CG__MEM_LS_ENABLE_MASK, 647 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK, 648 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK, 649 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK, 650 VM_L2_CG__MEM_LS_ENABLE_MASK, 651 }; 652 653 static const u32 mc_cg_en[] = { 654 MC_HUB_MISC_HUB_CG__ENABLE_MASK, 655 MC_HUB_MISC_SIP_CG__ENABLE_MASK, 656 MC_HUB_MISC_VM_CG__ENABLE_MASK, 657 MC_XPB_CLK_GAT__ENABLE_MASK, 658 ATC_MISC_CG__ENABLE_MASK, 659 MC_CITF_MISC_WR_CG__ENABLE_MASK, 660 MC_CITF_MISC_RD_CG__ENABLE_MASK, 661 MC_CITF_MISC_VM_CG__ENABLE_MASK, 662 VM_L2_CG__ENABLE_MASK, 663 }; 664 665 static void gmc_v6_0_enable_mc_ls(struct amdgpu_device *adev, 666 bool enable) 667 { 668 int i; 669 u32 orig, data; 670 671 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 672 orig = data = RREG32(mc_cg_registers[i]); 673 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS)) 674 data |= mc_cg_ls_en[i]; 675 else 676 data &= ~mc_cg_ls_en[i]; 677 if (data != orig) 678 WREG32(mc_cg_registers[i], data); 679 } 680 } 681 682 static void gmc_v6_0_enable_mc_mgcg(struct amdgpu_device *adev, 683 bool enable) 684 { 685 int i; 686 u32 orig, data; 687 688 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 689 orig = data = RREG32(mc_cg_registers[i]); 690 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG)) 691 data |= mc_cg_en[i]; 692 else 693 data &= ~mc_cg_en[i]; 694 if (data != orig) 695 WREG32(mc_cg_registers[i], data); 696 } 697 } 698 699 static void gmc_v6_0_enable_bif_mgls(struct amdgpu_device *adev, 700 bool enable) 701 { 702 u32 orig, data; 703 704 orig = data = RREG32_PCIE(ixPCIE_CNTL2); 705 706 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) { 707 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1); 708 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1); 709 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1); 710 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1); 711 } else { 712 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0); 713 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0); 714 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0); 715 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0); 716 } 717 718 if (orig != data) 719 WREG32_PCIE(ixPCIE_CNTL2, data); 720 } 721 722 static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev, 723 bool enable) 724 { 725 u32 orig, data; 726 727 orig = data = RREG32(mmHDP_HOST_PATH_CNTL); 728 729 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG)) 730 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0); 731 else 732 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1); 733 734 if (orig != data) 735 WREG32(mmHDP_HOST_PATH_CNTL, data); 736 } 737 738 static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev, 739 bool enable) 740 { 741 u32 orig, data; 742 743 orig = data = RREG32(mmHDP_MEM_POWER_LS); 744 745 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS)) 746 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1); 747 else 748 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0); 749 750 if (orig != data) 751 WREG32(mmHDP_MEM_POWER_LS, data); 752 } 753 */ 754 755 static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type) 756 { 757 switch (mc_seq_vram_type) { 758 case MC_SEQ_MISC0__MT__GDDR1: 759 return AMDGPU_VRAM_TYPE_GDDR1; 760 case MC_SEQ_MISC0__MT__DDR2: 761 return AMDGPU_VRAM_TYPE_DDR2; 762 case MC_SEQ_MISC0__MT__GDDR3: 763 return AMDGPU_VRAM_TYPE_GDDR3; 764 case MC_SEQ_MISC0__MT__GDDR4: 765 return AMDGPU_VRAM_TYPE_GDDR4; 766 case MC_SEQ_MISC0__MT__GDDR5: 767 return AMDGPU_VRAM_TYPE_GDDR5; 768 case MC_SEQ_MISC0__MT__DDR3: 769 return AMDGPU_VRAM_TYPE_DDR3; 770 default: 771 return AMDGPU_VRAM_TYPE_UNKNOWN; 772 } 773 } 774 775 static int gmc_v6_0_early_init(void *handle) 776 { 777 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 778 779 gmc_v6_0_set_gart_funcs(adev); 780 gmc_v6_0_set_irq_funcs(adev); 781 782 return 0; 783 } 784 785 static int gmc_v6_0_late_init(void *handle) 786 { 787 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 788 789 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 790 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0); 791 else 792 return 0; 793 } 794 795 static int gmc_v6_0_sw_init(void *handle) 796 { 797 int r; 798 int dma_bits; 799 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 800 801 if (adev->flags & AMD_IS_APU) { 802 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 803 } else { 804 u32 tmp = RREG32(mmMC_SEQ_MISC0); 805 tmp &= MC_SEQ_MISC0__MT__MASK; 806 adev->mc.vram_type = gmc_v6_0_convert_vram_type(tmp); 807 } 808 809 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault); 810 if (r) 811 return r; 812 813 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault); 814 if (r) 815 return r; 816 817 amdgpu_vm_adjust_size(adev, 64, 4); 818 adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; 819 820 adev->mc.mc_mask = 0xffffffffffULL; 821 822 adev->mc.stolen_size = 256 * 1024; 823 824 adev->need_dma32 = false; 825 dma_bits = adev->need_dma32 ? 32 : 40; 826 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 827 if (r) { 828 adev->need_dma32 = true; 829 dma_bits = 32; 830 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); 831 } 832 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 833 if (r) { 834 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); 835 dev_warn(adev->dev, "amdgpu: No coherent DMA available.\n"); 836 } 837 838 r = gmc_v6_0_init_microcode(adev); 839 if (r) { 840 dev_err(adev->dev, "Failed to load mc firmware!\n"); 841 return r; 842 } 843 844 r = gmc_v6_0_mc_init(adev); 845 if (r) 846 return r; 847 848 r = amdgpu_bo_init(adev); 849 if (r) 850 return r; 851 852 r = gmc_v6_0_gart_init(adev); 853 if (r) 854 return r; 855 856 /* 857 * number of VMs 858 * VMID 0 is reserved for System 859 * amdgpu graphics/compute will use VMIDs 1-7 860 * amdkfd will use VMIDs 8-15 861 */ 862 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; 863 adev->vm_manager.num_level = 1; 864 amdgpu_vm_manager_init(adev); 865 866 /* base offset of vram pages */ 867 if (adev->flags & AMD_IS_APU) { 868 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 869 870 tmp <<= 22; 871 adev->vm_manager.vram_base_offset = tmp; 872 } else { 873 adev->vm_manager.vram_base_offset = 0; 874 } 875 876 return 0; 877 } 878 879 static int gmc_v6_0_sw_fini(void *handle) 880 { 881 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 882 883 amdgpu_vm_manager_fini(adev); 884 gmc_v6_0_gart_fini(adev); 885 amdgpu_gem_force_release(adev); 886 amdgpu_bo_fini(adev); 887 888 return 0; 889 } 890 891 static int gmc_v6_0_hw_init(void *handle) 892 { 893 int r; 894 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 895 896 gmc_v6_0_mc_program(adev); 897 898 if (!(adev->flags & AMD_IS_APU)) { 899 r = gmc_v6_0_mc_load_microcode(adev); 900 if (r) { 901 dev_err(adev->dev, "Failed to load MC firmware!\n"); 902 return r; 903 } 904 } 905 906 r = gmc_v6_0_gart_enable(adev); 907 if (r) 908 return r; 909 910 return r; 911 } 912 913 static int gmc_v6_0_hw_fini(void *handle) 914 { 915 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 916 917 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0); 918 gmc_v6_0_gart_disable(adev); 919 920 return 0; 921 } 922 923 static int gmc_v6_0_suspend(void *handle) 924 { 925 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 926 927 gmc_v6_0_hw_fini(adev); 928 929 return 0; 930 } 931 932 static int gmc_v6_0_resume(void *handle) 933 { 934 int r; 935 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 936 937 r = gmc_v6_0_hw_init(adev); 938 if (r) 939 return r; 940 941 amdgpu_vm_reset_all_ids(adev); 942 943 return 0; 944 } 945 946 static bool gmc_v6_0_is_idle(void *handle) 947 { 948 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 949 u32 tmp = RREG32(mmSRBM_STATUS); 950 951 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 952 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 953 return false; 954 955 return true; 956 } 957 958 static int gmc_v6_0_wait_for_idle(void *handle) 959 { 960 unsigned i; 961 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 962 963 for (i = 0; i < adev->usec_timeout; i++) { 964 if (gmc_v6_0_is_idle(handle)) 965 return 0; 966 udelay(1); 967 } 968 return -ETIMEDOUT; 969 970 } 971 972 static int gmc_v6_0_soft_reset(void *handle) 973 { 974 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 975 u32 srbm_soft_reset = 0; 976 u32 tmp = RREG32(mmSRBM_STATUS); 977 978 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 979 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 980 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 981 982 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 983 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 984 if (!(adev->flags & AMD_IS_APU)) 985 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 986 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 987 } 988 989 if (srbm_soft_reset) { 990 gmc_v6_0_mc_stop(adev); 991 if (gmc_v6_0_wait_for_idle(adev)) { 992 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 993 } 994 995 996 tmp = RREG32(mmSRBM_SOFT_RESET); 997 tmp |= srbm_soft_reset; 998 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 999 WREG32(mmSRBM_SOFT_RESET, tmp); 1000 tmp = RREG32(mmSRBM_SOFT_RESET); 1001 1002 udelay(50); 1003 1004 tmp &= ~srbm_soft_reset; 1005 WREG32(mmSRBM_SOFT_RESET, tmp); 1006 tmp = RREG32(mmSRBM_SOFT_RESET); 1007 1008 udelay(50); 1009 1010 gmc_v6_0_mc_resume(adev); 1011 udelay(50); 1012 } 1013 1014 return 0; 1015 } 1016 1017 static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1018 struct amdgpu_irq_src *src, 1019 unsigned type, 1020 enum amdgpu_interrupt_state state) 1021 { 1022 u32 tmp; 1023 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1024 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1025 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1026 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1027 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1028 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1029 1030 switch (state) { 1031 case AMDGPU_IRQ_STATE_DISABLE: 1032 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1033 tmp &= ~bits; 1034 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1035 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1036 tmp &= ~bits; 1037 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1038 break; 1039 case AMDGPU_IRQ_STATE_ENABLE: 1040 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1041 tmp |= bits; 1042 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1043 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1044 tmp |= bits; 1045 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1046 break; 1047 default: 1048 break; 1049 } 1050 1051 return 0; 1052 } 1053 1054 static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev, 1055 struct amdgpu_irq_src *source, 1056 struct amdgpu_iv_entry *entry) 1057 { 1058 u32 addr, status; 1059 1060 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1061 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1062 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1063 1064 if (!addr && !status) 1065 return 0; 1066 1067 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1068 gmc_v6_0_set_fault_enable_default(adev, false); 1069 1070 if (printk_ratelimit()) { 1071 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1072 entry->src_id, entry->src_data[0]); 1073 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1074 addr); 1075 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1076 status); 1077 gmc_v6_0_vm_decode_fault(adev, status, addr, 0); 1078 } 1079 1080 return 0; 1081 } 1082 1083 static int gmc_v6_0_set_clockgating_state(void *handle, 1084 enum amd_clockgating_state state) 1085 { 1086 return 0; 1087 } 1088 1089 static int gmc_v6_0_set_powergating_state(void *handle, 1090 enum amd_powergating_state state) 1091 { 1092 return 0; 1093 } 1094 1095 static const struct amd_ip_funcs gmc_v6_0_ip_funcs = { 1096 .name = "gmc_v6_0", 1097 .early_init = gmc_v6_0_early_init, 1098 .late_init = gmc_v6_0_late_init, 1099 .sw_init = gmc_v6_0_sw_init, 1100 .sw_fini = gmc_v6_0_sw_fini, 1101 .hw_init = gmc_v6_0_hw_init, 1102 .hw_fini = gmc_v6_0_hw_fini, 1103 .suspend = gmc_v6_0_suspend, 1104 .resume = gmc_v6_0_resume, 1105 .is_idle = gmc_v6_0_is_idle, 1106 .wait_for_idle = gmc_v6_0_wait_for_idle, 1107 .soft_reset = gmc_v6_0_soft_reset, 1108 .set_clockgating_state = gmc_v6_0_set_clockgating_state, 1109 .set_powergating_state = gmc_v6_0_set_powergating_state, 1110 }; 1111 1112 static const struct amdgpu_gart_funcs gmc_v6_0_gart_funcs = { 1113 .flush_gpu_tlb = gmc_v6_0_gart_flush_gpu_tlb, 1114 .set_pte_pde = gmc_v6_0_gart_set_pte_pde, 1115 .set_prt = gmc_v6_0_set_prt, 1116 .get_vm_pde = gmc_v6_0_get_vm_pde, 1117 .get_vm_pte_flags = gmc_v6_0_get_vm_pte_flags 1118 }; 1119 1120 static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = { 1121 .set = gmc_v6_0_vm_fault_interrupt_state, 1122 .process = gmc_v6_0_process_interrupt, 1123 }; 1124 1125 static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev) 1126 { 1127 if (adev->gart.gart_funcs == NULL) 1128 adev->gart.gart_funcs = &gmc_v6_0_gart_funcs; 1129 } 1130 1131 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev) 1132 { 1133 adev->mc.vm_fault.num_types = 1; 1134 adev->mc.vm_fault.funcs = &gmc_v6_0_irq_funcs; 1135 } 1136 1137 const struct amdgpu_ip_block_version gmc_v6_0_ip_block = 1138 { 1139 .type = AMD_IP_BLOCK_TYPE_GMC, 1140 .major = 6, 1141 .minor = 0, 1142 .rev = 0, 1143 .funcs = &gmc_v6_0_ip_funcs, 1144 }; 1145