1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <drm/drmP.h> 25 #include <drm/drm_cache.h> 26 #include "amdgpu.h" 27 #include "gmc_v6_0.h" 28 #include "amdgpu_ucode.h" 29 #include "amdgpu_gem.h" 30 31 #include "bif/bif_3_0_d.h" 32 #include "bif/bif_3_0_sh_mask.h" 33 #include "oss/oss_1_0_d.h" 34 #include "oss/oss_1_0_sh_mask.h" 35 #include "gmc/gmc_6_0_d.h" 36 #include "gmc/gmc_6_0_sh_mask.h" 37 #include "dce/dce_6_0_d.h" 38 #include "dce/dce_6_0_sh_mask.h" 39 #include "si_enums.h" 40 41 static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev); 42 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev); 43 static int gmc_v6_0_wait_for_idle(void *handle); 44 45 MODULE_FIRMWARE("amdgpu/tahiti_mc.bin"); 46 MODULE_FIRMWARE("amdgpu/pitcairn_mc.bin"); 47 MODULE_FIRMWARE("amdgpu/verde_mc.bin"); 48 MODULE_FIRMWARE("amdgpu/oland_mc.bin"); 49 MODULE_FIRMWARE("amdgpu/hainan_mc.bin"); 50 MODULE_FIRMWARE("amdgpu/si58_mc.bin"); 51 52 #define MC_SEQ_MISC0__MT__MASK 0xf0000000 53 #define MC_SEQ_MISC0__MT__GDDR1 0x10000000 54 #define MC_SEQ_MISC0__MT__DDR2 0x20000000 55 #define MC_SEQ_MISC0__MT__GDDR3 0x30000000 56 #define MC_SEQ_MISC0__MT__GDDR4 0x40000000 57 #define MC_SEQ_MISC0__MT__GDDR5 0x50000000 58 #define MC_SEQ_MISC0__MT__HBM 0x60000000 59 #define MC_SEQ_MISC0__MT__DDR3 0xB0000000 60 61 62 static const u32 crtc_offsets[6] = 63 { 64 SI_CRTC0_REGISTER_OFFSET, 65 SI_CRTC1_REGISTER_OFFSET, 66 SI_CRTC2_REGISTER_OFFSET, 67 SI_CRTC3_REGISTER_OFFSET, 68 SI_CRTC4_REGISTER_OFFSET, 69 SI_CRTC5_REGISTER_OFFSET 70 }; 71 72 static void gmc_v6_0_mc_stop(struct amdgpu_device *adev) 73 { 74 u32 blackout; 75 76 gmc_v6_0_wait_for_idle((void *)adev); 77 78 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 79 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 80 /* Block CPU access */ 81 WREG32(mmBIF_FB_EN, 0); 82 /* blackout the MC */ 83 blackout = REG_SET_FIELD(blackout, 84 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 85 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); 86 } 87 /* wait for the MC to settle */ 88 udelay(100); 89 90 } 91 92 static void gmc_v6_0_mc_resume(struct amdgpu_device *adev) 93 { 94 u32 tmp; 95 96 /* unblackout the MC */ 97 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 98 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 99 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 100 /* allow CPU access */ 101 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 102 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 103 WREG32(mmBIF_FB_EN, tmp); 104 } 105 106 static int gmc_v6_0_init_microcode(struct amdgpu_device *adev) 107 { 108 const char *chip_name; 109 char fw_name[30]; 110 int err; 111 bool is_58_fw = false; 112 113 DRM_DEBUG("\n"); 114 115 switch (adev->asic_type) { 116 case CHIP_TAHITI: 117 chip_name = "tahiti"; 118 break; 119 case CHIP_PITCAIRN: 120 chip_name = "pitcairn"; 121 break; 122 case CHIP_VERDE: 123 chip_name = "verde"; 124 break; 125 case CHIP_OLAND: 126 chip_name = "oland"; 127 break; 128 case CHIP_HAINAN: 129 chip_name = "hainan"; 130 break; 131 default: BUG(); 132 } 133 134 /* this memory configuration requires special firmware */ 135 if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58) 136 is_58_fw = true; 137 138 if (is_58_fw) 139 snprintf(fw_name, sizeof(fw_name), "amdgpu/si58_mc.bin"); 140 else 141 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name); 142 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); 143 if (err) 144 goto out; 145 146 err = amdgpu_ucode_validate(adev->gmc.fw); 147 148 out: 149 if (err) { 150 dev_err(adev->dev, 151 "si_mc: Failed to load firmware \"%s\"\n", 152 fw_name); 153 release_firmware(adev->gmc.fw); 154 adev->gmc.fw = NULL; 155 } 156 return err; 157 } 158 159 static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev) 160 { 161 const __le32 *new_fw_data = NULL; 162 u32 running; 163 const __le32 *new_io_mc_regs = NULL; 164 int i, regs_size, ucode_size; 165 const struct mc_firmware_header_v1_0 *hdr; 166 167 if (!adev->gmc.fw) 168 return -EINVAL; 169 170 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 171 172 amdgpu_ucode_print_mc_hdr(&hdr->header); 173 174 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 175 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 176 new_io_mc_regs = (const __le32 *) 177 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 178 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 179 new_fw_data = (const __le32 *) 180 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 181 182 running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK; 183 184 if (running == 0) { 185 186 /* reset the engine and set to writable */ 187 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 188 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 189 190 /* load mc io regs */ 191 for (i = 0; i < regs_size; i++) { 192 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); 193 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); 194 } 195 /* load the MC ucode */ 196 for (i = 0; i < ucode_size; i++) { 197 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); 198 } 199 200 /* put the engine back into the active state */ 201 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 202 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 203 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 204 205 /* wait for training to complete */ 206 for (i = 0; i < adev->usec_timeout; i++) { 207 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK) 208 break; 209 udelay(1); 210 } 211 for (i = 0; i < adev->usec_timeout; i++) { 212 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK) 213 break; 214 udelay(1); 215 } 216 217 } 218 219 return 0; 220 } 221 222 static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev, 223 struct amdgpu_gmc *mc) 224 { 225 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; 226 base <<= 24; 227 228 amdgpu_gmc_vram_location(adev, mc, base); 229 amdgpu_gmc_gart_location(adev, mc); 230 } 231 232 static void gmc_v6_0_mc_program(struct amdgpu_device *adev) 233 { 234 int i, j; 235 236 /* Initialize HDP */ 237 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 238 WREG32((0xb05 + j), 0x00000000); 239 WREG32((0xb06 + j), 0x00000000); 240 WREG32((0xb07 + j), 0x00000000); 241 WREG32((0xb08 + j), 0x00000000); 242 WREG32((0xb09 + j), 0x00000000); 243 } 244 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 245 246 if (gmc_v6_0_wait_for_idle((void *)adev)) { 247 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 248 } 249 250 if (adev->mode_info.num_crtc) { 251 u32 tmp; 252 253 /* Lockout access through VGA aperture*/ 254 tmp = RREG32(mmVGA_HDP_CONTROL); 255 tmp |= VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK; 256 WREG32(mmVGA_HDP_CONTROL, tmp); 257 258 /* disable VGA render */ 259 tmp = RREG32(mmVGA_RENDER_CONTROL); 260 tmp &= ~VGA_VSTATUS_CNTL; 261 WREG32(mmVGA_RENDER_CONTROL, tmp); 262 } 263 /* Update configuration */ 264 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 265 adev->gmc.vram_start >> 12); 266 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 267 adev->gmc.vram_end >> 12); 268 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 269 adev->vram_scratch.gpu_addr >> 12); 270 WREG32(mmMC_VM_AGP_BASE, 0); 271 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); 272 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); 273 274 if (gmc_v6_0_wait_for_idle((void *)adev)) { 275 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 276 } 277 } 278 279 static int gmc_v6_0_mc_init(struct amdgpu_device *adev) 280 { 281 282 u32 tmp; 283 int chansize, numchan; 284 int r; 285 286 tmp = RREG32(mmMC_ARB_RAMCFG); 287 if (tmp & (1 << 11)) { 288 chansize = 16; 289 } else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK) { 290 chansize = 64; 291 } else { 292 chansize = 32; 293 } 294 tmp = RREG32(mmMC_SHARED_CHMAP); 295 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) { 296 case 0: 297 default: 298 numchan = 1; 299 break; 300 case 1: 301 numchan = 2; 302 break; 303 case 2: 304 numchan = 4; 305 break; 306 case 3: 307 numchan = 8; 308 break; 309 case 4: 310 numchan = 3; 311 break; 312 case 5: 313 numchan = 6; 314 break; 315 case 6: 316 numchan = 10; 317 break; 318 case 7: 319 numchan = 12; 320 break; 321 case 8: 322 numchan = 16; 323 break; 324 } 325 adev->gmc.vram_width = numchan * chansize; 326 /* size in MB on si */ 327 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 328 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 329 330 if (!(adev->flags & AMD_IS_APU)) { 331 r = amdgpu_device_resize_fb_bar(adev); 332 if (r) 333 return r; 334 } 335 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 336 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 337 adev->gmc.visible_vram_size = adev->gmc.aper_size; 338 339 /* set the gart size */ 340 if (amdgpu_gart_size == -1) { 341 switch (adev->asic_type) { 342 case CHIP_HAINAN: /* no MM engines */ 343 default: 344 adev->gmc.gart_size = 256ULL << 20; 345 break; 346 case CHIP_VERDE: /* UVD, VCE do not support GPUVM */ 347 case CHIP_TAHITI: /* UVD, VCE do not support GPUVM */ 348 case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */ 349 case CHIP_OLAND: /* UVD, VCE do not support GPUVM */ 350 adev->gmc.gart_size = 1024ULL << 20; 351 break; 352 } 353 } else { 354 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 355 } 356 357 gmc_v6_0_vram_gtt_location(adev, &adev->gmc); 358 359 return 0; 360 } 361 362 static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev, 363 uint32_t vmid, uint32_t flush_type) 364 { 365 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 366 } 367 368 static uint64_t gmc_v6_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 369 unsigned vmid, uint64_t pd_addr) 370 { 371 uint32_t reg; 372 373 /* write new base address */ 374 if (vmid < 8) 375 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; 376 else 377 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vmid - 8); 378 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); 379 380 /* bits 0-15 are the VM contexts0-15 */ 381 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); 382 383 return pd_addr; 384 } 385 386 static uint64_t gmc_v6_0_get_vm_pte_flags(struct amdgpu_device *adev, 387 uint32_t flags) 388 { 389 uint64_t pte_flag = 0; 390 391 if (flags & AMDGPU_VM_PAGE_READABLE) 392 pte_flag |= AMDGPU_PTE_READABLE; 393 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 394 pte_flag |= AMDGPU_PTE_WRITEABLE; 395 if (flags & AMDGPU_VM_PAGE_PRT) 396 pte_flag |= AMDGPU_PTE_PRT; 397 398 return pte_flag; 399 } 400 401 static void gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, int level, 402 uint64_t *addr, uint64_t *flags) 403 { 404 BUG_ON(*addr & 0xFFFFFF0000000FFFULL); 405 } 406 407 static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev, 408 bool value) 409 { 410 u32 tmp; 411 412 tmp = RREG32(mmVM_CONTEXT1_CNTL); 413 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 414 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 415 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 416 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 417 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 418 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 419 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 420 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 421 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 422 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 423 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 424 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 425 WREG32(mmVM_CONTEXT1_CNTL, tmp); 426 } 427 428 /** 429 + * gmc_v8_0_set_prt - set PRT VM fault 430 + * 431 + * @adev: amdgpu_device pointer 432 + * @enable: enable/disable VM fault handling for PRT 433 +*/ 434 static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable) 435 { 436 u32 tmp; 437 438 if (enable && !adev->gmc.prt_warning) { 439 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 440 adev->gmc.prt_warning = true; 441 } 442 443 tmp = RREG32(mmVM_PRT_CNTL); 444 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 445 CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS, 446 enable); 447 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 448 TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS, 449 enable); 450 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 451 L2_CACHE_STORE_INVALID_ENTRIES, 452 enable); 453 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 454 L1_TLB_STORE_INVALID_ENTRIES, 455 enable); 456 WREG32(mmVM_PRT_CNTL, tmp); 457 458 if (enable) { 459 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; 460 uint32_t high = adev->vm_manager.max_pfn - 461 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT); 462 463 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); 464 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); 465 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); 466 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); 467 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); 468 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); 469 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); 470 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); 471 } else { 472 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); 473 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); 474 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); 475 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); 476 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); 477 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); 478 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); 479 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); 480 } 481 } 482 483 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) 484 { 485 uint64_t table_addr; 486 int r, i; 487 u32 field; 488 489 if (adev->gart.bo == NULL) { 490 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 491 return -EINVAL; 492 } 493 r = amdgpu_gart_table_vram_pin(adev); 494 if (r) 495 return r; 496 497 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 498 499 /* Setup TLB control */ 500 WREG32(mmMC_VM_MX_L1_TLB_CNTL, 501 (0xA << 7) | 502 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK | 503 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK | 504 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK | 505 MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK | 506 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT)); 507 /* Setup L2 cache */ 508 WREG32(mmVM_L2_CNTL, 509 VM_L2_CNTL__ENABLE_L2_CACHE_MASK | 510 VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK | 511 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK | 512 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK | 513 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) | 514 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT)); 515 WREG32(mmVM_L2_CNTL2, 516 VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK | 517 VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK); 518 519 field = adev->vm_manager.fragment_size; 520 WREG32(mmVM_L2_CNTL3, 521 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK | 522 (field << VM_L2_CNTL3__BANK_SELECT__SHIFT) | 523 (field << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT)); 524 /* setup context0 */ 525 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); 526 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); 527 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12); 528 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 529 (u32)(adev->dummy_page_addr >> 12)); 530 WREG32(mmVM_CONTEXT0_CNTL2, 0); 531 WREG32(mmVM_CONTEXT0_CNTL, 532 VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK | 533 (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) | 534 VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK); 535 536 WREG32(0x575, 0); 537 WREG32(0x576, 0); 538 WREG32(0x577, 0); 539 540 /* empty context1-15 */ 541 /* set vm size, must be a multiple of 4 */ 542 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 543 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 544 /* Assign the pt base to something valid for now; the pts used for 545 * the VMs are determined by the application and setup and assigned 546 * on the fly in the vm part of radeon_gart.c 547 */ 548 for (i = 1; i < 16; i++) { 549 if (i < 8) 550 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 551 table_addr >> 12); 552 else 553 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 554 table_addr >> 12); 555 } 556 557 /* enable context1-15 */ 558 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 559 (u32)(adev->dummy_page_addr >> 12)); 560 WREG32(mmVM_CONTEXT1_CNTL2, 4); 561 WREG32(mmVM_CONTEXT1_CNTL, 562 VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK | 563 (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) | 564 ((adev->vm_manager.block_size - 9) 565 << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT)); 566 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 567 gmc_v6_0_set_fault_enable_default(adev, false); 568 else 569 gmc_v6_0_set_fault_enable_default(adev, true); 570 571 gmc_v6_0_flush_gpu_tlb(adev, 0, 0); 572 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n", 573 (unsigned)(adev->gmc.gart_size >> 20), 574 (unsigned long long)table_addr); 575 adev->gart.ready = true; 576 return 0; 577 } 578 579 static int gmc_v6_0_gart_init(struct amdgpu_device *adev) 580 { 581 int r; 582 583 if (adev->gart.bo) { 584 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n"); 585 return 0; 586 } 587 r = amdgpu_gart_init(adev); 588 if (r) 589 return r; 590 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 591 adev->gart.gart_pte_flags = 0; 592 return amdgpu_gart_table_vram_alloc(adev); 593 } 594 595 static void gmc_v6_0_gart_disable(struct amdgpu_device *adev) 596 { 597 /*unsigned i; 598 599 for (i = 1; i < 16; ++i) { 600 uint32_t reg; 601 if (i < 8) 602 reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i ; 603 else 604 reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (i - 8); 605 adev->vm_manager.saved_table_addr[i] = RREG32(reg); 606 }*/ 607 608 /* Disable all tables */ 609 WREG32(mmVM_CONTEXT0_CNTL, 0); 610 WREG32(mmVM_CONTEXT1_CNTL, 0); 611 /* Setup TLB control */ 612 WREG32(mmMC_VM_MX_L1_TLB_CNTL, 613 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK | 614 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT)); 615 /* Setup L2 cache */ 616 WREG32(mmVM_L2_CNTL, 617 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK | 618 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK | 619 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) | 620 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT)); 621 WREG32(mmVM_L2_CNTL2, 0); 622 WREG32(mmVM_L2_CNTL3, 623 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK | 624 (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT)); 625 amdgpu_gart_table_vram_unpin(adev); 626 } 627 628 static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev, 629 u32 status, u32 addr, u32 mc_client) 630 { 631 u32 mc_id; 632 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 633 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 634 PROTECTIONS); 635 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 636 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 637 638 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 639 MEMORY_CLIENT_ID); 640 641 dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 642 protections, vmid, addr, 643 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 644 MEMORY_CLIENT_RW) ? 645 "write" : "read", block, mc_client, mc_id); 646 } 647 648 /* 649 static const u32 mc_cg_registers[] = { 650 MC_HUB_MISC_HUB_CG, 651 MC_HUB_MISC_SIP_CG, 652 MC_HUB_MISC_VM_CG, 653 MC_XPB_CLK_GAT, 654 ATC_MISC_CG, 655 MC_CITF_MISC_WR_CG, 656 MC_CITF_MISC_RD_CG, 657 MC_CITF_MISC_VM_CG, 658 VM_L2_CG, 659 }; 660 661 static const u32 mc_cg_ls_en[] = { 662 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK, 663 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK, 664 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK, 665 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK, 666 ATC_MISC_CG__MEM_LS_ENABLE_MASK, 667 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK, 668 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK, 669 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK, 670 VM_L2_CG__MEM_LS_ENABLE_MASK, 671 }; 672 673 static const u32 mc_cg_en[] = { 674 MC_HUB_MISC_HUB_CG__ENABLE_MASK, 675 MC_HUB_MISC_SIP_CG__ENABLE_MASK, 676 MC_HUB_MISC_VM_CG__ENABLE_MASK, 677 MC_XPB_CLK_GAT__ENABLE_MASK, 678 ATC_MISC_CG__ENABLE_MASK, 679 MC_CITF_MISC_WR_CG__ENABLE_MASK, 680 MC_CITF_MISC_RD_CG__ENABLE_MASK, 681 MC_CITF_MISC_VM_CG__ENABLE_MASK, 682 VM_L2_CG__ENABLE_MASK, 683 }; 684 685 static void gmc_v6_0_enable_mc_ls(struct amdgpu_device *adev, 686 bool enable) 687 { 688 int i; 689 u32 orig, data; 690 691 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 692 orig = data = RREG32(mc_cg_registers[i]); 693 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS)) 694 data |= mc_cg_ls_en[i]; 695 else 696 data &= ~mc_cg_ls_en[i]; 697 if (data != orig) 698 WREG32(mc_cg_registers[i], data); 699 } 700 } 701 702 static void gmc_v6_0_enable_mc_mgcg(struct amdgpu_device *adev, 703 bool enable) 704 { 705 int i; 706 u32 orig, data; 707 708 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 709 orig = data = RREG32(mc_cg_registers[i]); 710 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG)) 711 data |= mc_cg_en[i]; 712 else 713 data &= ~mc_cg_en[i]; 714 if (data != orig) 715 WREG32(mc_cg_registers[i], data); 716 } 717 } 718 719 static void gmc_v6_0_enable_bif_mgls(struct amdgpu_device *adev, 720 bool enable) 721 { 722 u32 orig, data; 723 724 orig = data = RREG32_PCIE(ixPCIE_CNTL2); 725 726 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) { 727 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1); 728 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1); 729 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1); 730 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1); 731 } else { 732 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0); 733 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0); 734 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0); 735 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0); 736 } 737 738 if (orig != data) 739 WREG32_PCIE(ixPCIE_CNTL2, data); 740 } 741 742 static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev, 743 bool enable) 744 { 745 u32 orig, data; 746 747 orig = data = RREG32(mmHDP_HOST_PATH_CNTL); 748 749 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG)) 750 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0); 751 else 752 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1); 753 754 if (orig != data) 755 WREG32(mmHDP_HOST_PATH_CNTL, data); 756 } 757 758 static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev, 759 bool enable) 760 { 761 u32 orig, data; 762 763 orig = data = RREG32(mmHDP_MEM_POWER_LS); 764 765 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS)) 766 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1); 767 else 768 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0); 769 770 if (orig != data) 771 WREG32(mmHDP_MEM_POWER_LS, data); 772 } 773 */ 774 775 static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type) 776 { 777 switch (mc_seq_vram_type) { 778 case MC_SEQ_MISC0__MT__GDDR1: 779 return AMDGPU_VRAM_TYPE_GDDR1; 780 case MC_SEQ_MISC0__MT__DDR2: 781 return AMDGPU_VRAM_TYPE_DDR2; 782 case MC_SEQ_MISC0__MT__GDDR3: 783 return AMDGPU_VRAM_TYPE_GDDR3; 784 case MC_SEQ_MISC0__MT__GDDR4: 785 return AMDGPU_VRAM_TYPE_GDDR4; 786 case MC_SEQ_MISC0__MT__GDDR5: 787 return AMDGPU_VRAM_TYPE_GDDR5; 788 case MC_SEQ_MISC0__MT__DDR3: 789 return AMDGPU_VRAM_TYPE_DDR3; 790 default: 791 return AMDGPU_VRAM_TYPE_UNKNOWN; 792 } 793 } 794 795 static int gmc_v6_0_early_init(void *handle) 796 { 797 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 798 799 gmc_v6_0_set_gmc_funcs(adev); 800 gmc_v6_0_set_irq_funcs(adev); 801 802 return 0; 803 } 804 805 static int gmc_v6_0_late_init(void *handle) 806 { 807 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 808 809 amdgpu_bo_late_init(adev); 810 811 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 812 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 813 else 814 return 0; 815 } 816 817 static unsigned gmc_v6_0_get_vbios_fb_size(struct amdgpu_device *adev) 818 { 819 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); 820 unsigned size; 821 822 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 823 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */ 824 } else { 825 u32 viewport = RREG32(mmVIEWPORT_SIZE); 826 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 827 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * 828 4); 829 } 830 /* return 0 if the pre-OS buffer uses up most of vram */ 831 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 832 return 0; 833 return size; 834 } 835 836 static int gmc_v6_0_sw_init(void *handle) 837 { 838 int r; 839 int dma_bits; 840 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 841 842 if (adev->flags & AMD_IS_APU) { 843 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 844 } else { 845 u32 tmp = RREG32(mmMC_SEQ_MISC0); 846 tmp &= MC_SEQ_MISC0__MT__MASK; 847 adev->gmc.vram_type = gmc_v6_0_convert_vram_type(tmp); 848 } 849 850 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault); 851 if (r) 852 return r; 853 854 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault); 855 if (r) 856 return r; 857 858 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); 859 860 adev->gmc.mc_mask = 0xffffffffffULL; 861 862 adev->need_dma32 = false; 863 dma_bits = adev->need_dma32 ? 32 : 40; 864 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 865 if (r) { 866 adev->need_dma32 = true; 867 dma_bits = 32; 868 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); 869 } 870 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 871 if (r) { 872 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); 873 dev_warn(adev->dev, "amdgpu: No coherent DMA available.\n"); 874 } 875 adev->need_swiotlb = drm_need_swiotlb(dma_bits); 876 877 r = gmc_v6_0_init_microcode(adev); 878 if (r) { 879 dev_err(adev->dev, "Failed to load mc firmware!\n"); 880 return r; 881 } 882 883 r = gmc_v6_0_mc_init(adev); 884 if (r) 885 return r; 886 887 adev->gmc.stolen_size = gmc_v6_0_get_vbios_fb_size(adev); 888 889 r = amdgpu_bo_init(adev); 890 if (r) 891 return r; 892 893 r = gmc_v6_0_gart_init(adev); 894 if (r) 895 return r; 896 897 /* 898 * number of VMs 899 * VMID 0 is reserved for System 900 * amdgpu graphics/compute will use VMIDs 1-7 901 * amdkfd will use VMIDs 8-15 902 */ 903 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; 904 amdgpu_vm_manager_init(adev); 905 906 /* base offset of vram pages */ 907 if (adev->flags & AMD_IS_APU) { 908 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 909 910 tmp <<= 22; 911 adev->vm_manager.vram_base_offset = tmp; 912 } else { 913 adev->vm_manager.vram_base_offset = 0; 914 } 915 916 return 0; 917 } 918 919 static int gmc_v6_0_sw_fini(void *handle) 920 { 921 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 922 923 amdgpu_gem_force_release(adev); 924 amdgpu_vm_manager_fini(adev); 925 amdgpu_gart_table_vram_free(adev); 926 amdgpu_bo_fini(adev); 927 amdgpu_gart_fini(adev); 928 release_firmware(adev->gmc.fw); 929 adev->gmc.fw = NULL; 930 931 return 0; 932 } 933 934 static int gmc_v6_0_hw_init(void *handle) 935 { 936 int r; 937 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 938 939 gmc_v6_0_mc_program(adev); 940 941 if (!(adev->flags & AMD_IS_APU)) { 942 r = gmc_v6_0_mc_load_microcode(adev); 943 if (r) { 944 dev_err(adev->dev, "Failed to load MC firmware!\n"); 945 return r; 946 } 947 } 948 949 r = gmc_v6_0_gart_enable(adev); 950 if (r) 951 return r; 952 953 return r; 954 } 955 956 static int gmc_v6_0_hw_fini(void *handle) 957 { 958 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 959 960 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 961 gmc_v6_0_gart_disable(adev); 962 963 return 0; 964 } 965 966 static int gmc_v6_0_suspend(void *handle) 967 { 968 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 969 970 gmc_v6_0_hw_fini(adev); 971 972 return 0; 973 } 974 975 static int gmc_v6_0_resume(void *handle) 976 { 977 int r; 978 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 979 980 r = gmc_v6_0_hw_init(adev); 981 if (r) 982 return r; 983 984 amdgpu_vmid_reset_all(adev); 985 986 return 0; 987 } 988 989 static bool gmc_v6_0_is_idle(void *handle) 990 { 991 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 992 u32 tmp = RREG32(mmSRBM_STATUS); 993 994 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 995 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 996 return false; 997 998 return true; 999 } 1000 1001 static int gmc_v6_0_wait_for_idle(void *handle) 1002 { 1003 unsigned i; 1004 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1005 1006 for (i = 0; i < adev->usec_timeout; i++) { 1007 if (gmc_v6_0_is_idle(handle)) 1008 return 0; 1009 udelay(1); 1010 } 1011 return -ETIMEDOUT; 1012 1013 } 1014 1015 static int gmc_v6_0_soft_reset(void *handle) 1016 { 1017 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1018 u32 srbm_soft_reset = 0; 1019 u32 tmp = RREG32(mmSRBM_STATUS); 1020 1021 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1022 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1023 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 1024 1025 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1026 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 1027 if (!(adev->flags & AMD_IS_APU)) 1028 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1029 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1030 } 1031 1032 if (srbm_soft_reset) { 1033 gmc_v6_0_mc_stop(adev); 1034 if (gmc_v6_0_wait_for_idle(adev)) { 1035 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1036 } 1037 1038 1039 tmp = RREG32(mmSRBM_SOFT_RESET); 1040 tmp |= srbm_soft_reset; 1041 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1042 WREG32(mmSRBM_SOFT_RESET, tmp); 1043 tmp = RREG32(mmSRBM_SOFT_RESET); 1044 1045 udelay(50); 1046 1047 tmp &= ~srbm_soft_reset; 1048 WREG32(mmSRBM_SOFT_RESET, tmp); 1049 tmp = RREG32(mmSRBM_SOFT_RESET); 1050 1051 udelay(50); 1052 1053 gmc_v6_0_mc_resume(adev); 1054 udelay(50); 1055 } 1056 1057 return 0; 1058 } 1059 1060 static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1061 struct amdgpu_irq_src *src, 1062 unsigned type, 1063 enum amdgpu_interrupt_state state) 1064 { 1065 u32 tmp; 1066 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1067 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1068 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1069 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1070 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1071 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1072 1073 switch (state) { 1074 case AMDGPU_IRQ_STATE_DISABLE: 1075 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1076 tmp &= ~bits; 1077 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1078 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1079 tmp &= ~bits; 1080 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1081 break; 1082 case AMDGPU_IRQ_STATE_ENABLE: 1083 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1084 tmp |= bits; 1085 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1086 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1087 tmp |= bits; 1088 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1089 break; 1090 default: 1091 break; 1092 } 1093 1094 return 0; 1095 } 1096 1097 static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev, 1098 struct amdgpu_irq_src *source, 1099 struct amdgpu_iv_entry *entry) 1100 { 1101 u32 addr, status; 1102 1103 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1104 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1105 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1106 1107 if (!addr && !status) 1108 return 0; 1109 1110 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1111 gmc_v6_0_set_fault_enable_default(adev, false); 1112 1113 if (printk_ratelimit()) { 1114 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1115 entry->src_id, entry->src_data[0]); 1116 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1117 addr); 1118 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1119 status); 1120 gmc_v6_0_vm_decode_fault(adev, status, addr, 0); 1121 } 1122 1123 return 0; 1124 } 1125 1126 static int gmc_v6_0_set_clockgating_state(void *handle, 1127 enum amd_clockgating_state state) 1128 { 1129 return 0; 1130 } 1131 1132 static int gmc_v6_0_set_powergating_state(void *handle, 1133 enum amd_powergating_state state) 1134 { 1135 return 0; 1136 } 1137 1138 static const struct amd_ip_funcs gmc_v6_0_ip_funcs = { 1139 .name = "gmc_v6_0", 1140 .early_init = gmc_v6_0_early_init, 1141 .late_init = gmc_v6_0_late_init, 1142 .sw_init = gmc_v6_0_sw_init, 1143 .sw_fini = gmc_v6_0_sw_fini, 1144 .hw_init = gmc_v6_0_hw_init, 1145 .hw_fini = gmc_v6_0_hw_fini, 1146 .suspend = gmc_v6_0_suspend, 1147 .resume = gmc_v6_0_resume, 1148 .is_idle = gmc_v6_0_is_idle, 1149 .wait_for_idle = gmc_v6_0_wait_for_idle, 1150 .soft_reset = gmc_v6_0_soft_reset, 1151 .set_clockgating_state = gmc_v6_0_set_clockgating_state, 1152 .set_powergating_state = gmc_v6_0_set_powergating_state, 1153 }; 1154 1155 static const struct amdgpu_gmc_funcs gmc_v6_0_gmc_funcs = { 1156 .flush_gpu_tlb = gmc_v6_0_flush_gpu_tlb, 1157 .emit_flush_gpu_tlb = gmc_v6_0_emit_flush_gpu_tlb, 1158 .set_prt = gmc_v6_0_set_prt, 1159 .get_vm_pde = gmc_v6_0_get_vm_pde, 1160 .get_vm_pte_flags = gmc_v6_0_get_vm_pte_flags 1161 }; 1162 1163 static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = { 1164 .set = gmc_v6_0_vm_fault_interrupt_state, 1165 .process = gmc_v6_0_process_interrupt, 1166 }; 1167 1168 static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev) 1169 { 1170 adev->gmc.gmc_funcs = &gmc_v6_0_gmc_funcs; 1171 } 1172 1173 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev) 1174 { 1175 adev->gmc.vm_fault.num_types = 1; 1176 adev->gmc.vm_fault.funcs = &gmc_v6_0_irq_funcs; 1177 } 1178 1179 const struct amdgpu_ip_block_version gmc_v6_0_ip_block = 1180 { 1181 .type = AMD_IP_BLOCK_TYPE_GMC, 1182 .major = 6, 1183 .minor = 0, 1184 .rev = 0, 1185 .funcs = &gmc_v6_0_ip_funcs, 1186 }; 1187