1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 #include "amdgpu.h" 26 #include "amdgpu_atomfirmware.h" 27 #include "gmc_v11_0.h" 28 #include "umc_v8_7.h" 29 #include "athub/athub_3_0_0_sh_mask.h" 30 #include "athub/athub_3_0_0_offset.h" 31 #include "oss/osssys_6_0_0_offset.h" 32 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 33 #include "navi10_enum.h" 34 #include "soc15.h" 35 #include "soc15d.h" 36 #include "soc15_common.h" 37 #include "nbio_v4_3.h" 38 #include "gfxhub_v3_0.h" 39 #include "mmhub_v3_0.h" 40 #include "athub_v3_0.h" 41 42 43 static int gmc_v11_0_ecc_interrupt_state(struct amdgpu_device *adev, 44 struct amdgpu_irq_src *src, 45 unsigned type, 46 enum amdgpu_interrupt_state state) 47 { 48 return 0; 49 } 50 51 static int 52 gmc_v11_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 53 struct amdgpu_irq_src *src, unsigned type, 54 enum amdgpu_interrupt_state state) 55 { 56 switch (state) { 57 case AMDGPU_IRQ_STATE_DISABLE: 58 /* MM HUB */ 59 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false); 60 /* GFX HUB */ 61 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false); 62 break; 63 case AMDGPU_IRQ_STATE_ENABLE: 64 /* MM HUB */ 65 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true); 66 /* GFX HUB */ 67 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true); 68 break; 69 default: 70 break; 71 } 72 73 return 0; 74 } 75 76 static int gmc_v11_0_process_interrupt(struct amdgpu_device *adev, 77 struct amdgpu_irq_src *source, 78 struct amdgpu_iv_entry *entry) 79 { 80 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; 81 uint32_t status = 0; 82 u64 addr; 83 84 addr = (u64)entry->src_data[0] << 12; 85 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 86 87 if (!amdgpu_sriov_vf(adev)) { 88 /* 89 * Issue a dummy read to wait for the status register to 90 * be updated to avoid reading an incorrect value due to 91 * the new fast GRBM interface. 92 */ 93 if (entry->vmid_src == AMDGPU_GFXHUB_0) 94 RREG32(hub->vm_l2_pro_fault_status); 95 96 status = RREG32(hub->vm_l2_pro_fault_status); 97 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 98 } 99 100 if (printk_ratelimit()) { 101 struct amdgpu_task_info task_info; 102 103 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 104 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 105 106 dev_err(adev->dev, 107 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, " 108 "for process %s pid %d thread %s pid %d)\n", 109 entry->vmid_src ? "mmhub" : "gfxhub", 110 entry->src_id, entry->ring_id, entry->vmid, 111 entry->pasid, task_info.process_name, task_info.tgid, 112 task_info.task_name, task_info.pid); 113 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", 114 addr, entry->client_id); 115 if (!amdgpu_sriov_vf(adev)) 116 hub->vmhub_funcs->print_l2_protection_fault_status(adev, status); 117 } 118 119 return 0; 120 } 121 122 static const struct amdgpu_irq_src_funcs gmc_v11_0_irq_funcs = { 123 .set = gmc_v11_0_vm_fault_interrupt_state, 124 .process = gmc_v11_0_process_interrupt, 125 }; 126 127 static const struct amdgpu_irq_src_funcs gmc_v11_0_ecc_funcs = { 128 .set = gmc_v11_0_ecc_interrupt_state, 129 .process = amdgpu_umc_process_ecc_irq, 130 }; 131 132 static void gmc_v11_0_set_irq_funcs(struct amdgpu_device *adev) 133 { 134 adev->gmc.vm_fault.num_types = 1; 135 adev->gmc.vm_fault.funcs = &gmc_v11_0_irq_funcs; 136 137 if (!amdgpu_sriov_vf(adev)) { 138 adev->gmc.ecc_irq.num_types = 1; 139 adev->gmc.ecc_irq.funcs = &gmc_v11_0_ecc_funcs; 140 } 141 } 142 143 /** 144 * gmc_v11_0_use_invalidate_semaphore - judge whether to use semaphore 145 * 146 * @adev: amdgpu_device pointer 147 * @vmhub: vmhub type 148 * 149 */ 150 static bool gmc_v11_0_use_invalidate_semaphore(struct amdgpu_device *adev, 151 uint32_t vmhub) 152 { 153 return ((vmhub == AMDGPU_MMHUB_0) && 154 (!amdgpu_sriov_vf(adev))); 155 } 156 157 static bool gmc_v11_0_get_atc_vmid_pasid_mapping_info( 158 struct amdgpu_device *adev, 159 uint8_t vmid, uint16_t *p_pasid) 160 { 161 #if 0 // TODO: 162 uint32_t value; 163 164 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 165 + vmid); 166 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 167 168 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 169 #else 170 return 0; 171 #endif 172 } 173 174 /* 175 * GART 176 * VMID 0 is the physical GPU addresses as used by the kernel. 177 * VMIDs 1-15 are used for userspace clients and are handled 178 * by the amdgpu vm/hsa code. 179 */ 180 181 static void gmc_v11_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 182 unsigned int vmhub, uint32_t flush_type) 183 { 184 bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(adev, vmhub); 185 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 186 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 187 u32 tmp; 188 /* Use register 17 for GART */ 189 const unsigned eng = 17; 190 unsigned int i; 191 192 spin_lock(&adev->gmc.invalidate_lock); 193 /* 194 * It may lose gpuvm invalidate acknowldege state across power-gating 195 * off cycle, add semaphore acquire before invalidation and semaphore 196 * release after invalidation to avoid entering power gated state 197 * to WA the Issue 198 */ 199 200 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 201 if (use_semaphore) { 202 for (i = 0; i < adev->usec_timeout; i++) { 203 /* a read return value of 1 means semaphore acuqire */ 204 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + 205 hub->eng_distance * eng); 206 if (tmp & 0x1) 207 break; 208 udelay(1); 209 } 210 211 if (i >= adev->usec_timeout) 212 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 213 } 214 215 WREG32_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req); 216 217 /* Wait for ACK with a delay.*/ 218 for (i = 0; i < adev->usec_timeout; i++) { 219 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + 220 hub->eng_distance * eng); 221 tmp &= 1 << vmid; 222 if (tmp) 223 break; 224 225 udelay(1); 226 } 227 228 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 229 if (use_semaphore) 230 /* 231 * add semaphore release after invalidation, 232 * write with 0 means semaphore release 233 */ 234 WREG32_NO_KIQ(hub->vm_inv_eng0_sem + 235 hub->eng_distance * eng, 0); 236 237 /* Issue additional private vm invalidation to MMHUB */ 238 if ((vmhub != AMDGPU_GFXHUB_0) && 239 (hub->vm_l2_bank_select_reserved_cid2)) { 240 inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 241 /* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */ 242 inv_req |= (1 << 25); 243 /* Issue private invalidation */ 244 WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req); 245 /* Read back to ensure invalidation is done*/ 246 RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 247 } 248 249 spin_unlock(&adev->gmc.invalidate_lock); 250 251 if (i < adev->usec_timeout) 252 return; 253 254 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 255 } 256 257 /** 258 * gmc_v11_0_flush_gpu_tlb - gart tlb flush callback 259 * 260 * @adev: amdgpu_device pointer 261 * @vmid: vm instance to flush 262 * 263 * Flush the TLB for the requested page table. 264 */ 265 static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 266 uint32_t vmhub, uint32_t flush_type) 267 { 268 if ((vmhub == AMDGPU_GFXHUB_0) && !adev->gfx.is_poweron) 269 return; 270 271 /* flush hdp cache */ 272 adev->hdp.funcs->flush_hdp(adev, NULL); 273 274 /* For SRIOV run time, driver shouldn't access the register through MMIO 275 * Directly use kiq to do the vm invalidation instead 276 */ 277 if (adev->gfx.kiq.ring.sched.ready && !adev->enable_mes && 278 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 279 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 280 const unsigned eng = 17; 281 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 282 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 283 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 284 285 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 286 1 << vmid); 287 return; 288 } 289 290 mutex_lock(&adev->mman.gtt_window_lock); 291 gmc_v11_0_flush_vm_hub(adev, vmid, vmhub, 0); 292 mutex_unlock(&adev->mman.gtt_window_lock); 293 return; 294 } 295 296 /** 297 * gmc_v11_0_flush_gpu_tlb_pasid - tlb flush via pasid 298 * 299 * @adev: amdgpu_device pointer 300 * @pasid: pasid to be flush 301 * 302 * Flush the TLB for the requested pasid. 303 */ 304 static int gmc_v11_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 305 uint16_t pasid, uint32_t flush_type, 306 bool all_hub) 307 { 308 int vmid, i; 309 signed long r; 310 uint32_t seq; 311 uint16_t queried_pasid; 312 bool ret; 313 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 314 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 315 316 if (amdgpu_emu_mode == 0 && ring->sched.ready) { 317 spin_lock(&adev->gfx.kiq.ring_lock); 318 /* 2 dwords flush + 8 dwords fence */ 319 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8); 320 kiq->pmf->kiq_invalidate_tlbs(ring, 321 pasid, flush_type, all_hub); 322 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 323 if (r) { 324 amdgpu_ring_undo(ring); 325 spin_unlock(&adev->gfx.kiq.ring_lock); 326 return -ETIME; 327 } 328 329 amdgpu_ring_commit(ring); 330 spin_unlock(&adev->gfx.kiq.ring_lock); 331 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); 332 if (r < 1) { 333 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r); 334 return -ETIME; 335 } 336 337 return 0; 338 } 339 340 for (vmid = 1; vmid < 16; vmid++) { 341 342 ret = gmc_v11_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 343 &queried_pasid); 344 if (ret && queried_pasid == pasid) { 345 if (all_hub) { 346 for (i = 0; i < adev->num_vmhubs; i++) 347 gmc_v11_0_flush_gpu_tlb(adev, vmid, 348 i, flush_type); 349 } else { 350 gmc_v11_0_flush_gpu_tlb(adev, vmid, 351 AMDGPU_GFXHUB_0, flush_type); 352 } 353 break; 354 } 355 } 356 357 return 0; 358 } 359 360 static uint64_t gmc_v11_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 361 unsigned vmid, uint64_t pd_addr) 362 { 363 bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub); 364 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 365 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 366 unsigned eng = ring->vm_inv_eng; 367 368 /* 369 * It may lose gpuvm invalidate acknowldege state across power-gating 370 * off cycle, add semaphore acquire before invalidation and semaphore 371 * release after invalidation to avoid entering power gated state 372 * to WA the Issue 373 */ 374 375 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 376 if (use_semaphore) 377 /* a read return value of 1 means semaphore acuqire */ 378 amdgpu_ring_emit_reg_wait(ring, 379 hub->vm_inv_eng0_sem + 380 hub->eng_distance * eng, 0x1, 0x1); 381 382 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 383 (hub->ctx_addr_distance * vmid), 384 lower_32_bits(pd_addr)); 385 386 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 387 (hub->ctx_addr_distance * vmid), 388 upper_32_bits(pd_addr)); 389 390 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 391 hub->eng_distance * eng, 392 hub->vm_inv_eng0_ack + 393 hub->eng_distance * eng, 394 req, 1 << vmid); 395 396 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 397 if (use_semaphore) 398 /* 399 * add semaphore release after invalidation, 400 * write with 0 means semaphore release 401 */ 402 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 403 hub->eng_distance * eng, 0); 404 405 return pd_addr; 406 } 407 408 static void gmc_v11_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 409 unsigned pasid) 410 { 411 struct amdgpu_device *adev = ring->adev; 412 uint32_t reg; 413 414 /* MES fw manages IH_VMID_x_LUT updating */ 415 if (ring->is_mes_queue) 416 return; 417 418 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) 419 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid; 420 else 421 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid; 422 423 amdgpu_ring_emit_wreg(ring, reg, pasid); 424 } 425 426 /* 427 * PTE format: 428 * 63:59 reserved 429 * 58:57 reserved 430 * 56 F 431 * 55 L 432 * 54 reserved 433 * 53:52 SW 434 * 51 T 435 * 50:48 mtype 436 * 47:12 4k physical page base address 437 * 11:7 fragment 438 * 6 write 439 * 5 read 440 * 4 exe 441 * 3 Z 442 * 2 snooped 443 * 1 system 444 * 0 valid 445 * 446 * PDE format: 447 * 63:59 block fragment size 448 * 58:55 reserved 449 * 54 P 450 * 53:48 reserved 451 * 47:6 physical base address of PD or PTE 452 * 5:3 reserved 453 * 2 C 454 * 1 system 455 * 0 valid 456 */ 457 458 static uint64_t gmc_v11_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 459 { 460 switch (flags) { 461 case AMDGPU_VM_MTYPE_DEFAULT: 462 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 463 case AMDGPU_VM_MTYPE_NC: 464 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 465 case AMDGPU_VM_MTYPE_WC: 466 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC); 467 case AMDGPU_VM_MTYPE_CC: 468 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC); 469 case AMDGPU_VM_MTYPE_UC: 470 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 471 default: 472 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 473 } 474 } 475 476 static void gmc_v11_0_get_vm_pde(struct amdgpu_device *adev, int level, 477 uint64_t *addr, uint64_t *flags) 478 { 479 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 480 *addr = adev->vm_manager.vram_base_offset + *addr - 481 adev->gmc.vram_start; 482 BUG_ON(*addr & 0xFFFF00000000003FULL); 483 484 if (!adev->gmc.translate_further) 485 return; 486 487 if (level == AMDGPU_VM_PDB1) { 488 /* Set the block fragment size */ 489 if (!(*flags & AMDGPU_PDE_PTE)) 490 *flags |= AMDGPU_PDE_BFS(0x9); 491 492 } else if (level == AMDGPU_VM_PDB0) { 493 if (*flags & AMDGPU_PDE_PTE) 494 *flags &= ~AMDGPU_PDE_PTE; 495 else 496 *flags |= AMDGPU_PTE_TF; 497 } 498 } 499 500 static void gmc_v11_0_get_vm_pte(struct amdgpu_device *adev, 501 struct amdgpu_bo_va_mapping *mapping, 502 uint64_t *flags) 503 { 504 *flags &= ~AMDGPU_PTE_EXECUTABLE; 505 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 506 507 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; 508 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); 509 510 if (mapping->flags & AMDGPU_PTE_PRT) { 511 *flags |= AMDGPU_PTE_PRT; 512 *flags |= AMDGPU_PTE_SNOOPED; 513 *flags |= AMDGPU_PTE_LOG; 514 *flags |= AMDGPU_PTE_SYSTEM; 515 *flags &= ~AMDGPU_PTE_VALID; 516 } 517 } 518 519 static unsigned gmc_v11_0_get_vbios_fb_size(struct amdgpu_device *adev) 520 { 521 return 0; 522 } 523 524 static const struct amdgpu_gmc_funcs gmc_v11_0_gmc_funcs = { 525 .flush_gpu_tlb = gmc_v11_0_flush_gpu_tlb, 526 .flush_gpu_tlb_pasid = gmc_v11_0_flush_gpu_tlb_pasid, 527 .emit_flush_gpu_tlb = gmc_v11_0_emit_flush_gpu_tlb, 528 .emit_pasid_mapping = gmc_v11_0_emit_pasid_mapping, 529 .map_mtype = gmc_v11_0_map_mtype, 530 .get_vm_pde = gmc_v11_0_get_vm_pde, 531 .get_vm_pte = gmc_v11_0_get_vm_pte, 532 .get_vbios_fb_size = gmc_v11_0_get_vbios_fb_size, 533 }; 534 535 static void gmc_v11_0_set_gmc_funcs(struct amdgpu_device *adev) 536 { 537 adev->gmc.gmc_funcs = &gmc_v11_0_gmc_funcs; 538 } 539 540 static void gmc_v11_0_set_umc_funcs(struct amdgpu_device *adev) 541 { 542 switch (adev->ip_versions[UMC_HWIP][0]) { 543 case IP_VERSION(8, 10, 0): 544 break; 545 default: 546 break; 547 } 548 } 549 550 551 static void gmc_v11_0_set_mmhub_funcs(struct amdgpu_device *adev) 552 { 553 adev->mmhub.funcs = &mmhub_v3_0_funcs; 554 } 555 556 static void gmc_v11_0_set_gfxhub_funcs(struct amdgpu_device *adev) 557 { 558 adev->gfxhub.funcs = &gfxhub_v3_0_funcs; 559 } 560 561 static int gmc_v11_0_early_init(void *handle) 562 { 563 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 564 565 gmc_v11_0_set_gfxhub_funcs(adev); 566 gmc_v11_0_set_mmhub_funcs(adev); 567 gmc_v11_0_set_gmc_funcs(adev); 568 gmc_v11_0_set_irq_funcs(adev); 569 gmc_v11_0_set_umc_funcs(adev); 570 571 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 572 adev->gmc.shared_aperture_end = 573 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 574 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 575 adev->gmc.private_aperture_end = 576 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 577 578 return 0; 579 } 580 581 static int gmc_v11_0_late_init(void *handle) 582 { 583 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 584 int r; 585 586 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 587 if (r) 588 return r; 589 590 r = amdgpu_gmc_ras_late_init(adev); 591 if (r) 592 return r; 593 594 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 595 } 596 597 static void gmc_v11_0_vram_gtt_location(struct amdgpu_device *adev, 598 struct amdgpu_gmc *mc) 599 { 600 u64 base = 0; 601 602 base = adev->mmhub.funcs->get_fb_location(adev); 603 604 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 605 amdgpu_gmc_gart_location(adev, mc); 606 607 /* base offset of vram pages */ 608 adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev); 609 } 610 611 /** 612 * gmc_v11_0_mc_init - initialize the memory controller driver params 613 * 614 * @adev: amdgpu_device pointer 615 * 616 * Look up the amount of vram, vram width, and decide how to place 617 * vram and gart within the GPU's physical address space. 618 * Returns 0 for success. 619 */ 620 static int gmc_v11_0_mc_init(struct amdgpu_device *adev) 621 { 622 int r; 623 624 /* size in MB on si */ 625 adev->gmc.mc_vram_size = 626 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 627 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 628 629 if (!(adev->flags & AMD_IS_APU)) { 630 r = amdgpu_device_resize_fb_bar(adev); 631 if (r) 632 return r; 633 } 634 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 635 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 636 637 /* In case the PCI BAR is larger than the actual amount of vram */ 638 adev->gmc.visible_vram_size = adev->gmc.aper_size; 639 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 640 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 641 642 /* set the gart size */ 643 if (amdgpu_gart_size == -1) { 644 adev->gmc.gart_size = 512ULL << 20; 645 } else 646 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 647 648 gmc_v11_0_vram_gtt_location(adev, &adev->gmc); 649 650 return 0; 651 } 652 653 static int gmc_v11_0_gart_init(struct amdgpu_device *adev) 654 { 655 int r; 656 657 if (adev->gart.bo) { 658 WARN(1, "PCIE GART already initialized\n"); 659 return 0; 660 } 661 662 /* Initialize common gart structure */ 663 r = amdgpu_gart_init(adev); 664 if (r) 665 return r; 666 667 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 668 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) | 669 AMDGPU_PTE_EXECUTABLE; 670 671 return amdgpu_gart_table_vram_alloc(adev); 672 } 673 674 static int gmc_v11_0_sw_init(void *handle) 675 { 676 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 677 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 678 679 adev->mmhub.funcs->init(adev); 680 681 spin_lock_init(&adev->gmc.invalidate_lock); 682 683 r = amdgpu_atomfirmware_get_vram_info(adev, 684 &vram_width, &vram_type, &vram_vendor); 685 adev->gmc.vram_width = vram_width; 686 687 adev->gmc.vram_type = vram_type; 688 adev->gmc.vram_vendor = vram_vendor; 689 690 switch (adev->ip_versions[GC_HWIP][0]) { 691 case IP_VERSION(11, 0, 0): 692 adev->num_vmhubs = 2; 693 /* 694 * To fulfill 4-level page support, 695 * vm size is 256TB (48bit), maximum size, 696 * block size 512 (9bit) 697 */ 698 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 699 break; 700 default: 701 break; 702 } 703 704 /* This interrupt is VMC page fault.*/ 705 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_VMC, 706 VMC_1_0__SRCID__VM_FAULT, 707 &adev->gmc.vm_fault); 708 709 if (r) 710 return r; 711 712 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 713 UTCL2_1_0__SRCID__FAULT, 714 &adev->gmc.vm_fault); 715 if (r) 716 return r; 717 718 if (!amdgpu_sriov_vf(adev)) { 719 /* interrupt sent to DF. */ 720 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_DF, 0, 721 &adev->gmc.ecc_irq); 722 if (r) 723 return r; 724 } 725 726 /* 727 * Set the internal MC address mask This is the max address of the GPU's 728 * internal address space. 729 */ 730 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 731 732 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 733 if (r) { 734 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 735 return r; 736 } 737 738 r = gmc_v11_0_mc_init(adev); 739 if (r) 740 return r; 741 742 amdgpu_gmc_get_vbios_allocations(adev); 743 744 /* Memory manager */ 745 r = amdgpu_bo_init(adev); 746 if (r) 747 return r; 748 749 r = gmc_v11_0_gart_init(adev); 750 if (r) 751 return r; 752 753 /* 754 * number of VMs 755 * VMID 0 is reserved for System 756 * amdgpu graphics/compute will use VMIDs 1-7 757 * amdkfd will use VMIDs 8-15 758 */ 759 adev->vm_manager.first_kfd_vmid = 8; 760 761 amdgpu_vm_manager_init(adev); 762 763 return 0; 764 } 765 766 /** 767 * gmc_v11_0_gart_fini - vm fini callback 768 * 769 * @adev: amdgpu_device pointer 770 * 771 * Tears down the driver GART/VM setup (CIK). 772 */ 773 static void gmc_v11_0_gart_fini(struct amdgpu_device *adev) 774 { 775 amdgpu_gart_table_vram_free(adev); 776 } 777 778 static int gmc_v11_0_sw_fini(void *handle) 779 { 780 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 781 782 amdgpu_vm_manager_fini(adev); 783 gmc_v11_0_gart_fini(adev); 784 amdgpu_gem_force_release(adev); 785 amdgpu_bo_fini(adev); 786 787 return 0; 788 } 789 790 static void gmc_v11_0_init_golden_registers(struct amdgpu_device *adev) 791 { 792 } 793 794 /** 795 * gmc_v11_0_gart_enable - gart enable 796 * 797 * @adev: amdgpu_device pointer 798 */ 799 static int gmc_v11_0_gart_enable(struct amdgpu_device *adev) 800 { 801 int r; 802 bool value; 803 804 if (adev->gart.bo == NULL) { 805 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 806 return -EINVAL; 807 } 808 809 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 810 811 r = adev->mmhub.funcs->gart_enable(adev); 812 if (r) 813 return r; 814 815 /* Flush HDP after it is initialized */ 816 adev->hdp.funcs->flush_hdp(adev, NULL); 817 818 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 819 false : true; 820 821 adev->mmhub.funcs->set_fault_enable_default(adev, value); 822 gmc_v11_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0); 823 824 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 825 (unsigned)(adev->gmc.gart_size >> 20), 826 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 827 828 return 0; 829 } 830 831 static int gmc_v11_0_hw_init(void *handle) 832 { 833 int r; 834 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 835 836 /* The sequence of these two function calls matters.*/ 837 gmc_v11_0_init_golden_registers(adev); 838 839 r = gmc_v11_0_gart_enable(adev); 840 if (r) 841 return r; 842 843 if (adev->umc.funcs && adev->umc.funcs->init_registers) 844 adev->umc.funcs->init_registers(adev); 845 846 return 0; 847 } 848 849 /** 850 * gmc_v11_0_gart_disable - gart disable 851 * 852 * @adev: amdgpu_device pointer 853 * 854 * This disables all VM page table. 855 */ 856 static void gmc_v11_0_gart_disable(struct amdgpu_device *adev) 857 { 858 adev->mmhub.funcs->gart_disable(adev); 859 } 860 861 static int gmc_v11_0_hw_fini(void *handle) 862 { 863 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 864 865 if (amdgpu_sriov_vf(adev)) { 866 /* full access mode, so don't touch any GMC register */ 867 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 868 return 0; 869 } 870 871 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 872 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 873 gmc_v11_0_gart_disable(adev); 874 875 return 0; 876 } 877 878 static int gmc_v11_0_suspend(void *handle) 879 { 880 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 881 882 gmc_v11_0_hw_fini(adev); 883 884 return 0; 885 } 886 887 static int gmc_v11_0_resume(void *handle) 888 { 889 int r; 890 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 891 892 r = gmc_v11_0_hw_init(adev); 893 if (r) 894 return r; 895 896 amdgpu_vmid_reset_all(adev); 897 898 return 0; 899 } 900 901 static bool gmc_v11_0_is_idle(void *handle) 902 { 903 /* MC is always ready in GMC v11.*/ 904 return true; 905 } 906 907 static int gmc_v11_0_wait_for_idle(void *handle) 908 { 909 /* There is no need to wait for MC idle in GMC v11.*/ 910 return 0; 911 } 912 913 static int gmc_v11_0_soft_reset(void *handle) 914 { 915 return 0; 916 } 917 918 static int gmc_v11_0_set_clockgating_state(void *handle, 919 enum amd_clockgating_state state) 920 { 921 int r; 922 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 923 924 r = adev->mmhub.funcs->set_clockgating(adev, state); 925 if (r) 926 return r; 927 928 return athub_v3_0_set_clockgating(adev, state); 929 } 930 931 static void gmc_v11_0_get_clockgating_state(void *handle, u64 *flags) 932 { 933 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 934 935 adev->mmhub.funcs->get_clockgating(adev, flags); 936 937 athub_v3_0_get_clockgating(adev, flags); 938 } 939 940 static int gmc_v11_0_set_powergating_state(void *handle, 941 enum amd_powergating_state state) 942 { 943 return 0; 944 } 945 946 const struct amd_ip_funcs gmc_v11_0_ip_funcs = { 947 .name = "gmc_v11_0", 948 .early_init = gmc_v11_0_early_init, 949 .sw_init = gmc_v11_0_sw_init, 950 .hw_init = gmc_v11_0_hw_init, 951 .late_init = gmc_v11_0_late_init, 952 .sw_fini = gmc_v11_0_sw_fini, 953 .hw_fini = gmc_v11_0_hw_fini, 954 .suspend = gmc_v11_0_suspend, 955 .resume = gmc_v11_0_resume, 956 .is_idle = gmc_v11_0_is_idle, 957 .wait_for_idle = gmc_v11_0_wait_for_idle, 958 .soft_reset = gmc_v11_0_soft_reset, 959 .set_clockgating_state = gmc_v11_0_set_clockgating_state, 960 .set_powergating_state = gmc_v11_0_set_powergating_state, 961 .get_clockgating_state = gmc_v11_0_get_clockgating_state, 962 }; 963 964 const struct amdgpu_ip_block_version gmc_v11_0_ip_block = { 965 .type = AMD_IP_BLOCK_TYPE_GMC, 966 .major = 11, 967 .minor = 0, 968 .rev = 0, 969 .funcs = &gmc_v11_0_ip_funcs, 970 }; 971