1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 26 #include <drm/drm_cache.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atomfirmware.h" 30 #include "gmc_v11_0.h" 31 #include "umc_v8_10.h" 32 #include "athub/athub_3_0_0_sh_mask.h" 33 #include "athub/athub_3_0_0_offset.h" 34 #include "oss/osssys_6_0_0_offset.h" 35 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 36 #include "navi10_enum.h" 37 #include "soc15.h" 38 #include "soc15d.h" 39 #include "soc15_common.h" 40 #include "nbio_v4_3.h" 41 #include "gfxhub_v3_0.h" 42 #include "gfxhub_v3_0_3.h" 43 #include "mmhub_v3_0.h" 44 #include "mmhub_v3_0_1.h" 45 #include "mmhub_v3_0_2.h" 46 #include "athub_v3_0.h" 47 48 49 static int gmc_v11_0_ecc_interrupt_state(struct amdgpu_device *adev, 50 struct amdgpu_irq_src *src, 51 unsigned type, 52 enum amdgpu_interrupt_state state) 53 { 54 return 0; 55 } 56 57 static int 58 gmc_v11_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 59 struct amdgpu_irq_src *src, unsigned type, 60 enum amdgpu_interrupt_state state) 61 { 62 switch (state) { 63 case AMDGPU_IRQ_STATE_DISABLE: 64 /* MM HUB */ 65 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false); 66 /* GFX HUB */ 67 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false); 68 break; 69 case AMDGPU_IRQ_STATE_ENABLE: 70 /* MM HUB */ 71 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true); 72 /* GFX HUB */ 73 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true); 74 break; 75 default: 76 break; 77 } 78 79 return 0; 80 } 81 82 static int gmc_v11_0_process_interrupt(struct amdgpu_device *adev, 83 struct amdgpu_irq_src *source, 84 struct amdgpu_iv_entry *entry) 85 { 86 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; 87 uint32_t status = 0; 88 u64 addr; 89 90 addr = (u64)entry->src_data[0] << 12; 91 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 92 93 if (!amdgpu_sriov_vf(adev)) { 94 /* 95 * Issue a dummy read to wait for the status register to 96 * be updated to avoid reading an incorrect value due to 97 * the new fast GRBM interface. 98 */ 99 if (entry->vmid_src == AMDGPU_GFXHUB_0) 100 RREG32(hub->vm_l2_pro_fault_status); 101 102 status = RREG32(hub->vm_l2_pro_fault_status); 103 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 104 } 105 106 if (printk_ratelimit()) { 107 struct amdgpu_task_info task_info; 108 109 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 110 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 111 112 dev_err(adev->dev, 113 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, " 114 "for process %s pid %d thread %s pid %d)\n", 115 entry->vmid_src ? "mmhub" : "gfxhub", 116 entry->src_id, entry->ring_id, entry->vmid, 117 entry->pasid, task_info.process_name, task_info.tgid, 118 task_info.task_name, task_info.pid); 119 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", 120 addr, entry->client_id); 121 if (!amdgpu_sriov_vf(adev)) 122 hub->vmhub_funcs->print_l2_protection_fault_status(adev, status); 123 } 124 125 return 0; 126 } 127 128 static const struct amdgpu_irq_src_funcs gmc_v11_0_irq_funcs = { 129 .set = gmc_v11_0_vm_fault_interrupt_state, 130 .process = gmc_v11_0_process_interrupt, 131 }; 132 133 static const struct amdgpu_irq_src_funcs gmc_v11_0_ecc_funcs = { 134 .set = gmc_v11_0_ecc_interrupt_state, 135 .process = amdgpu_umc_process_ecc_irq, 136 }; 137 138 static void gmc_v11_0_set_irq_funcs(struct amdgpu_device *adev) 139 { 140 adev->gmc.vm_fault.num_types = 1; 141 adev->gmc.vm_fault.funcs = &gmc_v11_0_irq_funcs; 142 143 if (!amdgpu_sriov_vf(adev)) { 144 adev->gmc.ecc_irq.num_types = 1; 145 adev->gmc.ecc_irq.funcs = &gmc_v11_0_ecc_funcs; 146 } 147 } 148 149 /** 150 * gmc_v11_0_use_invalidate_semaphore - judge whether to use semaphore 151 * 152 * @adev: amdgpu_device pointer 153 * @vmhub: vmhub type 154 * 155 */ 156 static bool gmc_v11_0_use_invalidate_semaphore(struct amdgpu_device *adev, 157 uint32_t vmhub) 158 { 159 return ((vmhub == AMDGPU_MMHUB_0) && 160 (!amdgpu_sriov_vf(adev))); 161 } 162 163 static bool gmc_v11_0_get_vmid_pasid_mapping_info( 164 struct amdgpu_device *adev, 165 uint8_t vmid, uint16_t *p_pasid) 166 { 167 *p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff; 168 169 return !!(*p_pasid); 170 } 171 172 /* 173 * GART 174 * VMID 0 is the physical GPU addresses as used by the kernel. 175 * VMIDs 1-15 are used for userspace clients and are handled 176 * by the amdgpu vm/hsa code. 177 */ 178 179 static void gmc_v11_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 180 unsigned int vmhub, uint32_t flush_type) 181 { 182 bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(adev, vmhub); 183 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 184 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 185 u32 tmp; 186 /* Use register 17 for GART */ 187 const unsigned eng = 17; 188 unsigned int i; 189 unsigned char hub_ip = 0; 190 191 hub_ip = (vmhub == AMDGPU_GFXHUB_0) ? 192 GC_HWIP : MMHUB_HWIP; 193 194 spin_lock(&adev->gmc.invalidate_lock); 195 /* 196 * It may lose gpuvm invalidate acknowldege state across power-gating 197 * off cycle, add semaphore acquire before invalidation and semaphore 198 * release after invalidation to avoid entering power gated state 199 * to WA the Issue 200 */ 201 202 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 203 if (use_semaphore) { 204 for (i = 0; i < adev->usec_timeout; i++) { 205 /* a read return value of 1 means semaphore acuqire */ 206 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + 207 hub->eng_distance * eng, hub_ip); 208 if (tmp & 0x1) 209 break; 210 udelay(1); 211 } 212 213 if (i >= adev->usec_timeout) 214 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 215 } 216 217 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req, hub_ip); 218 219 /* Wait for ACK with a delay.*/ 220 for (i = 0; i < adev->usec_timeout; i++) { 221 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack + 222 hub->eng_distance * eng, hub_ip); 223 tmp &= 1 << vmid; 224 if (tmp) 225 break; 226 227 udelay(1); 228 } 229 230 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 231 if (use_semaphore) 232 /* 233 * add semaphore release after invalidation, 234 * write with 0 means semaphore release 235 */ 236 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + 237 hub->eng_distance * eng, 0, hub_ip); 238 239 /* Issue additional private vm invalidation to MMHUB */ 240 if ((vmhub != AMDGPU_GFXHUB_0) && 241 (hub->vm_l2_bank_select_reserved_cid2) && 242 !amdgpu_sriov_vf(adev)) { 243 inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 244 /* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */ 245 inv_req |= (1 << 25); 246 /* Issue private invalidation */ 247 WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req); 248 /* Read back to ensure invalidation is done*/ 249 RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 250 } 251 252 spin_unlock(&adev->gmc.invalidate_lock); 253 254 if (i < adev->usec_timeout) 255 return; 256 257 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 258 } 259 260 /** 261 * gmc_v11_0_flush_gpu_tlb - gart tlb flush callback 262 * 263 * @adev: amdgpu_device pointer 264 * @vmid: vm instance to flush 265 * 266 * Flush the TLB for the requested page table. 267 */ 268 static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 269 uint32_t vmhub, uint32_t flush_type) 270 { 271 if ((vmhub == AMDGPU_GFXHUB_0) && !adev->gfx.is_poweron) 272 return; 273 274 /* flush hdp cache */ 275 adev->hdp.funcs->flush_hdp(adev, NULL); 276 277 /* For SRIOV run time, driver shouldn't access the register through MMIO 278 * Directly use kiq to do the vm invalidation instead 279 */ 280 if ((adev->gfx.kiq.ring.sched.ready || adev->mes.ring.sched.ready) && 281 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 282 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 283 const unsigned eng = 17; 284 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 285 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 286 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 287 288 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 289 1 << vmid); 290 return; 291 } 292 293 mutex_lock(&adev->mman.gtt_window_lock); 294 gmc_v11_0_flush_vm_hub(adev, vmid, vmhub, 0); 295 mutex_unlock(&adev->mman.gtt_window_lock); 296 return; 297 } 298 299 /** 300 * gmc_v11_0_flush_gpu_tlb_pasid - tlb flush via pasid 301 * 302 * @adev: amdgpu_device pointer 303 * @pasid: pasid to be flush 304 * 305 * Flush the TLB for the requested pasid. 306 */ 307 static int gmc_v11_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 308 uint16_t pasid, uint32_t flush_type, 309 bool all_hub) 310 { 311 int vmid, i; 312 signed long r; 313 uint32_t seq; 314 uint16_t queried_pasid; 315 bool ret; 316 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 317 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 318 319 if (amdgpu_emu_mode == 0 && ring->sched.ready) { 320 spin_lock(&adev->gfx.kiq.ring_lock); 321 /* 2 dwords flush + 8 dwords fence */ 322 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8); 323 kiq->pmf->kiq_invalidate_tlbs(ring, 324 pasid, flush_type, all_hub); 325 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 326 if (r) { 327 amdgpu_ring_undo(ring); 328 spin_unlock(&adev->gfx.kiq.ring_lock); 329 return -ETIME; 330 } 331 332 amdgpu_ring_commit(ring); 333 spin_unlock(&adev->gfx.kiq.ring_lock); 334 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); 335 if (r < 1) { 336 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r); 337 return -ETIME; 338 } 339 340 return 0; 341 } 342 343 for (vmid = 1; vmid < 16; vmid++) { 344 345 ret = gmc_v11_0_get_vmid_pasid_mapping_info(adev, vmid, 346 &queried_pasid); 347 if (ret && queried_pasid == pasid) { 348 if (all_hub) { 349 for (i = 0; i < adev->num_vmhubs; i++) 350 gmc_v11_0_flush_gpu_tlb(adev, vmid, 351 i, flush_type); 352 } else { 353 gmc_v11_0_flush_gpu_tlb(adev, vmid, 354 AMDGPU_GFXHUB_0, flush_type); 355 } 356 } 357 } 358 359 return 0; 360 } 361 362 static uint64_t gmc_v11_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 363 unsigned vmid, uint64_t pd_addr) 364 { 365 bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub); 366 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 367 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 368 unsigned eng = ring->vm_inv_eng; 369 370 /* 371 * It may lose gpuvm invalidate acknowldege state across power-gating 372 * off cycle, add semaphore acquire before invalidation and semaphore 373 * release after invalidation to avoid entering power gated state 374 * to WA the Issue 375 */ 376 377 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 378 if (use_semaphore) 379 /* a read return value of 1 means semaphore acuqire */ 380 amdgpu_ring_emit_reg_wait(ring, 381 hub->vm_inv_eng0_sem + 382 hub->eng_distance * eng, 0x1, 0x1); 383 384 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 385 (hub->ctx_addr_distance * vmid), 386 lower_32_bits(pd_addr)); 387 388 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 389 (hub->ctx_addr_distance * vmid), 390 upper_32_bits(pd_addr)); 391 392 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 393 hub->eng_distance * eng, 394 hub->vm_inv_eng0_ack + 395 hub->eng_distance * eng, 396 req, 1 << vmid); 397 398 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 399 if (use_semaphore) 400 /* 401 * add semaphore release after invalidation, 402 * write with 0 means semaphore release 403 */ 404 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 405 hub->eng_distance * eng, 0); 406 407 return pd_addr; 408 } 409 410 static void gmc_v11_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 411 unsigned pasid) 412 { 413 struct amdgpu_device *adev = ring->adev; 414 uint32_t reg; 415 416 /* MES fw manages IH_VMID_x_LUT updating */ 417 if (ring->is_mes_queue) 418 return; 419 420 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) 421 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid; 422 else 423 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid; 424 425 amdgpu_ring_emit_wreg(ring, reg, pasid); 426 } 427 428 /* 429 * PTE format: 430 * 63:59 reserved 431 * 58:57 reserved 432 * 56 F 433 * 55 L 434 * 54 reserved 435 * 53:52 SW 436 * 51 T 437 * 50:48 mtype 438 * 47:12 4k physical page base address 439 * 11:7 fragment 440 * 6 write 441 * 5 read 442 * 4 exe 443 * 3 Z 444 * 2 snooped 445 * 1 system 446 * 0 valid 447 * 448 * PDE format: 449 * 63:59 block fragment size 450 * 58:55 reserved 451 * 54 P 452 * 53:48 reserved 453 * 47:6 physical base address of PD or PTE 454 * 5:3 reserved 455 * 2 C 456 * 1 system 457 * 0 valid 458 */ 459 460 static uint64_t gmc_v11_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 461 { 462 switch (flags) { 463 case AMDGPU_VM_MTYPE_DEFAULT: 464 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 465 case AMDGPU_VM_MTYPE_NC: 466 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 467 case AMDGPU_VM_MTYPE_WC: 468 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC); 469 case AMDGPU_VM_MTYPE_CC: 470 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC); 471 case AMDGPU_VM_MTYPE_UC: 472 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 473 default: 474 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 475 } 476 } 477 478 static void gmc_v11_0_get_vm_pde(struct amdgpu_device *adev, int level, 479 uint64_t *addr, uint64_t *flags) 480 { 481 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 482 *addr = adev->vm_manager.vram_base_offset + *addr - 483 adev->gmc.vram_start; 484 BUG_ON(*addr & 0xFFFF00000000003FULL); 485 486 if (!adev->gmc.translate_further) 487 return; 488 489 if (level == AMDGPU_VM_PDB1) { 490 /* Set the block fragment size */ 491 if (!(*flags & AMDGPU_PDE_PTE)) 492 *flags |= AMDGPU_PDE_BFS(0x9); 493 494 } else if (level == AMDGPU_VM_PDB0) { 495 if (*flags & AMDGPU_PDE_PTE) 496 *flags &= ~AMDGPU_PDE_PTE; 497 else 498 *flags |= AMDGPU_PTE_TF; 499 } 500 } 501 502 static void gmc_v11_0_get_vm_pte(struct amdgpu_device *adev, 503 struct amdgpu_bo_va_mapping *mapping, 504 uint64_t *flags) 505 { 506 struct amdgpu_bo *bo = mapping->bo_va->base.bo; 507 508 *flags &= ~AMDGPU_PTE_EXECUTABLE; 509 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 510 511 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; 512 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); 513 514 *flags &= ~AMDGPU_PTE_NOALLOC; 515 *flags |= (mapping->flags & AMDGPU_PTE_NOALLOC); 516 517 if (mapping->flags & AMDGPU_PTE_PRT) { 518 *flags |= AMDGPU_PTE_PRT; 519 *flags |= AMDGPU_PTE_SNOOPED; 520 *flags |= AMDGPU_PTE_LOG; 521 *flags |= AMDGPU_PTE_SYSTEM; 522 *flags &= ~AMDGPU_PTE_VALID; 523 } 524 525 if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT | 526 AMDGPU_GEM_CREATE_UNCACHED)) 527 *flags = (*flags & ~AMDGPU_PTE_MTYPE_NV10_MASK) | 528 AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 529 } 530 531 static unsigned gmc_v11_0_get_vbios_fb_size(struct amdgpu_device *adev) 532 { 533 return 0; 534 } 535 536 static const struct amdgpu_gmc_funcs gmc_v11_0_gmc_funcs = { 537 .flush_gpu_tlb = gmc_v11_0_flush_gpu_tlb, 538 .flush_gpu_tlb_pasid = gmc_v11_0_flush_gpu_tlb_pasid, 539 .emit_flush_gpu_tlb = gmc_v11_0_emit_flush_gpu_tlb, 540 .emit_pasid_mapping = gmc_v11_0_emit_pasid_mapping, 541 .map_mtype = gmc_v11_0_map_mtype, 542 .get_vm_pde = gmc_v11_0_get_vm_pde, 543 .get_vm_pte = gmc_v11_0_get_vm_pte, 544 .get_vbios_fb_size = gmc_v11_0_get_vbios_fb_size, 545 }; 546 547 static void gmc_v11_0_set_gmc_funcs(struct amdgpu_device *adev) 548 { 549 adev->gmc.gmc_funcs = &gmc_v11_0_gmc_funcs; 550 } 551 552 static void gmc_v11_0_set_umc_funcs(struct amdgpu_device *adev) 553 { 554 switch (adev->ip_versions[UMC_HWIP][0]) { 555 case IP_VERSION(8, 10, 0): 556 adev->umc.channel_inst_num = UMC_V8_10_CHANNEL_INSTANCE_NUM; 557 adev->umc.umc_inst_num = UMC_V8_10_UMC_INSTANCE_NUM; 558 adev->umc.node_inst_num = adev->gmc.num_umc; 559 adev->umc.max_ras_err_cnt_per_query = UMC_V8_10_TOTAL_CHANNEL_NUM(adev); 560 adev->umc.channel_offs = UMC_V8_10_PER_CHANNEL_OFFSET; 561 if (adev->umc.node_inst_num == 4) 562 adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl_ext0[0][0][0]; 563 else 564 adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl[0][0][0]; 565 adev->umc.ras = &umc_v8_10_ras; 566 break; 567 case IP_VERSION(8, 11, 0): 568 break; 569 default: 570 break; 571 } 572 573 if (adev->umc.ras) { 574 amdgpu_ras_register_ras_block(adev, &adev->umc.ras->ras_block); 575 576 strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc"); 577 adev->umc.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC; 578 adev->umc.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; 579 adev->umc.ras_if = &adev->umc.ras->ras_block.ras_comm; 580 581 /* If don't define special ras_late_init function, use default ras_late_init */ 582 if (!adev->umc.ras->ras_block.ras_late_init) 583 adev->umc.ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init; 584 585 /* If not define special ras_cb function, use default ras_cb */ 586 if (!adev->umc.ras->ras_block.ras_cb) 587 adev->umc.ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb; 588 } 589 } 590 591 592 static void gmc_v11_0_set_mmhub_funcs(struct amdgpu_device *adev) 593 { 594 switch (adev->ip_versions[MMHUB_HWIP][0]) { 595 case IP_VERSION(3, 0, 1): 596 adev->mmhub.funcs = &mmhub_v3_0_1_funcs; 597 break; 598 case IP_VERSION(3, 0, 2): 599 adev->mmhub.funcs = &mmhub_v3_0_2_funcs; 600 break; 601 default: 602 adev->mmhub.funcs = &mmhub_v3_0_funcs; 603 break; 604 } 605 } 606 607 static void gmc_v11_0_set_gfxhub_funcs(struct amdgpu_device *adev) 608 { 609 switch (adev->ip_versions[GC_HWIP][0]) { 610 case IP_VERSION(11, 0, 3): 611 adev->gfxhub.funcs = &gfxhub_v3_0_3_funcs; 612 break; 613 default: 614 adev->gfxhub.funcs = &gfxhub_v3_0_funcs; 615 break; 616 } 617 } 618 619 static int gmc_v11_0_early_init(void *handle) 620 { 621 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 622 623 gmc_v11_0_set_gfxhub_funcs(adev); 624 gmc_v11_0_set_mmhub_funcs(adev); 625 gmc_v11_0_set_gmc_funcs(adev); 626 gmc_v11_0_set_irq_funcs(adev); 627 gmc_v11_0_set_umc_funcs(adev); 628 629 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 630 adev->gmc.shared_aperture_end = 631 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 632 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 633 adev->gmc.private_aperture_end = 634 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 635 636 return 0; 637 } 638 639 static int gmc_v11_0_late_init(void *handle) 640 { 641 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 642 int r; 643 644 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 645 if (r) 646 return r; 647 648 r = amdgpu_gmc_ras_late_init(adev); 649 if (r) 650 return r; 651 652 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 653 } 654 655 static void gmc_v11_0_vram_gtt_location(struct amdgpu_device *adev, 656 struct amdgpu_gmc *mc) 657 { 658 u64 base = 0; 659 660 base = adev->mmhub.funcs->get_fb_location(adev); 661 662 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 663 amdgpu_gmc_gart_location(adev, mc); 664 665 /* base offset of vram pages */ 666 if (amdgpu_sriov_vf(adev)) 667 adev->vm_manager.vram_base_offset = 0; 668 else 669 adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev); 670 } 671 672 /** 673 * gmc_v11_0_mc_init - initialize the memory controller driver params 674 * 675 * @adev: amdgpu_device pointer 676 * 677 * Look up the amount of vram, vram width, and decide how to place 678 * vram and gart within the GPU's physical address space. 679 * Returns 0 for success. 680 */ 681 static int gmc_v11_0_mc_init(struct amdgpu_device *adev) 682 { 683 int r; 684 685 /* size in MB on si */ 686 adev->gmc.mc_vram_size = 687 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 688 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 689 690 if (!(adev->flags & AMD_IS_APU)) { 691 r = amdgpu_device_resize_fb_bar(adev); 692 if (r) 693 return r; 694 } 695 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 696 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 697 698 #ifdef CONFIG_X86_64 699 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { 700 adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev); 701 adev->gmc.aper_size = adev->gmc.real_vram_size; 702 } 703 #endif 704 /* In case the PCI BAR is larger than the actual amount of vram */ 705 adev->gmc.visible_vram_size = adev->gmc.aper_size; 706 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 707 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 708 709 /* set the gart size */ 710 if (amdgpu_gart_size == -1) { 711 adev->gmc.gart_size = 512ULL << 20; 712 } else 713 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 714 715 gmc_v11_0_vram_gtt_location(adev, &adev->gmc); 716 717 return 0; 718 } 719 720 static int gmc_v11_0_gart_init(struct amdgpu_device *adev) 721 { 722 int r; 723 724 if (adev->gart.bo) { 725 WARN(1, "PCIE GART already initialized\n"); 726 return 0; 727 } 728 729 /* Initialize common gart structure */ 730 r = amdgpu_gart_init(adev); 731 if (r) 732 return r; 733 734 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 735 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) | 736 AMDGPU_PTE_EXECUTABLE; 737 738 return amdgpu_gart_table_vram_alloc(adev); 739 } 740 741 static int gmc_v11_0_sw_init(void *handle) 742 { 743 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 744 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 745 746 adev->mmhub.funcs->init(adev); 747 748 spin_lock_init(&adev->gmc.invalidate_lock); 749 750 r = amdgpu_atomfirmware_get_vram_info(adev, 751 &vram_width, &vram_type, &vram_vendor); 752 adev->gmc.vram_width = vram_width; 753 754 adev->gmc.vram_type = vram_type; 755 adev->gmc.vram_vendor = vram_vendor; 756 757 switch (adev->ip_versions[GC_HWIP][0]) { 758 case IP_VERSION(11, 0, 0): 759 case IP_VERSION(11, 0, 1): 760 case IP_VERSION(11, 0, 2): 761 case IP_VERSION(11, 0, 3): 762 adev->num_vmhubs = 2; 763 /* 764 * To fulfill 4-level page support, 765 * vm size is 256TB (48bit), maximum size, 766 * block size 512 (9bit) 767 */ 768 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 769 break; 770 default: 771 break; 772 } 773 774 /* This interrupt is VMC page fault.*/ 775 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_VMC, 776 VMC_1_0__SRCID__VM_FAULT, 777 &adev->gmc.vm_fault); 778 779 if (r) 780 return r; 781 782 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 783 UTCL2_1_0__SRCID__FAULT, 784 &adev->gmc.vm_fault); 785 if (r) 786 return r; 787 788 if (!amdgpu_sriov_vf(adev)) { 789 /* interrupt sent to DF. */ 790 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_DF, 0, 791 &adev->gmc.ecc_irq); 792 if (r) 793 return r; 794 } 795 796 /* 797 * Set the internal MC address mask This is the max address of the GPU's 798 * internal address space. 799 */ 800 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 801 802 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 803 if (r) { 804 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 805 return r; 806 } 807 808 adev->need_swiotlb = drm_need_swiotlb(44); 809 810 r = gmc_v11_0_mc_init(adev); 811 if (r) 812 return r; 813 814 amdgpu_gmc_get_vbios_allocations(adev); 815 816 /* Memory manager */ 817 r = amdgpu_bo_init(adev); 818 if (r) 819 return r; 820 821 r = gmc_v11_0_gart_init(adev); 822 if (r) 823 return r; 824 825 /* 826 * number of VMs 827 * VMID 0 is reserved for System 828 * amdgpu graphics/compute will use VMIDs 1-7 829 * amdkfd will use VMIDs 8-15 830 */ 831 adev->vm_manager.first_kfd_vmid = 8; 832 833 amdgpu_vm_manager_init(adev); 834 835 return 0; 836 } 837 838 /** 839 * gmc_v11_0_gart_fini - vm fini callback 840 * 841 * @adev: amdgpu_device pointer 842 * 843 * Tears down the driver GART/VM setup (CIK). 844 */ 845 static void gmc_v11_0_gart_fini(struct amdgpu_device *adev) 846 { 847 amdgpu_gart_table_vram_free(adev); 848 } 849 850 static int gmc_v11_0_sw_fini(void *handle) 851 { 852 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 853 854 amdgpu_vm_manager_fini(adev); 855 gmc_v11_0_gart_fini(adev); 856 amdgpu_gem_force_release(adev); 857 amdgpu_bo_fini(adev); 858 859 return 0; 860 } 861 862 static void gmc_v11_0_init_golden_registers(struct amdgpu_device *adev) 863 { 864 } 865 866 /** 867 * gmc_v11_0_gart_enable - gart enable 868 * 869 * @adev: amdgpu_device pointer 870 */ 871 static int gmc_v11_0_gart_enable(struct amdgpu_device *adev) 872 { 873 int r; 874 bool value; 875 876 if (adev->gart.bo == NULL) { 877 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 878 return -EINVAL; 879 } 880 881 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 882 883 r = adev->mmhub.funcs->gart_enable(adev); 884 if (r) 885 return r; 886 887 /* Flush HDP after it is initialized */ 888 adev->hdp.funcs->flush_hdp(adev, NULL); 889 890 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 891 false : true; 892 893 adev->mmhub.funcs->set_fault_enable_default(adev, value); 894 gmc_v11_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0); 895 896 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 897 (unsigned)(adev->gmc.gart_size >> 20), 898 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 899 900 return 0; 901 } 902 903 static int gmc_v11_0_hw_init(void *handle) 904 { 905 int r; 906 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 907 908 /* The sequence of these two function calls matters.*/ 909 gmc_v11_0_init_golden_registers(adev); 910 911 r = gmc_v11_0_gart_enable(adev); 912 if (r) 913 return r; 914 915 if (adev->umc.funcs && adev->umc.funcs->init_registers) 916 adev->umc.funcs->init_registers(adev); 917 918 return 0; 919 } 920 921 /** 922 * gmc_v11_0_gart_disable - gart disable 923 * 924 * @adev: amdgpu_device pointer 925 * 926 * This disables all VM page table. 927 */ 928 static void gmc_v11_0_gart_disable(struct amdgpu_device *adev) 929 { 930 adev->mmhub.funcs->gart_disable(adev); 931 } 932 933 static int gmc_v11_0_hw_fini(void *handle) 934 { 935 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 936 937 if (amdgpu_sriov_vf(adev)) { 938 /* full access mode, so don't touch any GMC register */ 939 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 940 return 0; 941 } 942 943 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 944 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 945 gmc_v11_0_gart_disable(adev); 946 947 return 0; 948 } 949 950 static int gmc_v11_0_suspend(void *handle) 951 { 952 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 953 954 gmc_v11_0_hw_fini(adev); 955 956 return 0; 957 } 958 959 static int gmc_v11_0_resume(void *handle) 960 { 961 int r; 962 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 963 964 r = gmc_v11_0_hw_init(adev); 965 if (r) 966 return r; 967 968 amdgpu_vmid_reset_all(adev); 969 970 return 0; 971 } 972 973 static bool gmc_v11_0_is_idle(void *handle) 974 { 975 /* MC is always ready in GMC v11.*/ 976 return true; 977 } 978 979 static int gmc_v11_0_wait_for_idle(void *handle) 980 { 981 /* There is no need to wait for MC idle in GMC v11.*/ 982 return 0; 983 } 984 985 static int gmc_v11_0_soft_reset(void *handle) 986 { 987 return 0; 988 } 989 990 static int gmc_v11_0_set_clockgating_state(void *handle, 991 enum amd_clockgating_state state) 992 { 993 int r; 994 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 995 996 r = adev->mmhub.funcs->set_clockgating(adev, state); 997 if (r) 998 return r; 999 1000 return athub_v3_0_set_clockgating(adev, state); 1001 } 1002 1003 static void gmc_v11_0_get_clockgating_state(void *handle, u64 *flags) 1004 { 1005 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1006 1007 adev->mmhub.funcs->get_clockgating(adev, flags); 1008 1009 athub_v3_0_get_clockgating(adev, flags); 1010 } 1011 1012 static int gmc_v11_0_set_powergating_state(void *handle, 1013 enum amd_powergating_state state) 1014 { 1015 return 0; 1016 } 1017 1018 const struct amd_ip_funcs gmc_v11_0_ip_funcs = { 1019 .name = "gmc_v11_0", 1020 .early_init = gmc_v11_0_early_init, 1021 .sw_init = gmc_v11_0_sw_init, 1022 .hw_init = gmc_v11_0_hw_init, 1023 .late_init = gmc_v11_0_late_init, 1024 .sw_fini = gmc_v11_0_sw_fini, 1025 .hw_fini = gmc_v11_0_hw_fini, 1026 .suspend = gmc_v11_0_suspend, 1027 .resume = gmc_v11_0_resume, 1028 .is_idle = gmc_v11_0_is_idle, 1029 .wait_for_idle = gmc_v11_0_wait_for_idle, 1030 .soft_reset = gmc_v11_0_soft_reset, 1031 .set_clockgating_state = gmc_v11_0_set_clockgating_state, 1032 .set_powergating_state = gmc_v11_0_set_powergating_state, 1033 .get_clockgating_state = gmc_v11_0_get_clockgating_state, 1034 }; 1035 1036 const struct amdgpu_ip_block_version gmc_v11_0_ip_block = { 1037 .type = AMD_IP_BLOCK_TYPE_GMC, 1038 .major = 11, 1039 .minor = 0, 1040 .rev = 0, 1041 .funcs = &gmc_v11_0_ip_funcs, 1042 }; 1043