1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 26 #include <drm/drm_cache.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atomfirmware.h" 30 #include "gmc_v11_0.h" 31 #include "umc_v8_10.h" 32 #include "athub/athub_3_0_0_sh_mask.h" 33 #include "athub/athub_3_0_0_offset.h" 34 #include "oss/osssys_6_0_0_offset.h" 35 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 36 #include "navi10_enum.h" 37 #include "soc15.h" 38 #include "soc15d.h" 39 #include "soc15_common.h" 40 #include "nbio_v4_3.h" 41 #include "gfxhub_v3_0.h" 42 #include "mmhub_v3_0.h" 43 #include "mmhub_v3_0_1.h" 44 #include "mmhub_v3_0_2.h" 45 #include "athub_v3_0.h" 46 47 48 static int gmc_v11_0_ecc_interrupt_state(struct amdgpu_device *adev, 49 struct amdgpu_irq_src *src, 50 unsigned type, 51 enum amdgpu_interrupt_state state) 52 { 53 return 0; 54 } 55 56 static int 57 gmc_v11_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 58 struct amdgpu_irq_src *src, unsigned type, 59 enum amdgpu_interrupt_state state) 60 { 61 switch (state) { 62 case AMDGPU_IRQ_STATE_DISABLE: 63 /* MM HUB */ 64 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false); 65 /* GFX HUB */ 66 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false); 67 break; 68 case AMDGPU_IRQ_STATE_ENABLE: 69 /* MM HUB */ 70 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true); 71 /* GFX HUB */ 72 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true); 73 break; 74 default: 75 break; 76 } 77 78 return 0; 79 } 80 81 static int gmc_v11_0_process_interrupt(struct amdgpu_device *adev, 82 struct amdgpu_irq_src *source, 83 struct amdgpu_iv_entry *entry) 84 { 85 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; 86 uint32_t status = 0; 87 u64 addr; 88 89 addr = (u64)entry->src_data[0] << 12; 90 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 91 92 if (!amdgpu_sriov_vf(adev)) { 93 /* 94 * Issue a dummy read to wait for the status register to 95 * be updated to avoid reading an incorrect value due to 96 * the new fast GRBM interface. 97 */ 98 if (entry->vmid_src == AMDGPU_GFXHUB_0) 99 RREG32(hub->vm_l2_pro_fault_status); 100 101 status = RREG32(hub->vm_l2_pro_fault_status); 102 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 103 } 104 105 if (printk_ratelimit()) { 106 struct amdgpu_task_info task_info; 107 108 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 109 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 110 111 dev_err(adev->dev, 112 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, " 113 "for process %s pid %d thread %s pid %d)\n", 114 entry->vmid_src ? "mmhub" : "gfxhub", 115 entry->src_id, entry->ring_id, entry->vmid, 116 entry->pasid, task_info.process_name, task_info.tgid, 117 task_info.task_name, task_info.pid); 118 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", 119 addr, entry->client_id); 120 if (!amdgpu_sriov_vf(adev)) 121 hub->vmhub_funcs->print_l2_protection_fault_status(adev, status); 122 } 123 124 return 0; 125 } 126 127 static const struct amdgpu_irq_src_funcs gmc_v11_0_irq_funcs = { 128 .set = gmc_v11_0_vm_fault_interrupt_state, 129 .process = gmc_v11_0_process_interrupt, 130 }; 131 132 static const struct amdgpu_irq_src_funcs gmc_v11_0_ecc_funcs = { 133 .set = gmc_v11_0_ecc_interrupt_state, 134 .process = amdgpu_umc_process_ecc_irq, 135 }; 136 137 static void gmc_v11_0_set_irq_funcs(struct amdgpu_device *adev) 138 { 139 adev->gmc.vm_fault.num_types = 1; 140 adev->gmc.vm_fault.funcs = &gmc_v11_0_irq_funcs; 141 142 if (!amdgpu_sriov_vf(adev)) { 143 adev->gmc.ecc_irq.num_types = 1; 144 adev->gmc.ecc_irq.funcs = &gmc_v11_0_ecc_funcs; 145 } 146 } 147 148 /** 149 * gmc_v11_0_use_invalidate_semaphore - judge whether to use semaphore 150 * 151 * @adev: amdgpu_device pointer 152 * @vmhub: vmhub type 153 * 154 */ 155 static bool gmc_v11_0_use_invalidate_semaphore(struct amdgpu_device *adev, 156 uint32_t vmhub) 157 { 158 return ((vmhub == AMDGPU_MMHUB_0) && 159 (!amdgpu_sriov_vf(adev))); 160 } 161 162 static bool gmc_v11_0_get_vmid_pasid_mapping_info( 163 struct amdgpu_device *adev, 164 uint8_t vmid, uint16_t *p_pasid) 165 { 166 *p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff; 167 168 return !!(*p_pasid); 169 } 170 171 /* 172 * GART 173 * VMID 0 is the physical GPU addresses as used by the kernel. 174 * VMIDs 1-15 are used for userspace clients and are handled 175 * by the amdgpu vm/hsa code. 176 */ 177 178 static void gmc_v11_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 179 unsigned int vmhub, uint32_t flush_type) 180 { 181 bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(adev, vmhub); 182 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 183 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 184 u32 tmp; 185 /* Use register 17 for GART */ 186 const unsigned eng = 17; 187 unsigned int i; 188 189 spin_lock(&adev->gmc.invalidate_lock); 190 /* 191 * It may lose gpuvm invalidate acknowldege state across power-gating 192 * off cycle, add semaphore acquire before invalidation and semaphore 193 * release after invalidation to avoid entering power gated state 194 * to WA the Issue 195 */ 196 197 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 198 if (use_semaphore) { 199 for (i = 0; i < adev->usec_timeout; i++) { 200 /* a read return value of 1 means semaphore acuqire */ 201 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + 202 hub->eng_distance * eng); 203 if (tmp & 0x1) 204 break; 205 udelay(1); 206 } 207 208 if (i >= adev->usec_timeout) 209 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 210 } 211 212 WREG32_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req); 213 214 /* Wait for ACK with a delay.*/ 215 for (i = 0; i < adev->usec_timeout; i++) { 216 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + 217 hub->eng_distance * eng); 218 tmp &= 1 << vmid; 219 if (tmp) 220 break; 221 222 udelay(1); 223 } 224 225 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 226 if (use_semaphore) 227 /* 228 * add semaphore release after invalidation, 229 * write with 0 means semaphore release 230 */ 231 WREG32_NO_KIQ(hub->vm_inv_eng0_sem + 232 hub->eng_distance * eng, 0); 233 234 /* Issue additional private vm invalidation to MMHUB */ 235 if ((vmhub != AMDGPU_GFXHUB_0) && 236 (hub->vm_l2_bank_select_reserved_cid2)) { 237 inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 238 /* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */ 239 inv_req |= (1 << 25); 240 /* Issue private invalidation */ 241 WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req); 242 /* Read back to ensure invalidation is done*/ 243 RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 244 } 245 246 spin_unlock(&adev->gmc.invalidate_lock); 247 248 if (i < adev->usec_timeout) 249 return; 250 251 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 252 } 253 254 /** 255 * gmc_v11_0_flush_gpu_tlb - gart tlb flush callback 256 * 257 * @adev: amdgpu_device pointer 258 * @vmid: vm instance to flush 259 * 260 * Flush the TLB for the requested page table. 261 */ 262 static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 263 uint32_t vmhub, uint32_t flush_type) 264 { 265 if ((vmhub == AMDGPU_GFXHUB_0) && !adev->gfx.is_poweron) 266 return; 267 268 /* flush hdp cache */ 269 adev->hdp.funcs->flush_hdp(adev, NULL); 270 271 /* For SRIOV run time, driver shouldn't access the register through MMIO 272 * Directly use kiq to do the vm invalidation instead 273 */ 274 if ((adev->gfx.kiq.ring.sched.ready || adev->mes.ring.sched.ready) && 275 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 276 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 277 const unsigned eng = 17; 278 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 279 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 280 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 281 282 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 283 1 << vmid); 284 return; 285 } 286 287 mutex_lock(&adev->mman.gtt_window_lock); 288 gmc_v11_0_flush_vm_hub(adev, vmid, vmhub, 0); 289 mutex_unlock(&adev->mman.gtt_window_lock); 290 return; 291 } 292 293 /** 294 * gmc_v11_0_flush_gpu_tlb_pasid - tlb flush via pasid 295 * 296 * @adev: amdgpu_device pointer 297 * @pasid: pasid to be flush 298 * 299 * Flush the TLB for the requested pasid. 300 */ 301 static int gmc_v11_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 302 uint16_t pasid, uint32_t flush_type, 303 bool all_hub) 304 { 305 int vmid, i; 306 signed long r; 307 uint32_t seq; 308 uint16_t queried_pasid; 309 bool ret; 310 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 311 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 312 313 if (amdgpu_emu_mode == 0 && ring->sched.ready) { 314 spin_lock(&adev->gfx.kiq.ring_lock); 315 /* 2 dwords flush + 8 dwords fence */ 316 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8); 317 kiq->pmf->kiq_invalidate_tlbs(ring, 318 pasid, flush_type, all_hub); 319 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 320 if (r) { 321 amdgpu_ring_undo(ring); 322 spin_unlock(&adev->gfx.kiq.ring_lock); 323 return -ETIME; 324 } 325 326 amdgpu_ring_commit(ring); 327 spin_unlock(&adev->gfx.kiq.ring_lock); 328 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); 329 if (r < 1) { 330 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r); 331 return -ETIME; 332 } 333 334 return 0; 335 } 336 337 for (vmid = 1; vmid < 16; vmid++) { 338 339 ret = gmc_v11_0_get_vmid_pasid_mapping_info(adev, vmid, 340 &queried_pasid); 341 if (ret && queried_pasid == pasid) { 342 if (all_hub) { 343 for (i = 0; i < adev->num_vmhubs; i++) 344 gmc_v11_0_flush_gpu_tlb(adev, vmid, 345 i, flush_type); 346 } else { 347 gmc_v11_0_flush_gpu_tlb(adev, vmid, 348 AMDGPU_GFXHUB_0, flush_type); 349 } 350 } 351 } 352 353 return 0; 354 } 355 356 static uint64_t gmc_v11_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 357 unsigned vmid, uint64_t pd_addr) 358 { 359 bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub); 360 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 361 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 362 unsigned eng = ring->vm_inv_eng; 363 364 /* 365 * It may lose gpuvm invalidate acknowldege state across power-gating 366 * off cycle, add semaphore acquire before invalidation and semaphore 367 * release after invalidation to avoid entering power gated state 368 * to WA the Issue 369 */ 370 371 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 372 if (use_semaphore) 373 /* a read return value of 1 means semaphore acuqire */ 374 amdgpu_ring_emit_reg_wait(ring, 375 hub->vm_inv_eng0_sem + 376 hub->eng_distance * eng, 0x1, 0x1); 377 378 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 379 (hub->ctx_addr_distance * vmid), 380 lower_32_bits(pd_addr)); 381 382 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 383 (hub->ctx_addr_distance * vmid), 384 upper_32_bits(pd_addr)); 385 386 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 387 hub->eng_distance * eng, 388 hub->vm_inv_eng0_ack + 389 hub->eng_distance * eng, 390 req, 1 << vmid); 391 392 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 393 if (use_semaphore) 394 /* 395 * add semaphore release after invalidation, 396 * write with 0 means semaphore release 397 */ 398 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 399 hub->eng_distance * eng, 0); 400 401 return pd_addr; 402 } 403 404 static void gmc_v11_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 405 unsigned pasid) 406 { 407 struct amdgpu_device *adev = ring->adev; 408 uint32_t reg; 409 410 /* MES fw manages IH_VMID_x_LUT updating */ 411 if (ring->is_mes_queue) 412 return; 413 414 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) 415 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid; 416 else 417 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid; 418 419 amdgpu_ring_emit_wreg(ring, reg, pasid); 420 } 421 422 /* 423 * PTE format: 424 * 63:59 reserved 425 * 58:57 reserved 426 * 56 F 427 * 55 L 428 * 54 reserved 429 * 53:52 SW 430 * 51 T 431 * 50:48 mtype 432 * 47:12 4k physical page base address 433 * 11:7 fragment 434 * 6 write 435 * 5 read 436 * 4 exe 437 * 3 Z 438 * 2 snooped 439 * 1 system 440 * 0 valid 441 * 442 * PDE format: 443 * 63:59 block fragment size 444 * 58:55 reserved 445 * 54 P 446 * 53:48 reserved 447 * 47:6 physical base address of PD or PTE 448 * 5:3 reserved 449 * 2 C 450 * 1 system 451 * 0 valid 452 */ 453 454 static uint64_t gmc_v11_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 455 { 456 switch (flags) { 457 case AMDGPU_VM_MTYPE_DEFAULT: 458 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 459 case AMDGPU_VM_MTYPE_NC: 460 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 461 case AMDGPU_VM_MTYPE_WC: 462 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC); 463 case AMDGPU_VM_MTYPE_CC: 464 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC); 465 case AMDGPU_VM_MTYPE_UC: 466 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 467 default: 468 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 469 } 470 } 471 472 static void gmc_v11_0_get_vm_pde(struct amdgpu_device *adev, int level, 473 uint64_t *addr, uint64_t *flags) 474 { 475 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 476 *addr = adev->vm_manager.vram_base_offset + *addr - 477 adev->gmc.vram_start; 478 BUG_ON(*addr & 0xFFFF00000000003FULL); 479 480 if (!adev->gmc.translate_further) 481 return; 482 483 if (level == AMDGPU_VM_PDB1) { 484 /* Set the block fragment size */ 485 if (!(*flags & AMDGPU_PDE_PTE)) 486 *flags |= AMDGPU_PDE_BFS(0x9); 487 488 } else if (level == AMDGPU_VM_PDB0) { 489 if (*flags & AMDGPU_PDE_PTE) 490 *flags &= ~AMDGPU_PDE_PTE; 491 else 492 *flags |= AMDGPU_PTE_TF; 493 } 494 } 495 496 static void gmc_v11_0_get_vm_pte(struct amdgpu_device *adev, 497 struct amdgpu_bo_va_mapping *mapping, 498 uint64_t *flags) 499 { 500 *flags &= ~AMDGPU_PTE_EXECUTABLE; 501 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 502 503 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; 504 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); 505 506 *flags &= ~AMDGPU_PTE_NOALLOC; 507 *flags |= (mapping->flags & AMDGPU_PTE_NOALLOC); 508 509 if (mapping->flags & AMDGPU_PTE_PRT) { 510 *flags |= AMDGPU_PTE_PRT; 511 *flags |= AMDGPU_PTE_SNOOPED; 512 *flags |= AMDGPU_PTE_LOG; 513 *flags |= AMDGPU_PTE_SYSTEM; 514 *flags &= ~AMDGPU_PTE_VALID; 515 } 516 } 517 518 static unsigned gmc_v11_0_get_vbios_fb_size(struct amdgpu_device *adev) 519 { 520 return 0; 521 } 522 523 static const struct amdgpu_gmc_funcs gmc_v11_0_gmc_funcs = { 524 .flush_gpu_tlb = gmc_v11_0_flush_gpu_tlb, 525 .flush_gpu_tlb_pasid = gmc_v11_0_flush_gpu_tlb_pasid, 526 .emit_flush_gpu_tlb = gmc_v11_0_emit_flush_gpu_tlb, 527 .emit_pasid_mapping = gmc_v11_0_emit_pasid_mapping, 528 .map_mtype = gmc_v11_0_map_mtype, 529 .get_vm_pde = gmc_v11_0_get_vm_pde, 530 .get_vm_pte = gmc_v11_0_get_vm_pte, 531 .get_vbios_fb_size = gmc_v11_0_get_vbios_fb_size, 532 }; 533 534 static void gmc_v11_0_set_gmc_funcs(struct amdgpu_device *adev) 535 { 536 adev->gmc.gmc_funcs = &gmc_v11_0_gmc_funcs; 537 } 538 539 static void gmc_v11_0_set_umc_funcs(struct amdgpu_device *adev) 540 { 541 switch (adev->ip_versions[UMC_HWIP][0]) { 542 case IP_VERSION(8, 10, 0): 543 adev->umc.channel_inst_num = UMC_V8_10_CHANNEL_INSTANCE_NUM; 544 adev->umc.umc_inst_num = UMC_V8_10_UMC_INSTANCE_NUM; 545 adev->umc.node_inst_num = adev->gmc.num_umc; 546 adev->umc.max_ras_err_cnt_per_query = UMC_V8_10_TOTAL_CHANNEL_NUM(adev); 547 adev->umc.channel_offs = UMC_V8_10_PER_CHANNEL_OFFSET; 548 adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl[0][0][0]; 549 adev->umc.ras = &umc_v8_10_ras; 550 break; 551 case IP_VERSION(8, 11, 0): 552 break; 553 default: 554 break; 555 } 556 557 if (adev->umc.ras) { 558 amdgpu_ras_register_ras_block(adev, &adev->umc.ras->ras_block); 559 560 strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc"); 561 adev->umc.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC; 562 adev->umc.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; 563 adev->umc.ras_if = &adev->umc.ras->ras_block.ras_comm; 564 565 /* If don't define special ras_late_init function, use default ras_late_init */ 566 if (!adev->umc.ras->ras_block.ras_late_init) 567 adev->umc.ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init; 568 569 /* If not define special ras_cb function, use default ras_cb */ 570 if (!adev->umc.ras->ras_block.ras_cb) 571 adev->umc.ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb; 572 } 573 } 574 575 576 static void gmc_v11_0_set_mmhub_funcs(struct amdgpu_device *adev) 577 { 578 switch (adev->ip_versions[MMHUB_HWIP][0]) { 579 case IP_VERSION(3, 0, 1): 580 adev->mmhub.funcs = &mmhub_v3_0_1_funcs; 581 break; 582 case IP_VERSION(3, 0, 2): 583 adev->mmhub.funcs = &mmhub_v3_0_2_funcs; 584 break; 585 default: 586 adev->mmhub.funcs = &mmhub_v3_0_funcs; 587 break; 588 } 589 } 590 591 static void gmc_v11_0_set_gfxhub_funcs(struct amdgpu_device *adev) 592 { 593 adev->gfxhub.funcs = &gfxhub_v3_0_funcs; 594 } 595 596 static int gmc_v11_0_early_init(void *handle) 597 { 598 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 599 600 gmc_v11_0_set_gfxhub_funcs(adev); 601 gmc_v11_0_set_mmhub_funcs(adev); 602 gmc_v11_0_set_gmc_funcs(adev); 603 gmc_v11_0_set_irq_funcs(adev); 604 gmc_v11_0_set_umc_funcs(adev); 605 606 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 607 adev->gmc.shared_aperture_end = 608 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 609 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 610 adev->gmc.private_aperture_end = 611 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 612 613 return 0; 614 } 615 616 static int gmc_v11_0_late_init(void *handle) 617 { 618 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 619 int r; 620 621 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 622 if (r) 623 return r; 624 625 r = amdgpu_gmc_ras_late_init(adev); 626 if (r) 627 return r; 628 629 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 630 } 631 632 static void gmc_v11_0_vram_gtt_location(struct amdgpu_device *adev, 633 struct amdgpu_gmc *mc) 634 { 635 u64 base = 0; 636 637 base = adev->mmhub.funcs->get_fb_location(adev); 638 639 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 640 amdgpu_gmc_gart_location(adev, mc); 641 642 /* base offset of vram pages */ 643 adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev); 644 } 645 646 /** 647 * gmc_v11_0_mc_init - initialize the memory controller driver params 648 * 649 * @adev: amdgpu_device pointer 650 * 651 * Look up the amount of vram, vram width, and decide how to place 652 * vram and gart within the GPU's physical address space. 653 * Returns 0 for success. 654 */ 655 static int gmc_v11_0_mc_init(struct amdgpu_device *adev) 656 { 657 int r; 658 659 /* size in MB on si */ 660 adev->gmc.mc_vram_size = 661 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 662 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 663 664 if (!(adev->flags & AMD_IS_APU)) { 665 r = amdgpu_device_resize_fb_bar(adev); 666 if (r) 667 return r; 668 } 669 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 670 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 671 672 #ifdef CONFIG_X86_64 673 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { 674 adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev); 675 adev->gmc.aper_size = adev->gmc.real_vram_size; 676 } 677 #endif 678 /* In case the PCI BAR is larger than the actual amount of vram */ 679 adev->gmc.visible_vram_size = adev->gmc.aper_size; 680 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 681 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 682 683 /* set the gart size */ 684 if (amdgpu_gart_size == -1) { 685 adev->gmc.gart_size = 512ULL << 20; 686 } else 687 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 688 689 gmc_v11_0_vram_gtt_location(adev, &adev->gmc); 690 691 return 0; 692 } 693 694 static int gmc_v11_0_gart_init(struct amdgpu_device *adev) 695 { 696 int r; 697 698 if (adev->gart.bo) { 699 WARN(1, "PCIE GART already initialized\n"); 700 return 0; 701 } 702 703 /* Initialize common gart structure */ 704 r = amdgpu_gart_init(adev); 705 if (r) 706 return r; 707 708 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 709 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) | 710 AMDGPU_PTE_EXECUTABLE; 711 712 return amdgpu_gart_table_vram_alloc(adev); 713 } 714 715 static int gmc_v11_0_sw_init(void *handle) 716 { 717 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 718 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 719 720 adev->mmhub.funcs->init(adev); 721 722 spin_lock_init(&adev->gmc.invalidate_lock); 723 724 r = amdgpu_atomfirmware_get_vram_info(adev, 725 &vram_width, &vram_type, &vram_vendor); 726 adev->gmc.vram_width = vram_width; 727 728 adev->gmc.vram_type = vram_type; 729 adev->gmc.vram_vendor = vram_vendor; 730 731 switch (adev->ip_versions[GC_HWIP][0]) { 732 case IP_VERSION(11, 0, 0): 733 case IP_VERSION(11, 0, 1): 734 case IP_VERSION(11, 0, 2): 735 adev->num_vmhubs = 2; 736 /* 737 * To fulfill 4-level page support, 738 * vm size is 256TB (48bit), maximum size, 739 * block size 512 (9bit) 740 */ 741 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 742 break; 743 default: 744 break; 745 } 746 747 /* This interrupt is VMC page fault.*/ 748 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_VMC, 749 VMC_1_0__SRCID__VM_FAULT, 750 &adev->gmc.vm_fault); 751 752 if (r) 753 return r; 754 755 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 756 UTCL2_1_0__SRCID__FAULT, 757 &adev->gmc.vm_fault); 758 if (r) 759 return r; 760 761 if (!amdgpu_sriov_vf(adev)) { 762 /* interrupt sent to DF. */ 763 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_DF, 0, 764 &adev->gmc.ecc_irq); 765 if (r) 766 return r; 767 } 768 769 /* 770 * Set the internal MC address mask This is the max address of the GPU's 771 * internal address space. 772 */ 773 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 774 775 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 776 if (r) { 777 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 778 return r; 779 } 780 781 adev->need_swiotlb = drm_need_swiotlb(44); 782 783 r = gmc_v11_0_mc_init(adev); 784 if (r) 785 return r; 786 787 amdgpu_gmc_get_vbios_allocations(adev); 788 789 /* Memory manager */ 790 r = amdgpu_bo_init(adev); 791 if (r) 792 return r; 793 794 r = gmc_v11_0_gart_init(adev); 795 if (r) 796 return r; 797 798 /* 799 * number of VMs 800 * VMID 0 is reserved for System 801 * amdgpu graphics/compute will use VMIDs 1-7 802 * amdkfd will use VMIDs 8-15 803 */ 804 adev->vm_manager.first_kfd_vmid = 8; 805 806 amdgpu_vm_manager_init(adev); 807 808 return 0; 809 } 810 811 /** 812 * gmc_v11_0_gart_fini - vm fini callback 813 * 814 * @adev: amdgpu_device pointer 815 * 816 * Tears down the driver GART/VM setup (CIK). 817 */ 818 static void gmc_v11_0_gart_fini(struct amdgpu_device *adev) 819 { 820 amdgpu_gart_table_vram_free(adev); 821 } 822 823 static int gmc_v11_0_sw_fini(void *handle) 824 { 825 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 826 827 amdgpu_vm_manager_fini(adev); 828 gmc_v11_0_gart_fini(adev); 829 amdgpu_gem_force_release(adev); 830 amdgpu_bo_fini(adev); 831 832 return 0; 833 } 834 835 static void gmc_v11_0_init_golden_registers(struct amdgpu_device *adev) 836 { 837 } 838 839 /** 840 * gmc_v11_0_gart_enable - gart enable 841 * 842 * @adev: amdgpu_device pointer 843 */ 844 static int gmc_v11_0_gart_enable(struct amdgpu_device *adev) 845 { 846 int r; 847 bool value; 848 849 if (adev->gart.bo == NULL) { 850 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 851 return -EINVAL; 852 } 853 854 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 855 856 r = adev->mmhub.funcs->gart_enable(adev); 857 if (r) 858 return r; 859 860 /* Flush HDP after it is initialized */ 861 adev->hdp.funcs->flush_hdp(adev, NULL); 862 863 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 864 false : true; 865 866 adev->mmhub.funcs->set_fault_enable_default(adev, value); 867 gmc_v11_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0); 868 869 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 870 (unsigned)(adev->gmc.gart_size >> 20), 871 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 872 873 return 0; 874 } 875 876 static int gmc_v11_0_hw_init(void *handle) 877 { 878 int r; 879 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 880 881 /* The sequence of these two function calls matters.*/ 882 gmc_v11_0_init_golden_registers(adev); 883 884 r = gmc_v11_0_gart_enable(adev); 885 if (r) 886 return r; 887 888 if (adev->umc.funcs && adev->umc.funcs->init_registers) 889 adev->umc.funcs->init_registers(adev); 890 891 return 0; 892 } 893 894 /** 895 * gmc_v11_0_gart_disable - gart disable 896 * 897 * @adev: amdgpu_device pointer 898 * 899 * This disables all VM page table. 900 */ 901 static void gmc_v11_0_gart_disable(struct amdgpu_device *adev) 902 { 903 adev->mmhub.funcs->gart_disable(adev); 904 } 905 906 static int gmc_v11_0_hw_fini(void *handle) 907 { 908 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 909 910 if (amdgpu_sriov_vf(adev)) { 911 /* full access mode, so don't touch any GMC register */ 912 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 913 return 0; 914 } 915 916 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 917 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 918 gmc_v11_0_gart_disable(adev); 919 920 return 0; 921 } 922 923 static int gmc_v11_0_suspend(void *handle) 924 { 925 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 926 927 gmc_v11_0_hw_fini(adev); 928 929 return 0; 930 } 931 932 static int gmc_v11_0_resume(void *handle) 933 { 934 int r; 935 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 936 937 r = gmc_v11_0_hw_init(adev); 938 if (r) 939 return r; 940 941 amdgpu_vmid_reset_all(adev); 942 943 return 0; 944 } 945 946 static bool gmc_v11_0_is_idle(void *handle) 947 { 948 /* MC is always ready in GMC v11.*/ 949 return true; 950 } 951 952 static int gmc_v11_0_wait_for_idle(void *handle) 953 { 954 /* There is no need to wait for MC idle in GMC v11.*/ 955 return 0; 956 } 957 958 static int gmc_v11_0_soft_reset(void *handle) 959 { 960 return 0; 961 } 962 963 static int gmc_v11_0_set_clockgating_state(void *handle, 964 enum amd_clockgating_state state) 965 { 966 int r; 967 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 968 969 r = adev->mmhub.funcs->set_clockgating(adev, state); 970 if (r) 971 return r; 972 973 return athub_v3_0_set_clockgating(adev, state); 974 } 975 976 static void gmc_v11_0_get_clockgating_state(void *handle, u64 *flags) 977 { 978 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 979 980 adev->mmhub.funcs->get_clockgating(adev, flags); 981 982 athub_v3_0_get_clockgating(adev, flags); 983 } 984 985 static int gmc_v11_0_set_powergating_state(void *handle, 986 enum amd_powergating_state state) 987 { 988 return 0; 989 } 990 991 const struct amd_ip_funcs gmc_v11_0_ip_funcs = { 992 .name = "gmc_v11_0", 993 .early_init = gmc_v11_0_early_init, 994 .sw_init = gmc_v11_0_sw_init, 995 .hw_init = gmc_v11_0_hw_init, 996 .late_init = gmc_v11_0_late_init, 997 .sw_fini = gmc_v11_0_sw_fini, 998 .hw_fini = gmc_v11_0_hw_fini, 999 .suspend = gmc_v11_0_suspend, 1000 .resume = gmc_v11_0_resume, 1001 .is_idle = gmc_v11_0_is_idle, 1002 .wait_for_idle = gmc_v11_0_wait_for_idle, 1003 .soft_reset = gmc_v11_0_soft_reset, 1004 .set_clockgating_state = gmc_v11_0_set_clockgating_state, 1005 .set_powergating_state = gmc_v11_0_set_powergating_state, 1006 .get_clockgating_state = gmc_v11_0_get_clockgating_state, 1007 }; 1008 1009 const struct amdgpu_ip_block_version gmc_v11_0_ip_block = { 1010 .type = AMD_IP_BLOCK_TYPE_GMC, 1011 .major = 11, 1012 .minor = 0, 1013 .rev = 0, 1014 .funcs = &gmc_v11_0_ip_funcs, 1015 }; 1016