1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 #include "amdgpu.h" 26 #include "amdgpu_atomfirmware.h" 27 #include "gmc_v11_0.h" 28 #include "umc_v8_7.h" 29 #include "athub/athub_3_0_0_sh_mask.h" 30 #include "athub/athub_3_0_0_offset.h" 31 #include "oss/osssys_6_0_0_offset.h" 32 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 33 #include "navi10_enum.h" 34 #include "soc15.h" 35 #include "soc15d.h" 36 #include "soc15_common.h" 37 #include "nbio_v4_3.h" 38 #include "gfxhub_v3_0.h" 39 #include "mmhub_v3_0.h" 40 #include "mmhub_v3_0_1.h" 41 #include "mmhub_v3_0_2.h" 42 #include "athub_v3_0.h" 43 44 45 static int gmc_v11_0_ecc_interrupt_state(struct amdgpu_device *adev, 46 struct amdgpu_irq_src *src, 47 unsigned type, 48 enum amdgpu_interrupt_state state) 49 { 50 return 0; 51 } 52 53 static int 54 gmc_v11_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 55 struct amdgpu_irq_src *src, unsigned type, 56 enum amdgpu_interrupt_state state) 57 { 58 switch (state) { 59 case AMDGPU_IRQ_STATE_DISABLE: 60 /* MM HUB */ 61 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false); 62 /* GFX HUB */ 63 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false); 64 break; 65 case AMDGPU_IRQ_STATE_ENABLE: 66 /* MM HUB */ 67 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true); 68 /* GFX HUB */ 69 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true); 70 break; 71 default: 72 break; 73 } 74 75 return 0; 76 } 77 78 static int gmc_v11_0_process_interrupt(struct amdgpu_device *adev, 79 struct amdgpu_irq_src *source, 80 struct amdgpu_iv_entry *entry) 81 { 82 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; 83 uint32_t status = 0; 84 u64 addr; 85 86 addr = (u64)entry->src_data[0] << 12; 87 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 88 89 if (!amdgpu_sriov_vf(adev)) { 90 /* 91 * Issue a dummy read to wait for the status register to 92 * be updated to avoid reading an incorrect value due to 93 * the new fast GRBM interface. 94 */ 95 if (entry->vmid_src == AMDGPU_GFXHUB_0) 96 RREG32(hub->vm_l2_pro_fault_status); 97 98 status = RREG32(hub->vm_l2_pro_fault_status); 99 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 100 } 101 102 if (printk_ratelimit()) { 103 struct amdgpu_task_info task_info; 104 105 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 106 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 107 108 dev_err(adev->dev, 109 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, " 110 "for process %s pid %d thread %s pid %d)\n", 111 entry->vmid_src ? "mmhub" : "gfxhub", 112 entry->src_id, entry->ring_id, entry->vmid, 113 entry->pasid, task_info.process_name, task_info.tgid, 114 task_info.task_name, task_info.pid); 115 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", 116 addr, entry->client_id); 117 if (!amdgpu_sriov_vf(adev)) 118 hub->vmhub_funcs->print_l2_protection_fault_status(adev, status); 119 } 120 121 return 0; 122 } 123 124 static const struct amdgpu_irq_src_funcs gmc_v11_0_irq_funcs = { 125 .set = gmc_v11_0_vm_fault_interrupt_state, 126 .process = gmc_v11_0_process_interrupt, 127 }; 128 129 static const struct amdgpu_irq_src_funcs gmc_v11_0_ecc_funcs = { 130 .set = gmc_v11_0_ecc_interrupt_state, 131 .process = amdgpu_umc_process_ecc_irq, 132 }; 133 134 static void gmc_v11_0_set_irq_funcs(struct amdgpu_device *adev) 135 { 136 adev->gmc.vm_fault.num_types = 1; 137 adev->gmc.vm_fault.funcs = &gmc_v11_0_irq_funcs; 138 139 if (!amdgpu_sriov_vf(adev)) { 140 adev->gmc.ecc_irq.num_types = 1; 141 adev->gmc.ecc_irq.funcs = &gmc_v11_0_ecc_funcs; 142 } 143 } 144 145 /** 146 * gmc_v11_0_use_invalidate_semaphore - judge whether to use semaphore 147 * 148 * @adev: amdgpu_device pointer 149 * @vmhub: vmhub type 150 * 151 */ 152 static bool gmc_v11_0_use_invalidate_semaphore(struct amdgpu_device *adev, 153 uint32_t vmhub) 154 { 155 return ((vmhub == AMDGPU_MMHUB_0) && 156 (!amdgpu_sriov_vf(adev))); 157 } 158 159 static bool gmc_v11_0_get_vmid_pasid_mapping_info( 160 struct amdgpu_device *adev, 161 uint8_t vmid, uint16_t *p_pasid) 162 { 163 *p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff; 164 165 return !!(*p_pasid); 166 } 167 168 /* 169 * GART 170 * VMID 0 is the physical GPU addresses as used by the kernel. 171 * VMIDs 1-15 are used for userspace clients and are handled 172 * by the amdgpu vm/hsa code. 173 */ 174 175 static void gmc_v11_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 176 unsigned int vmhub, uint32_t flush_type) 177 { 178 bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(adev, vmhub); 179 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 180 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 181 u32 tmp; 182 /* Use register 17 for GART */ 183 const unsigned eng = 17; 184 unsigned int i; 185 186 spin_lock(&adev->gmc.invalidate_lock); 187 /* 188 * It may lose gpuvm invalidate acknowldege state across power-gating 189 * off cycle, add semaphore acquire before invalidation and semaphore 190 * release after invalidation to avoid entering power gated state 191 * to WA the Issue 192 */ 193 194 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 195 if (use_semaphore) { 196 for (i = 0; i < adev->usec_timeout; i++) { 197 /* a read return value of 1 means semaphore acuqire */ 198 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + 199 hub->eng_distance * eng); 200 if (tmp & 0x1) 201 break; 202 udelay(1); 203 } 204 205 if (i >= adev->usec_timeout) 206 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 207 } 208 209 WREG32_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req); 210 211 /* Wait for ACK with a delay.*/ 212 for (i = 0; i < adev->usec_timeout; i++) { 213 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + 214 hub->eng_distance * eng); 215 tmp &= 1 << vmid; 216 if (tmp) 217 break; 218 219 udelay(1); 220 } 221 222 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 223 if (use_semaphore) 224 /* 225 * add semaphore release after invalidation, 226 * write with 0 means semaphore release 227 */ 228 WREG32_NO_KIQ(hub->vm_inv_eng0_sem + 229 hub->eng_distance * eng, 0); 230 231 /* Issue additional private vm invalidation to MMHUB */ 232 if ((vmhub != AMDGPU_GFXHUB_0) && 233 (hub->vm_l2_bank_select_reserved_cid2)) { 234 inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 235 /* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */ 236 inv_req |= (1 << 25); 237 /* Issue private invalidation */ 238 WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req); 239 /* Read back to ensure invalidation is done*/ 240 RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 241 } 242 243 spin_unlock(&adev->gmc.invalidate_lock); 244 245 if (i < adev->usec_timeout) 246 return; 247 248 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 249 } 250 251 /** 252 * gmc_v11_0_flush_gpu_tlb - gart tlb flush callback 253 * 254 * @adev: amdgpu_device pointer 255 * @vmid: vm instance to flush 256 * 257 * Flush the TLB for the requested page table. 258 */ 259 static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 260 uint32_t vmhub, uint32_t flush_type) 261 { 262 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 263 struct dma_fence *fence; 264 struct amdgpu_job *job; 265 266 int r; 267 268 if ((vmhub == AMDGPU_GFXHUB_0) && !adev->gfx.is_poweron) 269 return; 270 271 /* flush hdp cache */ 272 adev->hdp.funcs->flush_hdp(adev, NULL); 273 274 /* For SRIOV run time, driver shouldn't access the register through MMIO 275 * Directly use kiq to do the vm invalidation instead 276 */ 277 if (adev->gfx.kiq.ring.sched.ready && !adev->enable_mes && 278 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 279 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 280 const unsigned eng = 17; 281 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 282 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 283 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 284 285 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 286 1 << vmid); 287 return; 288 } 289 290 mutex_lock(&adev->mman.gtt_window_lock); 291 292 if (vmhub == AMDGPU_MMHUB_0) { 293 gmc_v11_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0); 294 mutex_unlock(&adev->mman.gtt_window_lock); 295 return; 296 } 297 298 BUG_ON(vmhub != AMDGPU_GFXHUB_0); 299 300 if (!adev->mman.buffer_funcs_enabled || 301 !adev->ib_pool_ready || 302 amdgpu_in_reset(adev) || 303 ring->sched.ready == false) { 304 gmc_v11_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0); 305 mutex_unlock(&adev->mman.gtt_window_lock); 306 return; 307 } 308 309 r = amdgpu_job_alloc_with_ib(adev, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE, 310 &job); 311 if (r) 312 goto error_alloc; 313 314 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); 315 job->vm_needs_flush = true; 316 job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop; 317 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 318 r = amdgpu_job_submit(job, &adev->mman.entity, 319 AMDGPU_FENCE_OWNER_UNDEFINED, &fence); 320 if (r) 321 goto error_submit; 322 323 mutex_unlock(&adev->mman.gtt_window_lock); 324 325 dma_fence_wait(fence, false); 326 dma_fence_put(fence); 327 328 return; 329 330 error_submit: 331 amdgpu_job_free(job); 332 333 error_alloc: 334 mutex_unlock(&adev->mman.gtt_window_lock); 335 DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r); 336 return; 337 } 338 339 /** 340 * gmc_v11_0_flush_gpu_tlb_pasid - tlb flush via pasid 341 * 342 * @adev: amdgpu_device pointer 343 * @pasid: pasid to be flush 344 * 345 * Flush the TLB for the requested pasid. 346 */ 347 static int gmc_v11_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 348 uint16_t pasid, uint32_t flush_type, 349 bool all_hub) 350 { 351 int vmid, i; 352 signed long r; 353 uint32_t seq; 354 uint16_t queried_pasid; 355 bool ret; 356 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 357 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 358 359 if (amdgpu_emu_mode == 0 && ring->sched.ready) { 360 spin_lock(&adev->gfx.kiq.ring_lock); 361 /* 2 dwords flush + 8 dwords fence */ 362 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8); 363 kiq->pmf->kiq_invalidate_tlbs(ring, 364 pasid, flush_type, all_hub); 365 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 366 if (r) { 367 amdgpu_ring_undo(ring); 368 spin_unlock(&adev->gfx.kiq.ring_lock); 369 return -ETIME; 370 } 371 372 amdgpu_ring_commit(ring); 373 spin_unlock(&adev->gfx.kiq.ring_lock); 374 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); 375 if (r < 1) { 376 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r); 377 return -ETIME; 378 } 379 380 return 0; 381 } 382 383 for (vmid = 1; vmid < 16; vmid++) { 384 385 ret = gmc_v11_0_get_vmid_pasid_mapping_info(adev, vmid, 386 &queried_pasid); 387 if (ret && queried_pasid == pasid) { 388 if (all_hub) { 389 for (i = 0; i < adev->num_vmhubs; i++) 390 gmc_v11_0_flush_gpu_tlb(adev, vmid, 391 i, flush_type); 392 } else { 393 gmc_v11_0_flush_gpu_tlb(adev, vmid, 394 AMDGPU_GFXHUB_0, flush_type); 395 } 396 } 397 } 398 399 return 0; 400 } 401 402 static uint64_t gmc_v11_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 403 unsigned vmid, uint64_t pd_addr) 404 { 405 bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub); 406 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 407 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 408 unsigned eng = ring->vm_inv_eng; 409 410 /* 411 * It may lose gpuvm invalidate acknowldege state across power-gating 412 * off cycle, add semaphore acquire before invalidation and semaphore 413 * release after invalidation to avoid entering power gated state 414 * to WA the Issue 415 */ 416 417 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 418 if (use_semaphore) 419 /* a read return value of 1 means semaphore acuqire */ 420 amdgpu_ring_emit_reg_wait(ring, 421 hub->vm_inv_eng0_sem + 422 hub->eng_distance * eng, 0x1, 0x1); 423 424 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 425 (hub->ctx_addr_distance * vmid), 426 lower_32_bits(pd_addr)); 427 428 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 429 (hub->ctx_addr_distance * vmid), 430 upper_32_bits(pd_addr)); 431 432 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 433 hub->eng_distance * eng, 434 hub->vm_inv_eng0_ack + 435 hub->eng_distance * eng, 436 req, 1 << vmid); 437 438 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 439 if (use_semaphore) 440 /* 441 * add semaphore release after invalidation, 442 * write with 0 means semaphore release 443 */ 444 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 445 hub->eng_distance * eng, 0); 446 447 return pd_addr; 448 } 449 450 static void gmc_v11_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 451 unsigned pasid) 452 { 453 struct amdgpu_device *adev = ring->adev; 454 uint32_t reg; 455 456 /* MES fw manages IH_VMID_x_LUT updating */ 457 if (ring->is_mes_queue) 458 return; 459 460 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) 461 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid; 462 else 463 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid; 464 465 amdgpu_ring_emit_wreg(ring, reg, pasid); 466 } 467 468 /* 469 * PTE format: 470 * 63:59 reserved 471 * 58:57 reserved 472 * 56 F 473 * 55 L 474 * 54 reserved 475 * 53:52 SW 476 * 51 T 477 * 50:48 mtype 478 * 47:12 4k physical page base address 479 * 11:7 fragment 480 * 6 write 481 * 5 read 482 * 4 exe 483 * 3 Z 484 * 2 snooped 485 * 1 system 486 * 0 valid 487 * 488 * PDE format: 489 * 63:59 block fragment size 490 * 58:55 reserved 491 * 54 P 492 * 53:48 reserved 493 * 47:6 physical base address of PD or PTE 494 * 5:3 reserved 495 * 2 C 496 * 1 system 497 * 0 valid 498 */ 499 500 static uint64_t gmc_v11_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 501 { 502 switch (flags) { 503 case AMDGPU_VM_MTYPE_DEFAULT: 504 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 505 case AMDGPU_VM_MTYPE_NC: 506 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 507 case AMDGPU_VM_MTYPE_WC: 508 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC); 509 case AMDGPU_VM_MTYPE_CC: 510 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC); 511 case AMDGPU_VM_MTYPE_UC: 512 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 513 default: 514 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 515 } 516 } 517 518 static void gmc_v11_0_get_vm_pde(struct amdgpu_device *adev, int level, 519 uint64_t *addr, uint64_t *flags) 520 { 521 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 522 *addr = adev->vm_manager.vram_base_offset + *addr - 523 adev->gmc.vram_start; 524 BUG_ON(*addr & 0xFFFF00000000003FULL); 525 526 if (!adev->gmc.translate_further) 527 return; 528 529 if (level == AMDGPU_VM_PDB1) { 530 /* Set the block fragment size */ 531 if (!(*flags & AMDGPU_PDE_PTE)) 532 *flags |= AMDGPU_PDE_BFS(0x9); 533 534 } else if (level == AMDGPU_VM_PDB0) { 535 if (*flags & AMDGPU_PDE_PTE) 536 *flags &= ~AMDGPU_PDE_PTE; 537 else 538 *flags |= AMDGPU_PTE_TF; 539 } 540 } 541 542 static void gmc_v11_0_get_vm_pte(struct amdgpu_device *adev, 543 struct amdgpu_bo_va_mapping *mapping, 544 uint64_t *flags) 545 { 546 *flags &= ~AMDGPU_PTE_EXECUTABLE; 547 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 548 549 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; 550 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); 551 552 *flags &= ~AMDGPU_PTE_NOALLOC; 553 *flags |= (mapping->flags & AMDGPU_PTE_NOALLOC); 554 555 if (mapping->flags & AMDGPU_PTE_PRT) { 556 *flags |= AMDGPU_PTE_PRT; 557 *flags |= AMDGPU_PTE_SNOOPED; 558 *flags |= AMDGPU_PTE_LOG; 559 *flags |= AMDGPU_PTE_SYSTEM; 560 *flags &= ~AMDGPU_PTE_VALID; 561 } 562 } 563 564 static unsigned gmc_v11_0_get_vbios_fb_size(struct amdgpu_device *adev) 565 { 566 return 0; 567 } 568 569 static const struct amdgpu_gmc_funcs gmc_v11_0_gmc_funcs = { 570 .flush_gpu_tlb = gmc_v11_0_flush_gpu_tlb, 571 .flush_gpu_tlb_pasid = gmc_v11_0_flush_gpu_tlb_pasid, 572 .emit_flush_gpu_tlb = gmc_v11_0_emit_flush_gpu_tlb, 573 .emit_pasid_mapping = gmc_v11_0_emit_pasid_mapping, 574 .map_mtype = gmc_v11_0_map_mtype, 575 .get_vm_pde = gmc_v11_0_get_vm_pde, 576 .get_vm_pte = gmc_v11_0_get_vm_pte, 577 .get_vbios_fb_size = gmc_v11_0_get_vbios_fb_size, 578 }; 579 580 static void gmc_v11_0_set_gmc_funcs(struct amdgpu_device *adev) 581 { 582 adev->gmc.gmc_funcs = &gmc_v11_0_gmc_funcs; 583 } 584 585 static void gmc_v11_0_set_umc_funcs(struct amdgpu_device *adev) 586 { 587 switch (adev->ip_versions[UMC_HWIP][0]) { 588 case IP_VERSION(8, 10, 0): 589 case IP_VERSION(8, 11, 0): 590 break; 591 default: 592 break; 593 } 594 } 595 596 597 static void gmc_v11_0_set_mmhub_funcs(struct amdgpu_device *adev) 598 { 599 switch (adev->ip_versions[MMHUB_HWIP][0]) { 600 case IP_VERSION(3, 0, 1): 601 adev->mmhub.funcs = &mmhub_v3_0_1_funcs; 602 break; 603 case IP_VERSION(3, 0, 2): 604 adev->mmhub.funcs = &mmhub_v3_0_2_funcs; 605 break; 606 default: 607 adev->mmhub.funcs = &mmhub_v3_0_funcs; 608 break; 609 } 610 } 611 612 static void gmc_v11_0_set_gfxhub_funcs(struct amdgpu_device *adev) 613 { 614 adev->gfxhub.funcs = &gfxhub_v3_0_funcs; 615 } 616 617 static int gmc_v11_0_early_init(void *handle) 618 { 619 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 620 621 gmc_v11_0_set_gfxhub_funcs(adev); 622 gmc_v11_0_set_mmhub_funcs(adev); 623 gmc_v11_0_set_gmc_funcs(adev); 624 gmc_v11_0_set_irq_funcs(adev); 625 gmc_v11_0_set_umc_funcs(adev); 626 627 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 628 adev->gmc.shared_aperture_end = 629 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 630 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 631 adev->gmc.private_aperture_end = 632 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 633 634 return 0; 635 } 636 637 static int gmc_v11_0_late_init(void *handle) 638 { 639 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 640 int r; 641 642 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 643 if (r) 644 return r; 645 646 r = amdgpu_gmc_ras_late_init(adev); 647 if (r) 648 return r; 649 650 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 651 } 652 653 static void gmc_v11_0_vram_gtt_location(struct amdgpu_device *adev, 654 struct amdgpu_gmc *mc) 655 { 656 u64 base = 0; 657 658 base = adev->mmhub.funcs->get_fb_location(adev); 659 660 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 661 amdgpu_gmc_gart_location(adev, mc); 662 663 /* base offset of vram pages */ 664 adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev); 665 } 666 667 /** 668 * gmc_v11_0_mc_init - initialize the memory controller driver params 669 * 670 * @adev: amdgpu_device pointer 671 * 672 * Look up the amount of vram, vram width, and decide how to place 673 * vram and gart within the GPU's physical address space. 674 * Returns 0 for success. 675 */ 676 static int gmc_v11_0_mc_init(struct amdgpu_device *adev) 677 { 678 int r; 679 680 /* size in MB on si */ 681 adev->gmc.mc_vram_size = 682 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 683 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 684 685 if (!(adev->flags & AMD_IS_APU)) { 686 r = amdgpu_device_resize_fb_bar(adev); 687 if (r) 688 return r; 689 } 690 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 691 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 692 693 #ifdef CONFIG_X86_64 694 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { 695 adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev); 696 adev->gmc.aper_size = adev->gmc.real_vram_size; 697 } 698 #endif 699 /* In case the PCI BAR is larger than the actual amount of vram */ 700 adev->gmc.visible_vram_size = adev->gmc.aper_size; 701 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 702 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 703 704 /* set the gart size */ 705 if (amdgpu_gart_size == -1) { 706 adev->gmc.gart_size = 512ULL << 20; 707 } else 708 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 709 710 gmc_v11_0_vram_gtt_location(adev, &adev->gmc); 711 712 return 0; 713 } 714 715 static int gmc_v11_0_gart_init(struct amdgpu_device *adev) 716 { 717 int r; 718 719 if (adev->gart.bo) { 720 WARN(1, "PCIE GART already initialized\n"); 721 return 0; 722 } 723 724 /* Initialize common gart structure */ 725 r = amdgpu_gart_init(adev); 726 if (r) 727 return r; 728 729 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 730 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) | 731 AMDGPU_PTE_EXECUTABLE; 732 733 return amdgpu_gart_table_vram_alloc(adev); 734 } 735 736 static int gmc_v11_0_sw_init(void *handle) 737 { 738 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 739 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 740 741 adev->mmhub.funcs->init(adev); 742 743 spin_lock_init(&adev->gmc.invalidate_lock); 744 745 r = amdgpu_atomfirmware_get_vram_info(adev, 746 &vram_width, &vram_type, &vram_vendor); 747 adev->gmc.vram_width = vram_width; 748 749 adev->gmc.vram_type = vram_type; 750 adev->gmc.vram_vendor = vram_vendor; 751 752 switch (adev->ip_versions[GC_HWIP][0]) { 753 case IP_VERSION(11, 0, 0): 754 case IP_VERSION(11, 0, 1): 755 case IP_VERSION(11, 0, 2): 756 adev->num_vmhubs = 2; 757 /* 758 * To fulfill 4-level page support, 759 * vm size is 256TB (48bit), maximum size, 760 * block size 512 (9bit) 761 */ 762 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 763 break; 764 default: 765 break; 766 } 767 768 /* This interrupt is VMC page fault.*/ 769 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_VMC, 770 VMC_1_0__SRCID__VM_FAULT, 771 &adev->gmc.vm_fault); 772 773 if (r) 774 return r; 775 776 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 777 UTCL2_1_0__SRCID__FAULT, 778 &adev->gmc.vm_fault); 779 if (r) 780 return r; 781 782 if (!amdgpu_sriov_vf(adev)) { 783 /* interrupt sent to DF. */ 784 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_DF, 0, 785 &adev->gmc.ecc_irq); 786 if (r) 787 return r; 788 } 789 790 /* 791 * Set the internal MC address mask This is the max address of the GPU's 792 * internal address space. 793 */ 794 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 795 796 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 797 if (r) { 798 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 799 return r; 800 } 801 802 r = gmc_v11_0_mc_init(adev); 803 if (r) 804 return r; 805 806 amdgpu_gmc_get_vbios_allocations(adev); 807 808 /* Memory manager */ 809 r = amdgpu_bo_init(adev); 810 if (r) 811 return r; 812 813 r = gmc_v11_0_gart_init(adev); 814 if (r) 815 return r; 816 817 /* 818 * number of VMs 819 * VMID 0 is reserved for System 820 * amdgpu graphics/compute will use VMIDs 1-7 821 * amdkfd will use VMIDs 8-15 822 */ 823 adev->vm_manager.first_kfd_vmid = 8; 824 825 amdgpu_vm_manager_init(adev); 826 827 return 0; 828 } 829 830 /** 831 * gmc_v11_0_gart_fini - vm fini callback 832 * 833 * @adev: amdgpu_device pointer 834 * 835 * Tears down the driver GART/VM setup (CIK). 836 */ 837 static void gmc_v11_0_gart_fini(struct amdgpu_device *adev) 838 { 839 amdgpu_gart_table_vram_free(adev); 840 } 841 842 static int gmc_v11_0_sw_fini(void *handle) 843 { 844 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 845 846 amdgpu_vm_manager_fini(adev); 847 gmc_v11_0_gart_fini(adev); 848 amdgpu_gem_force_release(adev); 849 amdgpu_bo_fini(adev); 850 851 return 0; 852 } 853 854 static void gmc_v11_0_init_golden_registers(struct amdgpu_device *adev) 855 { 856 } 857 858 /** 859 * gmc_v11_0_gart_enable - gart enable 860 * 861 * @adev: amdgpu_device pointer 862 */ 863 static int gmc_v11_0_gart_enable(struct amdgpu_device *adev) 864 { 865 int r; 866 bool value; 867 868 if (adev->gart.bo == NULL) { 869 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 870 return -EINVAL; 871 } 872 873 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 874 875 r = adev->mmhub.funcs->gart_enable(adev); 876 if (r) 877 return r; 878 879 /* Flush HDP after it is initialized */ 880 adev->hdp.funcs->flush_hdp(adev, NULL); 881 882 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 883 false : true; 884 885 adev->mmhub.funcs->set_fault_enable_default(adev, value); 886 gmc_v11_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0); 887 888 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 889 (unsigned)(adev->gmc.gart_size >> 20), 890 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 891 892 return 0; 893 } 894 895 static int gmc_v11_0_hw_init(void *handle) 896 { 897 int r; 898 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 899 900 /* The sequence of these two function calls matters.*/ 901 gmc_v11_0_init_golden_registers(adev); 902 903 r = gmc_v11_0_gart_enable(adev); 904 if (r) 905 return r; 906 907 if (adev->umc.funcs && adev->umc.funcs->init_registers) 908 adev->umc.funcs->init_registers(adev); 909 910 return 0; 911 } 912 913 /** 914 * gmc_v11_0_gart_disable - gart disable 915 * 916 * @adev: amdgpu_device pointer 917 * 918 * This disables all VM page table. 919 */ 920 static void gmc_v11_0_gart_disable(struct amdgpu_device *adev) 921 { 922 adev->mmhub.funcs->gart_disable(adev); 923 } 924 925 static int gmc_v11_0_hw_fini(void *handle) 926 { 927 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 928 929 if (amdgpu_sriov_vf(adev)) { 930 /* full access mode, so don't touch any GMC register */ 931 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 932 return 0; 933 } 934 935 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 936 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 937 gmc_v11_0_gart_disable(adev); 938 939 return 0; 940 } 941 942 static int gmc_v11_0_suspend(void *handle) 943 { 944 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 945 946 gmc_v11_0_hw_fini(adev); 947 948 return 0; 949 } 950 951 static int gmc_v11_0_resume(void *handle) 952 { 953 int r; 954 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 955 956 r = gmc_v11_0_hw_init(adev); 957 if (r) 958 return r; 959 960 amdgpu_vmid_reset_all(adev); 961 962 return 0; 963 } 964 965 static bool gmc_v11_0_is_idle(void *handle) 966 { 967 /* MC is always ready in GMC v11.*/ 968 return true; 969 } 970 971 static int gmc_v11_0_wait_for_idle(void *handle) 972 { 973 /* There is no need to wait for MC idle in GMC v11.*/ 974 return 0; 975 } 976 977 static int gmc_v11_0_soft_reset(void *handle) 978 { 979 return 0; 980 } 981 982 static int gmc_v11_0_set_clockgating_state(void *handle, 983 enum amd_clockgating_state state) 984 { 985 int r; 986 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 987 988 r = adev->mmhub.funcs->set_clockgating(adev, state); 989 if (r) 990 return r; 991 992 return athub_v3_0_set_clockgating(adev, state); 993 } 994 995 static void gmc_v11_0_get_clockgating_state(void *handle, u64 *flags) 996 { 997 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 998 999 adev->mmhub.funcs->get_clockgating(adev, flags); 1000 1001 athub_v3_0_get_clockgating(adev, flags); 1002 } 1003 1004 static int gmc_v11_0_set_powergating_state(void *handle, 1005 enum amd_powergating_state state) 1006 { 1007 return 0; 1008 } 1009 1010 const struct amd_ip_funcs gmc_v11_0_ip_funcs = { 1011 .name = "gmc_v11_0", 1012 .early_init = gmc_v11_0_early_init, 1013 .sw_init = gmc_v11_0_sw_init, 1014 .hw_init = gmc_v11_0_hw_init, 1015 .late_init = gmc_v11_0_late_init, 1016 .sw_fini = gmc_v11_0_sw_fini, 1017 .hw_fini = gmc_v11_0_hw_fini, 1018 .suspend = gmc_v11_0_suspend, 1019 .resume = gmc_v11_0_resume, 1020 .is_idle = gmc_v11_0_is_idle, 1021 .wait_for_idle = gmc_v11_0_wait_for_idle, 1022 .soft_reset = gmc_v11_0_soft_reset, 1023 .set_clockgating_state = gmc_v11_0_set_clockgating_state, 1024 .set_powergating_state = gmc_v11_0_set_powergating_state, 1025 .get_clockgating_state = gmc_v11_0_get_clockgating_state, 1026 }; 1027 1028 const struct amdgpu_ip_block_version gmc_v11_0_ip_block = { 1029 .type = AMD_IP_BLOCK_TYPE_GMC, 1030 .major = 11, 1031 .minor = 0, 1032 .rev = 0, 1033 .funcs = &gmc_v11_0_ip_funcs, 1034 }; 1035