1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 26 #include <drm/drm_cache.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atomfirmware.h" 30 #include "gmc_v11_0.h" 31 #include "umc_v8_10.h" 32 #include "athub/athub_3_0_0_sh_mask.h" 33 #include "athub/athub_3_0_0_offset.h" 34 #include "dcn/dcn_3_2_0_offset.h" 35 #include "dcn/dcn_3_2_0_sh_mask.h" 36 #include "oss/osssys_6_0_0_offset.h" 37 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 38 #include "navi10_enum.h" 39 #include "soc15.h" 40 #include "soc15d.h" 41 #include "soc15_common.h" 42 #include "nbio_v4_3.h" 43 #include "gfxhub_v3_0.h" 44 #include "gfxhub_v3_0_3.h" 45 #include "mmhub_v3_0.h" 46 #include "mmhub_v3_0_1.h" 47 #include "mmhub_v3_0_2.h" 48 #include "athub_v3_0.h" 49 50 51 static int gmc_v11_0_ecc_interrupt_state(struct amdgpu_device *adev, 52 struct amdgpu_irq_src *src, 53 unsigned int type, 54 enum amdgpu_interrupt_state state) 55 { 56 return 0; 57 } 58 59 static int 60 gmc_v11_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 61 struct amdgpu_irq_src *src, unsigned int type, 62 enum amdgpu_interrupt_state state) 63 { 64 switch (state) { 65 case AMDGPU_IRQ_STATE_DISABLE: 66 /* MM HUB */ 67 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), false); 68 /* GFX HUB */ 69 /* This works because this interrupt is only 70 * enabled at init/resume and disabled in 71 * fini/suspend, so the overall state doesn't 72 * change over the course of suspend/resume. 73 */ 74 if (!adev->in_s0ix) 75 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), false); 76 break; 77 case AMDGPU_IRQ_STATE_ENABLE: 78 /* MM HUB */ 79 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), true); 80 /* GFX HUB */ 81 /* This works because this interrupt is only 82 * enabled at init/resume and disabled in 83 * fini/suspend, so the overall state doesn't 84 * change over the course of suspend/resume. 85 */ 86 if (!adev->in_s0ix) 87 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), true); 88 break; 89 default: 90 break; 91 } 92 93 return 0; 94 } 95 96 static int gmc_v11_0_process_interrupt(struct amdgpu_device *adev, 97 struct amdgpu_irq_src *source, 98 struct amdgpu_iv_entry *entry) 99 { 100 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; 101 uint32_t status = 0; 102 u64 addr; 103 104 addr = (u64)entry->src_data[0] << 12; 105 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 106 107 if (!amdgpu_sriov_vf(adev)) { 108 /* 109 * Issue a dummy read to wait for the status register to 110 * be updated to avoid reading an incorrect value due to 111 * the new fast GRBM interface. 112 */ 113 if (entry->vmid_src == AMDGPU_GFXHUB(0)) 114 RREG32(hub->vm_l2_pro_fault_status); 115 116 status = RREG32(hub->vm_l2_pro_fault_status); 117 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 118 } 119 120 if (printk_ratelimit()) { 121 struct amdgpu_task_info task_info; 122 123 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 124 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 125 126 dev_err(adev->dev, 127 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, for process %s pid %d thread %s pid %d)\n", 128 entry->vmid_src ? "mmhub" : "gfxhub", 129 entry->src_id, entry->ring_id, entry->vmid, 130 entry->pasid, task_info.process_name, task_info.tgid, 131 task_info.task_name, task_info.pid); 132 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", 133 addr, entry->client_id); 134 if (!amdgpu_sriov_vf(adev)) 135 hub->vmhub_funcs->print_l2_protection_fault_status(adev, status); 136 } 137 138 return 0; 139 } 140 141 static const struct amdgpu_irq_src_funcs gmc_v11_0_irq_funcs = { 142 .set = gmc_v11_0_vm_fault_interrupt_state, 143 .process = gmc_v11_0_process_interrupt, 144 }; 145 146 static const struct amdgpu_irq_src_funcs gmc_v11_0_ecc_funcs = { 147 .set = gmc_v11_0_ecc_interrupt_state, 148 .process = amdgpu_umc_process_ecc_irq, 149 }; 150 151 static void gmc_v11_0_set_irq_funcs(struct amdgpu_device *adev) 152 { 153 adev->gmc.vm_fault.num_types = 1; 154 adev->gmc.vm_fault.funcs = &gmc_v11_0_irq_funcs; 155 156 if (!amdgpu_sriov_vf(adev)) { 157 adev->gmc.ecc_irq.num_types = 1; 158 adev->gmc.ecc_irq.funcs = &gmc_v11_0_ecc_funcs; 159 } 160 } 161 162 /** 163 * gmc_v11_0_use_invalidate_semaphore - judge whether to use semaphore 164 * 165 * @adev: amdgpu_device pointer 166 * @vmhub: vmhub type 167 * 168 */ 169 static bool gmc_v11_0_use_invalidate_semaphore(struct amdgpu_device *adev, 170 uint32_t vmhub) 171 { 172 return ((vmhub == AMDGPU_MMHUB0(0)) && 173 (!amdgpu_sriov_vf(adev))); 174 } 175 176 static bool gmc_v11_0_get_vmid_pasid_mapping_info( 177 struct amdgpu_device *adev, 178 uint8_t vmid, uint16_t *p_pasid) 179 { 180 *p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff; 181 182 return !!(*p_pasid); 183 } 184 185 /* 186 * GART 187 * VMID 0 is the physical GPU addresses as used by the kernel. 188 * VMIDs 1-15 are used for userspace clients and are handled 189 * by the amdgpu vm/hsa code. 190 */ 191 192 static void gmc_v11_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 193 unsigned int vmhub, uint32_t flush_type) 194 { 195 bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(adev, vmhub); 196 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 197 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 198 u32 tmp; 199 /* Use register 17 for GART */ 200 const unsigned int eng = 17; 201 unsigned int i; 202 unsigned char hub_ip = 0; 203 204 hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? 205 GC_HWIP : MMHUB_HWIP; 206 207 spin_lock(&adev->gmc.invalidate_lock); 208 /* 209 * It may lose gpuvm invalidate acknowldege state across power-gating 210 * off cycle, add semaphore acquire before invalidation and semaphore 211 * release after invalidation to avoid entering power gated state 212 * to WA the Issue 213 */ 214 215 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 216 if (use_semaphore) { 217 for (i = 0; i < adev->usec_timeout; i++) { 218 /* a read return value of 1 means semaphore acuqire */ 219 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + 220 hub->eng_distance * eng, hub_ip); 221 if (tmp & 0x1) 222 break; 223 udelay(1); 224 } 225 226 if (i >= adev->usec_timeout) 227 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 228 } 229 230 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req, hub_ip); 231 232 /* Wait for ACK with a delay.*/ 233 for (i = 0; i < adev->usec_timeout; i++) { 234 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack + 235 hub->eng_distance * eng, hub_ip); 236 tmp &= 1 << vmid; 237 if (tmp) 238 break; 239 240 udelay(1); 241 } 242 243 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 244 if (use_semaphore) 245 /* 246 * add semaphore release after invalidation, 247 * write with 0 means semaphore release 248 */ 249 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + 250 hub->eng_distance * eng, 0, hub_ip); 251 252 /* Issue additional private vm invalidation to MMHUB */ 253 if ((vmhub != AMDGPU_GFXHUB(0)) && 254 (hub->vm_l2_bank_select_reserved_cid2) && 255 !amdgpu_sriov_vf(adev)) { 256 inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 257 /* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */ 258 inv_req |= (1 << 25); 259 /* Issue private invalidation */ 260 WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req); 261 /* Read back to ensure invalidation is done*/ 262 RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 263 } 264 265 spin_unlock(&adev->gmc.invalidate_lock); 266 267 if (i < adev->usec_timeout) 268 return; 269 270 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 271 } 272 273 /** 274 * gmc_v11_0_flush_gpu_tlb - gart tlb flush callback 275 * 276 * @adev: amdgpu_device pointer 277 * @vmid: vm instance to flush 278 * @vmhub: which hub to flush 279 * @flush_type: the flush type 280 * 281 * Flush the TLB for the requested page table. 282 */ 283 static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 284 uint32_t vmhub, uint32_t flush_type) 285 { 286 if ((vmhub == AMDGPU_GFXHUB(0)) && !adev->gfx.is_poweron) 287 return; 288 289 /* flush hdp cache */ 290 adev->hdp.funcs->flush_hdp(adev, NULL); 291 292 /* For SRIOV run time, driver shouldn't access the register through MMIO 293 * Directly use kiq to do the vm invalidation instead 294 */ 295 if ((adev->gfx.kiq[0].ring.sched.ready || adev->mes.ring.sched.ready) && 296 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 297 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 298 const unsigned int eng = 17; 299 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 300 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 301 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 302 303 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 304 1 << vmid); 305 return; 306 } 307 308 mutex_lock(&adev->mman.gtt_window_lock); 309 gmc_v11_0_flush_vm_hub(adev, vmid, vmhub, 0); 310 mutex_unlock(&adev->mman.gtt_window_lock); 311 } 312 313 /** 314 * gmc_v11_0_flush_gpu_tlb_pasid - tlb flush via pasid 315 * 316 * @adev: amdgpu_device pointer 317 * @pasid: pasid to be flush 318 * @flush_type: the flush type 319 * @all_hub: flush all hubs 320 * @inst: is used to select which instance of KIQ to use for the invalidation 321 * 322 * Flush the TLB for the requested pasid. 323 */ 324 static int gmc_v11_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 325 uint16_t pasid, uint32_t flush_type, 326 bool all_hub, uint32_t inst) 327 { 328 int vmid, i; 329 signed long r; 330 uint32_t seq; 331 uint16_t queried_pasid; 332 bool ret; 333 struct amdgpu_ring *ring = &adev->gfx.kiq[0].ring; 334 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 335 336 if (amdgpu_emu_mode == 0 && ring->sched.ready) { 337 spin_lock(&adev->gfx.kiq[0].ring_lock); 338 /* 2 dwords flush + 8 dwords fence */ 339 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8); 340 kiq->pmf->kiq_invalidate_tlbs(ring, 341 pasid, flush_type, all_hub); 342 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 343 if (r) { 344 amdgpu_ring_undo(ring); 345 spin_unlock(&adev->gfx.kiq[0].ring_lock); 346 return -ETIME; 347 } 348 349 amdgpu_ring_commit(ring); 350 spin_unlock(&adev->gfx.kiq[0].ring_lock); 351 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); 352 if (r < 1) { 353 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r); 354 return -ETIME; 355 } 356 357 return 0; 358 } 359 360 for (vmid = 1; vmid < 16; vmid++) { 361 362 ret = gmc_v11_0_get_vmid_pasid_mapping_info(adev, vmid, 363 &queried_pasid); 364 if (ret && queried_pasid == pasid) { 365 if (all_hub) { 366 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) 367 gmc_v11_0_flush_gpu_tlb(adev, vmid, 368 i, flush_type); 369 } else { 370 gmc_v11_0_flush_gpu_tlb(adev, vmid, 371 AMDGPU_GFXHUB(0), flush_type); 372 } 373 } 374 } 375 376 return 0; 377 } 378 379 static uint64_t gmc_v11_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 380 unsigned int vmid, uint64_t pd_addr) 381 { 382 bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 383 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 384 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 385 unsigned int eng = ring->vm_inv_eng; 386 387 /* 388 * It may lose gpuvm invalidate acknowldege state across power-gating 389 * off cycle, add semaphore acquire before invalidation and semaphore 390 * release after invalidation to avoid entering power gated state 391 * to WA the Issue 392 */ 393 394 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 395 if (use_semaphore) 396 /* a read return value of 1 means semaphore acuqire */ 397 amdgpu_ring_emit_reg_wait(ring, 398 hub->vm_inv_eng0_sem + 399 hub->eng_distance * eng, 0x1, 0x1); 400 401 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 402 (hub->ctx_addr_distance * vmid), 403 lower_32_bits(pd_addr)); 404 405 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 406 (hub->ctx_addr_distance * vmid), 407 upper_32_bits(pd_addr)); 408 409 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 410 hub->eng_distance * eng, 411 hub->vm_inv_eng0_ack + 412 hub->eng_distance * eng, 413 req, 1 << vmid); 414 415 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 416 if (use_semaphore) 417 /* 418 * add semaphore release after invalidation, 419 * write with 0 means semaphore release 420 */ 421 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 422 hub->eng_distance * eng, 0); 423 424 return pd_addr; 425 } 426 427 static void gmc_v11_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, 428 unsigned int pasid) 429 { 430 struct amdgpu_device *adev = ring->adev; 431 uint32_t reg; 432 433 /* MES fw manages IH_VMID_x_LUT updating */ 434 if (ring->is_mes_queue) 435 return; 436 437 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 438 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid; 439 else 440 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid; 441 442 amdgpu_ring_emit_wreg(ring, reg, pasid); 443 } 444 445 /* 446 * PTE format: 447 * 63:59 reserved 448 * 58:57 reserved 449 * 56 F 450 * 55 L 451 * 54 reserved 452 * 53:52 SW 453 * 51 T 454 * 50:48 mtype 455 * 47:12 4k physical page base address 456 * 11:7 fragment 457 * 6 write 458 * 5 read 459 * 4 exe 460 * 3 Z 461 * 2 snooped 462 * 1 system 463 * 0 valid 464 * 465 * PDE format: 466 * 63:59 block fragment size 467 * 58:55 reserved 468 * 54 P 469 * 53:48 reserved 470 * 47:6 physical base address of PD or PTE 471 * 5:3 reserved 472 * 2 C 473 * 1 system 474 * 0 valid 475 */ 476 477 static uint64_t gmc_v11_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 478 { 479 switch (flags) { 480 case AMDGPU_VM_MTYPE_DEFAULT: 481 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 482 case AMDGPU_VM_MTYPE_NC: 483 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 484 case AMDGPU_VM_MTYPE_WC: 485 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC); 486 case AMDGPU_VM_MTYPE_CC: 487 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC); 488 case AMDGPU_VM_MTYPE_UC: 489 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 490 default: 491 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 492 } 493 } 494 495 static void gmc_v11_0_get_vm_pde(struct amdgpu_device *adev, int level, 496 uint64_t *addr, uint64_t *flags) 497 { 498 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 499 *addr = adev->vm_manager.vram_base_offset + *addr - 500 adev->gmc.vram_start; 501 BUG_ON(*addr & 0xFFFF00000000003FULL); 502 503 if (!adev->gmc.translate_further) 504 return; 505 506 if (level == AMDGPU_VM_PDB1) { 507 /* Set the block fragment size */ 508 if (!(*flags & AMDGPU_PDE_PTE)) 509 *flags |= AMDGPU_PDE_BFS(0x9); 510 511 } else if (level == AMDGPU_VM_PDB0) { 512 if (*flags & AMDGPU_PDE_PTE) 513 *flags &= ~AMDGPU_PDE_PTE; 514 else 515 *flags |= AMDGPU_PTE_TF; 516 } 517 } 518 519 static void gmc_v11_0_get_vm_pte(struct amdgpu_device *adev, 520 struct amdgpu_bo_va_mapping *mapping, 521 uint64_t *flags) 522 { 523 struct amdgpu_bo *bo = mapping->bo_va->base.bo; 524 525 *flags &= ~AMDGPU_PTE_EXECUTABLE; 526 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 527 528 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; 529 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); 530 531 *flags &= ~AMDGPU_PTE_NOALLOC; 532 *flags |= (mapping->flags & AMDGPU_PTE_NOALLOC); 533 534 if (mapping->flags & AMDGPU_PTE_PRT) { 535 *flags |= AMDGPU_PTE_PRT; 536 *flags |= AMDGPU_PTE_SNOOPED; 537 *flags |= AMDGPU_PTE_LOG; 538 *flags |= AMDGPU_PTE_SYSTEM; 539 *flags &= ~AMDGPU_PTE_VALID; 540 } 541 542 if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT | 543 AMDGPU_GEM_CREATE_UNCACHED)) 544 *flags = (*flags & ~AMDGPU_PTE_MTYPE_NV10_MASK) | 545 AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 546 } 547 548 static unsigned int gmc_v11_0_get_vbios_fb_size(struct amdgpu_device *adev) 549 { 550 u32 d1vga_control = RREG32_SOC15(DCE, 0, regD1VGA_CONTROL); 551 unsigned int size; 552 553 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 554 size = AMDGPU_VBIOS_VGA_ALLOCATION; 555 } else { 556 u32 viewport; 557 u32 pitch; 558 559 viewport = RREG32_SOC15(DCE, 0, regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 560 pitch = RREG32_SOC15(DCE, 0, regHUBPREQ0_DCSURF_SURFACE_PITCH); 561 size = (REG_GET_FIELD(viewport, 562 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 563 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) * 564 4); 565 } 566 567 return size; 568 } 569 570 static const struct amdgpu_gmc_funcs gmc_v11_0_gmc_funcs = { 571 .flush_gpu_tlb = gmc_v11_0_flush_gpu_tlb, 572 .flush_gpu_tlb_pasid = gmc_v11_0_flush_gpu_tlb_pasid, 573 .emit_flush_gpu_tlb = gmc_v11_0_emit_flush_gpu_tlb, 574 .emit_pasid_mapping = gmc_v11_0_emit_pasid_mapping, 575 .map_mtype = gmc_v11_0_map_mtype, 576 .get_vm_pde = gmc_v11_0_get_vm_pde, 577 .get_vm_pte = gmc_v11_0_get_vm_pte, 578 .get_vbios_fb_size = gmc_v11_0_get_vbios_fb_size, 579 }; 580 581 static void gmc_v11_0_set_gmc_funcs(struct amdgpu_device *adev) 582 { 583 adev->gmc.gmc_funcs = &gmc_v11_0_gmc_funcs; 584 } 585 586 static void gmc_v11_0_set_umc_funcs(struct amdgpu_device *adev) 587 { 588 switch (adev->ip_versions[UMC_HWIP][0]) { 589 case IP_VERSION(8, 10, 0): 590 adev->umc.channel_inst_num = UMC_V8_10_CHANNEL_INSTANCE_NUM; 591 adev->umc.umc_inst_num = UMC_V8_10_UMC_INSTANCE_NUM; 592 adev->umc.max_ras_err_cnt_per_query = UMC_V8_10_TOTAL_CHANNEL_NUM(adev); 593 adev->umc.channel_offs = UMC_V8_10_PER_CHANNEL_OFFSET; 594 adev->umc.retire_unit = UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM; 595 if (adev->umc.node_inst_num == 4) 596 adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl_ext0[0][0][0]; 597 else 598 adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl[0][0][0]; 599 adev->umc.ras = &umc_v8_10_ras; 600 break; 601 case IP_VERSION(8, 11, 0): 602 break; 603 default: 604 break; 605 } 606 } 607 608 609 static void gmc_v11_0_set_mmhub_funcs(struct amdgpu_device *adev) 610 { 611 switch (adev->ip_versions[MMHUB_HWIP][0]) { 612 case IP_VERSION(3, 0, 1): 613 adev->mmhub.funcs = &mmhub_v3_0_1_funcs; 614 break; 615 case IP_VERSION(3, 0, 2): 616 adev->mmhub.funcs = &mmhub_v3_0_2_funcs; 617 break; 618 default: 619 adev->mmhub.funcs = &mmhub_v3_0_funcs; 620 break; 621 } 622 } 623 624 static void gmc_v11_0_set_gfxhub_funcs(struct amdgpu_device *adev) 625 { 626 switch (adev->ip_versions[GC_HWIP][0]) { 627 case IP_VERSION(11, 0, 3): 628 adev->gfxhub.funcs = &gfxhub_v3_0_3_funcs; 629 break; 630 default: 631 adev->gfxhub.funcs = &gfxhub_v3_0_funcs; 632 break; 633 } 634 } 635 636 static int gmc_v11_0_early_init(void *handle) 637 { 638 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 639 640 gmc_v11_0_set_gfxhub_funcs(adev); 641 gmc_v11_0_set_mmhub_funcs(adev); 642 gmc_v11_0_set_gmc_funcs(adev); 643 gmc_v11_0_set_irq_funcs(adev); 644 gmc_v11_0_set_umc_funcs(adev); 645 646 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 647 adev->gmc.shared_aperture_end = 648 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 649 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 650 adev->gmc.private_aperture_end = 651 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 652 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; 653 654 return 0; 655 } 656 657 static int gmc_v11_0_late_init(void *handle) 658 { 659 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 660 int r; 661 662 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 663 if (r) 664 return r; 665 666 r = amdgpu_gmc_ras_late_init(adev); 667 if (r) 668 return r; 669 670 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 671 } 672 673 static void gmc_v11_0_vram_gtt_location(struct amdgpu_device *adev, 674 struct amdgpu_gmc *mc) 675 { 676 u64 base = 0; 677 678 base = adev->mmhub.funcs->get_fb_location(adev); 679 680 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 681 amdgpu_gmc_gart_location(adev, mc); 682 amdgpu_gmc_agp_location(adev, mc); 683 684 /* base offset of vram pages */ 685 if (amdgpu_sriov_vf(adev)) 686 adev->vm_manager.vram_base_offset = 0; 687 else 688 adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev); 689 } 690 691 /** 692 * gmc_v11_0_mc_init - initialize the memory controller driver params 693 * 694 * @adev: amdgpu_device pointer 695 * 696 * Look up the amount of vram, vram width, and decide how to place 697 * vram and gart within the GPU's physical address space. 698 * Returns 0 for success. 699 */ 700 static int gmc_v11_0_mc_init(struct amdgpu_device *adev) 701 { 702 int r; 703 704 /* size in MB on si */ 705 adev->gmc.mc_vram_size = 706 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 707 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 708 709 if (!(adev->flags & AMD_IS_APU)) { 710 r = amdgpu_device_resize_fb_bar(adev); 711 if (r) 712 return r; 713 } 714 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 715 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 716 717 #ifdef CONFIG_X86_64 718 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { 719 adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev); 720 adev->gmc.aper_size = adev->gmc.real_vram_size; 721 } 722 #endif 723 /* In case the PCI BAR is larger than the actual amount of vram */ 724 adev->gmc.visible_vram_size = adev->gmc.aper_size; 725 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 726 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 727 728 /* set the gart size */ 729 if (amdgpu_gart_size == -1) 730 adev->gmc.gart_size = 512ULL << 20; 731 else 732 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 733 734 gmc_v11_0_vram_gtt_location(adev, &adev->gmc); 735 736 return 0; 737 } 738 739 static int gmc_v11_0_gart_init(struct amdgpu_device *adev) 740 { 741 int r; 742 743 if (adev->gart.bo) { 744 WARN(1, "PCIE GART already initialized\n"); 745 return 0; 746 } 747 748 /* Initialize common gart structure */ 749 r = amdgpu_gart_init(adev); 750 if (r) 751 return r; 752 753 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 754 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) | 755 AMDGPU_PTE_EXECUTABLE; 756 757 return amdgpu_gart_table_vram_alloc(adev); 758 } 759 760 static int gmc_v11_0_sw_init(void *handle) 761 { 762 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 763 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 764 765 adev->mmhub.funcs->init(adev); 766 767 spin_lock_init(&adev->gmc.invalidate_lock); 768 769 r = amdgpu_atomfirmware_get_vram_info(adev, 770 &vram_width, &vram_type, &vram_vendor); 771 adev->gmc.vram_width = vram_width; 772 773 adev->gmc.vram_type = vram_type; 774 adev->gmc.vram_vendor = vram_vendor; 775 776 switch (adev->ip_versions[GC_HWIP][0]) { 777 case IP_VERSION(11, 0, 0): 778 case IP_VERSION(11, 0, 1): 779 case IP_VERSION(11, 0, 2): 780 case IP_VERSION(11, 0, 3): 781 case IP_VERSION(11, 0, 4): 782 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 783 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 784 /* 785 * To fulfill 4-level page support, 786 * vm size is 256TB (48bit), maximum size, 787 * block size 512 (9bit) 788 */ 789 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 790 break; 791 default: 792 break; 793 } 794 795 /* This interrupt is VMC page fault.*/ 796 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_VMC, 797 VMC_1_0__SRCID__VM_FAULT, 798 &adev->gmc.vm_fault); 799 800 if (r) 801 return r; 802 803 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 804 UTCL2_1_0__SRCID__FAULT, 805 &adev->gmc.vm_fault); 806 if (r) 807 return r; 808 809 if (!amdgpu_sriov_vf(adev)) { 810 /* interrupt sent to DF. */ 811 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_DF, 0, 812 &adev->gmc.ecc_irq); 813 if (r) 814 return r; 815 } 816 817 /* 818 * Set the internal MC address mask This is the max address of the GPU's 819 * internal address space. 820 */ 821 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 822 823 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 824 if (r) { 825 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); 826 return r; 827 } 828 829 adev->need_swiotlb = drm_need_swiotlb(44); 830 831 r = gmc_v11_0_mc_init(adev); 832 if (r) 833 return r; 834 835 amdgpu_gmc_get_vbios_allocations(adev); 836 837 /* Memory manager */ 838 r = amdgpu_bo_init(adev); 839 if (r) 840 return r; 841 842 r = gmc_v11_0_gart_init(adev); 843 if (r) 844 return r; 845 846 /* 847 * number of VMs 848 * VMID 0 is reserved for System 849 * amdgpu graphics/compute will use VMIDs 1-7 850 * amdkfd will use VMIDs 8-15 851 */ 852 adev->vm_manager.first_kfd_vmid = 8; 853 854 amdgpu_vm_manager_init(adev); 855 856 r = amdgpu_gmc_ras_sw_init(adev); 857 if (r) 858 return r; 859 860 return 0; 861 } 862 863 /** 864 * gmc_v11_0_gart_fini - vm fini callback 865 * 866 * @adev: amdgpu_device pointer 867 * 868 * Tears down the driver GART/VM setup (CIK). 869 */ 870 static void gmc_v11_0_gart_fini(struct amdgpu_device *adev) 871 { 872 amdgpu_gart_table_vram_free(adev); 873 } 874 875 static int gmc_v11_0_sw_fini(void *handle) 876 { 877 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 878 879 amdgpu_vm_manager_fini(adev); 880 gmc_v11_0_gart_fini(adev); 881 amdgpu_gem_force_release(adev); 882 amdgpu_bo_fini(adev); 883 884 return 0; 885 } 886 887 static void gmc_v11_0_init_golden_registers(struct amdgpu_device *adev) 888 { 889 if (amdgpu_sriov_vf(adev)) { 890 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 891 892 WREG32(hub->vm_contexts_disable, 0); 893 return; 894 } 895 } 896 897 /** 898 * gmc_v11_0_gart_enable - gart enable 899 * 900 * @adev: amdgpu_device pointer 901 */ 902 static int gmc_v11_0_gart_enable(struct amdgpu_device *adev) 903 { 904 int r; 905 bool value; 906 907 if (adev->gart.bo == NULL) { 908 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 909 return -EINVAL; 910 } 911 912 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 913 914 r = adev->mmhub.funcs->gart_enable(adev); 915 if (r) 916 return r; 917 918 /* Flush HDP after it is initialized */ 919 adev->hdp.funcs->flush_hdp(adev, NULL); 920 921 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 922 false : true; 923 924 adev->mmhub.funcs->set_fault_enable_default(adev, value); 925 gmc_v11_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0); 926 927 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 928 (unsigned int)(adev->gmc.gart_size >> 20), 929 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 930 931 return 0; 932 } 933 934 static int gmc_v11_0_hw_init(void *handle) 935 { 936 int r; 937 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 938 939 /* The sequence of these two function calls matters.*/ 940 gmc_v11_0_init_golden_registers(adev); 941 942 r = gmc_v11_0_gart_enable(adev); 943 if (r) 944 return r; 945 946 if (adev->umc.funcs && adev->umc.funcs->init_registers) 947 adev->umc.funcs->init_registers(adev); 948 949 return 0; 950 } 951 952 /** 953 * gmc_v11_0_gart_disable - gart disable 954 * 955 * @adev: amdgpu_device pointer 956 * 957 * This disables all VM page table. 958 */ 959 static void gmc_v11_0_gart_disable(struct amdgpu_device *adev) 960 { 961 adev->mmhub.funcs->gart_disable(adev); 962 } 963 964 static int gmc_v11_0_hw_fini(void *handle) 965 { 966 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 967 968 if (amdgpu_sriov_vf(adev)) { 969 /* full access mode, so don't touch any GMC register */ 970 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 971 return 0; 972 } 973 974 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 975 gmc_v11_0_gart_disable(adev); 976 977 return 0; 978 } 979 980 static int gmc_v11_0_suspend(void *handle) 981 { 982 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 983 984 gmc_v11_0_hw_fini(adev); 985 986 return 0; 987 } 988 989 static int gmc_v11_0_resume(void *handle) 990 { 991 int r; 992 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 993 994 r = gmc_v11_0_hw_init(adev); 995 if (r) 996 return r; 997 998 amdgpu_vmid_reset_all(adev); 999 1000 return 0; 1001 } 1002 1003 static bool gmc_v11_0_is_idle(void *handle) 1004 { 1005 /* MC is always ready in GMC v11.*/ 1006 return true; 1007 } 1008 1009 static int gmc_v11_0_wait_for_idle(void *handle) 1010 { 1011 /* There is no need to wait for MC idle in GMC v11.*/ 1012 return 0; 1013 } 1014 1015 static int gmc_v11_0_soft_reset(void *handle) 1016 { 1017 return 0; 1018 } 1019 1020 static int gmc_v11_0_set_clockgating_state(void *handle, 1021 enum amd_clockgating_state state) 1022 { 1023 int r; 1024 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1025 1026 r = adev->mmhub.funcs->set_clockgating(adev, state); 1027 if (r) 1028 return r; 1029 1030 return athub_v3_0_set_clockgating(adev, state); 1031 } 1032 1033 static void gmc_v11_0_get_clockgating_state(void *handle, u64 *flags) 1034 { 1035 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1036 1037 adev->mmhub.funcs->get_clockgating(adev, flags); 1038 1039 athub_v3_0_get_clockgating(adev, flags); 1040 } 1041 1042 static int gmc_v11_0_set_powergating_state(void *handle, 1043 enum amd_powergating_state state) 1044 { 1045 return 0; 1046 } 1047 1048 const struct amd_ip_funcs gmc_v11_0_ip_funcs = { 1049 .name = "gmc_v11_0", 1050 .early_init = gmc_v11_0_early_init, 1051 .sw_init = gmc_v11_0_sw_init, 1052 .hw_init = gmc_v11_0_hw_init, 1053 .late_init = gmc_v11_0_late_init, 1054 .sw_fini = gmc_v11_0_sw_fini, 1055 .hw_fini = gmc_v11_0_hw_fini, 1056 .suspend = gmc_v11_0_suspend, 1057 .resume = gmc_v11_0_resume, 1058 .is_idle = gmc_v11_0_is_idle, 1059 .wait_for_idle = gmc_v11_0_wait_for_idle, 1060 .soft_reset = gmc_v11_0_soft_reset, 1061 .set_clockgating_state = gmc_v11_0_set_clockgating_state, 1062 .set_powergating_state = gmc_v11_0_set_powergating_state, 1063 .get_clockgating_state = gmc_v11_0_get_clockgating_state, 1064 }; 1065 1066 const struct amdgpu_ip_block_version gmc_v11_0_ip_block = { 1067 .type = AMD_IP_BLOCK_TYPE_GMC, 1068 .major = 11, 1069 .minor = 0, 1070 .rev = 0, 1071 .funcs = &gmc_v11_0_ip_funcs, 1072 }; 1073