1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 #include "amdgpu.h" 26 #include "amdgpu_atomfirmware.h" 27 #include "gmc_v11_0.h" 28 #include "umc_v8_10.h" 29 #include "athub/athub_3_0_0_sh_mask.h" 30 #include "athub/athub_3_0_0_offset.h" 31 #include "oss/osssys_6_0_0_offset.h" 32 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 33 #include "navi10_enum.h" 34 #include "soc15.h" 35 #include "soc15d.h" 36 #include "soc15_common.h" 37 #include "nbio_v4_3.h" 38 #include "gfxhub_v3_0.h" 39 #include "mmhub_v3_0.h" 40 #include "mmhub_v3_0_1.h" 41 #include "mmhub_v3_0_2.h" 42 #include "athub_v3_0.h" 43 44 45 static int gmc_v11_0_ecc_interrupt_state(struct amdgpu_device *adev, 46 struct amdgpu_irq_src *src, 47 unsigned type, 48 enum amdgpu_interrupt_state state) 49 { 50 return 0; 51 } 52 53 static int 54 gmc_v11_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 55 struct amdgpu_irq_src *src, unsigned type, 56 enum amdgpu_interrupt_state state) 57 { 58 switch (state) { 59 case AMDGPU_IRQ_STATE_DISABLE: 60 /* MM HUB */ 61 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false); 62 /* GFX HUB */ 63 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false); 64 break; 65 case AMDGPU_IRQ_STATE_ENABLE: 66 /* MM HUB */ 67 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true); 68 /* GFX HUB */ 69 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true); 70 break; 71 default: 72 break; 73 } 74 75 return 0; 76 } 77 78 static int gmc_v11_0_process_interrupt(struct amdgpu_device *adev, 79 struct amdgpu_irq_src *source, 80 struct amdgpu_iv_entry *entry) 81 { 82 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; 83 uint32_t status = 0; 84 u64 addr; 85 86 addr = (u64)entry->src_data[0] << 12; 87 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 88 89 if (!amdgpu_sriov_vf(adev)) { 90 /* 91 * Issue a dummy read to wait for the status register to 92 * be updated to avoid reading an incorrect value due to 93 * the new fast GRBM interface. 94 */ 95 if (entry->vmid_src == AMDGPU_GFXHUB_0) 96 RREG32(hub->vm_l2_pro_fault_status); 97 98 status = RREG32(hub->vm_l2_pro_fault_status); 99 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 100 } 101 102 if (printk_ratelimit()) { 103 struct amdgpu_task_info task_info; 104 105 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 106 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 107 108 dev_err(adev->dev, 109 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, " 110 "for process %s pid %d thread %s pid %d)\n", 111 entry->vmid_src ? "mmhub" : "gfxhub", 112 entry->src_id, entry->ring_id, entry->vmid, 113 entry->pasid, task_info.process_name, task_info.tgid, 114 task_info.task_name, task_info.pid); 115 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", 116 addr, entry->client_id); 117 if (!amdgpu_sriov_vf(adev)) 118 hub->vmhub_funcs->print_l2_protection_fault_status(adev, status); 119 } 120 121 return 0; 122 } 123 124 static const struct amdgpu_irq_src_funcs gmc_v11_0_irq_funcs = { 125 .set = gmc_v11_0_vm_fault_interrupt_state, 126 .process = gmc_v11_0_process_interrupt, 127 }; 128 129 static const struct amdgpu_irq_src_funcs gmc_v11_0_ecc_funcs = { 130 .set = gmc_v11_0_ecc_interrupt_state, 131 .process = amdgpu_umc_process_ecc_irq, 132 }; 133 134 static void gmc_v11_0_set_irq_funcs(struct amdgpu_device *adev) 135 { 136 adev->gmc.vm_fault.num_types = 1; 137 adev->gmc.vm_fault.funcs = &gmc_v11_0_irq_funcs; 138 139 if (!amdgpu_sriov_vf(adev)) { 140 adev->gmc.ecc_irq.num_types = 1; 141 adev->gmc.ecc_irq.funcs = &gmc_v11_0_ecc_funcs; 142 } 143 } 144 145 /** 146 * gmc_v11_0_use_invalidate_semaphore - judge whether to use semaphore 147 * 148 * @adev: amdgpu_device pointer 149 * @vmhub: vmhub type 150 * 151 */ 152 static bool gmc_v11_0_use_invalidate_semaphore(struct amdgpu_device *adev, 153 uint32_t vmhub) 154 { 155 return ((vmhub == AMDGPU_MMHUB_0) && 156 (!amdgpu_sriov_vf(adev))); 157 } 158 159 static bool gmc_v11_0_get_vmid_pasid_mapping_info( 160 struct amdgpu_device *adev, 161 uint8_t vmid, uint16_t *p_pasid) 162 { 163 *p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff; 164 165 return !!(*p_pasid); 166 } 167 168 /* 169 * GART 170 * VMID 0 is the physical GPU addresses as used by the kernel. 171 * VMIDs 1-15 are used for userspace clients and are handled 172 * by the amdgpu vm/hsa code. 173 */ 174 175 static void gmc_v11_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 176 unsigned int vmhub, uint32_t flush_type) 177 { 178 bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(adev, vmhub); 179 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 180 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 181 u32 tmp; 182 /* Use register 17 for GART */ 183 const unsigned eng = 17; 184 unsigned int i; 185 186 spin_lock(&adev->gmc.invalidate_lock); 187 /* 188 * It may lose gpuvm invalidate acknowldege state across power-gating 189 * off cycle, add semaphore acquire before invalidation and semaphore 190 * release after invalidation to avoid entering power gated state 191 * to WA the Issue 192 */ 193 194 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 195 if (use_semaphore) { 196 for (i = 0; i < adev->usec_timeout; i++) { 197 /* a read return value of 1 means semaphore acuqire */ 198 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + 199 hub->eng_distance * eng); 200 if (tmp & 0x1) 201 break; 202 udelay(1); 203 } 204 205 if (i >= adev->usec_timeout) 206 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 207 } 208 209 WREG32_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req); 210 211 /* Wait for ACK with a delay.*/ 212 for (i = 0; i < adev->usec_timeout; i++) { 213 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + 214 hub->eng_distance * eng); 215 tmp &= 1 << vmid; 216 if (tmp) 217 break; 218 219 udelay(1); 220 } 221 222 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 223 if (use_semaphore) 224 /* 225 * add semaphore release after invalidation, 226 * write with 0 means semaphore release 227 */ 228 WREG32_NO_KIQ(hub->vm_inv_eng0_sem + 229 hub->eng_distance * eng, 0); 230 231 /* Issue additional private vm invalidation to MMHUB */ 232 if ((vmhub != AMDGPU_GFXHUB_0) && 233 (hub->vm_l2_bank_select_reserved_cid2)) { 234 inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 235 /* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */ 236 inv_req |= (1 << 25); 237 /* Issue private invalidation */ 238 WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req); 239 /* Read back to ensure invalidation is done*/ 240 RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 241 } 242 243 spin_unlock(&adev->gmc.invalidate_lock); 244 245 if (i < adev->usec_timeout) 246 return; 247 248 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 249 } 250 251 /** 252 * gmc_v11_0_flush_gpu_tlb - gart tlb flush callback 253 * 254 * @adev: amdgpu_device pointer 255 * @vmid: vm instance to flush 256 * 257 * Flush the TLB for the requested page table. 258 */ 259 static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 260 uint32_t vmhub, uint32_t flush_type) 261 { 262 if ((vmhub == AMDGPU_GFXHUB_0) && !adev->gfx.is_poweron) 263 return; 264 265 /* flush hdp cache */ 266 adev->hdp.funcs->flush_hdp(adev, NULL); 267 268 /* For SRIOV run time, driver shouldn't access the register through MMIO 269 * Directly use kiq to do the vm invalidation instead 270 */ 271 if ((adev->gfx.kiq.ring.sched.ready || adev->mes.ring.sched.ready) && 272 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 273 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 274 const unsigned eng = 17; 275 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 276 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 277 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 278 279 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 280 1 << vmid); 281 return; 282 } 283 284 mutex_lock(&adev->mman.gtt_window_lock); 285 gmc_v11_0_flush_vm_hub(adev, vmid, vmhub, 0); 286 mutex_unlock(&adev->mman.gtt_window_lock); 287 return; 288 } 289 290 /** 291 * gmc_v11_0_flush_gpu_tlb_pasid - tlb flush via pasid 292 * 293 * @adev: amdgpu_device pointer 294 * @pasid: pasid to be flush 295 * 296 * Flush the TLB for the requested pasid. 297 */ 298 static int gmc_v11_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 299 uint16_t pasid, uint32_t flush_type, 300 bool all_hub) 301 { 302 int vmid, i; 303 signed long r; 304 uint32_t seq; 305 uint16_t queried_pasid; 306 bool ret; 307 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 308 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 309 310 if (amdgpu_emu_mode == 0 && ring->sched.ready) { 311 spin_lock(&adev->gfx.kiq.ring_lock); 312 /* 2 dwords flush + 8 dwords fence */ 313 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8); 314 kiq->pmf->kiq_invalidate_tlbs(ring, 315 pasid, flush_type, all_hub); 316 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 317 if (r) { 318 amdgpu_ring_undo(ring); 319 spin_unlock(&adev->gfx.kiq.ring_lock); 320 return -ETIME; 321 } 322 323 amdgpu_ring_commit(ring); 324 spin_unlock(&adev->gfx.kiq.ring_lock); 325 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); 326 if (r < 1) { 327 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r); 328 return -ETIME; 329 } 330 331 return 0; 332 } 333 334 for (vmid = 1; vmid < 16; vmid++) { 335 336 ret = gmc_v11_0_get_vmid_pasid_mapping_info(adev, vmid, 337 &queried_pasid); 338 if (ret && queried_pasid == pasid) { 339 if (all_hub) { 340 for (i = 0; i < adev->num_vmhubs; i++) 341 gmc_v11_0_flush_gpu_tlb(adev, vmid, 342 i, flush_type); 343 } else { 344 gmc_v11_0_flush_gpu_tlb(adev, vmid, 345 AMDGPU_GFXHUB_0, flush_type); 346 } 347 } 348 } 349 350 return 0; 351 } 352 353 static uint64_t gmc_v11_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 354 unsigned vmid, uint64_t pd_addr) 355 { 356 bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub); 357 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 358 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 359 unsigned eng = ring->vm_inv_eng; 360 361 /* 362 * It may lose gpuvm invalidate acknowldege state across power-gating 363 * off cycle, add semaphore acquire before invalidation and semaphore 364 * release after invalidation to avoid entering power gated state 365 * to WA the Issue 366 */ 367 368 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 369 if (use_semaphore) 370 /* a read return value of 1 means semaphore acuqire */ 371 amdgpu_ring_emit_reg_wait(ring, 372 hub->vm_inv_eng0_sem + 373 hub->eng_distance * eng, 0x1, 0x1); 374 375 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 376 (hub->ctx_addr_distance * vmid), 377 lower_32_bits(pd_addr)); 378 379 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 380 (hub->ctx_addr_distance * vmid), 381 upper_32_bits(pd_addr)); 382 383 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 384 hub->eng_distance * eng, 385 hub->vm_inv_eng0_ack + 386 hub->eng_distance * eng, 387 req, 1 << vmid); 388 389 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 390 if (use_semaphore) 391 /* 392 * add semaphore release after invalidation, 393 * write with 0 means semaphore release 394 */ 395 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 396 hub->eng_distance * eng, 0); 397 398 return pd_addr; 399 } 400 401 static void gmc_v11_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 402 unsigned pasid) 403 { 404 struct amdgpu_device *adev = ring->adev; 405 uint32_t reg; 406 407 /* MES fw manages IH_VMID_x_LUT updating */ 408 if (ring->is_mes_queue) 409 return; 410 411 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) 412 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid; 413 else 414 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid; 415 416 amdgpu_ring_emit_wreg(ring, reg, pasid); 417 } 418 419 /* 420 * PTE format: 421 * 63:59 reserved 422 * 58:57 reserved 423 * 56 F 424 * 55 L 425 * 54 reserved 426 * 53:52 SW 427 * 51 T 428 * 50:48 mtype 429 * 47:12 4k physical page base address 430 * 11:7 fragment 431 * 6 write 432 * 5 read 433 * 4 exe 434 * 3 Z 435 * 2 snooped 436 * 1 system 437 * 0 valid 438 * 439 * PDE format: 440 * 63:59 block fragment size 441 * 58:55 reserved 442 * 54 P 443 * 53:48 reserved 444 * 47:6 physical base address of PD or PTE 445 * 5:3 reserved 446 * 2 C 447 * 1 system 448 * 0 valid 449 */ 450 451 static uint64_t gmc_v11_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 452 { 453 switch (flags) { 454 case AMDGPU_VM_MTYPE_DEFAULT: 455 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 456 case AMDGPU_VM_MTYPE_NC: 457 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 458 case AMDGPU_VM_MTYPE_WC: 459 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC); 460 case AMDGPU_VM_MTYPE_CC: 461 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC); 462 case AMDGPU_VM_MTYPE_UC: 463 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 464 default: 465 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 466 } 467 } 468 469 static void gmc_v11_0_get_vm_pde(struct amdgpu_device *adev, int level, 470 uint64_t *addr, uint64_t *flags) 471 { 472 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 473 *addr = adev->vm_manager.vram_base_offset + *addr - 474 adev->gmc.vram_start; 475 BUG_ON(*addr & 0xFFFF00000000003FULL); 476 477 if (!adev->gmc.translate_further) 478 return; 479 480 if (level == AMDGPU_VM_PDB1) { 481 /* Set the block fragment size */ 482 if (!(*flags & AMDGPU_PDE_PTE)) 483 *flags |= AMDGPU_PDE_BFS(0x9); 484 485 } else if (level == AMDGPU_VM_PDB0) { 486 if (*flags & AMDGPU_PDE_PTE) 487 *flags &= ~AMDGPU_PDE_PTE; 488 else 489 *flags |= AMDGPU_PTE_TF; 490 } 491 } 492 493 static void gmc_v11_0_get_vm_pte(struct amdgpu_device *adev, 494 struct amdgpu_bo_va_mapping *mapping, 495 uint64_t *flags) 496 { 497 *flags &= ~AMDGPU_PTE_EXECUTABLE; 498 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 499 500 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; 501 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); 502 503 *flags &= ~AMDGPU_PTE_NOALLOC; 504 *flags |= (mapping->flags & AMDGPU_PTE_NOALLOC); 505 506 if (mapping->flags & AMDGPU_PTE_PRT) { 507 *flags |= AMDGPU_PTE_PRT; 508 *flags |= AMDGPU_PTE_SNOOPED; 509 *flags |= AMDGPU_PTE_LOG; 510 *flags |= AMDGPU_PTE_SYSTEM; 511 *flags &= ~AMDGPU_PTE_VALID; 512 } 513 } 514 515 static unsigned gmc_v11_0_get_vbios_fb_size(struct amdgpu_device *adev) 516 { 517 return 0; 518 } 519 520 static const struct amdgpu_gmc_funcs gmc_v11_0_gmc_funcs = { 521 .flush_gpu_tlb = gmc_v11_0_flush_gpu_tlb, 522 .flush_gpu_tlb_pasid = gmc_v11_0_flush_gpu_tlb_pasid, 523 .emit_flush_gpu_tlb = gmc_v11_0_emit_flush_gpu_tlb, 524 .emit_pasid_mapping = gmc_v11_0_emit_pasid_mapping, 525 .map_mtype = gmc_v11_0_map_mtype, 526 .get_vm_pde = gmc_v11_0_get_vm_pde, 527 .get_vm_pte = gmc_v11_0_get_vm_pte, 528 .get_vbios_fb_size = gmc_v11_0_get_vbios_fb_size, 529 }; 530 531 static void gmc_v11_0_set_gmc_funcs(struct amdgpu_device *adev) 532 { 533 adev->gmc.gmc_funcs = &gmc_v11_0_gmc_funcs; 534 } 535 536 static void gmc_v11_0_set_umc_funcs(struct amdgpu_device *adev) 537 { 538 switch (adev->ip_versions[UMC_HWIP][0]) { 539 case IP_VERSION(8, 10, 0): 540 adev->umc.channel_inst_num = UMC_V8_10_CHANNEL_INSTANCE_NUM; 541 adev->umc.umc_inst_num = UMC_V8_10_UMC_INSTANCE_NUM; 542 adev->umc.node_inst_num = adev->gmc.num_umc; 543 adev->umc.max_ras_err_cnt_per_query = UMC_V8_10_TOTAL_CHANNEL_NUM(adev); 544 adev->umc.channel_offs = UMC_V8_10_PER_CHANNEL_OFFSET; 545 adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl[0][0][0]; 546 adev->umc.ras = &umc_v8_10_ras; 547 break; 548 case IP_VERSION(8, 11, 0): 549 break; 550 default: 551 break; 552 } 553 554 if (adev->umc.ras) { 555 amdgpu_ras_register_ras_block(adev, &adev->umc.ras->ras_block); 556 557 strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc"); 558 adev->umc.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC; 559 adev->umc.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; 560 adev->umc.ras_if = &adev->umc.ras->ras_block.ras_comm; 561 562 /* If don't define special ras_late_init function, use default ras_late_init */ 563 if (!adev->umc.ras->ras_block.ras_late_init) 564 adev->umc.ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init; 565 566 /* If not define special ras_cb function, use default ras_cb */ 567 if (!adev->umc.ras->ras_block.ras_cb) 568 adev->umc.ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb; 569 } 570 } 571 572 573 static void gmc_v11_0_set_mmhub_funcs(struct amdgpu_device *adev) 574 { 575 switch (adev->ip_versions[MMHUB_HWIP][0]) { 576 case IP_VERSION(3, 0, 1): 577 adev->mmhub.funcs = &mmhub_v3_0_1_funcs; 578 break; 579 case IP_VERSION(3, 0, 2): 580 adev->mmhub.funcs = &mmhub_v3_0_2_funcs; 581 break; 582 default: 583 adev->mmhub.funcs = &mmhub_v3_0_funcs; 584 break; 585 } 586 } 587 588 static void gmc_v11_0_set_gfxhub_funcs(struct amdgpu_device *adev) 589 { 590 adev->gfxhub.funcs = &gfxhub_v3_0_funcs; 591 } 592 593 static int gmc_v11_0_early_init(void *handle) 594 { 595 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 596 597 gmc_v11_0_set_gfxhub_funcs(adev); 598 gmc_v11_0_set_mmhub_funcs(adev); 599 gmc_v11_0_set_gmc_funcs(adev); 600 gmc_v11_0_set_irq_funcs(adev); 601 gmc_v11_0_set_umc_funcs(adev); 602 603 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 604 adev->gmc.shared_aperture_end = 605 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 606 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 607 adev->gmc.private_aperture_end = 608 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 609 610 return 0; 611 } 612 613 static int gmc_v11_0_late_init(void *handle) 614 { 615 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 616 int r; 617 618 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 619 if (r) 620 return r; 621 622 r = amdgpu_gmc_ras_late_init(adev); 623 if (r) 624 return r; 625 626 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 627 } 628 629 static void gmc_v11_0_vram_gtt_location(struct amdgpu_device *adev, 630 struct amdgpu_gmc *mc) 631 { 632 u64 base = 0; 633 634 base = adev->mmhub.funcs->get_fb_location(adev); 635 636 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 637 amdgpu_gmc_gart_location(adev, mc); 638 639 /* base offset of vram pages */ 640 adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev); 641 } 642 643 /** 644 * gmc_v11_0_mc_init - initialize the memory controller driver params 645 * 646 * @adev: amdgpu_device pointer 647 * 648 * Look up the amount of vram, vram width, and decide how to place 649 * vram and gart within the GPU's physical address space. 650 * Returns 0 for success. 651 */ 652 static int gmc_v11_0_mc_init(struct amdgpu_device *adev) 653 { 654 int r; 655 656 /* size in MB on si */ 657 adev->gmc.mc_vram_size = 658 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 659 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 660 661 if (!(adev->flags & AMD_IS_APU)) { 662 r = amdgpu_device_resize_fb_bar(adev); 663 if (r) 664 return r; 665 } 666 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 667 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 668 669 #ifdef CONFIG_X86_64 670 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { 671 adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev); 672 adev->gmc.aper_size = adev->gmc.real_vram_size; 673 } 674 #endif 675 /* In case the PCI BAR is larger than the actual amount of vram */ 676 adev->gmc.visible_vram_size = adev->gmc.aper_size; 677 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 678 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 679 680 /* set the gart size */ 681 if (amdgpu_gart_size == -1) { 682 adev->gmc.gart_size = 512ULL << 20; 683 } else 684 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 685 686 gmc_v11_0_vram_gtt_location(adev, &adev->gmc); 687 688 return 0; 689 } 690 691 static int gmc_v11_0_gart_init(struct amdgpu_device *adev) 692 { 693 int r; 694 695 if (adev->gart.bo) { 696 WARN(1, "PCIE GART already initialized\n"); 697 return 0; 698 } 699 700 /* Initialize common gart structure */ 701 r = amdgpu_gart_init(adev); 702 if (r) 703 return r; 704 705 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 706 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) | 707 AMDGPU_PTE_EXECUTABLE; 708 709 return amdgpu_gart_table_vram_alloc(adev); 710 } 711 712 static int gmc_v11_0_sw_init(void *handle) 713 { 714 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 715 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 716 717 adev->mmhub.funcs->init(adev); 718 719 spin_lock_init(&adev->gmc.invalidate_lock); 720 721 r = amdgpu_atomfirmware_get_vram_info(adev, 722 &vram_width, &vram_type, &vram_vendor); 723 adev->gmc.vram_width = vram_width; 724 725 adev->gmc.vram_type = vram_type; 726 adev->gmc.vram_vendor = vram_vendor; 727 728 switch (adev->ip_versions[GC_HWIP][0]) { 729 case IP_VERSION(11, 0, 0): 730 case IP_VERSION(11, 0, 1): 731 case IP_VERSION(11, 0, 2): 732 adev->num_vmhubs = 2; 733 /* 734 * To fulfill 4-level page support, 735 * vm size is 256TB (48bit), maximum size, 736 * block size 512 (9bit) 737 */ 738 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 739 break; 740 default: 741 break; 742 } 743 744 /* This interrupt is VMC page fault.*/ 745 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_VMC, 746 VMC_1_0__SRCID__VM_FAULT, 747 &adev->gmc.vm_fault); 748 749 if (r) 750 return r; 751 752 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 753 UTCL2_1_0__SRCID__FAULT, 754 &adev->gmc.vm_fault); 755 if (r) 756 return r; 757 758 if (!amdgpu_sriov_vf(adev)) { 759 /* interrupt sent to DF. */ 760 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_DF, 0, 761 &adev->gmc.ecc_irq); 762 if (r) 763 return r; 764 } 765 766 /* 767 * Set the internal MC address mask This is the max address of the GPU's 768 * internal address space. 769 */ 770 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 771 772 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 773 if (r) { 774 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 775 return r; 776 } 777 778 r = gmc_v11_0_mc_init(adev); 779 if (r) 780 return r; 781 782 amdgpu_gmc_get_vbios_allocations(adev); 783 784 /* Memory manager */ 785 r = amdgpu_bo_init(adev); 786 if (r) 787 return r; 788 789 r = gmc_v11_0_gart_init(adev); 790 if (r) 791 return r; 792 793 /* 794 * number of VMs 795 * VMID 0 is reserved for System 796 * amdgpu graphics/compute will use VMIDs 1-7 797 * amdkfd will use VMIDs 8-15 798 */ 799 adev->vm_manager.first_kfd_vmid = 8; 800 801 amdgpu_vm_manager_init(adev); 802 803 return 0; 804 } 805 806 /** 807 * gmc_v11_0_gart_fini - vm fini callback 808 * 809 * @adev: amdgpu_device pointer 810 * 811 * Tears down the driver GART/VM setup (CIK). 812 */ 813 static void gmc_v11_0_gart_fini(struct amdgpu_device *adev) 814 { 815 amdgpu_gart_table_vram_free(adev); 816 } 817 818 static int gmc_v11_0_sw_fini(void *handle) 819 { 820 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 821 822 amdgpu_vm_manager_fini(adev); 823 gmc_v11_0_gart_fini(adev); 824 amdgpu_gem_force_release(adev); 825 amdgpu_bo_fini(adev); 826 827 return 0; 828 } 829 830 static void gmc_v11_0_init_golden_registers(struct amdgpu_device *adev) 831 { 832 } 833 834 /** 835 * gmc_v11_0_gart_enable - gart enable 836 * 837 * @adev: amdgpu_device pointer 838 */ 839 static int gmc_v11_0_gart_enable(struct amdgpu_device *adev) 840 { 841 int r; 842 bool value; 843 844 if (adev->gart.bo == NULL) { 845 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 846 return -EINVAL; 847 } 848 849 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 850 851 r = adev->mmhub.funcs->gart_enable(adev); 852 if (r) 853 return r; 854 855 /* Flush HDP after it is initialized */ 856 adev->hdp.funcs->flush_hdp(adev, NULL); 857 858 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 859 false : true; 860 861 adev->mmhub.funcs->set_fault_enable_default(adev, value); 862 gmc_v11_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0); 863 864 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 865 (unsigned)(adev->gmc.gart_size >> 20), 866 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 867 868 return 0; 869 } 870 871 static int gmc_v11_0_hw_init(void *handle) 872 { 873 int r; 874 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 875 876 /* The sequence of these two function calls matters.*/ 877 gmc_v11_0_init_golden_registers(adev); 878 879 r = gmc_v11_0_gart_enable(adev); 880 if (r) 881 return r; 882 883 if (adev->umc.funcs && adev->umc.funcs->init_registers) 884 adev->umc.funcs->init_registers(adev); 885 886 return 0; 887 } 888 889 /** 890 * gmc_v11_0_gart_disable - gart disable 891 * 892 * @adev: amdgpu_device pointer 893 * 894 * This disables all VM page table. 895 */ 896 static void gmc_v11_0_gart_disable(struct amdgpu_device *adev) 897 { 898 adev->mmhub.funcs->gart_disable(adev); 899 } 900 901 static int gmc_v11_0_hw_fini(void *handle) 902 { 903 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 904 905 if (amdgpu_sriov_vf(adev)) { 906 /* full access mode, so don't touch any GMC register */ 907 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 908 return 0; 909 } 910 911 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 912 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 913 gmc_v11_0_gart_disable(adev); 914 915 return 0; 916 } 917 918 static int gmc_v11_0_suspend(void *handle) 919 { 920 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 921 922 gmc_v11_0_hw_fini(adev); 923 924 return 0; 925 } 926 927 static int gmc_v11_0_resume(void *handle) 928 { 929 int r; 930 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 931 932 r = gmc_v11_0_hw_init(adev); 933 if (r) 934 return r; 935 936 amdgpu_vmid_reset_all(adev); 937 938 return 0; 939 } 940 941 static bool gmc_v11_0_is_idle(void *handle) 942 { 943 /* MC is always ready in GMC v11.*/ 944 return true; 945 } 946 947 static int gmc_v11_0_wait_for_idle(void *handle) 948 { 949 /* There is no need to wait for MC idle in GMC v11.*/ 950 return 0; 951 } 952 953 static int gmc_v11_0_soft_reset(void *handle) 954 { 955 return 0; 956 } 957 958 static int gmc_v11_0_set_clockgating_state(void *handle, 959 enum amd_clockgating_state state) 960 { 961 int r; 962 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 963 964 r = adev->mmhub.funcs->set_clockgating(adev, state); 965 if (r) 966 return r; 967 968 return athub_v3_0_set_clockgating(adev, state); 969 } 970 971 static void gmc_v11_0_get_clockgating_state(void *handle, u64 *flags) 972 { 973 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 974 975 adev->mmhub.funcs->get_clockgating(adev, flags); 976 977 athub_v3_0_get_clockgating(adev, flags); 978 } 979 980 static int gmc_v11_0_set_powergating_state(void *handle, 981 enum amd_powergating_state state) 982 { 983 return 0; 984 } 985 986 const struct amd_ip_funcs gmc_v11_0_ip_funcs = { 987 .name = "gmc_v11_0", 988 .early_init = gmc_v11_0_early_init, 989 .sw_init = gmc_v11_0_sw_init, 990 .hw_init = gmc_v11_0_hw_init, 991 .late_init = gmc_v11_0_late_init, 992 .sw_fini = gmc_v11_0_sw_fini, 993 .hw_fini = gmc_v11_0_hw_fini, 994 .suspend = gmc_v11_0_suspend, 995 .resume = gmc_v11_0_resume, 996 .is_idle = gmc_v11_0_is_idle, 997 .wait_for_idle = gmc_v11_0_wait_for_idle, 998 .soft_reset = gmc_v11_0_soft_reset, 999 .set_clockgating_state = gmc_v11_0_set_clockgating_state, 1000 .set_powergating_state = gmc_v11_0_set_powergating_state, 1001 .get_clockgating_state = gmc_v11_0_get_clockgating_state, 1002 }; 1003 1004 const struct amdgpu_ip_block_version gmc_v11_0_ip_block = { 1005 .type = AMD_IP_BLOCK_TYPE_GMC, 1006 .major = 11, 1007 .minor = 0, 1008 .rev = 0, 1009 .funcs = &gmc_v11_0_ip_funcs, 1010 }; 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