1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 26 #include <drm/drm_cache.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atomfirmware.h" 30 #include "gmc_v10_0.h" 31 #include "umc_v8_7.h" 32 33 #include "athub/athub_2_0_0_sh_mask.h" 34 #include "athub/athub_2_0_0_offset.h" 35 #include "dcn/dcn_2_0_0_offset.h" 36 #include "dcn/dcn_2_0_0_sh_mask.h" 37 #include "oss/osssys_5_0_0_offset.h" 38 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 39 #include "navi10_enum.h" 40 41 #include "soc15.h" 42 #include "soc15d.h" 43 #include "soc15_common.h" 44 45 #include "nbio_v2_3.h" 46 47 #include "gfxhub_v2_0.h" 48 #include "gfxhub_v2_1.h" 49 #include "mmhub_v2_0.h" 50 #include "mmhub_v2_3.h" 51 #include "athub_v2_0.h" 52 #include "athub_v2_1.h" 53 54 #include "amdgpu_reset.h" 55 56 #if 0 57 static const struct soc15_reg_golden golden_settings_navi10_hdp[] = 58 { 59 /* TODO add golden setting for hdp */ 60 }; 61 #endif 62 63 static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev, 64 struct amdgpu_irq_src *src, 65 unsigned type, 66 enum amdgpu_interrupt_state state) 67 { 68 return 0; 69 } 70 71 static int 72 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 73 struct amdgpu_irq_src *src, unsigned type, 74 enum amdgpu_interrupt_state state) 75 { 76 switch (state) { 77 case AMDGPU_IRQ_STATE_DISABLE: 78 /* MM HUB */ 79 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false); 80 /* GFX HUB */ 81 /* This works because this interrupt is only 82 * enabled at init/resume and disabled in 83 * fini/suspend, so the overall state doesn't 84 * change over the course of suspend/resume. 85 */ 86 if (!adev->in_s0ix) 87 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false); 88 break; 89 case AMDGPU_IRQ_STATE_ENABLE: 90 /* MM HUB */ 91 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true); 92 /* GFX HUB */ 93 /* This works because this interrupt is only 94 * enabled at init/resume and disabled in 95 * fini/suspend, so the overall state doesn't 96 * change over the course of suspend/resume. 97 */ 98 if (!adev->in_s0ix) 99 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true); 100 break; 101 default: 102 break; 103 } 104 105 return 0; 106 } 107 108 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, 109 struct amdgpu_irq_src *source, 110 struct amdgpu_iv_entry *entry) 111 { 112 bool retry_fault = !!(entry->src_data[1] & 0x80); 113 bool write_fault = !!(entry->src_data[1] & 0x20); 114 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; 115 struct amdgpu_task_info task_info; 116 uint32_t status = 0; 117 u64 addr; 118 119 addr = (u64)entry->src_data[0] << 12; 120 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 121 122 if (retry_fault) { 123 /* Returning 1 here also prevents sending the IV to the KFD */ 124 125 /* Process it onyl if it's the first fault for this address */ 126 if (entry->ih != &adev->irq.ih_soft && 127 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, 128 entry->timestamp)) 129 return 1; 130 131 /* Delegate it to a different ring if the hardware hasn't 132 * already done it. 133 */ 134 if (entry->ih == &adev->irq.ih) { 135 amdgpu_irq_delegate(adev, entry, 8); 136 return 1; 137 } 138 139 /* Try to handle the recoverable page faults by filling page 140 * tables 141 */ 142 if (amdgpu_vm_handle_fault(adev, entry->pasid, addr, write_fault)) 143 return 1; 144 } 145 146 if (!amdgpu_sriov_vf(adev)) { 147 /* 148 * Issue a dummy read to wait for the status register to 149 * be updated to avoid reading an incorrect value due to 150 * the new fast GRBM interface. 151 */ 152 if ((entry->vmid_src == AMDGPU_GFXHUB_0) && 153 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0))) 154 RREG32(hub->vm_l2_pro_fault_status); 155 156 status = RREG32(hub->vm_l2_pro_fault_status); 157 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 158 } 159 160 if (!printk_ratelimit()) 161 return 0; 162 163 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 164 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 165 166 dev_err(adev->dev, 167 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, " 168 "for process %s pid %d thread %s pid %d)\n", 169 entry->vmid_src ? "mmhub" : "gfxhub", 170 entry->src_id, entry->ring_id, entry->vmid, 171 entry->pasid, task_info.process_name, task_info.tgid, 172 task_info.task_name, task_info.pid); 173 dev_err(adev->dev, " in page starting at address 0x%016llx from client 0x%x (%s)\n", 174 addr, entry->client_id, 175 soc15_ih_clientid_name[entry->client_id]); 176 177 if (!amdgpu_sriov_vf(adev)) 178 hub->vmhub_funcs->print_l2_protection_fault_status(adev, 179 status); 180 181 return 0; 182 } 183 184 static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = { 185 .set = gmc_v10_0_vm_fault_interrupt_state, 186 .process = gmc_v10_0_process_interrupt, 187 }; 188 189 static const struct amdgpu_irq_src_funcs gmc_v10_0_ecc_funcs = { 190 .set = gmc_v10_0_ecc_interrupt_state, 191 .process = amdgpu_umc_process_ecc_irq, 192 }; 193 194 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev) 195 { 196 adev->gmc.vm_fault.num_types = 1; 197 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs; 198 199 if (!amdgpu_sriov_vf(adev)) { 200 adev->gmc.ecc_irq.num_types = 1; 201 adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs; 202 } 203 } 204 205 /** 206 * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore 207 * 208 * @adev: amdgpu_device pointer 209 * @vmhub: vmhub type 210 * 211 */ 212 static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev, 213 uint32_t vmhub) 214 { 215 return ((vmhub == AMDGPU_MMHUB_0 || 216 vmhub == AMDGPU_MMHUB_1) && 217 (!amdgpu_sriov_vf(adev))); 218 } 219 220 static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info( 221 struct amdgpu_device *adev, 222 uint8_t vmid, uint16_t *p_pasid) 223 { 224 uint32_t value; 225 226 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 227 + vmid); 228 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 229 230 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 231 } 232 233 /* 234 * GART 235 * VMID 0 is the physical GPU addresses as used by the kernel. 236 * VMIDs 1-15 are used for userspace clients and are handled 237 * by the amdgpu vm/hsa code. 238 */ 239 240 static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 241 unsigned int vmhub, uint32_t flush_type) 242 { 243 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub); 244 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 245 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 246 u32 tmp; 247 /* Use register 17 for GART */ 248 const unsigned eng = 17; 249 unsigned int i; 250 unsigned char hub_ip = 0; 251 252 hub_ip = (vmhub == AMDGPU_GFXHUB_0) ? 253 GC_HWIP : MMHUB_HWIP; 254 255 spin_lock(&adev->gmc.invalidate_lock); 256 /* 257 * It may lose gpuvm invalidate acknowldege state across power-gating 258 * off cycle, add semaphore acquire before invalidation and semaphore 259 * release after invalidation to avoid entering power gated state 260 * to WA the Issue 261 */ 262 263 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 264 if (use_semaphore) { 265 for (i = 0; i < adev->usec_timeout; i++) { 266 /* a read return value of 1 means semaphore acuqire */ 267 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + 268 hub->eng_distance * eng, hub_ip); 269 270 if (tmp & 0x1) 271 break; 272 udelay(1); 273 } 274 275 if (i >= adev->usec_timeout) 276 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 277 } 278 279 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + 280 hub->eng_distance * eng, 281 inv_req, hub_ip); 282 283 /* 284 * Issue a dummy read to wait for the ACK register to be cleared 285 * to avoid a false ACK due to the new fast GRBM interface. 286 */ 287 if ((vmhub == AMDGPU_GFXHUB_0) && 288 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0))) 289 RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + 290 hub->eng_distance * eng, hub_ip); 291 292 /* Wait for ACK with a delay.*/ 293 for (i = 0; i < adev->usec_timeout; i++) { 294 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack + 295 hub->eng_distance * eng, hub_ip); 296 297 tmp &= 1 << vmid; 298 if (tmp) 299 break; 300 301 udelay(1); 302 } 303 304 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 305 if (use_semaphore) 306 /* 307 * add semaphore release after invalidation, 308 * write with 0 means semaphore release 309 */ 310 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + 311 hub->eng_distance * eng, 0, hub_ip); 312 313 spin_unlock(&adev->gmc.invalidate_lock); 314 315 if (i < adev->usec_timeout) 316 return; 317 318 DRM_ERROR("Timeout waiting for VM flush hub: %d!\n", vmhub); 319 } 320 321 /** 322 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback 323 * 324 * @adev: amdgpu_device pointer 325 * @vmid: vm instance to flush 326 * @vmhub: vmhub type 327 * @flush_type: the flush type 328 * 329 * Flush the TLB for the requested page table. 330 */ 331 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 332 uint32_t vmhub, uint32_t flush_type) 333 { 334 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 335 struct dma_fence *fence; 336 struct amdgpu_job *job; 337 338 int r; 339 340 /* flush hdp cache */ 341 adev->hdp.funcs->flush_hdp(adev, NULL); 342 343 /* For SRIOV run time, driver shouldn't access the register through MMIO 344 * Directly use kiq to do the vm invalidation instead 345 */ 346 if (adev->gfx.kiq.ring.sched.ready && !adev->enable_mes && 347 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && 348 down_read_trylock(&adev->reset_domain->sem)) { 349 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 350 const unsigned eng = 17; 351 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 352 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 353 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 354 355 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 356 1 << vmid); 357 358 up_read(&adev->reset_domain->sem); 359 return; 360 } 361 362 mutex_lock(&adev->mman.gtt_window_lock); 363 364 if (vmhub == AMDGPU_MMHUB_0) { 365 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0); 366 mutex_unlock(&adev->mman.gtt_window_lock); 367 return; 368 } 369 370 BUG_ON(vmhub != AMDGPU_GFXHUB_0); 371 372 if (!adev->mman.buffer_funcs_enabled || 373 !adev->ib_pool_ready || 374 amdgpu_in_reset(adev) || 375 ring->sched.ready == false) { 376 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0); 377 mutex_unlock(&adev->mman.gtt_window_lock); 378 return; 379 } 380 381 /* The SDMA on Navi has a bug which can theoretically result in memory 382 * corruption if an invalidation happens at the same time as an VA 383 * translation. Avoid this by doing the invalidation from the SDMA 384 * itself. 385 */ 386 r = amdgpu_job_alloc_with_ib(ring->adev, &adev->mman.entity, 387 AMDGPU_FENCE_OWNER_UNDEFINED, 388 16 * 4, AMDGPU_IB_POOL_IMMEDIATE, 389 &job); 390 if (r) 391 goto error_alloc; 392 393 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); 394 job->vm_needs_flush = true; 395 job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop; 396 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 397 fence = amdgpu_job_submit(job); 398 399 mutex_unlock(&adev->mman.gtt_window_lock); 400 401 dma_fence_wait(fence, false); 402 dma_fence_put(fence); 403 404 return; 405 406 error_alloc: 407 mutex_unlock(&adev->mman.gtt_window_lock); 408 DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r); 409 } 410 411 /** 412 * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid 413 * 414 * @adev: amdgpu_device pointer 415 * @pasid: pasid to be flush 416 * @flush_type: the flush type 417 * @all_hub: Used with PACKET3_INVALIDATE_TLBS_ALL_HUB() 418 * 419 * Flush the TLB for the requested pasid. 420 */ 421 static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 422 uint16_t pasid, uint32_t flush_type, 423 bool all_hub) 424 { 425 int vmid, i; 426 signed long r; 427 uint32_t seq; 428 uint16_t queried_pasid; 429 bool ret; 430 u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT : adev->usec_timeout; 431 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 432 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 433 434 if (amdgpu_emu_mode == 0 && ring->sched.ready) { 435 spin_lock(&adev->gfx.kiq.ring_lock); 436 /* 2 dwords flush + 8 dwords fence */ 437 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8); 438 kiq->pmf->kiq_invalidate_tlbs(ring, 439 pasid, flush_type, all_hub); 440 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 441 if (r) { 442 amdgpu_ring_undo(ring); 443 spin_unlock(&adev->gfx.kiq.ring_lock); 444 return -ETIME; 445 } 446 447 amdgpu_ring_commit(ring); 448 spin_unlock(&adev->gfx.kiq.ring_lock); 449 r = amdgpu_fence_wait_polling(ring, seq, usec_timeout); 450 if (r < 1) { 451 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r); 452 return -ETIME; 453 } 454 455 return 0; 456 } 457 458 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 459 460 ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 461 &queried_pasid); 462 if (ret && queried_pasid == pasid) { 463 if (all_hub) { 464 for (i = 0; i < adev->num_vmhubs; i++) 465 gmc_v10_0_flush_gpu_tlb(adev, vmid, 466 i, flush_type); 467 } else { 468 gmc_v10_0_flush_gpu_tlb(adev, vmid, 469 AMDGPU_GFXHUB_0, flush_type); 470 } 471 if (!adev->enable_mes) 472 break; 473 } 474 } 475 476 return 0; 477 } 478 479 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 480 unsigned vmid, uint64_t pd_addr) 481 { 482 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 483 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 484 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 485 unsigned eng = ring->vm_inv_eng; 486 487 /* 488 * It may lose gpuvm invalidate acknowldege state across power-gating 489 * off cycle, add semaphore acquire before invalidation and semaphore 490 * release after invalidation to avoid entering power gated state 491 * to WA the Issue 492 */ 493 494 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 495 if (use_semaphore) 496 /* a read return value of 1 means semaphore acuqire */ 497 amdgpu_ring_emit_reg_wait(ring, 498 hub->vm_inv_eng0_sem + 499 hub->eng_distance * eng, 0x1, 0x1); 500 501 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 502 (hub->ctx_addr_distance * vmid), 503 lower_32_bits(pd_addr)); 504 505 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 506 (hub->ctx_addr_distance * vmid), 507 upper_32_bits(pd_addr)); 508 509 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 510 hub->eng_distance * eng, 511 hub->vm_inv_eng0_ack + 512 hub->eng_distance * eng, 513 req, 1 << vmid); 514 515 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 516 if (use_semaphore) 517 /* 518 * add semaphore release after invalidation, 519 * write with 0 means semaphore release 520 */ 521 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 522 hub->eng_distance * eng, 0); 523 524 return pd_addr; 525 } 526 527 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 528 unsigned pasid) 529 { 530 struct amdgpu_device *adev = ring->adev; 531 uint32_t reg; 532 533 /* MES fw manages IH_VMID_x_LUT updating */ 534 if (ring->is_mes_queue) 535 return; 536 537 if (ring->vm_hub == AMDGPU_GFXHUB_0) 538 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 539 else 540 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 541 542 amdgpu_ring_emit_wreg(ring, reg, pasid); 543 } 544 545 /* 546 * PTE format on NAVI 10: 547 * 63:59 reserved 548 * 58 reserved and for sienna_cichlid is used for MALL noalloc 549 * 57 reserved 550 * 56 F 551 * 55 L 552 * 54 reserved 553 * 53:52 SW 554 * 51 T 555 * 50:48 mtype 556 * 47:12 4k physical page base address 557 * 11:7 fragment 558 * 6 write 559 * 5 read 560 * 4 exe 561 * 3 Z 562 * 2 snooped 563 * 1 system 564 * 0 valid 565 * 566 * PDE format on NAVI 10: 567 * 63:59 block fragment size 568 * 58:55 reserved 569 * 54 P 570 * 53:48 reserved 571 * 47:6 physical base address of PD or PTE 572 * 5:3 reserved 573 * 2 C 574 * 1 system 575 * 0 valid 576 */ 577 578 static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 579 { 580 switch (flags) { 581 case AMDGPU_VM_MTYPE_DEFAULT: 582 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 583 case AMDGPU_VM_MTYPE_NC: 584 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 585 case AMDGPU_VM_MTYPE_WC: 586 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC); 587 case AMDGPU_VM_MTYPE_CC: 588 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC); 589 case AMDGPU_VM_MTYPE_UC: 590 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 591 default: 592 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 593 } 594 } 595 596 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level, 597 uint64_t *addr, uint64_t *flags) 598 { 599 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 600 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 601 BUG_ON(*addr & 0xFFFF00000000003FULL); 602 603 if (!adev->gmc.translate_further) 604 return; 605 606 if (level == AMDGPU_VM_PDB1) { 607 /* Set the block fragment size */ 608 if (!(*flags & AMDGPU_PDE_PTE)) 609 *flags |= AMDGPU_PDE_BFS(0x9); 610 611 } else if (level == AMDGPU_VM_PDB0) { 612 if (*flags & AMDGPU_PDE_PTE) 613 *flags &= ~AMDGPU_PDE_PTE; 614 else 615 *flags |= AMDGPU_PTE_TF; 616 } 617 } 618 619 static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev, 620 struct amdgpu_bo_va_mapping *mapping, 621 uint64_t *flags) 622 { 623 struct amdgpu_bo *bo = mapping->bo_va->base.bo; 624 625 *flags &= ~AMDGPU_PTE_EXECUTABLE; 626 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 627 628 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; 629 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); 630 631 *flags &= ~AMDGPU_PTE_NOALLOC; 632 *flags |= (mapping->flags & AMDGPU_PTE_NOALLOC); 633 634 if (mapping->flags & AMDGPU_PTE_PRT) { 635 *flags |= AMDGPU_PTE_PRT; 636 *flags |= AMDGPU_PTE_SNOOPED; 637 *flags |= AMDGPU_PTE_LOG; 638 *flags |= AMDGPU_PTE_SYSTEM; 639 *flags &= ~AMDGPU_PTE_VALID; 640 } 641 642 if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT | 643 AMDGPU_GEM_CREATE_UNCACHED)) 644 *flags = (*flags & ~AMDGPU_PTE_MTYPE_NV10_MASK) | 645 AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 646 } 647 648 static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev) 649 { 650 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 651 unsigned size; 652 653 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 654 size = AMDGPU_VBIOS_VGA_ALLOCATION; 655 } else { 656 u32 viewport; 657 u32 pitch; 658 659 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 660 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH); 661 size = (REG_GET_FIELD(viewport, 662 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 663 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) * 664 4); 665 } 666 667 return size; 668 } 669 670 static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = { 671 .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb, 672 .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid, 673 .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb, 674 .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping, 675 .map_mtype = gmc_v10_0_map_mtype, 676 .get_vm_pde = gmc_v10_0_get_vm_pde, 677 .get_vm_pte = gmc_v10_0_get_vm_pte, 678 .get_vbios_fb_size = gmc_v10_0_get_vbios_fb_size, 679 }; 680 681 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev) 682 { 683 if (adev->gmc.gmc_funcs == NULL) 684 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs; 685 } 686 687 static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev) 688 { 689 switch (adev->ip_versions[UMC_HWIP][0]) { 690 case IP_VERSION(8, 7, 0): 691 adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM; 692 adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM; 693 adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM; 694 adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA; 695 adev->umc.retire_unit = 1; 696 adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0]; 697 adev->umc.ras = &umc_v8_7_ras; 698 break; 699 default: 700 break; 701 } 702 } 703 704 static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev) 705 { 706 switch (adev->ip_versions[MMHUB_HWIP][0]) { 707 case IP_VERSION(2, 3, 0): 708 case IP_VERSION(2, 4, 0): 709 case IP_VERSION(2, 4, 1): 710 adev->mmhub.funcs = &mmhub_v2_3_funcs; 711 break; 712 default: 713 adev->mmhub.funcs = &mmhub_v2_0_funcs; 714 break; 715 } 716 } 717 718 static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev) 719 { 720 switch (adev->ip_versions[GC_HWIP][0]) { 721 case IP_VERSION(10, 3, 0): 722 case IP_VERSION(10, 3, 2): 723 case IP_VERSION(10, 3, 1): 724 case IP_VERSION(10, 3, 4): 725 case IP_VERSION(10, 3, 5): 726 case IP_VERSION(10, 3, 6): 727 case IP_VERSION(10, 3, 3): 728 case IP_VERSION(10, 3, 7): 729 adev->gfxhub.funcs = &gfxhub_v2_1_funcs; 730 break; 731 default: 732 adev->gfxhub.funcs = &gfxhub_v2_0_funcs; 733 break; 734 } 735 } 736 737 738 static int gmc_v10_0_early_init(void *handle) 739 { 740 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 741 742 gmc_v10_0_set_mmhub_funcs(adev); 743 gmc_v10_0_set_gfxhub_funcs(adev); 744 gmc_v10_0_set_gmc_funcs(adev); 745 gmc_v10_0_set_irq_funcs(adev); 746 gmc_v10_0_set_umc_funcs(adev); 747 748 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 749 adev->gmc.shared_aperture_end = 750 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 751 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 752 adev->gmc.private_aperture_end = 753 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 754 755 return 0; 756 } 757 758 static int gmc_v10_0_late_init(void *handle) 759 { 760 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 761 int r; 762 763 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 764 if (r) 765 return r; 766 767 r = amdgpu_gmc_ras_late_init(adev); 768 if (r) 769 return r; 770 771 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 772 } 773 774 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev, 775 struct amdgpu_gmc *mc) 776 { 777 u64 base = 0; 778 779 base = adev->gfxhub.funcs->get_fb_location(adev); 780 781 /* add the xgmi offset of the physical node */ 782 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 783 784 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 785 amdgpu_gmc_gart_location(adev, mc); 786 amdgpu_gmc_agp_location(adev, mc); 787 788 /* base offset of vram pages */ 789 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 790 791 /* add the xgmi offset of the physical node */ 792 adev->vm_manager.vram_base_offset += 793 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 794 } 795 796 /** 797 * gmc_v10_0_mc_init - initialize the memory controller driver params 798 * 799 * @adev: amdgpu_device pointer 800 * 801 * Look up the amount of vram, vram width, and decide how to place 802 * vram and gart within the GPU's physical address space. 803 * Returns 0 for success. 804 */ 805 static int gmc_v10_0_mc_init(struct amdgpu_device *adev) 806 { 807 int r; 808 809 /* size in MB on si */ 810 adev->gmc.mc_vram_size = 811 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 812 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 813 814 if (!(adev->flags & AMD_IS_APU)) { 815 r = amdgpu_device_resize_fb_bar(adev); 816 if (r) 817 return r; 818 } 819 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 820 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 821 822 #ifdef CONFIG_X86_64 823 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { 824 adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev); 825 adev->gmc.aper_size = adev->gmc.real_vram_size; 826 } 827 #endif 828 829 adev->gmc.visible_vram_size = adev->gmc.aper_size; 830 831 /* set the gart size */ 832 if (amdgpu_gart_size == -1) { 833 switch (adev->ip_versions[GC_HWIP][0]) { 834 default: 835 adev->gmc.gart_size = 512ULL << 20; 836 break; 837 case IP_VERSION(10, 3, 1): /* DCE SG support */ 838 case IP_VERSION(10, 3, 3): /* DCE SG support */ 839 case IP_VERSION(10, 3, 6): /* DCE SG support */ 840 case IP_VERSION(10, 3, 7): /* DCE SG support */ 841 adev->gmc.gart_size = 1024ULL << 20; 842 break; 843 } 844 } else { 845 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 846 } 847 848 gmc_v10_0_vram_gtt_location(adev, &adev->gmc); 849 850 return 0; 851 } 852 853 static int gmc_v10_0_gart_init(struct amdgpu_device *adev) 854 { 855 int r; 856 857 if (adev->gart.bo) { 858 WARN(1, "NAVI10 PCIE GART already initialized\n"); 859 return 0; 860 } 861 862 /* Initialize common gart structure */ 863 r = amdgpu_gart_init(adev); 864 if (r) 865 return r; 866 867 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 868 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) | 869 AMDGPU_PTE_EXECUTABLE; 870 871 return amdgpu_gart_table_vram_alloc(adev); 872 } 873 874 static int gmc_v10_0_sw_init(void *handle) 875 { 876 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 877 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 878 879 adev->gfxhub.funcs->init(adev); 880 881 adev->mmhub.funcs->init(adev); 882 883 spin_lock_init(&adev->gmc.invalidate_lock); 884 885 if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) { 886 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; 887 adev->gmc.vram_width = 64; 888 } else if (amdgpu_emu_mode == 1) { 889 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6; 890 adev->gmc.vram_width = 1 * 128; /* numchan * chansize */ 891 } else { 892 r = amdgpu_atomfirmware_get_vram_info(adev, 893 &vram_width, &vram_type, &vram_vendor); 894 adev->gmc.vram_width = vram_width; 895 896 adev->gmc.vram_type = vram_type; 897 adev->gmc.vram_vendor = vram_vendor; 898 } 899 900 switch (adev->ip_versions[GC_HWIP][0]) { 901 case IP_VERSION(10, 3, 0): 902 adev->gmc.mall_size = 128 * 1024 * 1024; 903 break; 904 case IP_VERSION(10, 3, 2): 905 adev->gmc.mall_size = 96 * 1024 * 1024; 906 break; 907 case IP_VERSION(10, 3, 4): 908 adev->gmc.mall_size = 32 * 1024 * 1024; 909 break; 910 case IP_VERSION(10, 3, 5): 911 adev->gmc.mall_size = 16 * 1024 * 1024; 912 break; 913 default: 914 adev->gmc.mall_size = 0; 915 break; 916 } 917 918 switch (adev->ip_versions[GC_HWIP][0]) { 919 case IP_VERSION(10, 1, 10): 920 case IP_VERSION(10, 1, 1): 921 case IP_VERSION(10, 1, 2): 922 case IP_VERSION(10, 1, 3): 923 case IP_VERSION(10, 1, 4): 924 case IP_VERSION(10, 3, 0): 925 case IP_VERSION(10, 3, 2): 926 case IP_VERSION(10, 3, 1): 927 case IP_VERSION(10, 3, 4): 928 case IP_VERSION(10, 3, 5): 929 case IP_VERSION(10, 3, 6): 930 case IP_VERSION(10, 3, 3): 931 case IP_VERSION(10, 3, 7): 932 adev->num_vmhubs = 2; 933 /* 934 * To fulfill 4-level page support, 935 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12, 936 * block size 512 (9bit) 937 */ 938 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 939 break; 940 default: 941 break; 942 } 943 944 /* This interrupt is VMC page fault.*/ 945 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, 946 VMC_1_0__SRCID__VM_FAULT, 947 &adev->gmc.vm_fault); 948 949 if (r) 950 return r; 951 952 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, 953 UTCL2_1_0__SRCID__FAULT, 954 &adev->gmc.vm_fault); 955 if (r) 956 return r; 957 958 if (!amdgpu_sriov_vf(adev)) { 959 /* interrupt sent to DF. */ 960 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 961 &adev->gmc.ecc_irq); 962 if (r) 963 return r; 964 } 965 966 /* 967 * Set the internal MC address mask This is the max address of the GPU's 968 * internal address space. 969 */ 970 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 971 972 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 973 if (r) { 974 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 975 return r; 976 } 977 978 adev->need_swiotlb = drm_need_swiotlb(44); 979 980 r = gmc_v10_0_mc_init(adev); 981 if (r) 982 return r; 983 984 amdgpu_gmc_get_vbios_allocations(adev); 985 986 /* Memory manager */ 987 r = amdgpu_bo_init(adev); 988 if (r) 989 return r; 990 991 r = gmc_v10_0_gart_init(adev); 992 if (r) 993 return r; 994 995 /* 996 * number of VMs 997 * VMID 0 is reserved for System 998 * amdgpu graphics/compute will use VMIDs 1-7 999 * amdkfd will use VMIDs 8-15 1000 */ 1001 adev->vm_manager.first_kfd_vmid = 8; 1002 1003 amdgpu_vm_manager_init(adev); 1004 1005 r = amdgpu_gmc_ras_sw_init(adev); 1006 if (r) 1007 return r; 1008 1009 return 0; 1010 } 1011 1012 /** 1013 * gmc_v10_0_gart_fini - vm fini callback 1014 * 1015 * @adev: amdgpu_device pointer 1016 * 1017 * Tears down the driver GART/VM setup (CIK). 1018 */ 1019 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev) 1020 { 1021 amdgpu_gart_table_vram_free(adev); 1022 } 1023 1024 static int gmc_v10_0_sw_fini(void *handle) 1025 { 1026 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1027 1028 amdgpu_vm_manager_fini(adev); 1029 gmc_v10_0_gart_fini(adev); 1030 amdgpu_gem_force_release(adev); 1031 amdgpu_bo_fini(adev); 1032 1033 return 0; 1034 } 1035 1036 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev) 1037 { 1038 } 1039 1040 /** 1041 * gmc_v10_0_gart_enable - gart enable 1042 * 1043 * @adev: amdgpu_device pointer 1044 */ 1045 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) 1046 { 1047 int r; 1048 bool value; 1049 1050 if (adev->gart.bo == NULL) { 1051 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 1052 return -EINVAL; 1053 } 1054 1055 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 1056 1057 if (!adev->in_s0ix) { 1058 r = adev->gfxhub.funcs->gart_enable(adev); 1059 if (r) 1060 return r; 1061 } 1062 1063 r = adev->mmhub.funcs->gart_enable(adev); 1064 if (r) 1065 return r; 1066 1067 adev->hdp.funcs->init_registers(adev); 1068 1069 /* Flush HDP after it is initialized */ 1070 adev->hdp.funcs->flush_hdp(adev, NULL); 1071 1072 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 1073 false : true; 1074 1075 if (!adev->in_s0ix) 1076 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 1077 adev->mmhub.funcs->set_fault_enable_default(adev, value); 1078 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0); 1079 if (!adev->in_s0ix) 1080 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0); 1081 1082 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1083 (unsigned)(adev->gmc.gart_size >> 20), 1084 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 1085 1086 return 0; 1087 } 1088 1089 static int gmc_v10_0_hw_init(void *handle) 1090 { 1091 int r; 1092 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1093 1094 /* The sequence of these two function calls matters.*/ 1095 gmc_v10_0_init_golden_registers(adev); 1096 1097 /* 1098 * harvestable groups in gc_utcl2 need to be programmed before any GFX block 1099 * register setup within GMC, or else system hang when harvesting SA. 1100 */ 1101 if (!adev->in_s0ix && adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest) 1102 adev->gfxhub.funcs->utcl2_harvest(adev); 1103 1104 r = gmc_v10_0_gart_enable(adev); 1105 if (r) 1106 return r; 1107 1108 if (amdgpu_emu_mode == 1) { 1109 r = amdgpu_gmc_vram_checking(adev); 1110 if (r) 1111 return r; 1112 } 1113 1114 if (adev->umc.funcs && adev->umc.funcs->init_registers) 1115 adev->umc.funcs->init_registers(adev); 1116 1117 return 0; 1118 } 1119 1120 /** 1121 * gmc_v10_0_gart_disable - gart disable 1122 * 1123 * @adev: amdgpu_device pointer 1124 * 1125 * This disables all VM page table. 1126 */ 1127 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev) 1128 { 1129 if (!adev->in_s0ix) 1130 adev->gfxhub.funcs->gart_disable(adev); 1131 adev->mmhub.funcs->gart_disable(adev); 1132 } 1133 1134 static int gmc_v10_0_hw_fini(void *handle) 1135 { 1136 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1137 1138 gmc_v10_0_gart_disable(adev); 1139 1140 if (amdgpu_sriov_vf(adev)) { 1141 /* full access mode, so don't touch any GMC register */ 1142 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 1143 return 0; 1144 } 1145 1146 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1147 1148 return 0; 1149 } 1150 1151 static int gmc_v10_0_suspend(void *handle) 1152 { 1153 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1154 1155 gmc_v10_0_hw_fini(adev); 1156 1157 return 0; 1158 } 1159 1160 static int gmc_v10_0_resume(void *handle) 1161 { 1162 int r; 1163 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1164 1165 r = gmc_v10_0_hw_init(adev); 1166 if (r) 1167 return r; 1168 1169 amdgpu_vmid_reset_all(adev); 1170 1171 return 0; 1172 } 1173 1174 static bool gmc_v10_0_is_idle(void *handle) 1175 { 1176 /* MC is always ready in GMC v10.*/ 1177 return true; 1178 } 1179 1180 static int gmc_v10_0_wait_for_idle(void *handle) 1181 { 1182 /* There is no need to wait for MC idle in GMC v10.*/ 1183 return 0; 1184 } 1185 1186 static int gmc_v10_0_soft_reset(void *handle) 1187 { 1188 return 0; 1189 } 1190 1191 static int gmc_v10_0_set_clockgating_state(void *handle, 1192 enum amd_clockgating_state state) 1193 { 1194 int r; 1195 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1196 1197 /* 1198 * The issue mmhub can't disconnect from DF with MMHUB clock gating being disabled 1199 * is a new problem observed at DF 3.0.3, however with the same suspend sequence not 1200 * seen any issue on the DF 3.0.2 series platform. 1201 */ 1202 if (adev->in_s0ix && adev->ip_versions[DF_HWIP][0] > IP_VERSION(3, 0, 2)) { 1203 dev_dbg(adev->dev, "keep mmhub clock gating being enabled for s0ix\n"); 1204 return 0; 1205 } 1206 1207 r = adev->mmhub.funcs->set_clockgating(adev, state); 1208 if (r) 1209 return r; 1210 1211 if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0)) 1212 return athub_v2_1_set_clockgating(adev, state); 1213 else 1214 return athub_v2_0_set_clockgating(adev, state); 1215 } 1216 1217 static void gmc_v10_0_get_clockgating_state(void *handle, u64 *flags) 1218 { 1219 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1220 1221 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 3) || 1222 adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 4)) 1223 return; 1224 1225 adev->mmhub.funcs->get_clockgating(adev, flags); 1226 1227 if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0)) 1228 athub_v2_1_get_clockgating(adev, flags); 1229 else 1230 athub_v2_0_get_clockgating(adev, flags); 1231 } 1232 1233 static int gmc_v10_0_set_powergating_state(void *handle, 1234 enum amd_powergating_state state) 1235 { 1236 return 0; 1237 } 1238 1239 const struct amd_ip_funcs gmc_v10_0_ip_funcs = { 1240 .name = "gmc_v10_0", 1241 .early_init = gmc_v10_0_early_init, 1242 .late_init = gmc_v10_0_late_init, 1243 .sw_init = gmc_v10_0_sw_init, 1244 .sw_fini = gmc_v10_0_sw_fini, 1245 .hw_init = gmc_v10_0_hw_init, 1246 .hw_fini = gmc_v10_0_hw_fini, 1247 .suspend = gmc_v10_0_suspend, 1248 .resume = gmc_v10_0_resume, 1249 .is_idle = gmc_v10_0_is_idle, 1250 .wait_for_idle = gmc_v10_0_wait_for_idle, 1251 .soft_reset = gmc_v10_0_soft_reset, 1252 .set_clockgating_state = gmc_v10_0_set_clockgating_state, 1253 .set_powergating_state = gmc_v10_0_set_powergating_state, 1254 .get_clockgating_state = gmc_v10_0_get_clockgating_state, 1255 }; 1256 1257 const struct amdgpu_ip_block_version gmc_v10_0_ip_block = 1258 { 1259 .type = AMD_IP_BLOCK_TYPE_GMC, 1260 .major = 10, 1261 .minor = 0, 1262 .rev = 0, 1263 .funcs = &gmc_v10_0_ip_funcs, 1264 }; 1265