1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 #include "amdgpu.h" 26 #include "amdgpu_atomfirmware.h" 27 #include "gmc_v10_0.h" 28 29 #include "hdp/hdp_5_0_0_offset.h" 30 #include "hdp/hdp_5_0_0_sh_mask.h" 31 #include "gc/gc_10_1_0_sh_mask.h" 32 #include "mmhub/mmhub_2_0_0_sh_mask.h" 33 #include "dcn/dcn_2_0_0_offset.h" 34 #include "dcn/dcn_2_0_0_sh_mask.h" 35 #include "oss/osssys_5_0_0_offset.h" 36 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 37 #include "navi10_enum.h" 38 39 #include "soc15.h" 40 #include "soc15_common.h" 41 42 #include "nbio_v2_3.h" 43 44 #include "gfxhub_v2_0.h" 45 #include "mmhub_v2_0.h" 46 #include "athub_v2_0.h" 47 /* XXX Move this macro to navi10 header file, which is like vid.h for VI.*/ 48 #define AMDGPU_NUM_OF_VMIDS 8 49 50 #if 0 51 static const struct soc15_reg_golden golden_settings_navi10_hdp[] = 52 { 53 /* TODO add golden setting for hdp */ 54 }; 55 #endif 56 57 static int 58 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 59 struct amdgpu_irq_src *src, unsigned type, 60 enum amdgpu_interrupt_state state) 61 { 62 struct amdgpu_vmhub *hub; 63 u32 tmp, reg, bits[AMDGPU_MAX_VMHUBS], i; 64 65 bits[AMDGPU_GFXHUB_0] = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 66 GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 67 GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 68 GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 69 GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 70 GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 71 GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 72 73 bits[AMDGPU_MMHUB_0] = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 74 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 75 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 76 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 77 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 78 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 79 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 80 81 switch (state) { 82 case AMDGPU_IRQ_STATE_DISABLE: 83 /* MM HUB */ 84 hub = &adev->vmhub[AMDGPU_MMHUB_0]; 85 for (i = 0; i < 16; i++) { 86 reg = hub->vm_context0_cntl + i; 87 tmp = RREG32(reg); 88 tmp &= ~bits[AMDGPU_MMHUB_0]; 89 WREG32(reg, tmp); 90 } 91 92 /* GFX HUB */ 93 hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 94 for (i = 0; i < 16; i++) { 95 reg = hub->vm_context0_cntl + i; 96 tmp = RREG32(reg); 97 tmp &= ~bits[AMDGPU_GFXHUB_0]; 98 WREG32(reg, tmp); 99 } 100 break; 101 case AMDGPU_IRQ_STATE_ENABLE: 102 /* MM HUB */ 103 hub = &adev->vmhub[AMDGPU_MMHUB_0]; 104 for (i = 0; i < 16; i++) { 105 reg = hub->vm_context0_cntl + i; 106 tmp = RREG32(reg); 107 tmp |= bits[AMDGPU_MMHUB_0]; 108 WREG32(reg, tmp); 109 } 110 111 /* GFX HUB */ 112 hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 113 for (i = 0; i < 16; i++) { 114 reg = hub->vm_context0_cntl + i; 115 tmp = RREG32(reg); 116 tmp |= bits[AMDGPU_GFXHUB_0]; 117 WREG32(reg, tmp); 118 } 119 break; 120 default: 121 break; 122 } 123 124 return 0; 125 } 126 127 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, 128 struct amdgpu_irq_src *source, 129 struct amdgpu_iv_entry *entry) 130 { 131 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; 132 uint32_t status = 0; 133 u64 addr; 134 135 addr = (u64)entry->src_data[0] << 12; 136 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 137 138 if (!amdgpu_sriov_vf(adev)) { 139 /* 140 * Issue a dummy read to wait for the status register to 141 * be updated to avoid reading an incorrect value due to 142 * the new fast GRBM interface. 143 */ 144 if (entry->vmid_src == AMDGPU_GFXHUB_0) 145 RREG32(hub->vm_l2_pro_fault_status); 146 147 status = RREG32(hub->vm_l2_pro_fault_status); 148 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 149 } 150 151 if (printk_ratelimit()) { 152 struct amdgpu_task_info task_info; 153 154 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 155 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 156 157 dev_err(adev->dev, 158 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, " 159 "for process %s pid %d thread %s pid %d)\n", 160 entry->vmid_src ? "mmhub" : "gfxhub", 161 entry->src_id, entry->ring_id, entry->vmid, 162 entry->pasid, task_info.process_name, task_info.tgid, 163 task_info.task_name, task_info.pid); 164 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", 165 addr, entry->client_id); 166 if (!amdgpu_sriov_vf(adev)) { 167 dev_err(adev->dev, 168 "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 169 status); 170 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 171 REG_GET_FIELD(status, 172 GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 173 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 174 REG_GET_FIELD(status, 175 GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 176 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 177 REG_GET_FIELD(status, 178 GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 179 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 180 REG_GET_FIELD(status, 181 GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 182 dev_err(adev->dev, "\t RW: 0x%lx\n", 183 REG_GET_FIELD(status, 184 GCVM_L2_PROTECTION_FAULT_STATUS, RW)); 185 } 186 } 187 188 return 0; 189 } 190 191 static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = { 192 .set = gmc_v10_0_vm_fault_interrupt_state, 193 .process = gmc_v10_0_process_interrupt, 194 }; 195 196 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev) 197 { 198 adev->gmc.vm_fault.num_types = 1; 199 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs; 200 } 201 202 static uint32_t gmc_v10_0_get_invalidate_req(unsigned int vmid, 203 uint32_t flush_type) 204 { 205 u32 req = 0; 206 207 /* invalidate using legacy mode on vmid*/ 208 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 209 PER_VMID_INVALIDATE_REQ, 1 << vmid); 210 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 211 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 212 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 213 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 214 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 215 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 216 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 217 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 218 219 return req; 220 } 221 222 /* 223 * GART 224 * VMID 0 is the physical GPU addresses as used by the kernel. 225 * VMIDs 1-15 are used for userspace clients and are handled 226 * by the amdgpu vm/hsa code. 227 */ 228 229 static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 230 unsigned int vmhub, uint32_t flush_type) 231 { 232 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 233 u32 tmp = gmc_v10_0_get_invalidate_req(vmid, flush_type); 234 /* Use register 17 for GART */ 235 const unsigned eng = 17; 236 unsigned int i; 237 238 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp); 239 240 /* 241 * Issue a dummy read to wait for the ACK register to be cleared 242 * to avoid a false ACK due to the new fast GRBM interface. 243 */ 244 if (vmhub == AMDGPU_GFXHUB_0) 245 RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng); 246 247 /* Wait for ACK with a delay.*/ 248 for (i = 0; i < adev->usec_timeout; i++) { 249 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); 250 tmp &= 1 << vmid; 251 if (tmp) 252 break; 253 254 udelay(1); 255 } 256 257 if (i < adev->usec_timeout) 258 return; 259 260 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 261 } 262 263 /** 264 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback 265 * 266 * @adev: amdgpu_device pointer 267 * @vmid: vm instance to flush 268 * 269 * Flush the TLB for the requested page table. 270 */ 271 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 272 uint32_t vmhub, uint32_t flush_type) 273 { 274 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 275 struct dma_fence *fence; 276 struct amdgpu_job *job; 277 278 int r; 279 280 /* flush hdp cache */ 281 adev->nbio_funcs->hdp_flush(adev, NULL); 282 283 mutex_lock(&adev->mman.gtt_window_lock); 284 285 if (vmhub == AMDGPU_MMHUB_0) { 286 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0); 287 mutex_unlock(&adev->mman.gtt_window_lock); 288 return; 289 } 290 291 BUG_ON(vmhub != AMDGPU_GFXHUB_0); 292 293 if (!adev->mman.buffer_funcs_enabled || 294 !adev->ib_pool_ready || 295 adev->in_gpu_reset) { 296 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0); 297 mutex_unlock(&adev->mman.gtt_window_lock); 298 return; 299 } 300 301 /* The SDMA on Navi has a bug which can theoretically result in memory 302 * corruption if an invalidation happens at the same time as an VA 303 * translation. Avoid this by doing the invalidation from the SDMA 304 * itself. 305 */ 306 r = amdgpu_job_alloc_with_ib(adev, 16 * 4, &job); 307 if (r) 308 goto error_alloc; 309 310 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); 311 job->vm_needs_flush = true; 312 job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop; 313 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 314 r = amdgpu_job_submit(job, &adev->mman.entity, 315 AMDGPU_FENCE_OWNER_UNDEFINED, &fence); 316 if (r) 317 goto error_submit; 318 319 mutex_unlock(&adev->mman.gtt_window_lock); 320 321 dma_fence_wait(fence, false); 322 dma_fence_put(fence); 323 324 return; 325 326 error_submit: 327 amdgpu_job_free(job); 328 329 error_alloc: 330 mutex_unlock(&adev->mman.gtt_window_lock); 331 DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r); 332 } 333 334 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 335 unsigned vmid, uint64_t pd_addr) 336 { 337 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 338 uint32_t req = gmc_v10_0_get_invalidate_req(vmid, 0); 339 unsigned eng = ring->vm_inv_eng; 340 341 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid), 342 lower_32_bits(pd_addr)); 343 344 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid), 345 upper_32_bits(pd_addr)); 346 347 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_req + eng, req); 348 349 /* wait for the invalidate to complete */ 350 amdgpu_ring_emit_reg_wait(ring, hub->vm_inv_eng0_ack + eng, 351 1 << vmid, 1 << vmid); 352 353 return pd_addr; 354 } 355 356 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 357 unsigned pasid) 358 { 359 struct amdgpu_device *adev = ring->adev; 360 uint32_t reg; 361 362 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) 363 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 364 else 365 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 366 367 amdgpu_ring_emit_wreg(ring, reg, pasid); 368 } 369 370 /* 371 * PTE format on NAVI 10: 372 * 63:59 reserved 373 * 58:57 reserved 374 * 56 F 375 * 55 L 376 * 54 reserved 377 * 53:52 SW 378 * 51 T 379 * 50:48 mtype 380 * 47:12 4k physical page base address 381 * 11:7 fragment 382 * 6 write 383 * 5 read 384 * 4 exe 385 * 3 Z 386 * 2 snooped 387 * 1 system 388 * 0 valid 389 * 390 * PDE format on NAVI 10: 391 * 63:59 block fragment size 392 * 58:55 reserved 393 * 54 P 394 * 53:48 reserved 395 * 47:6 physical base address of PD or PTE 396 * 5:3 reserved 397 * 2 C 398 * 1 system 399 * 0 valid 400 */ 401 static uint64_t gmc_v10_0_get_vm_pte_flags(struct amdgpu_device *adev, 402 uint32_t flags) 403 { 404 uint64_t pte_flag = 0; 405 406 if (flags & AMDGPU_VM_PAGE_EXECUTABLE) 407 pte_flag |= AMDGPU_PTE_EXECUTABLE; 408 if (flags & AMDGPU_VM_PAGE_READABLE) 409 pte_flag |= AMDGPU_PTE_READABLE; 410 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 411 pte_flag |= AMDGPU_PTE_WRITEABLE; 412 413 switch (flags & AMDGPU_VM_MTYPE_MASK) { 414 case AMDGPU_VM_MTYPE_DEFAULT: 415 pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 416 break; 417 case AMDGPU_VM_MTYPE_NC: 418 pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 419 break; 420 case AMDGPU_VM_MTYPE_WC: 421 pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_WC); 422 break; 423 case AMDGPU_VM_MTYPE_CC: 424 pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_CC); 425 break; 426 case AMDGPU_VM_MTYPE_UC: 427 pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 428 break; 429 default: 430 pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 431 break; 432 } 433 434 if (flags & AMDGPU_VM_PAGE_PRT) 435 pte_flag |= AMDGPU_PTE_PRT; 436 437 return pte_flag; 438 } 439 440 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level, 441 uint64_t *addr, uint64_t *flags) 442 { 443 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 444 *addr = adev->vm_manager.vram_base_offset + *addr - 445 adev->gmc.vram_start; 446 BUG_ON(*addr & 0xFFFF00000000003FULL); 447 448 if (!adev->gmc.translate_further) 449 return; 450 451 if (level == AMDGPU_VM_PDB1) { 452 /* Set the block fragment size */ 453 if (!(*flags & AMDGPU_PDE_PTE)) 454 *flags |= AMDGPU_PDE_BFS(0x9); 455 456 } else if (level == AMDGPU_VM_PDB0) { 457 if (*flags & AMDGPU_PDE_PTE) 458 *flags &= ~AMDGPU_PDE_PTE; 459 else 460 *flags |= AMDGPU_PTE_TF; 461 } 462 } 463 464 static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = { 465 .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb, 466 .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb, 467 .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping, 468 .get_vm_pte_flags = gmc_v10_0_get_vm_pte_flags, 469 .get_vm_pde = gmc_v10_0_get_vm_pde 470 }; 471 472 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev) 473 { 474 if (adev->gmc.gmc_funcs == NULL) 475 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs; 476 } 477 478 static int gmc_v10_0_early_init(void *handle) 479 { 480 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 481 482 gmc_v10_0_set_gmc_funcs(adev); 483 gmc_v10_0_set_irq_funcs(adev); 484 485 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 486 adev->gmc.shared_aperture_end = 487 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 488 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 489 adev->gmc.private_aperture_end = 490 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 491 492 return 0; 493 } 494 495 static int gmc_v10_0_late_init(void *handle) 496 { 497 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 498 unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 }; 499 unsigned i; 500 501 for(i = 0; i < adev->num_rings; ++i) { 502 struct amdgpu_ring *ring = adev->rings[i]; 503 unsigned vmhub = ring->funcs->vmhub; 504 505 ring->vm_inv_eng = vm_inv_eng[vmhub]++; 506 dev_info(adev->dev, "ring %u(%s) uses VM inv eng %u on hub %u\n", 507 ring->idx, ring->name, ring->vm_inv_eng, 508 ring->funcs->vmhub); 509 } 510 511 /* Engine 17 is used for GART flushes */ 512 for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i) 513 BUG_ON(vm_inv_eng[i] > 17); 514 515 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 516 } 517 518 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev, 519 struct amdgpu_gmc *mc) 520 { 521 u64 base = 0; 522 523 if (!amdgpu_sriov_vf(adev)) 524 base = gfxhub_v2_0_get_fb_location(adev); 525 526 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 527 amdgpu_gmc_gart_location(adev, mc); 528 529 /* base offset of vram pages */ 530 adev->vm_manager.vram_base_offset = gfxhub_v2_0_get_mc_fb_offset(adev); 531 } 532 533 /** 534 * gmc_v10_0_mc_init - initialize the memory controller driver params 535 * 536 * @adev: amdgpu_device pointer 537 * 538 * Look up the amount of vram, vram width, and decide how to place 539 * vram and gart within the GPU's physical address space. 540 * Returns 0 for success. 541 */ 542 static int gmc_v10_0_mc_init(struct amdgpu_device *adev) 543 { 544 int chansize, numchan; 545 546 if (!amdgpu_emu_mode) 547 adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev); 548 else { 549 /* hard code vram_width for emulation */ 550 chansize = 128; 551 numchan = 1; 552 adev->gmc.vram_width = numchan * chansize; 553 } 554 555 /* Could aper size report 0 ? */ 556 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 557 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 558 559 /* size in MB on si */ 560 adev->gmc.mc_vram_size = 561 adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL; 562 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 563 adev->gmc.visible_vram_size = adev->gmc.aper_size; 564 565 /* In case the PCI BAR is larger than the actual amount of vram */ 566 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 567 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 568 569 /* set the gart size */ 570 if (amdgpu_gart_size == -1) { 571 switch (adev->asic_type) { 572 case CHIP_NAVI10: 573 case CHIP_NAVI14: 574 case CHIP_NAVI12: 575 default: 576 adev->gmc.gart_size = 512ULL << 20; 577 break; 578 } 579 } else 580 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 581 582 gmc_v10_0_vram_gtt_location(adev, &adev->gmc); 583 584 return 0; 585 } 586 587 static int gmc_v10_0_gart_init(struct amdgpu_device *adev) 588 { 589 int r; 590 591 if (adev->gart.bo) { 592 WARN(1, "NAVI10 PCIE GART already initialized\n"); 593 return 0; 594 } 595 596 /* Initialize common gart structure */ 597 r = amdgpu_gart_init(adev); 598 if (r) 599 return r; 600 601 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 602 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) | 603 AMDGPU_PTE_EXECUTABLE; 604 605 return amdgpu_gart_table_vram_alloc(adev); 606 } 607 608 static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev) 609 { 610 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 611 unsigned size; 612 613 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 614 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */ 615 } else { 616 u32 viewport; 617 u32 pitch; 618 619 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 620 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH); 621 size = (REG_GET_FIELD(viewport, 622 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 623 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) * 624 4); 625 } 626 /* return 0 if the pre-OS buffer uses up most of vram */ 627 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) { 628 DRM_ERROR("Warning: pre-OS buffer uses most of vram, \ 629 be aware of gart table overwrite\n"); 630 return 0; 631 } 632 633 return size; 634 } 635 636 637 638 static int gmc_v10_0_sw_init(void *handle) 639 { 640 int r; 641 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 642 643 gfxhub_v2_0_init(adev); 644 mmhub_v2_0_init(adev); 645 646 spin_lock_init(&adev->gmc.invalidate_lock); 647 648 adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev); 649 switch (adev->asic_type) { 650 case CHIP_NAVI10: 651 case CHIP_NAVI14: 652 case CHIP_NAVI12: 653 adev->num_vmhubs = 2; 654 /* 655 * To fulfill 4-level page support, 656 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12, 657 * block size 512 (9bit) 658 */ 659 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 660 break; 661 default: 662 break; 663 } 664 665 /* This interrupt is VMC page fault.*/ 666 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, 667 VMC_1_0__SRCID__VM_FAULT, 668 &adev->gmc.vm_fault); 669 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, 670 UTCL2_1_0__SRCID__FAULT, 671 &adev->gmc.vm_fault); 672 if (r) 673 return r; 674 675 /* 676 * Set the internal MC address mask This is the max address of the GPU's 677 * internal address space. 678 */ 679 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 680 681 /* 682 * Reserve 8M stolen memory for navi10 like vega10 683 * TODO: will check if it's really needed on asic. 684 */ 685 if (amdgpu_emu_mode == 1) 686 adev->gmc.stolen_size = 0; 687 else 688 adev->gmc.stolen_size = 9 * 1024 *1024; 689 690 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 691 if (r) { 692 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 693 return r; 694 } 695 696 r = gmc_v10_0_mc_init(adev); 697 if (r) 698 return r; 699 700 adev->gmc.stolen_size = gmc_v10_0_get_vbios_fb_size(adev); 701 702 /* Memory manager */ 703 r = amdgpu_bo_init(adev); 704 if (r) 705 return r; 706 707 r = gmc_v10_0_gart_init(adev); 708 if (r) 709 return r; 710 711 /* 712 * number of VMs 713 * VMID 0 is reserved for System 714 * amdgpu graphics/compute will use VMIDs 1-7 715 * amdkfd will use VMIDs 8-15 716 */ 717 adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; 718 adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; 719 720 amdgpu_vm_manager_init(adev); 721 722 return 0; 723 } 724 725 /** 726 * gmc_v8_0_gart_fini - vm fini callback 727 * 728 * @adev: amdgpu_device pointer 729 * 730 * Tears down the driver GART/VM setup (CIK). 731 */ 732 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev) 733 { 734 amdgpu_gart_table_vram_free(adev); 735 amdgpu_gart_fini(adev); 736 } 737 738 static int gmc_v10_0_sw_fini(void *handle) 739 { 740 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 741 742 amdgpu_vm_manager_fini(adev); 743 gmc_v10_0_gart_fini(adev); 744 amdgpu_gem_force_release(adev); 745 amdgpu_bo_fini(adev); 746 747 return 0; 748 } 749 750 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev) 751 { 752 switch (adev->asic_type) { 753 case CHIP_NAVI10: 754 case CHIP_NAVI14: 755 case CHIP_NAVI12: 756 break; 757 default: 758 break; 759 } 760 } 761 762 /** 763 * gmc_v10_0_gart_enable - gart enable 764 * 765 * @adev: amdgpu_device pointer 766 */ 767 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) 768 { 769 int r; 770 bool value; 771 u32 tmp; 772 773 if (adev->gart.bo == NULL) { 774 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 775 return -EINVAL; 776 } 777 778 r = amdgpu_gart_table_vram_pin(adev); 779 if (r) 780 return r; 781 782 r = gfxhub_v2_0_gart_enable(adev); 783 if (r) 784 return r; 785 786 r = mmhub_v2_0_gart_enable(adev); 787 if (r) 788 return r; 789 790 tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL); 791 tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK; 792 WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp); 793 794 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL); 795 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp); 796 797 /* Flush HDP after it is initialized */ 798 adev->nbio_funcs->hdp_flush(adev, NULL); 799 800 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 801 false : true; 802 803 gfxhub_v2_0_set_fault_enable_default(adev, value); 804 mmhub_v2_0_set_fault_enable_default(adev, value); 805 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0); 806 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0); 807 808 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 809 (unsigned)(adev->gmc.gart_size >> 20), 810 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 811 812 adev->gart.ready = true; 813 814 return 0; 815 } 816 817 static int gmc_v10_0_hw_init(void *handle) 818 { 819 int r; 820 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 821 822 /* The sequence of these two function calls matters.*/ 823 gmc_v10_0_init_golden_registers(adev); 824 825 r = gmc_v10_0_gart_enable(adev); 826 if (r) 827 return r; 828 829 return 0; 830 } 831 832 /** 833 * gmc_v10_0_gart_disable - gart disable 834 * 835 * @adev: amdgpu_device pointer 836 * 837 * This disables all VM page table. 838 */ 839 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev) 840 { 841 gfxhub_v2_0_gart_disable(adev); 842 mmhub_v2_0_gart_disable(adev); 843 amdgpu_gart_table_vram_unpin(adev); 844 } 845 846 static int gmc_v10_0_hw_fini(void *handle) 847 { 848 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 849 850 if (amdgpu_sriov_vf(adev)) { 851 /* full access mode, so don't touch any GMC register */ 852 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 853 return 0; 854 } 855 856 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 857 gmc_v10_0_gart_disable(adev); 858 859 return 0; 860 } 861 862 static int gmc_v10_0_suspend(void *handle) 863 { 864 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 865 866 gmc_v10_0_hw_fini(adev); 867 868 return 0; 869 } 870 871 static int gmc_v10_0_resume(void *handle) 872 { 873 int r; 874 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 875 876 r = gmc_v10_0_hw_init(adev); 877 if (r) 878 return r; 879 880 amdgpu_vmid_reset_all(adev); 881 882 return 0; 883 } 884 885 static bool gmc_v10_0_is_idle(void *handle) 886 { 887 /* MC is always ready in GMC v10.*/ 888 return true; 889 } 890 891 static int gmc_v10_0_wait_for_idle(void *handle) 892 { 893 /* There is no need to wait for MC idle in GMC v10.*/ 894 return 0; 895 } 896 897 static int gmc_v10_0_soft_reset(void *handle) 898 { 899 return 0; 900 } 901 902 static int gmc_v10_0_set_clockgating_state(void *handle, 903 enum amd_clockgating_state state) 904 { 905 int r; 906 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 907 908 r = mmhub_v2_0_set_clockgating(adev, state); 909 if (r) 910 return r; 911 912 return athub_v2_0_set_clockgating(adev, state); 913 } 914 915 static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags) 916 { 917 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 918 919 mmhub_v2_0_get_clockgating(adev, flags); 920 921 athub_v2_0_get_clockgating(adev, flags); 922 } 923 924 static int gmc_v10_0_set_powergating_state(void *handle, 925 enum amd_powergating_state state) 926 { 927 return 0; 928 } 929 930 const struct amd_ip_funcs gmc_v10_0_ip_funcs = { 931 .name = "gmc_v10_0", 932 .early_init = gmc_v10_0_early_init, 933 .late_init = gmc_v10_0_late_init, 934 .sw_init = gmc_v10_0_sw_init, 935 .sw_fini = gmc_v10_0_sw_fini, 936 .hw_init = gmc_v10_0_hw_init, 937 .hw_fini = gmc_v10_0_hw_fini, 938 .suspend = gmc_v10_0_suspend, 939 .resume = gmc_v10_0_resume, 940 .is_idle = gmc_v10_0_is_idle, 941 .wait_for_idle = gmc_v10_0_wait_for_idle, 942 .soft_reset = gmc_v10_0_soft_reset, 943 .set_clockgating_state = gmc_v10_0_set_clockgating_state, 944 .set_powergating_state = gmc_v10_0_set_powergating_state, 945 .get_clockgating_state = gmc_v10_0_get_clockgating_state, 946 }; 947 948 const struct amdgpu_ip_block_version gmc_v10_0_ip_block = 949 { 950 .type = AMD_IP_BLOCK_TYPE_GMC, 951 .major = 10, 952 .minor = 0, 953 .rev = 0, 954 .funcs = &gmc_v10_0_ip_funcs, 955 }; 956