1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 26 #include <drm/drm_cache.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atomfirmware.h" 30 #include "gmc_v10_0.h" 31 #include "umc_v8_7.h" 32 33 #include "athub/athub_2_0_0_sh_mask.h" 34 #include "athub/athub_2_0_0_offset.h" 35 #include "dcn/dcn_2_0_0_offset.h" 36 #include "dcn/dcn_2_0_0_sh_mask.h" 37 #include "oss/osssys_5_0_0_offset.h" 38 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 39 #include "navi10_enum.h" 40 41 #include "soc15.h" 42 #include "soc15d.h" 43 #include "soc15_common.h" 44 45 #include "nbio_v2_3.h" 46 47 #include "gfxhub_v2_0.h" 48 #include "gfxhub_v2_1.h" 49 #include "mmhub_v2_0.h" 50 #include "mmhub_v2_3.h" 51 #include "athub_v2_0.h" 52 #include "athub_v2_1.h" 53 54 #include "amdgpu_reset.h" 55 56 #if 0 57 static const struct soc15_reg_golden golden_settings_navi10_hdp[] = 58 { 59 /* TODO add golden setting for hdp */ 60 }; 61 #endif 62 63 static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev, 64 struct amdgpu_irq_src *src, 65 unsigned type, 66 enum amdgpu_interrupt_state state) 67 { 68 return 0; 69 } 70 71 static int 72 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 73 struct amdgpu_irq_src *src, unsigned type, 74 enum amdgpu_interrupt_state state) 75 { 76 switch (state) { 77 case AMDGPU_IRQ_STATE_DISABLE: 78 /* MM HUB */ 79 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false); 80 /* GFX HUB */ 81 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false); 82 break; 83 case AMDGPU_IRQ_STATE_ENABLE: 84 /* MM HUB */ 85 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true); 86 /* GFX HUB */ 87 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true); 88 break; 89 default: 90 break; 91 } 92 93 return 0; 94 } 95 96 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, 97 struct amdgpu_irq_src *source, 98 struct amdgpu_iv_entry *entry) 99 { 100 bool retry_fault = !!(entry->src_data[1] & 0x80); 101 bool write_fault = !!(entry->src_data[1] & 0x20); 102 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; 103 struct amdgpu_task_info task_info; 104 uint32_t status = 0; 105 u64 addr; 106 107 addr = (u64)entry->src_data[0] << 12; 108 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 109 110 if (retry_fault) { 111 /* Returning 1 here also prevents sending the IV to the KFD */ 112 113 /* Process it onyl if it's the first fault for this address */ 114 if (entry->ih != &adev->irq.ih_soft && 115 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, 116 entry->timestamp)) 117 return 1; 118 119 /* Delegate it to a different ring if the hardware hasn't 120 * already done it. 121 */ 122 if (entry->ih == &adev->irq.ih) { 123 amdgpu_irq_delegate(adev, entry, 8); 124 return 1; 125 } 126 127 /* Try to handle the recoverable page faults by filling page 128 * tables 129 */ 130 if (amdgpu_vm_handle_fault(adev, entry->pasid, addr, write_fault)) 131 return 1; 132 } 133 134 if (!amdgpu_sriov_vf(adev)) { 135 /* 136 * Issue a dummy read to wait for the status register to 137 * be updated to avoid reading an incorrect value due to 138 * the new fast GRBM interface. 139 */ 140 if ((entry->vmid_src == AMDGPU_GFXHUB_0) && 141 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0))) 142 RREG32(hub->vm_l2_pro_fault_status); 143 144 status = RREG32(hub->vm_l2_pro_fault_status); 145 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 146 } 147 148 if (!printk_ratelimit()) 149 return 0; 150 151 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 152 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 153 154 dev_err(adev->dev, 155 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, " 156 "for process %s pid %d thread %s pid %d)\n", 157 entry->vmid_src ? "mmhub" : "gfxhub", 158 entry->src_id, entry->ring_id, entry->vmid, 159 entry->pasid, task_info.process_name, task_info.tgid, 160 task_info.task_name, task_info.pid); 161 dev_err(adev->dev, " in page starting at address 0x%016llx from client 0x%x (%s)\n", 162 addr, entry->client_id, 163 soc15_ih_clientid_name[entry->client_id]); 164 165 if (!amdgpu_sriov_vf(adev)) 166 hub->vmhub_funcs->print_l2_protection_fault_status(adev, 167 status); 168 169 return 0; 170 } 171 172 static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = { 173 .set = gmc_v10_0_vm_fault_interrupt_state, 174 .process = gmc_v10_0_process_interrupt, 175 }; 176 177 static const struct amdgpu_irq_src_funcs gmc_v10_0_ecc_funcs = { 178 .set = gmc_v10_0_ecc_interrupt_state, 179 .process = amdgpu_umc_process_ecc_irq, 180 }; 181 182 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev) 183 { 184 adev->gmc.vm_fault.num_types = 1; 185 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs; 186 187 if (!amdgpu_sriov_vf(adev)) { 188 adev->gmc.ecc_irq.num_types = 1; 189 adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs; 190 } 191 } 192 193 /** 194 * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore 195 * 196 * @adev: amdgpu_device pointer 197 * @vmhub: vmhub type 198 * 199 */ 200 static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev, 201 uint32_t vmhub) 202 { 203 return ((vmhub == AMDGPU_MMHUB_0 || 204 vmhub == AMDGPU_MMHUB_1) && 205 (!amdgpu_sriov_vf(adev))); 206 } 207 208 static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info( 209 struct amdgpu_device *adev, 210 uint8_t vmid, uint16_t *p_pasid) 211 { 212 uint32_t value; 213 214 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 215 + vmid); 216 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 217 218 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 219 } 220 221 /* 222 * GART 223 * VMID 0 is the physical GPU addresses as used by the kernel. 224 * VMIDs 1-15 are used for userspace clients and are handled 225 * by the amdgpu vm/hsa code. 226 */ 227 228 static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 229 unsigned int vmhub, uint32_t flush_type) 230 { 231 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub); 232 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 233 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 234 u32 tmp; 235 /* Use register 17 for GART */ 236 const unsigned eng = 17; 237 unsigned int i; 238 unsigned char hub_ip = 0; 239 240 hub_ip = (vmhub == AMDGPU_GFXHUB_0) ? 241 GC_HWIP : MMHUB_HWIP; 242 243 spin_lock(&adev->gmc.invalidate_lock); 244 /* 245 * It may lose gpuvm invalidate acknowldege state across power-gating 246 * off cycle, add semaphore acquire before invalidation and semaphore 247 * release after invalidation to avoid entering power gated state 248 * to WA the Issue 249 */ 250 251 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 252 if (use_semaphore) { 253 for (i = 0; i < adev->usec_timeout; i++) { 254 /* a read return value of 1 means semaphore acuqire */ 255 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + 256 hub->eng_distance * eng, hub_ip); 257 258 if (tmp & 0x1) 259 break; 260 udelay(1); 261 } 262 263 if (i >= adev->usec_timeout) 264 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 265 } 266 267 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + 268 hub->eng_distance * eng, 269 inv_req, hub_ip); 270 271 /* 272 * Issue a dummy read to wait for the ACK register to be cleared 273 * to avoid a false ACK due to the new fast GRBM interface. 274 */ 275 if ((vmhub == AMDGPU_GFXHUB_0) && 276 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0))) 277 RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + 278 hub->eng_distance * eng, hub_ip); 279 280 /* Wait for ACK with a delay.*/ 281 for (i = 0; i < adev->usec_timeout; i++) { 282 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack + 283 hub->eng_distance * eng, hub_ip); 284 285 tmp &= 1 << vmid; 286 if (tmp) 287 break; 288 289 udelay(1); 290 } 291 292 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 293 if (use_semaphore) 294 /* 295 * add semaphore release after invalidation, 296 * write with 0 means semaphore release 297 */ 298 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + 299 hub->eng_distance * eng, 0, hub_ip); 300 301 spin_unlock(&adev->gmc.invalidate_lock); 302 303 if (i < adev->usec_timeout) 304 return; 305 306 DRM_ERROR("Timeout waiting for VM flush hub: %d!\n", vmhub); 307 } 308 309 /** 310 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback 311 * 312 * @adev: amdgpu_device pointer 313 * @vmid: vm instance to flush 314 * @vmhub: vmhub type 315 * @flush_type: the flush type 316 * 317 * Flush the TLB for the requested page table. 318 */ 319 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 320 uint32_t vmhub, uint32_t flush_type) 321 { 322 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 323 struct dma_fence *fence; 324 struct amdgpu_job *job; 325 326 int r; 327 328 /* flush hdp cache */ 329 adev->hdp.funcs->flush_hdp(adev, NULL); 330 331 /* For SRIOV run time, driver shouldn't access the register through MMIO 332 * Directly use kiq to do the vm invalidation instead 333 */ 334 if (adev->gfx.kiq.ring.sched.ready && !adev->enable_mes && 335 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && 336 down_read_trylock(&adev->reset_domain->sem)) { 337 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 338 const unsigned eng = 17; 339 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 340 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 341 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 342 343 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 344 1 << vmid); 345 346 up_read(&adev->reset_domain->sem); 347 return; 348 } 349 350 mutex_lock(&adev->mman.gtt_window_lock); 351 352 if (vmhub == AMDGPU_MMHUB_0) { 353 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0); 354 mutex_unlock(&adev->mman.gtt_window_lock); 355 return; 356 } 357 358 BUG_ON(vmhub != AMDGPU_GFXHUB_0); 359 360 if (!adev->mman.buffer_funcs_enabled || 361 !adev->ib_pool_ready || 362 amdgpu_in_reset(adev) || 363 ring->sched.ready == false) { 364 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0); 365 mutex_unlock(&adev->mman.gtt_window_lock); 366 return; 367 } 368 369 /* The SDMA on Navi has a bug which can theoretically result in memory 370 * corruption if an invalidation happens at the same time as an VA 371 * translation. Avoid this by doing the invalidation from the SDMA 372 * itself. 373 */ 374 r = amdgpu_job_alloc_with_ib(adev, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE, 375 &job); 376 if (r) 377 goto error_alloc; 378 379 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); 380 job->vm_needs_flush = true; 381 job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop; 382 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 383 r = amdgpu_job_submit(job, &adev->mman.entity, 384 AMDGPU_FENCE_OWNER_UNDEFINED, &fence); 385 if (r) 386 goto error_submit; 387 388 mutex_unlock(&adev->mman.gtt_window_lock); 389 390 dma_fence_wait(fence, false); 391 dma_fence_put(fence); 392 393 return; 394 395 error_submit: 396 amdgpu_job_free(job); 397 398 error_alloc: 399 mutex_unlock(&adev->mman.gtt_window_lock); 400 DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r); 401 } 402 403 /** 404 * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid 405 * 406 * @adev: amdgpu_device pointer 407 * @pasid: pasid to be flush 408 * @flush_type: the flush type 409 * @all_hub: Used with PACKET3_INVALIDATE_TLBS_ALL_HUB() 410 * 411 * Flush the TLB for the requested pasid. 412 */ 413 static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 414 uint16_t pasid, uint32_t flush_type, 415 bool all_hub) 416 { 417 int vmid, i; 418 signed long r; 419 uint32_t seq; 420 uint16_t queried_pasid; 421 bool ret; 422 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 423 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 424 425 if (amdgpu_emu_mode == 0 && ring->sched.ready) { 426 spin_lock(&adev->gfx.kiq.ring_lock); 427 /* 2 dwords flush + 8 dwords fence */ 428 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8); 429 kiq->pmf->kiq_invalidate_tlbs(ring, 430 pasid, flush_type, all_hub); 431 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 432 if (r) { 433 amdgpu_ring_undo(ring); 434 spin_unlock(&adev->gfx.kiq.ring_lock); 435 return -ETIME; 436 } 437 438 amdgpu_ring_commit(ring); 439 spin_unlock(&adev->gfx.kiq.ring_lock); 440 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); 441 if (r < 1) { 442 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r); 443 return -ETIME; 444 } 445 446 return 0; 447 } 448 449 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 450 451 ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 452 &queried_pasid); 453 if (ret && queried_pasid == pasid) { 454 if (all_hub) { 455 for (i = 0; i < adev->num_vmhubs; i++) 456 gmc_v10_0_flush_gpu_tlb(adev, vmid, 457 i, flush_type); 458 } else { 459 gmc_v10_0_flush_gpu_tlb(adev, vmid, 460 AMDGPU_GFXHUB_0, flush_type); 461 } 462 if (!adev->enable_mes) 463 break; 464 } 465 } 466 467 return 0; 468 } 469 470 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 471 unsigned vmid, uint64_t pd_addr) 472 { 473 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub); 474 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 475 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 476 unsigned eng = ring->vm_inv_eng; 477 478 /* 479 * It may lose gpuvm invalidate acknowldege state across power-gating 480 * off cycle, add semaphore acquire before invalidation and semaphore 481 * release after invalidation to avoid entering power gated state 482 * to WA the Issue 483 */ 484 485 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 486 if (use_semaphore) 487 /* a read return value of 1 means semaphore acuqire */ 488 amdgpu_ring_emit_reg_wait(ring, 489 hub->vm_inv_eng0_sem + 490 hub->eng_distance * eng, 0x1, 0x1); 491 492 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 493 (hub->ctx_addr_distance * vmid), 494 lower_32_bits(pd_addr)); 495 496 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 497 (hub->ctx_addr_distance * vmid), 498 upper_32_bits(pd_addr)); 499 500 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 501 hub->eng_distance * eng, 502 hub->vm_inv_eng0_ack + 503 hub->eng_distance * eng, 504 req, 1 << vmid); 505 506 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 507 if (use_semaphore) 508 /* 509 * add semaphore release after invalidation, 510 * write with 0 means semaphore release 511 */ 512 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 513 hub->eng_distance * eng, 0); 514 515 return pd_addr; 516 } 517 518 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 519 unsigned pasid) 520 { 521 struct amdgpu_device *adev = ring->adev; 522 uint32_t reg; 523 524 /* MES fw manages IH_VMID_x_LUT updating */ 525 if (ring->is_mes_queue) 526 return; 527 528 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) 529 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 530 else 531 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 532 533 amdgpu_ring_emit_wreg(ring, reg, pasid); 534 } 535 536 /* 537 * PTE format on NAVI 10: 538 * 63:59 reserved 539 * 58 reserved and for sienna_cichlid is used for MALL noalloc 540 * 57 reserved 541 * 56 F 542 * 55 L 543 * 54 reserved 544 * 53:52 SW 545 * 51 T 546 * 50:48 mtype 547 * 47:12 4k physical page base address 548 * 11:7 fragment 549 * 6 write 550 * 5 read 551 * 4 exe 552 * 3 Z 553 * 2 snooped 554 * 1 system 555 * 0 valid 556 * 557 * PDE format on NAVI 10: 558 * 63:59 block fragment size 559 * 58:55 reserved 560 * 54 P 561 * 53:48 reserved 562 * 47:6 physical base address of PD or PTE 563 * 5:3 reserved 564 * 2 C 565 * 1 system 566 * 0 valid 567 */ 568 569 static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 570 { 571 switch (flags) { 572 case AMDGPU_VM_MTYPE_DEFAULT: 573 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 574 case AMDGPU_VM_MTYPE_NC: 575 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 576 case AMDGPU_VM_MTYPE_WC: 577 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC); 578 case AMDGPU_VM_MTYPE_CC: 579 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC); 580 case AMDGPU_VM_MTYPE_UC: 581 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 582 default: 583 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 584 } 585 } 586 587 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level, 588 uint64_t *addr, uint64_t *flags) 589 { 590 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 591 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 592 BUG_ON(*addr & 0xFFFF00000000003FULL); 593 594 if (!adev->gmc.translate_further) 595 return; 596 597 if (level == AMDGPU_VM_PDB1) { 598 /* Set the block fragment size */ 599 if (!(*flags & AMDGPU_PDE_PTE)) 600 *flags |= AMDGPU_PDE_BFS(0x9); 601 602 } else if (level == AMDGPU_VM_PDB0) { 603 if (*flags & AMDGPU_PDE_PTE) 604 *flags &= ~AMDGPU_PDE_PTE; 605 else 606 *flags |= AMDGPU_PTE_TF; 607 } 608 } 609 610 static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev, 611 struct amdgpu_bo_va_mapping *mapping, 612 uint64_t *flags) 613 { 614 *flags &= ~AMDGPU_PTE_EXECUTABLE; 615 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 616 617 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; 618 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); 619 620 *flags &= ~AMDGPU_PTE_NOALLOC; 621 *flags |= (mapping->flags & AMDGPU_PTE_NOALLOC); 622 623 if (mapping->flags & AMDGPU_PTE_PRT) { 624 *flags |= AMDGPU_PTE_PRT; 625 *flags |= AMDGPU_PTE_SNOOPED; 626 *flags |= AMDGPU_PTE_LOG; 627 *flags |= AMDGPU_PTE_SYSTEM; 628 *flags &= ~AMDGPU_PTE_VALID; 629 } 630 } 631 632 static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev) 633 { 634 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 635 unsigned size; 636 637 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 638 size = AMDGPU_VBIOS_VGA_ALLOCATION; 639 } else { 640 u32 viewport; 641 u32 pitch; 642 643 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 644 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH); 645 size = (REG_GET_FIELD(viewport, 646 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 647 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) * 648 4); 649 } 650 651 return size; 652 } 653 654 static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = { 655 .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb, 656 .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid, 657 .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb, 658 .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping, 659 .map_mtype = gmc_v10_0_map_mtype, 660 .get_vm_pde = gmc_v10_0_get_vm_pde, 661 .get_vm_pte = gmc_v10_0_get_vm_pte, 662 .get_vbios_fb_size = gmc_v10_0_get_vbios_fb_size, 663 }; 664 665 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev) 666 { 667 if (adev->gmc.gmc_funcs == NULL) 668 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs; 669 } 670 671 static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev) 672 { 673 switch (adev->ip_versions[UMC_HWIP][0]) { 674 case IP_VERSION(8, 7, 0): 675 adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM; 676 adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM; 677 adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM; 678 adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA; 679 adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0]; 680 adev->umc.ras = &umc_v8_7_ras; 681 break; 682 default: 683 break; 684 } 685 if (adev->umc.ras) { 686 amdgpu_ras_register_ras_block(adev, &adev->umc.ras->ras_block); 687 688 strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc"); 689 adev->umc.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC; 690 adev->umc.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; 691 adev->umc.ras_if = &adev->umc.ras->ras_block.ras_comm; 692 693 /* If don't define special ras_late_init function, use default ras_late_init */ 694 if (!adev->umc.ras->ras_block.ras_late_init) 695 adev->umc.ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init; 696 697 /* If not defined special ras_cb function, use default ras_cb */ 698 if (!adev->umc.ras->ras_block.ras_cb) 699 adev->umc.ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb; 700 } 701 } 702 703 704 static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev) 705 { 706 switch (adev->ip_versions[MMHUB_HWIP][0]) { 707 case IP_VERSION(2, 3, 0): 708 case IP_VERSION(2, 4, 0): 709 case IP_VERSION(2, 4, 1): 710 adev->mmhub.funcs = &mmhub_v2_3_funcs; 711 break; 712 default: 713 adev->mmhub.funcs = &mmhub_v2_0_funcs; 714 break; 715 } 716 } 717 718 static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev) 719 { 720 switch (adev->ip_versions[GC_HWIP][0]) { 721 case IP_VERSION(10, 3, 0): 722 case IP_VERSION(10, 3, 2): 723 case IP_VERSION(10, 3, 1): 724 case IP_VERSION(10, 3, 4): 725 case IP_VERSION(10, 3, 5): 726 case IP_VERSION(10, 3, 6): 727 case IP_VERSION(10, 3, 3): 728 case IP_VERSION(10, 3, 7): 729 adev->gfxhub.funcs = &gfxhub_v2_1_funcs; 730 break; 731 default: 732 adev->gfxhub.funcs = &gfxhub_v2_0_funcs; 733 break; 734 } 735 } 736 737 738 static int gmc_v10_0_early_init(void *handle) 739 { 740 int r; 741 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 742 743 gmc_v10_0_set_mmhub_funcs(adev); 744 gmc_v10_0_set_gfxhub_funcs(adev); 745 gmc_v10_0_set_gmc_funcs(adev); 746 gmc_v10_0_set_irq_funcs(adev); 747 gmc_v10_0_set_umc_funcs(adev); 748 749 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 750 adev->gmc.shared_aperture_end = 751 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 752 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 753 adev->gmc.private_aperture_end = 754 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 755 756 r = amdgpu_gmc_ras_early_init(adev); 757 if (r) 758 return r; 759 760 return 0; 761 } 762 763 static int gmc_v10_0_late_init(void *handle) 764 { 765 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 766 int r; 767 768 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 769 if (r) 770 return r; 771 772 r = amdgpu_gmc_ras_late_init(adev); 773 if (r) 774 return r; 775 776 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 777 } 778 779 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev, 780 struct amdgpu_gmc *mc) 781 { 782 u64 base = 0; 783 784 base = adev->gfxhub.funcs->get_fb_location(adev); 785 786 /* add the xgmi offset of the physical node */ 787 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 788 789 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 790 amdgpu_gmc_gart_location(adev, mc); 791 amdgpu_gmc_agp_location(adev, mc); 792 793 /* base offset of vram pages */ 794 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 795 796 /* add the xgmi offset of the physical node */ 797 adev->vm_manager.vram_base_offset += 798 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 799 } 800 801 /** 802 * gmc_v10_0_mc_init - initialize the memory controller driver params 803 * 804 * @adev: amdgpu_device pointer 805 * 806 * Look up the amount of vram, vram width, and decide how to place 807 * vram and gart within the GPU's physical address space. 808 * Returns 0 for success. 809 */ 810 static int gmc_v10_0_mc_init(struct amdgpu_device *adev) 811 { 812 int r; 813 814 /* size in MB on si */ 815 adev->gmc.mc_vram_size = 816 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 817 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 818 819 if (!(adev->flags & AMD_IS_APU)) { 820 r = amdgpu_device_resize_fb_bar(adev); 821 if (r) 822 return r; 823 } 824 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 825 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 826 827 #ifdef CONFIG_X86_64 828 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { 829 adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev); 830 adev->gmc.aper_size = adev->gmc.real_vram_size; 831 } 832 #endif 833 834 /* In case the PCI BAR is larger than the actual amount of vram */ 835 adev->gmc.visible_vram_size = adev->gmc.aper_size; 836 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 837 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 838 839 /* set the gart size */ 840 if (amdgpu_gart_size == -1) { 841 switch (adev->ip_versions[GC_HWIP][0]) { 842 default: 843 adev->gmc.gart_size = 512ULL << 20; 844 break; 845 case IP_VERSION(10, 3, 1): /* DCE SG support */ 846 case IP_VERSION(10, 3, 3): /* DCE SG support */ 847 case IP_VERSION(10, 3, 6): /* DCE SG support */ 848 case IP_VERSION(10, 3, 7): /* DCE SG support */ 849 adev->gmc.gart_size = 1024ULL << 20; 850 break; 851 } 852 } else { 853 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 854 } 855 856 gmc_v10_0_vram_gtt_location(adev, &adev->gmc); 857 858 return 0; 859 } 860 861 static int gmc_v10_0_gart_init(struct amdgpu_device *adev) 862 { 863 int r; 864 865 if (adev->gart.bo) { 866 WARN(1, "NAVI10 PCIE GART already initialized\n"); 867 return 0; 868 } 869 870 /* Initialize common gart structure */ 871 r = amdgpu_gart_init(adev); 872 if (r) 873 return r; 874 875 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 876 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) | 877 AMDGPU_PTE_EXECUTABLE; 878 879 return amdgpu_gart_table_vram_alloc(adev); 880 } 881 882 static int gmc_v10_0_sw_init(void *handle) 883 { 884 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 885 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 886 887 adev->gfxhub.funcs->init(adev); 888 889 adev->mmhub.funcs->init(adev); 890 891 spin_lock_init(&adev->gmc.invalidate_lock); 892 893 if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) { 894 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; 895 adev->gmc.vram_width = 64; 896 } else if (amdgpu_emu_mode == 1) { 897 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6; 898 adev->gmc.vram_width = 1 * 128; /* numchan * chansize */ 899 } else { 900 r = amdgpu_atomfirmware_get_vram_info(adev, 901 &vram_width, &vram_type, &vram_vendor); 902 adev->gmc.vram_width = vram_width; 903 904 adev->gmc.vram_type = vram_type; 905 adev->gmc.vram_vendor = vram_vendor; 906 } 907 908 switch (adev->ip_versions[GC_HWIP][0]) { 909 case IP_VERSION(10, 3, 0): 910 adev->gmc.mall_size = 128 * 1024 * 1024; 911 break; 912 case IP_VERSION(10, 3, 2): 913 adev->gmc.mall_size = 96 * 1024 * 1024; 914 break; 915 case IP_VERSION(10, 3, 4): 916 adev->gmc.mall_size = 32 * 1024 * 1024; 917 break; 918 case IP_VERSION(10, 3, 5): 919 adev->gmc.mall_size = 16 * 1024 * 1024; 920 break; 921 default: 922 adev->gmc.mall_size = 0; 923 break; 924 } 925 926 switch (adev->ip_versions[GC_HWIP][0]) { 927 case IP_VERSION(10, 1, 10): 928 case IP_VERSION(10, 1, 1): 929 case IP_VERSION(10, 1, 2): 930 case IP_VERSION(10, 1, 3): 931 case IP_VERSION(10, 1, 4): 932 case IP_VERSION(10, 3, 0): 933 case IP_VERSION(10, 3, 2): 934 case IP_VERSION(10, 3, 1): 935 case IP_VERSION(10, 3, 4): 936 case IP_VERSION(10, 3, 5): 937 case IP_VERSION(10, 3, 6): 938 case IP_VERSION(10, 3, 3): 939 case IP_VERSION(10, 3, 7): 940 adev->num_vmhubs = 2; 941 /* 942 * To fulfill 4-level page support, 943 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12, 944 * block size 512 (9bit) 945 */ 946 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 947 break; 948 default: 949 break; 950 } 951 952 /* This interrupt is VMC page fault.*/ 953 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, 954 VMC_1_0__SRCID__VM_FAULT, 955 &adev->gmc.vm_fault); 956 957 if (r) 958 return r; 959 960 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, 961 UTCL2_1_0__SRCID__FAULT, 962 &adev->gmc.vm_fault); 963 if (r) 964 return r; 965 966 if (!amdgpu_sriov_vf(adev)) { 967 /* interrupt sent to DF. */ 968 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 969 &adev->gmc.ecc_irq); 970 if (r) 971 return r; 972 } 973 974 /* 975 * Set the internal MC address mask This is the max address of the GPU's 976 * internal address space. 977 */ 978 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 979 980 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 981 if (r) { 982 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 983 return r; 984 } 985 986 adev->need_swiotlb = drm_need_swiotlb(44); 987 988 r = gmc_v10_0_mc_init(adev); 989 if (r) 990 return r; 991 992 amdgpu_gmc_get_vbios_allocations(adev); 993 994 /* Memory manager */ 995 r = amdgpu_bo_init(adev); 996 if (r) 997 return r; 998 999 r = gmc_v10_0_gart_init(adev); 1000 if (r) 1001 return r; 1002 1003 /* 1004 * number of VMs 1005 * VMID 0 is reserved for System 1006 * amdgpu graphics/compute will use VMIDs 1-7 1007 * amdkfd will use VMIDs 8-15 1008 */ 1009 adev->vm_manager.first_kfd_vmid = 8; 1010 1011 amdgpu_vm_manager_init(adev); 1012 1013 return 0; 1014 } 1015 1016 /** 1017 * gmc_v10_0_gart_fini - vm fini callback 1018 * 1019 * @adev: amdgpu_device pointer 1020 * 1021 * Tears down the driver GART/VM setup (CIK). 1022 */ 1023 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev) 1024 { 1025 amdgpu_gart_table_vram_free(adev); 1026 } 1027 1028 static int gmc_v10_0_sw_fini(void *handle) 1029 { 1030 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1031 1032 amdgpu_vm_manager_fini(adev); 1033 gmc_v10_0_gart_fini(adev); 1034 amdgpu_gem_force_release(adev); 1035 amdgpu_bo_fini(adev); 1036 1037 return 0; 1038 } 1039 1040 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev) 1041 { 1042 } 1043 1044 /** 1045 * gmc_v10_0_gart_enable - gart enable 1046 * 1047 * @adev: amdgpu_device pointer 1048 */ 1049 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) 1050 { 1051 int r; 1052 bool value; 1053 1054 if (adev->gart.bo == NULL) { 1055 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 1056 return -EINVAL; 1057 } 1058 1059 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 1060 r = adev->gfxhub.funcs->gart_enable(adev); 1061 if (r) 1062 return r; 1063 1064 r = adev->mmhub.funcs->gart_enable(adev); 1065 if (r) 1066 return r; 1067 1068 adev->hdp.funcs->init_registers(adev); 1069 1070 /* Flush HDP after it is initialized */ 1071 adev->hdp.funcs->flush_hdp(adev, NULL); 1072 1073 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 1074 false : true; 1075 1076 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 1077 adev->mmhub.funcs->set_fault_enable_default(adev, value); 1078 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0); 1079 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0); 1080 1081 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1082 (unsigned)(adev->gmc.gart_size >> 20), 1083 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 1084 1085 return 0; 1086 } 1087 1088 static int gmc_v10_0_hw_init(void *handle) 1089 { 1090 int r; 1091 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1092 1093 /* The sequence of these two function calls matters.*/ 1094 gmc_v10_0_init_golden_registers(adev); 1095 1096 /* 1097 * harvestable groups in gc_utcl2 need to be programmed before any GFX block 1098 * register setup within GMC, or else system hang when harvesting SA. 1099 */ 1100 if (adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest) 1101 adev->gfxhub.funcs->utcl2_harvest(adev); 1102 1103 r = gmc_v10_0_gart_enable(adev); 1104 if (r) 1105 return r; 1106 1107 if (amdgpu_emu_mode == 1) { 1108 r = amdgpu_gmc_vram_checking(adev); 1109 if (r) 1110 return r; 1111 } 1112 1113 if (adev->umc.funcs && adev->umc.funcs->init_registers) 1114 adev->umc.funcs->init_registers(adev); 1115 1116 return 0; 1117 } 1118 1119 /** 1120 * gmc_v10_0_gart_disable - gart disable 1121 * 1122 * @adev: amdgpu_device pointer 1123 * 1124 * This disables all VM page table. 1125 */ 1126 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev) 1127 { 1128 adev->gfxhub.funcs->gart_disable(adev); 1129 adev->mmhub.funcs->gart_disable(adev); 1130 } 1131 1132 static int gmc_v10_0_hw_fini(void *handle) 1133 { 1134 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1135 1136 gmc_v10_0_gart_disable(adev); 1137 1138 if (amdgpu_sriov_vf(adev)) { 1139 /* full access mode, so don't touch any GMC register */ 1140 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 1141 return 0; 1142 } 1143 1144 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 1145 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1146 1147 return 0; 1148 } 1149 1150 static int gmc_v10_0_suspend(void *handle) 1151 { 1152 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1153 1154 gmc_v10_0_hw_fini(adev); 1155 1156 return 0; 1157 } 1158 1159 static int gmc_v10_0_resume(void *handle) 1160 { 1161 int r; 1162 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1163 1164 r = gmc_v10_0_hw_init(adev); 1165 if (r) 1166 return r; 1167 1168 amdgpu_vmid_reset_all(adev); 1169 1170 return 0; 1171 } 1172 1173 static bool gmc_v10_0_is_idle(void *handle) 1174 { 1175 /* MC is always ready in GMC v10.*/ 1176 return true; 1177 } 1178 1179 static int gmc_v10_0_wait_for_idle(void *handle) 1180 { 1181 /* There is no need to wait for MC idle in GMC v10.*/ 1182 return 0; 1183 } 1184 1185 static int gmc_v10_0_soft_reset(void *handle) 1186 { 1187 return 0; 1188 } 1189 1190 static int gmc_v10_0_set_clockgating_state(void *handle, 1191 enum amd_clockgating_state state) 1192 { 1193 int r; 1194 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1195 1196 /* 1197 * The issue mmhub can't disconnect from DF with MMHUB clock gating being disabled 1198 * is a new problem observed at DF 3.0.3, however with the same suspend sequence not 1199 * seen any issue on the DF 3.0.2 series platform. 1200 */ 1201 if (adev->in_s0ix && adev->ip_versions[DF_HWIP][0] > IP_VERSION(3, 0, 2)) { 1202 dev_dbg(adev->dev, "keep mmhub clock gating being enabled for s0ix\n"); 1203 return 0; 1204 } 1205 1206 r = adev->mmhub.funcs->set_clockgating(adev, state); 1207 if (r) 1208 return r; 1209 1210 if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0)) 1211 return athub_v2_1_set_clockgating(adev, state); 1212 else 1213 return athub_v2_0_set_clockgating(adev, state); 1214 } 1215 1216 static void gmc_v10_0_get_clockgating_state(void *handle, u64 *flags) 1217 { 1218 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1219 1220 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 3) || 1221 adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 4)) 1222 return; 1223 1224 adev->mmhub.funcs->get_clockgating(adev, flags); 1225 1226 if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0)) 1227 athub_v2_1_get_clockgating(adev, flags); 1228 else 1229 athub_v2_0_get_clockgating(adev, flags); 1230 } 1231 1232 static int gmc_v10_0_set_powergating_state(void *handle, 1233 enum amd_powergating_state state) 1234 { 1235 return 0; 1236 } 1237 1238 const struct amd_ip_funcs gmc_v10_0_ip_funcs = { 1239 .name = "gmc_v10_0", 1240 .early_init = gmc_v10_0_early_init, 1241 .late_init = gmc_v10_0_late_init, 1242 .sw_init = gmc_v10_0_sw_init, 1243 .sw_fini = gmc_v10_0_sw_fini, 1244 .hw_init = gmc_v10_0_hw_init, 1245 .hw_fini = gmc_v10_0_hw_fini, 1246 .suspend = gmc_v10_0_suspend, 1247 .resume = gmc_v10_0_resume, 1248 .is_idle = gmc_v10_0_is_idle, 1249 .wait_for_idle = gmc_v10_0_wait_for_idle, 1250 .soft_reset = gmc_v10_0_soft_reset, 1251 .set_clockgating_state = gmc_v10_0_set_clockgating_state, 1252 .set_powergating_state = gmc_v10_0_set_powergating_state, 1253 .get_clockgating_state = gmc_v10_0_get_clockgating_state, 1254 }; 1255 1256 const struct amdgpu_ip_block_version gmc_v10_0_ip_block = 1257 { 1258 .type = AMD_IP_BLOCK_TYPE_GMC, 1259 .major = 10, 1260 .minor = 0, 1261 .rev = 0, 1262 .funcs = &gmc_v10_0_ip_funcs, 1263 }; 1264