1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 #include "amdgpu.h" 26 #include "amdgpu_atomfirmware.h" 27 #include "gmc_v10_0.h" 28 29 #include "hdp/hdp_5_0_0_offset.h" 30 #include "hdp/hdp_5_0_0_sh_mask.h" 31 #include "gc/gc_10_1_0_sh_mask.h" 32 #include "mmhub/mmhub_2_0_0_sh_mask.h" 33 #include "dcn/dcn_2_0_0_offset.h" 34 #include "dcn/dcn_2_0_0_sh_mask.h" 35 #include "oss/osssys_5_0_0_offset.h" 36 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 37 #include "navi10_enum.h" 38 39 #include "soc15.h" 40 #include "soc15_common.h" 41 42 #include "nbio_v2_3.h" 43 44 #include "gfxhub_v2_0.h" 45 #include "mmhub_v2_0.h" 46 #include "athub_v2_0.h" 47 /* XXX Move this macro to navi10 header file, which is like vid.h for VI.*/ 48 #define AMDGPU_NUM_OF_VMIDS 8 49 50 #if 0 51 static const struct soc15_reg_golden golden_settings_navi10_hdp[] = 52 { 53 /* TODO add golden setting for hdp */ 54 }; 55 #endif 56 57 static int 58 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 59 struct amdgpu_irq_src *src, unsigned type, 60 enum amdgpu_interrupt_state state) 61 { 62 struct amdgpu_vmhub *hub; 63 u32 tmp, reg, bits[AMDGPU_MAX_VMHUBS], i; 64 65 bits[AMDGPU_GFXHUB] = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 66 GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 67 GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 68 GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 69 GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 70 GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 71 GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 72 73 bits[AMDGPU_MMHUB] = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 74 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 75 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 76 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 77 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 78 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 79 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 80 81 switch (state) { 82 case AMDGPU_IRQ_STATE_DISABLE: 83 /* MM HUB */ 84 hub = &adev->vmhub[AMDGPU_MMHUB]; 85 for (i = 0; i < 16; i++) { 86 reg = hub->vm_context0_cntl + i; 87 tmp = RREG32(reg); 88 tmp &= ~bits[AMDGPU_MMHUB]; 89 WREG32(reg, tmp); 90 } 91 92 /* GFX HUB */ 93 hub = &adev->vmhub[AMDGPU_GFXHUB]; 94 for (i = 0; i < 16; i++) { 95 reg = hub->vm_context0_cntl + i; 96 tmp = RREG32(reg); 97 tmp &= ~bits[AMDGPU_GFXHUB]; 98 WREG32(reg, tmp); 99 } 100 break; 101 case AMDGPU_IRQ_STATE_ENABLE: 102 /* MM HUB */ 103 hub = &adev->vmhub[AMDGPU_MMHUB]; 104 for (i = 0; i < 16; i++) { 105 reg = hub->vm_context0_cntl + i; 106 tmp = RREG32(reg); 107 tmp |= bits[AMDGPU_MMHUB]; 108 WREG32(reg, tmp); 109 } 110 111 /* GFX HUB */ 112 hub = &adev->vmhub[AMDGPU_GFXHUB]; 113 for (i = 0; i < 16; i++) { 114 reg = hub->vm_context0_cntl + i; 115 tmp = RREG32(reg); 116 tmp |= bits[AMDGPU_GFXHUB]; 117 WREG32(reg, tmp); 118 } 119 break; 120 default: 121 break; 122 } 123 124 return 0; 125 } 126 127 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, 128 struct amdgpu_irq_src *source, 129 struct amdgpu_iv_entry *entry) 130 { 131 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; 132 uint32_t status = 0; 133 u64 addr; 134 135 addr = (u64)entry->src_data[0] << 12; 136 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 137 138 if (!amdgpu_sriov_vf(adev)) { 139 status = RREG32(hub->vm_l2_pro_fault_status); 140 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 141 } 142 143 if (printk_ratelimit()) { 144 dev_err(adev->dev, 145 "[%s] VMC page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n", 146 entry->vmid_src ? "mmhub" : "gfxhub", 147 entry->src_id, entry->ring_id, entry->vmid, 148 entry->pasid); 149 dev_err(adev->dev, " at page 0x%016llx from %d\n", 150 addr, entry->client_id); 151 if (!amdgpu_sriov_vf(adev)) 152 dev_err(adev->dev, 153 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 154 status); 155 } 156 157 return 0; 158 } 159 160 static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = { 161 .set = gmc_v10_0_vm_fault_interrupt_state, 162 .process = gmc_v10_0_process_interrupt, 163 }; 164 165 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev) 166 { 167 adev->gmc.vm_fault.num_types = 1; 168 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs; 169 } 170 171 static uint32_t gmc_v10_0_get_invalidate_req(unsigned int vmid, 172 uint32_t flush_type) 173 { 174 u32 req = 0; 175 176 /* invalidate using legacy mode on vmid*/ 177 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 178 PER_VMID_INVALIDATE_REQ, 1 << vmid); 179 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 180 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 181 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 182 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 183 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 184 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 185 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 186 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 187 188 return req; 189 } 190 191 /* 192 * GART 193 * VMID 0 is the physical GPU addresses as used by the kernel. 194 * VMIDs 1-15 are used for userspace clients and are handled 195 * by the amdgpu vm/hsa code. 196 */ 197 198 static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 199 unsigned int vmhub, uint32_t flush_type) 200 { 201 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 202 u32 tmp = gmc_v10_0_get_invalidate_req(vmid, flush_type); 203 /* Use register 17 for GART */ 204 const unsigned eng = 17; 205 unsigned int i; 206 207 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp); 208 209 /* Wait for ACK with a delay.*/ 210 for (i = 0; i < adev->usec_timeout; i++) { 211 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); 212 tmp &= 1 << vmid; 213 if (tmp) 214 break; 215 216 udelay(1); 217 } 218 219 if (i < adev->usec_timeout) 220 return; 221 222 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 223 } 224 225 /** 226 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback 227 * 228 * @adev: amdgpu_device pointer 229 * @vmid: vm instance to flush 230 * 231 * Flush the TLB for the requested page table. 232 */ 233 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, 234 uint32_t vmid, uint32_t flush_type) 235 { 236 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 237 struct dma_fence *fence; 238 struct amdgpu_job *job; 239 240 int r; 241 242 /* flush hdp cache */ 243 adev->nbio_funcs->hdp_flush(adev, NULL); 244 245 mutex_lock(&adev->mman.gtt_window_lock); 246 247 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB, 0); 248 if (!adev->mman.buffer_funcs_enabled || 249 !adev->ib_pool_ready || 250 adev->in_gpu_reset) { 251 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB, 0); 252 mutex_unlock(&adev->mman.gtt_window_lock); 253 return; 254 } 255 256 /* The SDMA on Navi has a bug which can theoretically result in memory 257 * corruption if an invalidation happens at the same time as an VA 258 * translation. Avoid this by doing the invalidation from the SDMA 259 * itself. 260 */ 261 r = amdgpu_job_alloc_with_ib(adev, 16 * 4, &job); 262 if (r) 263 goto error_alloc; 264 265 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); 266 job->vm_needs_flush = true; 267 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 268 r = amdgpu_job_submit(job, &adev->mman.entity, 269 AMDGPU_FENCE_OWNER_UNDEFINED, &fence); 270 if (r) 271 goto error_submit; 272 273 mutex_unlock(&adev->mman.gtt_window_lock); 274 275 dma_fence_wait(fence, false); 276 dma_fence_put(fence); 277 278 return; 279 280 error_submit: 281 amdgpu_job_free(job); 282 283 error_alloc: 284 mutex_unlock(&adev->mman.gtt_window_lock); 285 DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r); 286 } 287 288 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 289 unsigned vmid, uint64_t pd_addr) 290 { 291 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 292 uint32_t req = gmc_v10_0_get_invalidate_req(vmid, 0); 293 unsigned eng = ring->vm_inv_eng; 294 295 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid), 296 lower_32_bits(pd_addr)); 297 298 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid), 299 upper_32_bits(pd_addr)); 300 301 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_req + eng, req); 302 303 /* wait for the invalidate to complete */ 304 amdgpu_ring_emit_reg_wait(ring, hub->vm_inv_eng0_ack + eng, 305 1 << vmid, 1 << vmid); 306 307 return pd_addr; 308 } 309 310 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 311 unsigned pasid) 312 { 313 struct amdgpu_device *adev = ring->adev; 314 uint32_t reg; 315 316 if (ring->funcs->vmhub == AMDGPU_GFXHUB) 317 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 318 else 319 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 320 321 amdgpu_ring_emit_wreg(ring, reg, pasid); 322 } 323 324 /* 325 * PTE format on NAVI 10: 326 * 63:59 reserved 327 * 58:57 reserved 328 * 56 F 329 * 55 L 330 * 54 reserved 331 * 53:52 SW 332 * 51 T 333 * 50:48 mtype 334 * 47:12 4k physical page base address 335 * 11:7 fragment 336 * 6 write 337 * 5 read 338 * 4 exe 339 * 3 Z 340 * 2 snooped 341 * 1 system 342 * 0 valid 343 * 344 * PDE format on NAVI 10: 345 * 63:59 block fragment size 346 * 58:55 reserved 347 * 54 P 348 * 53:48 reserved 349 * 47:6 physical base address of PD or PTE 350 * 5:3 reserved 351 * 2 C 352 * 1 system 353 * 0 valid 354 */ 355 static uint64_t gmc_v10_0_get_vm_pte_flags(struct amdgpu_device *adev, 356 uint32_t flags) 357 { 358 uint64_t pte_flag = 0; 359 360 if (flags & AMDGPU_VM_PAGE_EXECUTABLE) 361 pte_flag |= AMDGPU_PTE_EXECUTABLE; 362 if (flags & AMDGPU_VM_PAGE_READABLE) 363 pte_flag |= AMDGPU_PTE_READABLE; 364 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 365 pte_flag |= AMDGPU_PTE_WRITEABLE; 366 367 switch (flags & AMDGPU_VM_MTYPE_MASK) { 368 case AMDGPU_VM_MTYPE_DEFAULT: 369 pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 370 break; 371 case AMDGPU_VM_MTYPE_NC: 372 pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 373 break; 374 case AMDGPU_VM_MTYPE_WC: 375 pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_WC); 376 break; 377 case AMDGPU_VM_MTYPE_CC: 378 pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_CC); 379 break; 380 case AMDGPU_VM_MTYPE_UC: 381 pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 382 break; 383 default: 384 pte_flag |= AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 385 break; 386 } 387 388 if (flags & AMDGPU_VM_PAGE_PRT) 389 pte_flag |= AMDGPU_PTE_PRT; 390 391 return pte_flag; 392 } 393 394 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level, 395 uint64_t *addr, uint64_t *flags) 396 { 397 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 398 *addr = adev->vm_manager.vram_base_offset + *addr - 399 adev->gmc.vram_start; 400 BUG_ON(*addr & 0xFFFF00000000003FULL); 401 402 if (!adev->gmc.translate_further) 403 return; 404 405 if (level == AMDGPU_VM_PDB1) { 406 /* Set the block fragment size */ 407 if (!(*flags & AMDGPU_PDE_PTE)) 408 *flags |= AMDGPU_PDE_BFS(0x9); 409 410 } else if (level == AMDGPU_VM_PDB0) { 411 if (*flags & AMDGPU_PDE_PTE) 412 *flags &= ~AMDGPU_PDE_PTE; 413 else 414 *flags |= AMDGPU_PTE_TF; 415 } 416 } 417 418 static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = { 419 .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb, 420 .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb, 421 .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping, 422 .get_vm_pte_flags = gmc_v10_0_get_vm_pte_flags, 423 .get_vm_pde = gmc_v10_0_get_vm_pde 424 }; 425 426 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev) 427 { 428 if (adev->gmc.gmc_funcs == NULL) 429 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs; 430 } 431 432 static int gmc_v10_0_early_init(void *handle) 433 { 434 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 435 436 gmc_v10_0_set_gmc_funcs(adev); 437 gmc_v10_0_set_irq_funcs(adev); 438 439 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 440 adev->gmc.shared_aperture_end = 441 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 442 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 443 adev->gmc.private_aperture_end = 444 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 445 446 return 0; 447 } 448 449 static int gmc_v10_0_late_init(void *handle) 450 { 451 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 452 unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 }; 453 unsigned i; 454 455 for(i = 0; i < adev->num_rings; ++i) { 456 struct amdgpu_ring *ring = adev->rings[i]; 457 unsigned vmhub = ring->funcs->vmhub; 458 459 ring->vm_inv_eng = vm_inv_eng[vmhub]++; 460 dev_info(adev->dev, "ring %u(%s) uses VM inv eng %u on hub %u\n", 461 ring->idx, ring->name, ring->vm_inv_eng, 462 ring->funcs->vmhub); 463 } 464 465 /* Engine 17 is used for GART flushes */ 466 for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i) 467 BUG_ON(vm_inv_eng[i] > 17); 468 469 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 470 } 471 472 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev, 473 struct amdgpu_gmc *mc) 474 { 475 u64 base = 0; 476 477 if (!amdgpu_sriov_vf(adev)) 478 base = gfxhub_v2_0_get_fb_location(adev); 479 480 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 481 amdgpu_gmc_gart_location(adev, mc); 482 483 /* base offset of vram pages */ 484 adev->vm_manager.vram_base_offset = gfxhub_v2_0_get_mc_fb_offset(adev); 485 } 486 487 /** 488 * gmc_v10_0_mc_init - initialize the memory controller driver params 489 * 490 * @adev: amdgpu_device pointer 491 * 492 * Look up the amount of vram, vram width, and decide how to place 493 * vram and gart within the GPU's physical address space. 494 * Returns 0 for success. 495 */ 496 static int gmc_v10_0_mc_init(struct amdgpu_device *adev) 497 { 498 int chansize, numchan; 499 500 if (!amdgpu_emu_mode) 501 adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev); 502 else { 503 /* hard code vram_width for emulation */ 504 chansize = 128; 505 numchan = 1; 506 adev->gmc.vram_width = numchan * chansize; 507 } 508 509 /* Could aper size report 0 ? */ 510 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 511 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 512 513 /* size in MB on si */ 514 adev->gmc.mc_vram_size = 515 adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL; 516 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 517 adev->gmc.visible_vram_size = adev->gmc.aper_size; 518 519 /* In case the PCI BAR is larger than the actual amount of vram */ 520 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 521 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 522 523 /* set the gart size */ 524 if (amdgpu_gart_size == -1) { 525 switch (adev->asic_type) { 526 case CHIP_NAVI10: 527 default: 528 adev->gmc.gart_size = 512ULL << 20; 529 break; 530 } 531 } else 532 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 533 534 gmc_v10_0_vram_gtt_location(adev, &adev->gmc); 535 536 return 0; 537 } 538 539 static int gmc_v10_0_gart_init(struct amdgpu_device *adev) 540 { 541 int r; 542 543 if (adev->gart.bo) { 544 WARN(1, "NAVI10 PCIE GART already initialized\n"); 545 return 0; 546 } 547 548 /* Initialize common gart structure */ 549 r = amdgpu_gart_init(adev); 550 if (r) 551 return r; 552 553 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 554 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) | 555 AMDGPU_PTE_EXECUTABLE; 556 557 return amdgpu_gart_table_vram_alloc(adev); 558 } 559 560 static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev) 561 { 562 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 563 unsigned size; 564 565 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 566 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */ 567 } else { 568 u32 viewport; 569 u32 pitch; 570 571 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 572 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH); 573 size = (REG_GET_FIELD(viewport, 574 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 575 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) * 576 4); 577 } 578 /* return 0 if the pre-OS buffer uses up most of vram */ 579 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) { 580 DRM_ERROR("Warning: pre-OS buffer uses most of vram, \ 581 be aware of gart table overwrite\n"); 582 return 0; 583 } 584 585 return size; 586 } 587 588 589 590 static int gmc_v10_0_sw_init(void *handle) 591 { 592 int r; 593 int dma_bits; 594 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 595 596 gfxhub_v2_0_init(adev); 597 mmhub_v2_0_init(adev); 598 599 spin_lock_init(&adev->gmc.invalidate_lock); 600 601 adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev); 602 switch (adev->asic_type) { 603 case CHIP_NAVI10: 604 /* 605 * To fulfill 4-level page support, 606 * vm size is 256TB (48bit), maximum size of Navi10, 607 * block size 512 (9bit) 608 */ 609 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 610 break; 611 default: 612 break; 613 } 614 615 /* This interrupt is VMC page fault.*/ 616 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, 617 VMC_1_0__SRCID__VM_FAULT, 618 &adev->gmc.vm_fault); 619 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, 620 UTCL2_1_0__SRCID__FAULT, 621 &adev->gmc.vm_fault); 622 if (r) 623 return r; 624 625 /* 626 * Set the internal MC address mask This is the max address of the GPU's 627 * internal address space. 628 */ 629 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 630 631 /* 632 * Reserve 8M stolen memory for navi10 like vega10 633 * TODO: will check if it's really needed on asic. 634 */ 635 if (amdgpu_emu_mode == 1) 636 adev->gmc.stolen_size = 0; 637 else 638 adev->gmc.stolen_size = 9 * 1024 *1024; 639 640 /* 641 * Set DMA mask + need_dma32 flags. 642 * PCIE - can handle 44-bits. 643 * IGP - can handle 44-bits 644 * PCI - dma32 for legacy pci gart, 44 bits on navi10 645 */ 646 adev->need_dma32 = false; 647 dma_bits = adev->need_dma32 ? 32 : 44; 648 649 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 650 if (r) { 651 adev->need_dma32 = true; 652 dma_bits = 32; 653 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 654 } 655 656 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 657 if (r) { 658 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); 659 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n"); 660 } 661 662 r = gmc_v10_0_mc_init(adev); 663 if (r) 664 return r; 665 666 adev->gmc.stolen_size = gmc_v10_0_get_vbios_fb_size(adev); 667 668 /* Memory manager */ 669 r = amdgpu_bo_init(adev); 670 if (r) 671 return r; 672 673 r = gmc_v10_0_gart_init(adev); 674 if (r) 675 return r; 676 677 /* 678 * number of VMs 679 * VMID 0 is reserved for System 680 * amdgpu graphics/compute will use VMIDs 1-7 681 * amdkfd will use VMIDs 8-15 682 */ 683 adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS; 684 adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS; 685 686 amdgpu_vm_manager_init(adev); 687 688 return 0; 689 } 690 691 /** 692 * gmc_v8_0_gart_fini - vm fini callback 693 * 694 * @adev: amdgpu_device pointer 695 * 696 * Tears down the driver GART/VM setup (CIK). 697 */ 698 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev) 699 { 700 amdgpu_gart_table_vram_free(adev); 701 amdgpu_gart_fini(adev); 702 } 703 704 static int gmc_v10_0_sw_fini(void *handle) 705 { 706 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 707 708 amdgpu_vm_manager_fini(adev); 709 gmc_v10_0_gart_fini(adev); 710 amdgpu_gem_force_release(adev); 711 amdgpu_bo_fini(adev); 712 713 return 0; 714 } 715 716 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev) 717 { 718 switch (adev->asic_type) { 719 case CHIP_NAVI10: 720 break; 721 default: 722 break; 723 } 724 } 725 726 /** 727 * gmc_v10_0_gart_enable - gart enable 728 * 729 * @adev: amdgpu_device pointer 730 */ 731 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) 732 { 733 int r; 734 bool value; 735 u32 tmp; 736 737 if (adev->gart.bo == NULL) { 738 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 739 return -EINVAL; 740 } 741 742 r = amdgpu_gart_table_vram_pin(adev); 743 if (r) 744 return r; 745 746 r = gfxhub_v2_0_gart_enable(adev); 747 if (r) 748 return r; 749 750 r = mmhub_v2_0_gart_enable(adev); 751 if (r) 752 return r; 753 754 tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL); 755 tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK; 756 WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp); 757 758 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL); 759 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp); 760 761 /* Flush HDP after it is initialized */ 762 adev->nbio_funcs->hdp_flush(adev, NULL); 763 764 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 765 false : true; 766 767 gfxhub_v2_0_set_fault_enable_default(adev, value); 768 mmhub_v2_0_set_fault_enable_default(adev, value); 769 gmc_v10_0_flush_gpu_tlb(adev, 0, 0); 770 771 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 772 (unsigned)(adev->gmc.gart_size >> 20), 773 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 774 775 adev->gart.ready = true; 776 777 return 0; 778 } 779 780 static int gmc_v10_0_hw_init(void *handle) 781 { 782 int r; 783 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 784 785 /* The sequence of these two function calls matters.*/ 786 gmc_v10_0_init_golden_registers(adev); 787 788 r = gmc_v10_0_gart_enable(adev); 789 if (r) 790 return r; 791 792 return 0; 793 } 794 795 /** 796 * gmc_v10_0_gart_disable - gart disable 797 * 798 * @adev: amdgpu_device pointer 799 * 800 * This disables all VM page table. 801 */ 802 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev) 803 { 804 gfxhub_v2_0_gart_disable(adev); 805 mmhub_v2_0_gart_disable(adev); 806 amdgpu_gart_table_vram_unpin(adev); 807 } 808 809 static int gmc_v10_0_hw_fini(void *handle) 810 { 811 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 812 813 if (amdgpu_sriov_vf(adev)) { 814 /* full access mode, so don't touch any GMC register */ 815 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 816 return 0; 817 } 818 819 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 820 gmc_v10_0_gart_disable(adev); 821 822 return 0; 823 } 824 825 static int gmc_v10_0_suspend(void *handle) 826 { 827 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 828 829 gmc_v10_0_hw_fini(adev); 830 831 return 0; 832 } 833 834 static int gmc_v10_0_resume(void *handle) 835 { 836 int r; 837 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 838 839 r = gmc_v10_0_hw_init(adev); 840 if (r) 841 return r; 842 843 amdgpu_vmid_reset_all(adev); 844 845 return 0; 846 } 847 848 static bool gmc_v10_0_is_idle(void *handle) 849 { 850 /* MC is always ready in GMC v10.*/ 851 return true; 852 } 853 854 static int gmc_v10_0_wait_for_idle(void *handle) 855 { 856 /* There is no need to wait for MC idle in GMC v10.*/ 857 return 0; 858 } 859 860 static int gmc_v10_0_soft_reset(void *handle) 861 { 862 return 0; 863 } 864 865 static int gmc_v10_0_set_clockgating_state(void *handle, 866 enum amd_clockgating_state state) 867 { 868 int r; 869 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 870 871 r = mmhub_v2_0_set_clockgating(adev, state); 872 if (r) 873 return r; 874 875 return athub_v2_0_set_clockgating(adev, state); 876 } 877 878 static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags) 879 { 880 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 881 882 mmhub_v2_0_get_clockgating(adev, flags); 883 884 athub_v2_0_get_clockgating(adev, flags); 885 } 886 887 static int gmc_v10_0_set_powergating_state(void *handle, 888 enum amd_powergating_state state) 889 { 890 return 0; 891 } 892 893 const struct amd_ip_funcs gmc_v10_0_ip_funcs = { 894 .name = "gmc_v10_0", 895 .early_init = gmc_v10_0_early_init, 896 .late_init = gmc_v10_0_late_init, 897 .sw_init = gmc_v10_0_sw_init, 898 .sw_fini = gmc_v10_0_sw_fini, 899 .hw_init = gmc_v10_0_hw_init, 900 .hw_fini = gmc_v10_0_hw_fini, 901 .suspend = gmc_v10_0_suspend, 902 .resume = gmc_v10_0_resume, 903 .is_idle = gmc_v10_0_is_idle, 904 .wait_for_idle = gmc_v10_0_wait_for_idle, 905 .soft_reset = gmc_v10_0_soft_reset, 906 .set_clockgating_state = gmc_v10_0_set_clockgating_state, 907 .set_powergating_state = gmc_v10_0_set_powergating_state, 908 .get_clockgating_state = gmc_v10_0_get_clockgating_state, 909 }; 910 911 const struct amdgpu_ip_block_version gmc_v10_0_ip_block = 912 { 913 .type = AMD_IP_BLOCK_TYPE_GMC, 914 .major = 10, 915 .minor = 0, 916 .rev = 0, 917 .funcs = &gmc_v10_0_ip_funcs, 918 }; 919